diff options
Diffstat (limited to 'gcc/config')
39 files changed, 1885 insertions, 1677 deletions
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 228fd1b908d..ec501b78bdb 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -7059,7 +7059,8 @@ aarch64_print_address_internal (FILE *f, machine_mode mode, rtx x, unsigned int size; /* Check all addresses are Pmode - including ILP32. */ - gcc_assert (GET_MODE (x) == Pmode); + if (GET_MODE (x) != Pmode) + output_operand_lossage ("invalid address mode"); if (aarch64_classify_address (&addr, x, mode, true, type)) switch (addr.type) @@ -10628,11 +10629,21 @@ aarch64_print_hint_for_core_or_arch (const char *str, bool arch) const struct processor *entry = arch ? all_architectures : all_cores; for (; entry->name != NULL; entry++) candidates.safe_push (entry->name); + +#ifdef HAVE_LOCAL_CPU_DETECT + /* Add also "native" as possible value. */ + if (arch) + candidates.safe_push ("native"); +#endif + char *s; const char *hint = candidates_list_and_hint (str, s, candidates); if (hint) inform (input_location, "valid arguments are: %s;" " did you mean %qs?", s, hint); + else + inform (input_location, "valid arguments are: %s", s); + XDELETEVEC (s); } diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h index e3c52f63683..976f9afae54 100644 --- a/gcc/config/aarch64/aarch64.h +++ b/gcc/config/aarch64/aarch64.h @@ -1002,6 +1002,7 @@ extern const char *aarch64_rewrite_mcpu (int argc, const char **argv); #if defined(__aarch64__) extern const char *host_detect_local_cpu (int argc, const char **argv); +#define HAVE_LOCAL_CPU_DETECT # define EXTRA_SPEC_FUNCTIONS \ { "local_cpu_detect", host_detect_local_cpu }, \ MCPU_TO_MARCH_SPEC_FUNCTIONS diff --git a/gcc/config/aarch64/cortex-a57-fma-steering.c b/gcc/config/aarch64/cortex-a57-fma-steering.c index 92e3d045996..50e5108aa59 100644 --- a/gcc/config/aarch64/cortex-a57-fma-steering.c +++ b/gcc/config/aarch64/cortex-a57-fma-steering.c @@ -406,7 +406,7 @@ fma_forest::merge_forest (fma_forest *other_forest) /* Update root nodes' pointer to forest. */ for (other_root_iter = other_roots->begin (); - other_root_iter != other_roots->end (); other_root_iter++) + other_root_iter != other_roots->end (); ++other_root_iter) (*other_root_iter)->set_forest (this); /* Remove other_forest from the list of forests and move its tree roots in @@ -847,14 +847,13 @@ func_fma_steering::dfs (void (*process_forest) (fma_forest *), void (*process_node) (fma_forest *, fma_node *), bool free) { - vec<fma_node *> to_process; + auto_vec<fma_node *> to_process; + auto_vec<fma_node *> to_free; std::list<fma_forest *>::iterator forest_iter; - to_process.create (0); - /* For each forest. */ for (forest_iter = this->m_fma_forests.begin (); - forest_iter != this->m_fma_forests.end (); forest_iter++) + forest_iter != this->m_fma_forests.end (); ++forest_iter) { std::list<fma_root_node *>::iterator root_iter; @@ -863,7 +862,7 @@ func_fma_steering::dfs (void (*process_forest) (fma_forest *), /* For each tree root in this forest. */ for (root_iter = (*forest_iter)->get_roots ()->begin (); - root_iter != (*forest_iter)->get_roots ()->end (); root_iter++) + root_iter != (*forest_iter)->get_roots ()->end (); ++root_iter) { if (process_root) process_root (*forest_iter, *root_iter); @@ -881,28 +880,30 @@ func_fma_steering::dfs (void (*process_forest) (fma_forest *), if (process_node) process_node (*forest_iter, node); - /* Absence of children might indicate an alternate root of a *chain*. - It's ok to skip it here as the chain will be renamed when - processing the canonical root for that chain. */ - if (node->get_children ()->empty ()) - continue; - for (child_iter = node->get_children ()->begin (); - child_iter != node->get_children ()->end (); child_iter++) + child_iter != node->get_children ()->end (); ++child_iter) to_process.safe_push (*child_iter); + + /* Defer freeing so that the process_node callback can access the + parent and children of the node being processed. */ if (free) + to_free.safe_push (node); + } + + if (free) + { + delete *forest_iter; + + while (!to_free.is_empty ()) { + fma_node *node = to_free.pop (); if (node->root_p ()) delete static_cast<fma_root_node *> (node); else delete node; } } - if (free) - delete *forest_iter; } - - to_process.release (); } /* Build the dependency trees of FMUL and FMADD/FMSUB instructions. */ diff --git a/gcc/config/alpha/alpha.c b/gcc/config/alpha/alpha.c index 2f6d118606a..a039f045262 100644 --- a/gcc/config/alpha/alpha.c +++ b/gcc/config/alpha/alpha.c @@ -9406,14 +9406,6 @@ alpha_pad_function_end (void) || find_reg_note (insn, REG_NORETURN, NULL_RTX))) continue; - /* Make sure we do not split a call and its corresponding - CALL_ARG_LOCATION note. */ - next = NEXT_INSN (insn); - if (next == NULL) - continue; - if (NOTE_P (next) && NOTE_KIND (next) == NOTE_INSN_CALL_ARG_LOCATION) - insn = next; - next = next_active_insn (insn); if (next) { diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c index 843defd4cda..196d0e4a727 100644 --- a/gcc/config/arc/arc.c +++ b/gcc/config/arc/arc.c @@ -7700,10 +7700,7 @@ hwloop_optimize (hwloop_info loop) #if 0 while (DEBUG_INSN_P (entry_after) || (NOTE_P (entry_after) - && NOTE_KIND (entry_after) != NOTE_INSN_BASIC_BLOCK - /* Make sure we don't split a call and its corresponding - CALL_ARG_LOCATION note. */ - && NOTE_KIND (entry_after) != NOTE_INSN_CALL_ARG_LOCATION)) + && NOTE_KIND (entry_after) != NOTE_INSN_BASIC_BLOCK)) entry_after = NEXT_INSN (entry_after); #endif entry_after = next_nonnote_nondebug_insn_bb (entry_after); diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 17feba46619..90d62e699bc 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -16556,16 +16556,6 @@ create_fix_barrier (Mfix *fix, HOST_WIDE_INT max_address) /* Make sure that we found a place to insert the jump. */ gcc_assert (selected); - /* Make sure we do not split a call and its corresponding - CALL_ARG_LOCATION note. */ - if (CALL_P (selected)) - { - rtx_insn *next = NEXT_INSN (selected); - if (next && NOTE_P (next) - && NOTE_KIND (next) == NOTE_INSN_CALL_ARG_LOCATION) - selected = next; - } - /* Create a new JUMP_INSN that branches around a barrier. */ from = emit_jump_insn_after (gen_jump (label), selected); JUMP_LABEL (from) = label; diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index 6f3c4f461b9..bbf3937a592 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -2194,6 +2194,7 @@ extern const char *arm_target_thumb_only (int argc, const char **argv); an ARM chip. */ #if defined(__arm__) extern const char *host_detect_local_cpu (int argc, const char **argv); +#define HAVE_LOCAL_CPU_DETECT # define MCPU_MTUNE_NATIVE_FUNCTIONS \ { "local_cpu_detect", host_detect_local_cpu }, # define MCPU_MTUNE_NATIVE_SPECS \ diff --git a/gcc/config/arm/t-multilib b/gcc/config/arm/t-multilib index 2f790097670..3d0c824b4ec 100644 --- a/gcc/config/arm/t-multilib +++ b/gcc/config/arm/t-multilib @@ -70,6 +70,7 @@ v8_a_simd_variants := $(call all_feat_combs, simd crypto) v8_1_a_simd_variants := $(call all_feat_combs, simd crypto) v8_2_a_simd_variants := $(call all_feat_combs, simd fp16 fp16fml crypto dotprod) v8_4_a_simd_variants := $(call all_feat_combs, simd fp16 crypto) +v8_r_nosimd_variants := +crc ifneq (,$(HAS_APROFILE)) include $(srcdir)/config/arm/t-aprofile @@ -105,6 +106,14 @@ MULTILIB_MATCHES += march?armv7+fp=march?armv7-r+fp+idiv MULTILIB_MATCHES += $(foreach ARCH, $(all_early_arch), \ march?armv5te+fp=march?$(ARCH)+fp) +# Map v8-r down onto common v7 code. +MULTILIB_MATCHES += march?armv7=march?armv8-r +MULTILIB_MATCHES += $(foreach ARCH, $(v8_r_nosimd_variants), \ + march?armv7=march?armv8-r$(ARCH)) +MULTILIB_MATCHES += $(foreach ARCH,+simd +crypto, \ + march?armv7+fp=march?armv8-r$(ARCH) \ + march?armv7+fp=march?armv8-r+crc$(ARCH)) + ifeq (,$(HAS_APROFILE)) # Map all v7-a diff --git a/gcc/config/c6x/c6x.c b/gcc/config/c6x/c6x.c index 762e29faa17..f12edfd0821 100644 --- a/gcc/config/c6x/c6x.c +++ b/gcc/config/c6x/c6x.c @@ -4637,7 +4637,6 @@ static void c6x_gen_bundles (void) { basic_block bb; - rtx_insn *insn, *next, *last_call; FOR_EACH_BB_FN (bb, cfun) { @@ -4704,29 +4703,6 @@ c6x_gen_bundles (void) break; } } - /* Bundling, and emitting nops, can separate - NOTE_INSN_CALL_ARG_LOCATION from the corresponding calls. Fix - that up here. */ - last_call = NULL; - for (insn = get_insns (); insn; insn = next) - { - next = NEXT_INSN (insn); - if (CALL_P (insn) - || (INSN_P (insn) && GET_CODE (PATTERN (insn)) == SEQUENCE - && CALL_P (XVECEXP (PATTERN (insn), 0, 0)))) - last_call = insn; - if (!NOTE_P (insn) || NOTE_KIND (insn) != NOTE_INSN_CALL_ARG_LOCATION) - continue; - if (NEXT_INSN (last_call) == insn) - continue; - SET_NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn); - SET_PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn); - SET_PREV_INSN (insn) = last_call; - SET_NEXT_INSN (insn) = NEXT_INSN (last_call); - SET_PREV_INSN (NEXT_INSN (insn)) = insn; - SET_NEXT_INSN (PREV_INSN (insn)) = insn; - last_call = insn; - } } /* Emit a NOP instruction for CYCLES cycles after insn AFTER. Return it. */ diff --git a/gcc/config/frv/frv.c b/gcc/config/frv/frv.c index 3bf770b3649..56027bd67d9 100644 --- a/gcc/config/frv/frv.c +++ b/gcc/config/frv/frv.c @@ -1415,8 +1415,6 @@ frv_function_contains_far_jump (void) static void frv_function_prologue (FILE *file) { - rtx_insn *insn, *next, *last_call; - /* If no frame was created, check whether the function uses a call instruction to implement a far jump. If so, save the link in gr3 and replace all returns to LR with returns to GR3. GR3 is used because it @@ -1457,32 +1455,6 @@ frv_function_prologue (FILE *file) /* Allow the garbage collector to free the nops created by frv_reorg. */ memset (frv_nops, 0, sizeof (frv_nops)); - - /* Locate CALL_ARG_LOCATION notes that have been misplaced - and move them back to where they should be located. */ - last_call = NULL; - for (insn = get_insns (); insn; insn = next) - { - next = NEXT_INSN (insn); - if (CALL_P (insn) - || (INSN_P (insn) && GET_CODE (PATTERN (insn)) == SEQUENCE - && CALL_P (XVECEXP (PATTERN (insn), 0, 0)))) - last_call = insn; - - if (!NOTE_P (insn) || NOTE_KIND (insn) != NOTE_INSN_CALL_ARG_LOCATION) - continue; - - if (NEXT_INSN (last_call) == insn) - continue; - - SET_NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn); - SET_PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn); - SET_PREV_INSN (insn) = last_call; - SET_NEXT_INSN (insn) = NEXT_INSN (last_call); - SET_PREV_INSN (NEXT_INSN (insn)) = insn; - SET_NEXT_INSN (PREV_INSN (insn)) = insn; - last_call = insn; - } } diff --git a/gcc/config/i386/cetintrin.h b/gcc/config/i386/cetintrin.h index 7a4b4d8bf24..e9abcf3c580 100644 --- a/gcc/config/i386/cetintrin.h +++ b/gcc/config/i386/cetintrin.h @@ -34,37 +34,32 @@ #define __DISABLE_SHSTK__ #endif /* __SHSTK__ */ -extern __inline unsigned int -__attribute__((__gnu_inline__, __always_inline__, __artificial__)) -_rdsspd (unsigned int __B) -{ - return __builtin_ia32_rdsspd (__B); -} - #ifdef __x86_64__ extern __inline unsigned long long __attribute__((__gnu_inline__, __always_inline__, __artificial__)) -_rdsspq (unsigned long long __B) +_get_ssp (void) { - return __builtin_ia32_rdsspq (__B); + return __builtin_ia32_rdsspq (); } -#endif - -extern __inline void +#else +extern __inline unsigned int __attribute__((__gnu_inline__, __always_inline__, __artificial__)) -_incsspd (unsigned int __B) +_get_ssp (void) { - __builtin_ia32_incsspd (__B); + return __builtin_ia32_rdsspd (); } +#endif -#ifdef __x86_64__ extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__)) -_incsspq (unsigned long long __B) +_inc_ssp (unsigned int __B) { - __builtin_ia32_incsspq (__B); -} +#ifdef __x86_64__ + __builtin_ia32_incsspq ((unsigned long long) __B); +#else + __builtin_ia32_incsspd (__B); #endif +} extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__)) diff --git a/gcc/config/i386/i386-builtin-types.def b/gcc/config/i386/i386-builtin-types.def index ba335490489..08360d23cbb 100644 --- a/gcc/config/i386/i386-builtin-types.def +++ b/gcc/config/i386/i386-builtin-types.def @@ -192,6 +192,7 @@ DEF_POINTER_TYPE (PCV64QI, V64QI, CONST) DEF_FUNCTION_TYPE (FLOAT128) DEF_FUNCTION_TYPE (UINT64) DEF_FUNCTION_TYPE (UNSIGNED) +DEF_FUNCTION_TYPE (UINT) DEF_FUNCTION_TYPE (USHORT) DEF_FUNCTION_TYPE (INT) DEF_FUNCTION_TYPE (VOID) diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def index 169189d962c..a48019499bd 100644 --- a/gcc/config/i386/i386-builtin.def +++ b/gcc/config/i386/i386-builtin.def @@ -3043,7 +3043,7 @@ BDESC (OPTION_MASK_ISA_SHSTK, CODE_FOR_clrssbsy, "__builtin_ia32_clrssbsy", IX86 BDESC_END (CET, CET_NORMAL) BDESC_FIRST (cet_rdssp, CET_NORMAL, - OPTION_MASK_ISA_SHSTK, CODE_FOR_rdsspsi, "__builtin_ia32_rdsspd", IX86_BUILTIN_RDSSPD, UNKNOWN, (int) UINT_FTYPE_UINT) -BDESC (OPTION_MASK_ISA_SHSTK | OPTION_MASK_ISA_64BIT, CODE_FOR_rdsspdi, "__builtin_ia32_rdsspq", IX86_BUILTIN_RDSSPQ, UNKNOWN, (int) UINT64_FTYPE_UINT64) + OPTION_MASK_ISA_SHSTK, CODE_FOR_rdsspsi, "__builtin_ia32_rdsspd", IX86_BUILTIN_RDSSPD, UNKNOWN, (int) UINT_FTYPE_VOID) +BDESC (OPTION_MASK_ISA_SHSTK | OPTION_MASK_ISA_64BIT, CODE_FOR_rdsspdi, "__builtin_ia32_rdsspq", IX86_BUILTIN_RDSSPQ, UNKNOWN, (int) UINT64_FTYPE_VOID) BDESC_END (CET_NORMAL, MAX) diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 020eef9fd7b..640c5921863 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -2619,16 +2619,8 @@ rest_of_insert_endbranch (void) /* Generate ENDBRANCH after CALL, which can return more than twice, setjmp-like functions. */ - /* Skip notes that must immediately follow the call insn. */ - rtx_insn *next_insn = insn; - if (NEXT_INSN (insn) - && NOTE_P (NEXT_INSN (insn)) - && (NOTE_KIND (NEXT_INSN (insn)) - == NOTE_INSN_CALL_ARG_LOCATION)) - next_insn = NEXT_INSN (insn); - cet_eb = gen_nop_endbr (); - emit_insn_after_setloc (cet_eb, next_insn, INSN_LOCATION (insn)); + emit_insn_after_setloc (cet_eb, insn, INSN_LOCATION (insn)); continue; } @@ -3470,8 +3462,9 @@ ix86_option_override_internal (bool main_args_p, const wide_int_bitmask PTA_SKYLAKE_AVX512 = PTA_SKYLAKE | PTA_AVX512F | PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU | PTA_CLWB; - const wide_int_bitmask PTA_CANNONLAKE = PTA_SKYLAKE_AVX512 | PTA_AVX512VBMI - | PTA_AVX512IFMA | PTA_SHA; + const wide_int_bitmask PTA_CANNONLAKE = PTA_SKYLAKE | PTA_AVX512F + | PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU + | PTA_AVX512VBMI | PTA_AVX512IFMA | PTA_SHA; const wide_int_bitmask PTA_ICELAKE = PTA_CANNONLAKE | PTA_AVX512VNNI | PTA_GFNI | PTA_VAES | PTA_AVX512VBMI2 | PTA_VPCLMULQDQ | PTA_AVX512BITALG | PTA_RDPID; @@ -4200,6 +4193,11 @@ ix86_option_override_internal (bool main_args_p, || ((processor_alias_table[i].flags & PTA_64BIT) != 0))) candidates.safe_push (processor_alias_table[i].name); +#ifdef HAVE_LOCAL_CPU_DETECT + /* Add also "native" as possible value. */ + candidates.safe_push ("native"); +#endif + char *s; const char *hint = candidates_list_and_hint (opts->x_ix86_arch_string, s, candidates); @@ -4272,6 +4270,11 @@ ix86_option_override_internal (bool main_args_p, || ((processor_alias_table[i].flags & PTA_64BIT) != 0)) candidates.safe_push (processor_alias_table[i].name); +#ifdef HAVE_LOCAL_CPU_DETECT + /* Add also "native" as possible value. */ + candidates.safe_push ("native"); +#endif + char *s; const char *hint = candidates_list_and_hint (opts->x_ix86_tune_string, s, candidates); @@ -5895,6 +5898,16 @@ ix86_set_indirect_branch_type (tree fndecl) ((cfun->machine->indirect_branch_type == indirect_branch_thunk_extern) ? "thunk-extern" : "thunk")); + + /* -mindirect-branch=thunk-extern, -fcf-protection=branch and + -fcheck-pointer-bounds are not compatible. */ + if ((cfun->machine->indirect_branch_type + == indirect_branch_thunk_extern) + && flag_check_pointer_bounds + && (flag_cf_protection & CF_BRANCH) != 0) + error ("%<-mindirect-branch=thunk-extern%>, " + "%<-fcf-protection=branch%> and " + "%<-fcheck-pointer-bounds%> are not compatible"); } if (cfun->machine->function_return_type == indirect_branch_unset) @@ -10803,18 +10816,62 @@ static int indirect_thunks_bnd_used; # define INDIRECT_LABEL "LIND" #endif +/* Indicate what prefix is needed for an indirect branch. */ +enum indirect_thunk_prefix +{ + indirect_thunk_prefix_none, + indirect_thunk_prefix_bnd, + indirect_thunk_prefix_nt +}; + +/* Return the prefix needed for an indirect branch INSN. */ + +enum indirect_thunk_prefix +indirect_thunk_need_prefix (rtx_insn *insn) +{ + enum indirect_thunk_prefix need_prefix; + if (ix86_bnd_prefixed_insn_p (insn)) + need_prefix = indirect_thunk_prefix_bnd; + else if ((cfun->machine->indirect_branch_type + == indirect_branch_thunk_extern) + && ix86_notrack_prefixed_insn_p (insn)) + { + /* NOTRACK prefix is only used with external thunk so that it + can be properly updated to support CET at run-time. */ + need_prefix = indirect_thunk_prefix_nt; + } + else + need_prefix = indirect_thunk_prefix_none; + return need_prefix; +} + /* Fills in the label name that should be used for the indirect thunk. */ static void indirect_thunk_name (char name[32], unsigned int regno, - bool need_bnd_p, bool ret_p) + enum indirect_thunk_prefix need_prefix, + bool ret_p) { if (regno != INVALID_REGNUM && ret_p) gcc_unreachable (); if (USE_HIDDEN_LINKONCE) { - const char *bnd = need_bnd_p ? "_bnd" : ""; + const char *prefix; + + if (need_prefix == indirect_thunk_prefix_bnd) + prefix = "_bnd"; + else if (need_prefix == indirect_thunk_prefix_nt + && regno != INVALID_REGNUM) + { + /* NOTRACK prefix is only used with external thunk via + register so that NOTRACK prefix can be added to indirect + branch via register to support CET at run-time. */ + prefix = "_nt"; + } + else + prefix = ""; + if (regno != INVALID_REGNUM) { const char *reg_prefix; @@ -10823,19 +10880,19 @@ indirect_thunk_name (char name[32], unsigned int regno, else reg_prefix = ""; sprintf (name, "__x86_indirect_thunk%s_%s%s", - bnd, reg_prefix, reg_names[regno]); + prefix, reg_prefix, reg_names[regno]); } else { const char *ret = ret_p ? "return" : "indirect"; - sprintf (name, "__x86_%s_thunk%s", ret, bnd); + sprintf (name, "__x86_%s_thunk%s", ret, prefix); } } else { if (regno != INVALID_REGNUM) { - if (need_bnd_p) + if (need_prefix == indirect_thunk_prefix_bnd) ASM_GENERATE_INTERNAL_LABEL (name, "LITBR", regno); else ASM_GENERATE_INTERNAL_LABEL (name, "LITR", regno); @@ -10844,14 +10901,14 @@ indirect_thunk_name (char name[32], unsigned int regno, { if (ret_p) { - if (need_bnd_p) + if (need_prefix == indirect_thunk_prefix_bnd) ASM_GENERATE_INTERNAL_LABEL (name, "LRTB", 0); else ASM_GENERATE_INTERNAL_LABEL (name, "LRT", 0); } else { - if (need_bnd_p) + if (need_prefix == indirect_thunk_prefix_bnd) ASM_GENERATE_INTERNAL_LABEL (name, "LITB", 0); else ASM_GENERATE_INTERNAL_LABEL (name, "LIT", 0); @@ -10887,7 +10944,8 @@ indirect_thunk_name (char name[32], unsigned int regno, */ static void -output_indirect_thunk (bool need_bnd_p, unsigned int regno) +output_indirect_thunk (enum indirect_thunk_prefix need_prefix, + unsigned int regno) { char indirectlabel1[32]; char indirectlabel2[32]; @@ -10898,7 +10956,7 @@ output_indirect_thunk (bool need_bnd_p, unsigned int regno) indirectlabelno++); /* Call */ - if (need_bnd_p) + if (need_prefix == indirect_thunk_prefix_bnd) fputs ("\tbnd call\t", asm_out_file); else fputs ("\tcall\t", asm_out_file); @@ -10935,7 +10993,7 @@ output_indirect_thunk (bool need_bnd_p, unsigned int regno) output_asm_insn ("lea\t{%E1, %0|%0, %E1}", xops); } - if (need_bnd_p) + if (need_prefix == indirect_thunk_prefix_bnd) fputs ("\tbnd ret\n", asm_out_file); else fputs ("\tret\n", asm_out_file); @@ -10947,13 +11005,14 @@ output_indirect_thunk (bool need_bnd_p, unsigned int regno) on the top of stack. */ static void -output_indirect_thunk_function (bool need_bnd_p, unsigned int regno) +output_indirect_thunk_function (enum indirect_thunk_prefix need_prefix, + unsigned int regno) { char name[32]; tree decl; /* Create __x86_indirect_thunk/__x86_indirect_thunk_bnd. */ - indirect_thunk_name (name, regno, need_bnd_p, false); + indirect_thunk_name (name, regno, need_prefix, false); decl = build_decl (BUILTINS_LOCATION, FUNCTION_DECL, get_identifier (name), build_function_type_list (void_type_node, NULL_TREE)); @@ -11001,7 +11060,7 @@ output_indirect_thunk_function (bool need_bnd_p, unsigned int regno) /* Create alias for __x86.return_thunk/__x86.return_thunk_bnd. */ char alias[32]; - indirect_thunk_name (alias, regno, need_bnd_p, true); + indirect_thunk_name (alias, regno, need_prefix, true); #if TARGET_MACHO if (TARGET_MACHO) { @@ -11037,7 +11096,7 @@ output_indirect_thunk_function (bool need_bnd_p, unsigned int regno) /* Make sure unwind info is emitted for the thunk if needed. */ final_start_function (emit_barrier (), asm_out_file, 1); - output_indirect_thunk (need_bnd_p, regno); + output_indirect_thunk (need_prefix, regno); final_end_function (); init_insn_lengths (); @@ -11073,18 +11132,22 @@ ix86_code_end (void) unsigned int regno; if (indirect_thunk_needed) - output_indirect_thunk_function (false, INVALID_REGNUM); + output_indirect_thunk_function (indirect_thunk_prefix_none, + INVALID_REGNUM); if (indirect_thunk_bnd_needed) - output_indirect_thunk_function (true, INVALID_REGNUM); + output_indirect_thunk_function (indirect_thunk_prefix_bnd, + INVALID_REGNUM); for (regno = FIRST_REX_INT_REG; regno <= LAST_REX_INT_REG; regno++) { unsigned int i = regno - FIRST_REX_INT_REG + LAST_INT_REG + 1; if ((indirect_thunks_used & (1 << i))) - output_indirect_thunk_function (false, regno); + output_indirect_thunk_function (indirect_thunk_prefix_none, + regno); if ((indirect_thunks_bnd_used & (1 << i))) - output_indirect_thunk_function (true, regno); + output_indirect_thunk_function (indirect_thunk_prefix_bnd, + regno); } for (regno = FIRST_INT_REG; regno <= LAST_INT_REG; regno++) @@ -11093,10 +11156,12 @@ ix86_code_end (void) tree decl; if ((indirect_thunks_used & (1 << regno))) - output_indirect_thunk_function (false, regno); + output_indirect_thunk_function (indirect_thunk_prefix_none, + regno); if ((indirect_thunks_bnd_used & (1 << regno))) - output_indirect_thunk_function (true, regno); + output_indirect_thunk_function (indirect_thunk_prefix_bnd, + regno); if (!(pic_labels_used & (1 << regno))) continue; @@ -28673,7 +28738,8 @@ ix86_output_indirect_branch_via_reg (rtx call_op, bool sibcall_p) { char thunk_name_buf[32]; char *thunk_name; - bool need_bnd_p = ix86_bnd_prefixed_insn_p (current_output_insn); + enum indirect_thunk_prefix need_prefix + = indirect_thunk_need_prefix (current_output_insn); int regno = REGNO (call_op); if (cfun->machine->indirect_branch_type @@ -28684,12 +28750,12 @@ ix86_output_indirect_branch_via_reg (rtx call_op, bool sibcall_p) int i = regno; if (i >= FIRST_REX_INT_REG) i -= (FIRST_REX_INT_REG - LAST_INT_REG - 1); - if (need_bnd_p) + if (need_prefix == indirect_thunk_prefix_bnd) indirect_thunks_bnd_used |= 1 << i; else indirect_thunks_used |= 1 << i; } - indirect_thunk_name (thunk_name_buf, regno, need_bnd_p, false); + indirect_thunk_name (thunk_name_buf, regno, need_prefix, false); thunk_name = thunk_name_buf; } else @@ -28699,19 +28765,19 @@ ix86_output_indirect_branch_via_reg (rtx call_op, bool sibcall_p) { if (thunk_name != NULL) { - if (need_bnd_p) + if (need_prefix == indirect_thunk_prefix_bnd) fprintf (asm_out_file, "\tbnd jmp\t%s\n", thunk_name); else fprintf (asm_out_file, "\tjmp\t%s\n", thunk_name); } else - output_indirect_thunk (need_bnd_p, regno); + output_indirect_thunk (need_prefix, regno); } else { if (thunk_name != NULL) { - if (need_bnd_p) + if (need_prefix == indirect_thunk_prefix_bnd) fprintf (asm_out_file, "\tbnd call\t%s\n", thunk_name); else fprintf (asm_out_file, "\tcall\t%s\n", thunk_name); @@ -28729,7 +28795,7 @@ ix86_output_indirect_branch_via_reg (rtx call_op, bool sibcall_p) indirectlabelno++); /* Jump. */ - if (need_bnd_p) + if (need_prefix == indirect_thunk_prefix_bnd) fputs ("\tbnd jmp\t", asm_out_file); else fputs ("\tjmp\t", asm_out_file); @@ -28740,18 +28806,18 @@ ix86_output_indirect_branch_via_reg (rtx call_op, bool sibcall_p) if (thunk_name != NULL) { - if (need_bnd_p) + if (need_prefix == indirect_thunk_prefix_bnd) fprintf (asm_out_file, "\tbnd jmp\t%s\n", thunk_name); else fprintf (asm_out_file, "\tjmp\t%s\n", thunk_name); } else - output_indirect_thunk (need_bnd_p, regno); + output_indirect_thunk (need_prefix, regno); ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, indirectlabel2); /* Call. */ - if (need_bnd_p) + if (need_prefix == indirect_thunk_prefix_bnd) fputs ("\tbnd call\t", asm_out_file); else fputs ("\tcall\t", asm_out_file); @@ -28785,7 +28851,8 @@ ix86_output_indirect_branch_via_push (rtx call_op, const char *xasm, char thunk_name_buf[32]; char *thunk_name; char push_buf[64]; - bool need_bnd_p = ix86_bnd_prefixed_insn_p (current_output_insn); + enum indirect_thunk_prefix need_prefix + = indirect_thunk_need_prefix (current_output_insn); int regno = -1; if (cfun->machine->indirect_branch_type @@ -28793,12 +28860,12 @@ ix86_output_indirect_branch_via_push (rtx call_op, const char *xasm, { if (cfun->machine->indirect_branch_type == indirect_branch_thunk) { - if (need_bnd_p) + if (need_prefix == indirect_thunk_prefix_bnd) indirect_thunk_bnd_needed = true; else indirect_thunk_needed = true; } - indirect_thunk_name (thunk_name_buf, regno, need_bnd_p, false); + indirect_thunk_name (thunk_name_buf, regno, need_prefix, false); thunk_name = thunk_name_buf; } else @@ -28812,13 +28879,13 @@ ix86_output_indirect_branch_via_push (rtx call_op, const char *xasm, output_asm_insn (push_buf, &call_op); if (thunk_name != NULL) { - if (need_bnd_p) + if (need_prefix == indirect_thunk_prefix_bnd) fprintf (asm_out_file, "\tbnd jmp\t%s\n", thunk_name); else fprintf (asm_out_file, "\tjmp\t%s\n", thunk_name); } else - output_indirect_thunk (need_bnd_p, regno); + output_indirect_thunk (need_prefix, regno); } else { @@ -28833,7 +28900,7 @@ ix86_output_indirect_branch_via_push (rtx call_op, const char *xasm, indirectlabelno++); /* Jump. */ - if (need_bnd_p) + if (need_prefix == indirect_thunk_prefix_bnd) fputs ("\tbnd jmp\t", asm_out_file); else fputs ("\tjmp\t", asm_out_file); @@ -28879,18 +28946,18 @@ ix86_output_indirect_branch_via_push (rtx call_op, const char *xasm, if (thunk_name != NULL) { - if (need_bnd_p) + if (need_prefix == indirect_thunk_prefix_bnd) fprintf (asm_out_file, "\tbnd jmp\t%s\n", thunk_name); else fprintf (asm_out_file, "\tjmp\t%s\n", thunk_name); } else - output_indirect_thunk (need_bnd_p, regno); + output_indirect_thunk (need_prefix, regno); ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, indirectlabel2); /* Call. */ - if (need_bnd_p) + if (need_prefix == indirect_thunk_prefix_bnd) fputs ("\tbnd call\t", asm_out_file); else fputs ("\tcall\t", asm_out_file); @@ -28942,16 +29009,17 @@ ix86_output_function_return (bool long_p) if (cfun->machine->function_return_type != indirect_branch_keep) { char thunk_name[32]; - bool need_bnd_p = ix86_bnd_prefixed_insn_p (current_output_insn); + enum indirect_thunk_prefix need_prefix + = indirect_thunk_need_prefix (current_output_insn); if (cfun->machine->function_return_type != indirect_branch_thunk_inline) { bool need_thunk = (cfun->machine->function_return_type == indirect_branch_thunk); - indirect_thunk_name (thunk_name, INVALID_REGNUM, need_bnd_p, + indirect_thunk_name (thunk_name, INVALID_REGNUM, need_prefix, true); - if (need_bnd_p) + if (need_prefix == indirect_thunk_prefix_bnd) { indirect_thunk_bnd_needed |= need_thunk; fprintf (asm_out_file, "\tbnd jmp\t%s\n", thunk_name); @@ -28963,7 +29031,7 @@ ix86_output_function_return (bool long_p) } } else - output_indirect_thunk (need_bnd_p, INVALID_REGNUM); + output_indirect_thunk (need_prefix, INVALID_REGNUM); return ""; } @@ -35708,6 +35776,7 @@ ix86_expand_special_args_builtin (const struct builtin_description *d, case INT_FTYPE_VOID: case USHORT_FTYPE_VOID: case UINT64_FTYPE_VOID: + case UINT_FTYPE_VOID: case UNSIGNED_FTYPE_VOID: nargs = 0; klass = load; @@ -38497,7 +38566,7 @@ s4fma_expand: && fcode <= IX86_BUILTIN__BDESC_CET_NORMAL_LAST) { i = fcode - IX86_BUILTIN__BDESC_CET_NORMAL_FIRST; - return ix86_expand_args_builtin (bdesc_cet_rdssp + i, exp, + return ix86_expand_special_args_builtin (bdesc_cet_rdssp + i, exp, target); } @@ -42126,9 +42195,7 @@ ix86_seh_fixup_eh_fallthru (void) /* Do not separate calls from their debug information. */ for (next = NEXT_INSN (insn); next != NULL; next = NEXT_INSN (next)) - if (NOTE_P (next) - && (NOTE_KIND (next) == NOTE_INSN_VAR_LOCATION - || NOTE_KIND (next) == NOTE_INSN_CALL_ARG_LOCATION)) + if (NOTE_P (next) && NOTE_KIND (next) == NOTE_INSN_VAR_LOCATION) insn = next; else break; @@ -45904,7 +45971,18 @@ ix86_builtin_vectorization_cost (enum vect_cost_for_stmt type_of_cost, ix86_cost->sse_op, true); case vec_construct: - return ix86_vec_cost (mode, ix86_cost->sse_op, false); + { + /* N element inserts. */ + int cost = ix86_vec_cost (mode, ix86_cost->sse_op, false); + /* One vinserti128 for combining two SSE vectors for AVX256. */ + if (GET_MODE_BITSIZE (mode) == 256) + cost += ix86_vec_cost (mode, ix86_cost->addss, true); + /* One vinserti64x4 and two vinserti128 for combining SSE + and AVX256 vectors to AVX512. */ + else if (GET_MODE_BITSIZE (mode) == 512) + cost += 3 * ix86_vec_cost (mode, ix86_cost->addss, true); + return cost; + } default: gcc_unreachable (); @@ -50243,6 +50321,18 @@ ix86_add_stmt_cost (void *data, int count, enum vect_cost_for_stmt kind, break; } } + /* If we do elementwise loads into a vector then we are bound by + latency and execution resources for the many scalar loads + (AGU and load ports). Try to account for this by scaling the + construction cost by the number of elements involved. */ + if (kind == vec_construct + && stmt_info + && stmt_info->type == load_vec_info_type + && stmt_info->memory_access_type == VMAT_ELEMENTWISE) + { + stmt_cost = ix86_builtin_vectorization_cost (kind, vectype, misalign); + stmt_cost *= TYPE_VECTOR_SUBPARTS (vectype); + } if (stmt_cost == -1) stmt_cost = ix86_builtin_vectorization_cost (kind, vectype, misalign); diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index a4832bf696f..3998053a506 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -18391,8 +18391,8 @@ reg_ssp = gen_reg_rtx (word_mode); emit_insn (gen_rtx_SET (reg_ssp, const0_rtx)); emit_insn ((word_mode == SImode) - ? gen_rdsspsi (reg_ssp, reg_ssp) - : gen_rdsspdi (reg_ssp, reg_ssp)); + ? gen_rdsspsi (reg_ssp) + : gen_rdsspdi (reg_ssp)); emit_move_insn (mem, reg_ssp); } DONE; @@ -18437,8 +18437,8 @@ reg_ssp = gen_reg_rtx (word_mode); emit_insn (gen_rtx_SET (reg_ssp, const0_rtx)); emit_insn ((word_mode == SImode) - ? gen_rdsspsi (reg_ssp, reg_ssp) - : gen_rdsspdi (reg_ssp, reg_ssp)); + ? gen_rdsspsi (reg_ssp) + : gen_rdsspdi (reg_ssp)); mem_buf = gen_rtx_MEM (word_mode, plus_constant (Pmode, operands[0], 3 * GET_MODE_SIZE (ptr_mode))); @@ -20167,12 +20167,10 @@ ;; CET instructions (define_insn "rdssp<mode>" [(set (match_operand:SWI48x 0 "register_operand" "=r") - (unspec_volatile:SWI48x - [(match_operand:SWI48x 1 "register_operand" "0")] - UNSPECV_NOP_RDSSP))] + (unspec_volatile:SWI48x [(const_int 0)] UNSPECV_NOP_RDSSP))] "TARGET_SHSTK" - "rdssp<mskmodesuffix>\t%0" - [(set_attr "length" "4") + "xor{l}\t%k0, %k0\n\trdssp<mskmodesuffix>\t%0" + [(set_attr "length" "6") (set_attr "type" "other")]) (define_insn "incssp<mode>" diff --git a/gcc/config/iq2000/iq2000.c b/gcc/config/iq2000/iq2000.c index 18588084c10..ee89ced0e2f 100644 --- a/gcc/config/iq2000/iq2000.c +++ b/gcc/config/iq2000/iq2000.c @@ -1578,13 +1578,7 @@ final_prescan_insn (rtx_insn *insn, rtx opvec[] ATTRIBUTE_UNUSED, || (GET_CODE (PATTERN (insn)) == RETURN)) && NEXT_INSN (PREV_INSN (insn)) == insn) { - rtx_insn *tmp = insn; - while (NEXT_INSN (tmp) - && NOTE_P (NEXT_INSN (tmp)) - && NOTE_KIND (NEXT_INSN (tmp)) == NOTE_INSN_CALL_ARG_LOCATION) - tmp = NEXT_INSN (tmp); - - rtx_insn *nop_insn = emit_insn_after (gen_nop (), tmp); + rtx_insn *nop_insn = emit_insn_after (gen_nop (), insn); INSN_ADDRESSES_NEW (nop_insn, -1); } diff --git a/gcc/config/msp430/msp430.c b/gcc/config/msp430/msp430.c index 83e9e38af4c..a8fed123f7a 100644 --- a/gcc/config/msp430/msp430.c +++ b/gcc/config/msp430/msp430.c @@ -914,6 +914,8 @@ msp430_hard_regno_nregs (unsigned int, machine_mode mode) { if (mode == PSImode && msp430x) return 1; + if (mode == CPSImode && msp430x) + return 2; return ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD); } @@ -936,6 +938,8 @@ msp430_hard_regno_nregs_with_padding (int regno ATTRIBUTE_UNUSED, { if (mode == PSImode) return 2; + if (mode == CPSImode) + return 4; return msp430_hard_regno_nregs (regno, mode); } diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md index e581aadd15e..e748f053651 100644 --- a/gcc/config/pa/pa.md +++ b/gcc/config/pa/pa.md @@ -2536,24 +2536,40 @@ xoperands[0] = operands[0]; xoperands[1] = operands[1]; - xoperands[2] = gen_label_rtx (); - (*targetm.asm_out.internal_label) (asm_out_file, \"L\", - CODE_LABEL_NUMBER (xoperands[2])); - output_asm_insn (\"mfia %0\", xoperands); - - /* If we're trying to load the address of a label that happens to be - close, then we can use a shorter sequence. */ if (GET_CODE (operands[1]) == LABEL_REF - && !LABEL_REF_NONLOCAL_P (operands[1]) - && INSN_ADDRESSES_SET_P () - && abs (INSN_ADDRESSES (INSN_UID (XEXP (operands[1], 0))) - - INSN_ADDRESSES (INSN_UID (insn))) < 8100) - output_asm_insn (\"ldo %1-%2(%0),%0\", xoperands); + && !LABEL_REF_NONLOCAL_P (operands[1])) + { + xoperands[2] = gen_label_rtx (); + (*targetm.asm_out.internal_label) (asm_out_file, \"L\", + CODE_LABEL_NUMBER (xoperands[2])); + output_asm_insn (\"mfia %0\", xoperands); + + /* If we're trying to load the address of a label that happens to be + close, then we can use a shorter sequence. */ + if (INSN_ADDRESSES_SET_P () + && abs (INSN_ADDRESSES (INSN_UID (XEXP (operands[1], 0))) + - INSN_ADDRESSES (INSN_UID (insn))) < 8100) + output_asm_insn (\"ldo %1-%2(%0),%0\", xoperands); + else + { + output_asm_insn (\"addil L%%%1-%2,%0\", xoperands); + output_asm_insn (\"ldo R%%%1-%2(%0),%0\", xoperands); + } + } else { - output_asm_insn (\"addil L%%%1-%2,%0\", xoperands); - output_asm_insn (\"ldo R%%%1-%2(%0),%0\", xoperands); + /* Load using linkage table. */ + if (TARGET_64BIT) + { + output_asm_insn (\"addil LT%%%1,%%r27\", xoperands); + output_asm_insn (\"ldd RT%%%1(%0),%0\", xoperands); + } + else + { + output_asm_insn (\"addil LT%%%1,%%r19\", xoperands); + output_asm_insn (\"ldw RT%%%1(%0),%0\", xoperands); + } } return \"\"; }" @@ -2570,25 +2586,33 @@ xoperands[0] = operands[0]; xoperands[1] = operands[1]; - xoperands[2] = gen_label_rtx (); - output_asm_insn (\"bl .+8,%0\", xoperands); - output_asm_insn (\"depi 0,31,2,%0\", xoperands); - (*targetm.asm_out.internal_label) (asm_out_file, \"L\", - CODE_LABEL_NUMBER (xoperands[2])); - - /* If we're trying to load the address of a label that happens to be - close, then we can use a shorter sequence. */ if (GET_CODE (operands[1]) == LABEL_REF - && !LABEL_REF_NONLOCAL_P (operands[1]) - && INSN_ADDRESSES_SET_P () - && abs (INSN_ADDRESSES (INSN_UID (XEXP (operands[1], 0))) - - INSN_ADDRESSES (INSN_UID (insn))) < 8100) - output_asm_insn (\"ldo %1-%2(%0),%0\", xoperands); + && !LABEL_REF_NONLOCAL_P (operands[1])) + { + xoperands[2] = gen_label_rtx (); + output_asm_insn (\"bl .+8,%0\", xoperands); + output_asm_insn (\"depi 0,31,2,%0\", xoperands); + (*targetm.asm_out.internal_label) (asm_out_file, \"L\", + CODE_LABEL_NUMBER (xoperands[2])); + + /* If we're trying to load the address of a label that happens to be + close, then we can use a shorter sequence. */ + if (INSN_ADDRESSES_SET_P () + && abs (INSN_ADDRESSES (INSN_UID (XEXP (operands[1], 0))) + - INSN_ADDRESSES (INSN_UID (insn))) < 8100) + output_asm_insn (\"ldo %1-%2(%0),%0\", xoperands); + else + { + output_asm_insn (\"addil L%%%1-%2,%0\", xoperands); + output_asm_insn (\"ldo R%%%1-%2(%0),%0\", xoperands); + } + } else { - output_asm_insn (\"addil L%%%1-%2,%0\", xoperands); - output_asm_insn (\"ldo R%%%1-%2(%0),%0\", xoperands); + /* Load using linkage table. */ + output_asm_insn (\"addil LT%%%1,%%r19\", xoperands); + output_asm_insn (\"ldw RT%%%1(%0),%0\", xoperands); } return \"\"; }" diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c index 4ef7a1774c4..c38f6c394d5 100644 --- a/gcc/config/riscv/riscv.c +++ b/gcc/config/riscv/riscv.c @@ -3495,25 +3495,43 @@ riscv_output_gpr_save (unsigned mask) /* For stack frames that can't be allocated with a single ADDI instruction, compute the best value to initially allocate. It must at a minimum - allocate enough space to spill the callee-saved registers. */ + allocate enough space to spill the callee-saved registers. If TARGET_RVC, + try to pick a value that will allow compression of the register saves + without adding extra instructions. */ static HOST_WIDE_INT riscv_first_stack_step (struct riscv_frame_info *frame) { - HOST_WIDE_INT min_first_step = frame->total_size - frame->fp_sp_offset; - HOST_WIDE_INT max_first_step = IMM_REACH / 2 - STACK_BOUNDARY / 8; - if (SMALL_OPERAND (frame->total_size)) return frame->total_size; + HOST_WIDE_INT min_first_step = frame->total_size - frame->fp_sp_offset; + HOST_WIDE_INT max_first_step = IMM_REACH / 2 - STACK_BOUNDARY / 8; + HOST_WIDE_INT min_second_step = frame->total_size - max_first_step; + gcc_assert (min_first_step <= max_first_step); + /* As an optimization, use the least-significant bits of the total frame size, so that the second adjustment step is just LUI + ADD. */ - if (!SMALL_OPERAND (frame->total_size - max_first_step) + if (!SMALL_OPERAND (min_second_step) && frame->total_size % IMM_REACH < IMM_REACH / 2 && frame->total_size % IMM_REACH >= min_first_step) return frame->total_size % IMM_REACH; - gcc_assert (min_first_step <= max_first_step); + if (TARGET_RVC) + { + /* If we need two subtracts, and one is small enough to allow compressed + loads and stores, then put that one first. */ + if (IN_RANGE (min_second_step, 0, + (TARGET_64BIT ? SDSP_REACH : SWSP_REACH))) + return MAX (min_second_step, min_first_step); + + /* If we need LUI + ADDI + ADD for the second adjustment step, then start + with the minimum first step, so that we can get compressed loads and + stores. */ + else if (!SMALL_OPERAND (min_second_step)) + return min_first_step; + } + return max_first_step; } diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h index 1c1c3431119..6144e267727 100644 --- a/gcc/config/riscv/riscv.h +++ b/gcc/config/riscv/riscv.h @@ -891,9 +891,13 @@ extern unsigned riscv_stack_boundary; #define SHIFT_RS1 15 #define SHIFT_IMM 20 #define IMM_BITS 12 +#define C_SxSP_BITS 6 #define IMM_REACH (1LL << IMM_BITS) #define CONST_HIGH_PART(VALUE) (((VALUE) + (IMM_REACH/2)) & ~(IMM_REACH-1)) #define CONST_LOW_PART(VALUE) ((VALUE) - CONST_HIGH_PART (VALUE)) +#define SWSP_REACH (4LL << C_SxSP_BITS) +#define SDSP_REACH (8LL << C_SxSP_BITS) + #endif /* ! GCC_RISCV_H */ diff --git a/gcc/config/rl78/rl78.md b/gcc/config/rl78/rl78.md index 2b39b469ef5..03b776b6191 100644 --- a/gcc/config/rl78/rl78.md +++ b/gcc/config/rl78/rl78.md @@ -727,6 +727,14 @@ DONE;" ) +(define_expand "movdf" + [(set (match_operand:DF 0 "nonimmediate_operand" "") + (match_operand:DF 1 "general_operand" ""))] + "" + "rl78_split_movdi(operands, DFmode); + DONE;" +) + (define_expand "umindi3" [(set (match_operand:DI 0 "nonimmediate_operand" "") (umin:DI (match_operand:DI 1 "general_operand" "") diff --git a/gcc/config/rs6000/aix71.h b/gcc/config/rs6000/aix71.h index 2ad865a13ec..501af2be3c9 100644 --- a/gcc/config/rs6000/aix71.h +++ b/gcc/config/rs6000/aix71.h @@ -127,8 +127,12 @@ do { \ %{mpe: -I%R/usr/lpp/ppe.poe/include} \ %{pthread: -D_THREAD_SAFE}" +#define RS6000_CPU(NAME, CPU, FLAGS) +#include "rs6000-cpus.def" +#undef RS6000_CPU + #undef TARGET_DEFAULT -#define TARGET_DEFAULT (MASK_PPC_GPOPT | MASK_PPC_GFXOPT | MASK_MFCRF) +#define TARGET_DEFAULT ISA_2_5_MASKS_EMBEDDED #undef PROCESSOR_DEFAULT #define PROCESSOR_DEFAULT PROCESSOR_POWER7 diff --git a/gcc/config/rs6000/altivec.h b/gcc/config/rs6000/altivec.h index 684cb1990ef..1e495e69c42 100644 --- a/gcc/config/rs6000/altivec.h +++ b/gcc/config/rs6000/altivec.h @@ -433,8 +433,8 @@ #define vec_vctzd __builtin_vec_vctzd #define vec_vctzh __builtin_vec_vctzh #define vec_vctzw __builtin_vec_vctzw -#define vec_vextract4b __builtin_vec_vextract4b -#define vec_vinsert4b __builtin_vec_vinsert4b +#define vec_extract4b __builtin_vec_extract4b +#define vec_insert4b __builtin_vec_insert4b #define vec_vprtyb __builtin_vec_vprtyb #define vec_vprtybd __builtin_vec_vprtybd #define vec_vprtybw __builtin_vec_vprtybw diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index a01a3c69239..2759f2d31a5 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -291,8 +291,8 @@ ;; Load up a vector with the most significant bit set by loading up -1 and ;; doing a shift left (define_split - [(set (match_operand:VM 0 "altivec_register_operand" "") - (match_operand:VM 1 "easy_vector_constant_msb" ""))] + [(set (match_operand:VM 0 "altivec_register_operand") + (match_operand:VM 1 "easy_vector_constant_msb"))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode) && reload_completed" [(const_int 0)] { @@ -318,8 +318,8 @@ }) (define_split - [(set (match_operand:VM 0 "altivec_register_operand" "") - (match_operand:VM 1 "easy_vector_constant_add_self" ""))] + [(set (match_operand:VM 0 "altivec_register_operand") + (match_operand:VM 1 "easy_vector_constant_add_self"))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode) && reload_completed" [(set (match_dup 0) (match_dup 3)) (set (match_dup 0) (match_dup 4))] @@ -347,8 +347,8 @@ }) (define_split - [(set (match_operand:VM 0 "altivec_register_operand" "") - (match_operand:VM 1 "easy_vector_constant_vsldoi" ""))] + [(set (match_operand:VM 0 "altivec_register_operand") + (match_operand:VM 1 "easy_vector_constant_vsldoi"))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode) && can_create_pseudo_p ()" [(set (match_dup 2) (match_dup 3)) (set (match_dup 4) (match_dup 5)) @@ -692,9 +692,9 @@ ;; We do multiply as a fused multiply-add with an add of a -0.0 vector. (define_expand "altivec_mulv4sf3" - [(set (match_operand:V4SF 0 "register_operand" "") - (fma:V4SF (match_operand:V4SF 1 "register_operand" "") - (match_operand:V4SF 2 "register_operand" "") + [(set (match_operand:V4SF 0 "register_operand") + (fma:V4SF (match_operand:V4SF 1 "register_operand") + (match_operand:V4SF 2 "register_operand") (match_dup 3)))] "VECTOR_UNIT_ALTIVEC_P (V4SFmode)" { @@ -728,9 +728,9 @@ [(set_attr "type" "veccomplex")]) (define_expand "mulv4si3" - [(use (match_operand:V4SI 0 "register_operand" "")) - (use (match_operand:V4SI 1 "register_operand" "")) - (use (match_operand:V4SI 2 "register_operand" ""))] + [(use (match_operand:V4SI 0 "register_operand")) + (use (match_operand:V4SI 1 "register_operand")) + (use (match_operand:V4SI 2 "register_operand"))] "TARGET_ALTIVEC" { rtx zero; @@ -780,9 +780,9 @@ }) (define_expand "mulv8hi3" - [(use (match_operand:V8HI 0 "register_operand" "")) - (use (match_operand:V8HI 1 "register_operand" "")) - (use (match_operand:V8HI 2 "register_operand" ""))] + [(use (match_operand:V8HI 0 "register_operand")) + (use (match_operand:V8HI 1 "register_operand")) + (use (match_operand:V8HI 2 "register_operand"))] "TARGET_ALTIVEC" { rtx zero = gen_reg_rtx (V8HImode); @@ -940,9 +940,9 @@ [(set_attr "type" "veccomplex")]) (define_expand "altivec_vmrghb" - [(use (match_operand:V16QI 0 "register_operand" "")) - (use (match_operand:V16QI 1 "register_operand" "")) - (use (match_operand:V16QI 2 "register_operand" ""))] + [(use (match_operand:V16QI 0 "register_operand")) + (use (match_operand:V16QI 1 "register_operand")) + (use (match_operand:V16QI 2 "register_operand"))] "TARGET_ALTIVEC" { rtvec v; @@ -1004,9 +1004,9 @@ [(set_attr "type" "vecperm")]) (define_expand "altivec_vmrghh" - [(use (match_operand:V8HI 0 "register_operand" "")) - (use (match_operand:V8HI 1 "register_operand" "")) - (use (match_operand:V8HI 2 "register_operand" ""))] + [(use (match_operand:V8HI 0 "register_operand")) + (use (match_operand:V8HI 1 "register_operand")) + (use (match_operand:V8HI 2 "register_operand"))] "TARGET_ALTIVEC" { rtvec v; @@ -1060,9 +1060,9 @@ [(set_attr "type" "vecperm")]) (define_expand "altivec_vmrghw" - [(use (match_operand:V4SI 0 "register_operand" "")) - (use (match_operand:V4SI 1 "register_operand" "")) - (use (match_operand:V4SI 2 "register_operand" ""))] + [(use (match_operand:V4SI 0 "register_operand")) + (use (match_operand:V4SI 1 "register_operand")) + (use (match_operand:V4SI 2 "register_operand"))] "VECTOR_MEM_ALTIVEC_P (V4SImode)" { rtvec v; @@ -1131,9 +1131,9 @@ [(set_attr "type" "vecperm")]) (define_expand "altivec_vmrglb" - [(use (match_operand:V16QI 0 "register_operand" "")) - (use (match_operand:V16QI 1 "register_operand" "")) - (use (match_operand:V16QI 2 "register_operand" ""))] + [(use (match_operand:V16QI 0 "register_operand")) + (use (match_operand:V16QI 1 "register_operand")) + (use (match_operand:V16QI 2 "register_operand"))] "TARGET_ALTIVEC" { rtvec v; @@ -1195,9 +1195,9 @@ [(set_attr "type" "vecperm")]) (define_expand "altivec_vmrglh" - [(use (match_operand:V8HI 0 "register_operand" "")) - (use (match_operand:V8HI 1 "register_operand" "")) - (use (match_operand:V8HI 2 "register_operand" ""))] + [(use (match_operand:V8HI 0 "register_operand")) + (use (match_operand:V8HI 1 "register_operand")) + (use (match_operand:V8HI 2 "register_operand"))] "TARGET_ALTIVEC" { rtvec v; @@ -1251,9 +1251,9 @@ [(set_attr "type" "vecperm")]) (define_expand "altivec_vmrglw" - [(use (match_operand:V4SI 0 "register_operand" "")) - (use (match_operand:V4SI 1 "register_operand" "")) - (use (match_operand:V4SI 2 "register_operand" ""))] + [(use (match_operand:V4SI 0 "register_operand")) + (use (match_operand:V4SI 1 "register_operand")) + (use (match_operand:V4SI 2 "register_operand"))] "VECTOR_MEM_ALTIVEC_P (V4SImode)" { rtvec v; @@ -1410,9 +1410,9 @@ [(set_attr "type" "vecperm")]) (define_expand "vec_widen_umult_even_v16qi" - [(use (match_operand:V8HI 0 "register_operand" "")) - (use (match_operand:V16QI 1 "register_operand" "")) - (use (match_operand:V16QI 2 "register_operand" ""))] + [(use (match_operand:V8HI 0 "register_operand")) + (use (match_operand:V16QI 1 "register_operand")) + (use (match_operand:V16QI 2 "register_operand"))] "TARGET_ALTIVEC" { if (VECTOR_ELT_ORDER_BIG) @@ -1423,9 +1423,9 @@ }) (define_expand "vec_widen_smult_even_v16qi" - [(use (match_operand:V8HI 0 "register_operand" "")) - (use (match_operand:V16QI 1 "register_operand" "")) - (use (match_operand:V16QI 2 "register_operand" ""))] + [(use (match_operand:V8HI 0 "register_operand")) + (use (match_operand:V16QI 1 "register_operand")) + (use (match_operand:V16QI 2 "register_operand"))] "TARGET_ALTIVEC" { if (VECTOR_ELT_ORDER_BIG) @@ -1436,9 +1436,9 @@ }) (define_expand "vec_widen_umult_even_v8hi" - [(use (match_operand:V4SI 0 "register_operand" "")) - (use (match_operand:V8HI 1 "register_operand" "")) - (use (match_operand:V8HI 2 "register_operand" ""))] + [(use (match_operand:V4SI 0 "register_operand")) + (use (match_operand:V8HI 1 "register_operand")) + (use (match_operand:V8HI 2 "register_operand"))] "TARGET_ALTIVEC" { if (VECTOR_ELT_ORDER_BIG) @@ -1449,9 +1449,9 @@ }) (define_expand "vec_widen_smult_even_v8hi" - [(use (match_operand:V4SI 0 "register_operand" "")) - (use (match_operand:V8HI 1 "register_operand" "")) - (use (match_operand:V8HI 2 "register_operand" ""))] + [(use (match_operand:V4SI 0 "register_operand")) + (use (match_operand:V8HI 1 "register_operand")) + (use (match_operand:V8HI 2 "register_operand"))] "TARGET_ALTIVEC" { if (VECTOR_ELT_ORDER_BIG) @@ -1488,9 +1488,9 @@ }) (define_expand "vec_widen_umult_odd_v16qi" - [(use (match_operand:V8HI 0 "register_operand" "")) - (use (match_operand:V16QI 1 "register_operand" "")) - (use (match_operand:V16QI 2 "register_operand" ""))] + [(use (match_operand:V8HI 0 "register_operand")) + (use (match_operand:V16QI 1 "register_operand")) + (use (match_operand:V16QI 2 "register_operand"))] "TARGET_ALTIVEC" { if (VECTOR_ELT_ORDER_BIG) @@ -1501,9 +1501,9 @@ }) (define_expand "vec_widen_smult_odd_v16qi" - [(use (match_operand:V8HI 0 "register_operand" "")) - (use (match_operand:V16QI 1 "register_operand" "")) - (use (match_operand:V16QI 2 "register_operand" ""))] + [(use (match_operand:V8HI 0 "register_operand")) + (use (match_operand:V16QI 1 "register_operand")) + (use (match_operand:V16QI 2 "register_operand"))] "TARGET_ALTIVEC" { if (VECTOR_ELT_ORDER_BIG) @@ -1514,9 +1514,9 @@ }) (define_expand "vec_widen_umult_odd_v8hi" - [(use (match_operand:V4SI 0 "register_operand" "")) - (use (match_operand:V8HI 1 "register_operand" "")) - (use (match_operand:V8HI 2 "register_operand" ""))] + [(use (match_operand:V4SI 0 "register_operand")) + (use (match_operand:V8HI 1 "register_operand")) + (use (match_operand:V8HI 2 "register_operand"))] "TARGET_ALTIVEC" { if (VECTOR_ELT_ORDER_BIG) @@ -1527,9 +1527,9 @@ }) (define_expand "vec_widen_smult_odd_v8hi" - [(use (match_operand:V4SI 0 "register_operand" "")) - (use (match_operand:V8HI 1 "register_operand" "")) - (use (match_operand:V8HI 2 "register_operand" ""))] + [(use (match_operand:V4SI 0 "register_operand")) + (use (match_operand:V8HI 1 "register_operand")) + (use (match_operand:V8HI 2 "register_operand"))] "TARGET_ALTIVEC" { if (VECTOR_ELT_ORDER_BIG) @@ -1680,13 +1680,12 @@ (match_operand:V4SI 2 "register_operand" "v")] UNSPEC_VPKPX))] "TARGET_ALTIVEC" - "* - { - if (VECTOR_ELT_ORDER_BIG) - return \"vpkpx %0,%1,%2\"; - else - return \"vpkpx %0,%2,%1\"; - }" +{ + if (VECTOR_ELT_ORDER_BIG) + return "vpkpx %0,%1,%2"; + else + return "vpkpx %0,%2,%1"; +} [(set_attr "type" "vecperm")]) (define_insn "altivec_vpks<VI_char>ss" @@ -1695,13 +1694,12 @@ (match_operand:VP 2 "register_operand" "v")] UNSPEC_VPACK_SIGN_SIGN_SAT))] "<VI_unit>" - "* - { - if (VECTOR_ELT_ORDER_BIG) - return \"vpks<VI_char>ss %0,%1,%2\"; - else - return \"vpks<VI_char>ss %0,%2,%1\"; - }" +{ + if (VECTOR_ELT_ORDER_BIG) + return "vpks<VI_char>ss %0,%1,%2"; + else + return "vpks<VI_char>ss %0,%2,%1"; +} [(set_attr "type" "vecperm")]) (define_insn "altivec_vpks<VI_char>us" @@ -1710,13 +1708,12 @@ (match_operand:VP 2 "register_operand" "v")] UNSPEC_VPACK_SIGN_UNS_SAT))] "<VI_unit>" - "* - { - if (VECTOR_ELT_ORDER_BIG) - return \"vpks<VI_char>us %0,%1,%2\"; - else - return \"vpks<VI_char>us %0,%2,%1\"; - }" +{ + if (VECTOR_ELT_ORDER_BIG) + return "vpks<VI_char>us %0,%1,%2"; + else + return "vpks<VI_char>us %0,%2,%1"; +} [(set_attr "type" "vecperm")]) (define_insn "altivec_vpku<VI_char>us" @@ -1725,13 +1722,12 @@ (match_operand:VP 2 "register_operand" "v")] UNSPEC_VPACK_UNS_UNS_SAT))] "<VI_unit>" - "* - { - if (VECTOR_ELT_ORDER_BIG) - return \"vpku<VI_char>us %0,%1,%2\"; - else - return \"vpku<VI_char>us %0,%2,%1\"; - }" +{ + if (VECTOR_ELT_ORDER_BIG) + return "vpku<VI_char>us %0,%1,%2"; + else + return "vpku<VI_char>us %0,%2,%1"; +} [(set_attr "type" "vecperm")]) (define_insn "altivec_vpku<VI_char>um" @@ -1740,13 +1736,12 @@ (match_operand:VP 2 "register_operand" "v")] UNSPEC_VPACK_UNS_UNS_MOD))] "<VI_unit>" - "* - { - if (VECTOR_ELT_ORDER_BIG) - return \"vpku<VI_char>um %0,%1,%2\"; - else - return \"vpku<VI_char>um %0,%2,%1\"; - }" +{ + if (VECTOR_ELT_ORDER_BIG) + return "vpku<VI_char>um %0,%1,%2"; + else + return "vpku<VI_char>um %0,%2,%1"; +} [(set_attr "type" "vecperm")]) (define_insn "altivec_vpku<VI_char>um_direct" @@ -1755,13 +1750,12 @@ (match_operand:VP 2 "register_operand" "v")] UNSPEC_VPACK_UNS_UNS_MOD_DIRECT))] "<VI_unit>" - "* - { - if (BYTES_BIG_ENDIAN) - return \"vpku<VI_char>um %0,%1,%2\"; - else - return \"vpku<VI_char>um %0,%2,%1\"; - }" +{ + if (BYTES_BIG_ENDIAN) + return "vpku<VI_char>um %0,%1,%2"; + else + return "vpku<VI_char>um %0,%2,%1"; +} [(set_attr "type" "vecperm")]) (define_insn "*altivec_vrl<VI_char>" @@ -1955,9 +1949,9 @@ [(set_attr "type" "veccomplex")]) (define_expand "altivec_vspltb" - [(use (match_operand:V16QI 0 "register_operand" "")) - (use (match_operand:V16QI 1 "register_operand" "")) - (use (match_operand:QI 2 "u5bit_cint_operand" ""))] + [(use (match_operand:V16QI 0 "register_operand")) + (use (match_operand:V16QI 1 "register_operand")) + (use (match_operand:QI 2 "u5bit_cint_operand"))] "TARGET_ALTIVEC" { rtvec v; @@ -2003,9 +1997,9 @@ [(set_attr "type" "vecperm")]) (define_expand "altivec_vsplth" - [(use (match_operand:V8HI 0 "register_operand" "")) - (use (match_operand:V8HI 1 "register_operand" "")) - (use (match_operand:QI 2 "u5bit_cint_operand" ""))] + [(use (match_operand:V8HI 0 "register_operand")) + (use (match_operand:V8HI 1 "register_operand")) + (use (match_operand:QI 2 "u5bit_cint_operand"))] "TARGET_ALTIVEC" { rtvec v; @@ -2051,9 +2045,9 @@ [(set_attr "type" "vecperm")]) (define_expand "altivec_vspltw" - [(use (match_operand:V4SI 0 "register_operand" "")) - (use (match_operand:V4SI 1 "register_operand" "")) - (use (match_operand:QI 2 "u5bit_cint_operand" ""))] + [(use (match_operand:V4SI 0 "register_operand")) + (use (match_operand:V4SI 1 "register_operand")) + (use (match_operand:QI 2 "u5bit_cint_operand"))] "TARGET_ALTIVEC" { rtvec v; @@ -2099,9 +2093,9 @@ [(set_attr "type" "vecperm")]) (define_expand "altivec_vspltsf" - [(use (match_operand:V4SF 0 "register_operand" "")) - (use (match_operand:V4SF 1 "register_operand" "")) - (use (match_operand:QI 2 "u5bit_cint_operand" ""))] + [(use (match_operand:V4SF 0 "register_operand")) + (use (match_operand:V4SF 1 "register_operand")) + (use (match_operand:QI 2 "u5bit_cint_operand"))] "TARGET_ALTIVEC" { rtvec v; @@ -2153,10 +2147,10 @@ [(set_attr "type" "vecfloat")]) (define_expand "altivec_vperm_<mode>" - [(set (match_operand:VM 0 "register_operand" "") - (unspec:VM [(match_operand:VM 1 "register_operand" "") - (match_operand:VM 2 "register_operand" "") - (match_operand:V16QI 3 "register_operand" "")] + [(set (match_operand:VM 0 "register_operand") + (unspec:VM [(match_operand:VM 1 "register_operand") + (match_operand:VM 2 "register_operand") + (match_operand:V16QI 3 "register_operand")] UNSPEC_VPERM))] "TARGET_ALTIVEC" { @@ -2195,10 +2189,10 @@ (set_attr "length" "4")]) (define_expand "altivec_vperm_<mode>_uns" - [(set (match_operand:VM 0 "register_operand" "") - (unspec:VM [(match_operand:VM 1 "register_operand" "") - (match_operand:VM 2 "register_operand" "") - (match_operand:V16QI 3 "register_operand" "")] + [(set (match_operand:VM 0 "register_operand") + (unspec:VM [(match_operand:VM 1 "register_operand") + (match_operand:VM 2 "register_operand") + (match_operand:V16QI 3 "register_operand")] UNSPEC_VPERM_UNS))] "TARGET_ALTIVEC" { @@ -2223,10 +2217,10 @@ (set_attr "length" "4")]) (define_expand "vec_permv16qi" - [(set (match_operand:V16QI 0 "register_operand" "") - (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "") - (match_operand:V16QI 2 "register_operand" "") - (match_operand:V16QI 3 "register_operand" "")] + [(set (match_operand:V16QI 0 "register_operand") + (unspec:V16QI [(match_operand:V16QI 1 "register_operand") + (match_operand:V16QI 2 "register_operand") + (match_operand:V16QI 3 "register_operand")] UNSPEC_VPERM))] "TARGET_ALTIVEC" { @@ -2344,11 +2338,10 @@ [(set_attr "type" "vecfloat")]) (define_expand "altivec_copysign_v4sf3" - [(use (match_operand:V4SF 0 "register_operand" "")) - (use (match_operand:V4SF 1 "register_operand" "")) - (use (match_operand:V4SF 2 "register_operand" ""))] + [(use (match_operand:V4SF 0 "register_operand")) + (use (match_operand:V4SF 1 "register_operand")) + (use (match_operand:V4SF 2 "register_operand"))] "VECTOR_UNIT_ALTIVEC_P (V4SFmode)" - " { rtx mask = gen_reg_rtx (V4SImode); rtvec v = rtvec_alloc (4); @@ -2363,7 +2356,7 @@ emit_insn (gen_vector_select_v4sf (operands[0], operands[1], operands[2], gen_lowpart (V4SFmode, mask))); DONE; -}") +}) (define_insn "altivec_vsldoi_<mode>" [(set (match_operand:VM 0 "register_operand" "=v") @@ -2591,8 +2584,8 @@ [(set_attr "type" "vecsimple")]) (define_expand "altivec_lvsl" - [(use (match_operand:V16QI 0 "register_operand" "")) - (use (match_operand:V16QI 1 "memory_operand" ""))] + [(use (match_operand:V16QI 0 "register_operand")) + (use (match_operand:V16QI 1 "memory_operand"))] "TARGET_ALTIVEC" { if (VECTOR_ELT_ORDER_BIG) @@ -2667,11 +2660,10 @@ [(set_attr "type" "vecload")]) (define_expand "build_vector_mask_for_load" - [(set (match_operand:V16QI 0 "register_operand" "") - (unspec:V16QI [(match_operand 1 "memory_operand" "")] UNSPEC_LVSR))] + [(set (match_operand:V16QI 0 "register_operand") + (unspec:V16QI [(match_operand 1 "memory_operand")] UNSPEC_LVSR))] "TARGET_ALTIVEC" - " -{ +{ rtx addr; rtx temp; @@ -2683,7 +2675,7 @@ emit_insn (gen_altivec_lvsr (operands[0], replace_equiv_address (operands[1], temp))); DONE; -}") +}) ;; Parallel some of the LVE* and STV*'s with unspecs because some have ;; identical rtl but different instructions-- and gcc gets confused. @@ -3339,8 +3331,8 @@ [(set_attr "type" "vecsimple")]) (define_expand "neg<mode>2" - [(set (match_operand:VI2 0 "register_operand" "") - (neg:VI2 (match_operand:VI2 1 "register_operand" "")))] + [(set (match_operand:VI2 0 "register_operand") + (neg:VI2 (match_operand:VI2 1 "register_operand")))] "<VI_unit>" { if (!TARGET_P9_VECTOR || (<MODE>mode != V4SImode && <MODE>mode != V2DImode)) @@ -3361,12 +3353,11 @@ (match_operand:VIshort 2 "register_operand" "v")] UNSPEC_VMSUMU)))] "TARGET_ALTIVEC" - " -{ +{ emit_insn (gen_altivec_vmsumu<VI_char>m (operands[0], operands[1], operands[2], operands[3])); DONE; -}") - +}) + (define_expand "sdot_prodv8hi" [(set (match_operand:V4SI 0 "register_operand" "=v") (plus:V4SI (match_operand:V4SI 3 "register_operand" "v") @@ -3374,11 +3365,10 @@ (match_operand:V8HI 2 "register_operand" "v")] UNSPEC_VMSUMSHM)))] "TARGET_ALTIVEC" - " { emit_insn (gen_altivec_vmsumshm (operands[0], operands[1], operands[2], operands[3])); DONE; -}") +}) (define_expand "widen_usum<mode>3" [(set (match_operand:V4SI 0 "register_operand" "=v") @@ -3386,14 +3376,13 @@ (unspec:V4SI [(match_operand:VIshort 1 "register_operand" "v")] UNSPEC_VMSUMU)))] "TARGET_ALTIVEC" - " { rtx vones = gen_reg_rtx (GET_MODE (operands[1])); emit_insn (gen_altivec_vspltis<VI_char> (vones, const1_rtx)); emit_insn (gen_altivec_vmsumu<VI_char>m (operands[0], operands[1], vones, operands[2])); DONE; -}") +}) (define_expand "widen_ssumv16qi3" [(set (match_operand:V4SI 0 "register_operand" "=v") @@ -3401,14 +3390,13 @@ (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")] UNSPEC_VMSUMM)))] "TARGET_ALTIVEC" - " { rtx vones = gen_reg_rtx (V16QImode); emit_insn (gen_altivec_vspltisb (vones, const1_rtx)); emit_insn (gen_altivec_vmsummbm (operands[0], operands[1], vones, operands[2])); DONE; -}") +}) (define_expand "widen_ssumv8hi3" [(set (match_operand:V4SI 0 "register_operand" "=v") @@ -3416,14 +3404,13 @@ (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] UNSPEC_VMSUMSHM)))] "TARGET_ALTIVEC" - " { rtx vones = gen_reg_rtx (V8HImode); emit_insn (gen_altivec_vspltish (vones, const1_rtx)); emit_insn (gen_altivec_vmsumshm (operands[0], operands[1], vones, operands[2])); DONE; -}") +}) (define_expand "vec_unpacks_hi_<VP_small_lc>" [(set (match_operand:VP 0 "register_operand" "=v") @@ -3471,7 +3458,6 @@ (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")] UNSPEC_VUPKHUB))] "TARGET_ALTIVEC" - " { rtx vzero = gen_reg_rtx (V8HImode); rtx mask = gen_reg_rtx (V16QImode); @@ -3500,14 +3486,13 @@ emit_insn (gen_vec_initv16qiqi (mask, gen_rtx_PARALLEL (V16QImode, v))); emit_insn (gen_vperm_v16qiv8hi (operands[0], operands[1], vzero, mask)); DONE; -}") +}) (define_expand "vec_unpacku_hi_v8hi" [(set (match_operand:V4SI 0 "register_operand" "=v") (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] UNSPEC_VUPKHUH))] "TARGET_ALTIVEC" - " { rtx vzero = gen_reg_rtx (V4SImode); rtx mask = gen_reg_rtx (V16QImode); @@ -3536,14 +3521,13 @@ emit_insn (gen_vec_initv16qiqi (mask, gen_rtx_PARALLEL (V16QImode, v))); emit_insn (gen_vperm_v8hiv4si (operands[0], operands[1], vzero, mask)); DONE; -}") +}) (define_expand "vec_unpacku_lo_v16qi" [(set (match_operand:V8HI 0 "register_operand" "=v") (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")] UNSPEC_VUPKLUB))] "TARGET_ALTIVEC" - " { rtx vzero = gen_reg_rtx (V8HImode); rtx mask = gen_reg_rtx (V16QImode); @@ -3572,14 +3556,13 @@ emit_insn (gen_vec_initv16qiqi (mask, gen_rtx_PARALLEL (V16QImode, v))); emit_insn (gen_vperm_v16qiv8hi (operands[0], operands[1], vzero, mask)); DONE; -}") +}) (define_expand "vec_unpacku_lo_v8hi" [(set (match_operand:V4SI 0 "register_operand" "=v") (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] UNSPEC_VUPKLUH))] "TARGET_ALTIVEC" - " { rtx vzero = gen_reg_rtx (V4SImode); rtx mask = gen_reg_rtx (V16QImode); @@ -3608,7 +3591,7 @@ emit_insn (gen_vec_initv16qiqi (mask, gen_rtx_PARALLEL (V16QImode, v))); emit_insn (gen_vperm_v8hiv4si (operands[0], operands[1], vzero, mask)); DONE; -}") +}) (define_expand "vec_widen_umult_hi_v16qi" [(set (match_operand:V8HI 0 "register_operand" "=v") @@ -3616,7 +3599,6 @@ (match_operand:V16QI 2 "register_operand" "v")] UNSPEC_VMULWHUB))] "TARGET_ALTIVEC" - " { rtx ve = gen_reg_rtx (V8HImode); rtx vo = gen_reg_rtx (V8HImode); @@ -3634,7 +3616,7 @@ emit_insn (gen_altivec_vmrghh_direct (operands[0], vo, ve)); } DONE; -}") +}) (define_expand "vec_widen_umult_lo_v16qi" [(set (match_operand:V8HI 0 "register_operand" "=v") @@ -3642,7 +3624,6 @@ (match_operand:V16QI 2 "register_operand" "v")] UNSPEC_VMULWLUB))] "TARGET_ALTIVEC" - " { rtx ve = gen_reg_rtx (V8HImode); rtx vo = gen_reg_rtx (V8HImode); @@ -3660,7 +3641,7 @@ emit_insn (gen_altivec_vmrglh_direct (operands[0], vo, ve)); } DONE; -}") +}) (define_expand "vec_widen_smult_hi_v16qi" [(set (match_operand:V8HI 0 "register_operand" "=v") @@ -3668,7 +3649,6 @@ (match_operand:V16QI 2 "register_operand" "v")] UNSPEC_VMULWHSB))] "TARGET_ALTIVEC" - " { rtx ve = gen_reg_rtx (V8HImode); rtx vo = gen_reg_rtx (V8HImode); @@ -3686,7 +3666,7 @@ emit_insn (gen_altivec_vmrghh_direct (operands[0], vo, ve)); } DONE; -}") +}) (define_expand "vec_widen_smult_lo_v16qi" [(set (match_operand:V8HI 0 "register_operand" "=v") @@ -3694,7 +3674,6 @@ (match_operand:V16QI 2 "register_operand" "v")] UNSPEC_VMULWLSB))] "TARGET_ALTIVEC" - " { rtx ve = gen_reg_rtx (V8HImode); rtx vo = gen_reg_rtx (V8HImode); @@ -3712,7 +3691,7 @@ emit_insn (gen_altivec_vmrglh_direct (operands[0], vo, ve)); } DONE; -}") +}) (define_expand "vec_widen_umult_hi_v8hi" [(set (match_operand:V4SI 0 "register_operand" "=v") @@ -3720,7 +3699,6 @@ (match_operand:V8HI 2 "register_operand" "v")] UNSPEC_VMULWHUH))] "TARGET_ALTIVEC" - " { rtx ve = gen_reg_rtx (V4SImode); rtx vo = gen_reg_rtx (V4SImode); @@ -3738,7 +3716,7 @@ emit_insn (gen_altivec_vmrghw_direct (operands[0], vo, ve)); } DONE; -}") +}) (define_expand "vec_widen_umult_lo_v8hi" [(set (match_operand:V4SI 0 "register_operand" "=v") @@ -3746,7 +3724,6 @@ (match_operand:V8HI 2 "register_operand" "v")] UNSPEC_VMULWLUH))] "TARGET_ALTIVEC" - " { rtx ve = gen_reg_rtx (V4SImode); rtx vo = gen_reg_rtx (V4SImode); @@ -3764,7 +3741,7 @@ emit_insn (gen_altivec_vmrglw_direct (operands[0], vo, ve)); } DONE; -}") +}) (define_expand "vec_widen_smult_hi_v8hi" [(set (match_operand:V4SI 0 "register_operand" "=v") @@ -3772,7 +3749,6 @@ (match_operand:V8HI 2 "register_operand" "v")] UNSPEC_VMULWHSH))] "TARGET_ALTIVEC" - " { rtx ve = gen_reg_rtx (V4SImode); rtx vo = gen_reg_rtx (V4SImode); @@ -3790,7 +3766,7 @@ emit_insn (gen_altivec_vmrghw_direct (operands[0], vo, ve)); } DONE; -}") +}) (define_expand "vec_widen_smult_lo_v8hi" [(set (match_operand:V4SI 0 "register_operand" "=v") @@ -3798,7 +3774,6 @@ (match_operand:V8HI 2 "register_operand" "v")] UNSPEC_VMULWLSH))] "TARGET_ALTIVEC" - " { rtx ve = gen_reg_rtx (V4SImode); rtx vo = gen_reg_rtx (V4SImode); @@ -3816,7 +3791,7 @@ emit_insn (gen_altivec_vmrglw_direct (operands[0], vo, ve)); } DONE; -}") +}) (define_expand "vec_pack_trunc_<mode>" [(set (match_operand:<VP_small> 0 "register_operand" "=v") @@ -3831,7 +3806,6 @@ (mult:V16QI (match_operand:V16QI 1 "register_operand" "v") (match_operand:V16QI 2 "register_operand" "v")))] "TARGET_ALTIVEC" - " { rtx even = gen_reg_rtx (V8HImode); rtx odd = gen_reg_rtx (V8HImode); @@ -3851,13 +3825,12 @@ emit_insn (gen_altivec_vmulosb (odd, operands[1], operands[2])); emit_insn (gen_altivec_vperm_v8hiv16qi (operands[0], even, odd, mask)); DONE; -}") +}) (define_expand "altivec_negv4sf2" - [(use (match_operand:V4SF 0 "register_operand" "")) - (use (match_operand:V4SF 1 "register_operand" ""))] + [(use (match_operand:V4SF 0 "register_operand")) + (use (match_operand:V4SF 1 "register_operand"))] "TARGET_ALTIVEC" - " { rtx neg0; @@ -3871,7 +3844,7 @@ gen_lowpart (V4SFmode, neg0), operands[1])); DONE; -}") +}) ;; Vector reverse elements (define_expand "altivec_vreve<mode>2" @@ -3969,60 +3942,56 @@ [(set_attr "type" "vecstore")]) (define_expand "vec_unpacks_float_hi_v8hi" - [(set (match_operand:V4SF 0 "register_operand" "") - (unspec:V4SF [(match_operand:V8HI 1 "register_operand" "")] + [(set (match_operand:V4SF 0 "register_operand") + (unspec:V4SF [(match_operand:V8HI 1 "register_operand")] UNSPEC_VUPKHS_V4SF))] "TARGET_ALTIVEC" - " { rtx tmp = gen_reg_rtx (V4SImode); emit_insn (gen_vec_unpacks_hi_v8hi (tmp, operands[1])); emit_insn (gen_altivec_vcfsx (operands[0], tmp, const0_rtx)); DONE; -}") +}) (define_expand "vec_unpacks_float_lo_v8hi" - [(set (match_operand:V4SF 0 "register_operand" "") - (unspec:V4SF [(match_operand:V8HI 1 "register_operand" "")] + [(set (match_operand:V4SF 0 "register_operand") + (unspec:V4SF [(match_operand:V8HI 1 "register_operand")] UNSPEC_VUPKLS_V4SF))] "TARGET_ALTIVEC" - " { rtx tmp = gen_reg_rtx (V4SImode); emit_insn (gen_vec_unpacks_lo_v8hi (tmp, operands[1])); emit_insn (gen_altivec_vcfsx (operands[0], tmp, const0_rtx)); DONE; -}") +}) (define_expand "vec_unpacku_float_hi_v8hi" - [(set (match_operand:V4SF 0 "register_operand" "") - (unspec:V4SF [(match_operand:V8HI 1 "register_operand" "")] + [(set (match_operand:V4SF 0 "register_operand") + (unspec:V4SF [(match_operand:V8HI 1 "register_operand")] UNSPEC_VUPKHU_V4SF))] "TARGET_ALTIVEC" - " { rtx tmp = gen_reg_rtx (V4SImode); emit_insn (gen_vec_unpacku_hi_v8hi (tmp, operands[1])); emit_insn (gen_altivec_vcfux (operands[0], tmp, const0_rtx)); DONE; -}") +}) (define_expand "vec_unpacku_float_lo_v8hi" - [(set (match_operand:V4SF 0 "register_operand" "") - (unspec:V4SF [(match_operand:V8HI 1 "register_operand" "")] + [(set (match_operand:V4SF 0 "register_operand") + (unspec:V4SF [(match_operand:V8HI 1 "register_operand")] UNSPEC_VUPKLU_V4SF))] "TARGET_ALTIVEC" - " { rtx tmp = gen_reg_rtx (V4SImode); emit_insn (gen_vec_unpacku_lo_v8hi (tmp, operands[1])); emit_insn (gen_altivec_vcfux (operands[0], tmp, const0_rtx)); DONE; -}") +}) ;; Power8/power9 vector instructions encoded as Altivec instructions @@ -4529,13 +4498,13 @@ (define_expand "bcd<bcd_add_sub>_<code>" [(parallel [(set (reg:CCFP CR6_REGNO) (compare:CCFP - (unspec:V2DF [(match_operand:V1TI 1 "register_operand" "") - (match_operand:V1TI 2 "register_operand" "") - (match_operand:QI 3 "const_0_to_1_operand" "")] + (unspec:V2DF [(match_operand:V1TI 1 "register_operand") + (match_operand:V1TI 2 "register_operand") + (match_operand:QI 3 "const_0_to_1_operand")] UNSPEC_BCD_ADD_SUB) (match_dup 4))) - (clobber (match_scratch:V1TI 5 ""))]) - (set (match_operand:SI 0 "register_operand" "") + (clobber (match_scratch:V1TI 5))]) + (set (match_operand:SI 0 "register_operand") (BCD_TEST:SI (reg:CCFP CR6_REGNO) (const_int 0)))] "TARGET_P8_VECTOR" @@ -4550,10 +4519,10 @@ ;; a register class for CR6. (define_peephole2 - [(parallel [(set (match_operand:V1TI 0 "register_operand" "") - (unspec:V1TI [(match_operand:V1TI 1 "register_operand" "") - (match_operand:V1TI 2 "register_operand" "") - (match_operand:QI 3 "const_0_to_1_operand" "")] + [(parallel [(set (match_operand:V1TI 0 "register_operand") + (unspec:V1TI [(match_operand:V1TI 1 "register_operand") + (match_operand:V1TI 2 "register_operand") + (match_operand:QI 3 "const_0_to_1_operand")] UNSPEC_BCD_ADD_SUB)) (clobber (reg:CCFP CR6_REGNO))]) (parallel [(set (reg:CCFP CR6_REGNO) @@ -4562,8 +4531,8 @@ (match_dup 2) (match_dup 3)] UNSPEC_BCD_ADD_SUB) - (match_operand:V2DF 4 "zero_constant" ""))) - (clobber (match_operand:V1TI 5 "register_operand" ""))])] + (match_operand:V2DF 4 "zero_constant"))) + (clobber (match_operand:V1TI 5 "register_operand"))])] "TARGET_P8_VECTOR" [(parallel [(set (match_dup 0) (unspec:V1TI [(match_dup 1) diff --git a/gcc/config/rs6000/darwin.md b/gcc/config/rs6000/darwin.md index 066518d072f..48fd5b9613c 100644 --- a/gcc/config/rs6000/darwin.md +++ b/gcc/config/rs6000/darwin.md @@ -31,28 +31,27 @@ You should have received a copy of the GNU General Public License (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b") (match_operand 2 "" ""))))] "TARGET_MACHO && TARGET_HARD_FLOAT && !TARGET_64BIT" - "* { switch (which_alternative) { case 0: - return \"lfd %0,lo16(%2)(%1)\"; + return "lfd %0,lo16(%2)(%1)"; case 1: { if (TARGET_POWERPC64 && TARGET_32BIT) /* Note, old assemblers didn't support relocation here. */ - return \"ld %0,lo16(%2)(%1)\"; + return "ld %0,lo16(%2)(%1)"; else { - output_asm_insn (\"la %0,lo16(%2)(%1)\", operands); - output_asm_insn (\"lwz %L0,4(%0)\", operands); - return (\"lwz %0,0(%0)\"); + output_asm_insn ("la %0,lo16(%2)(%1)", operands); + output_asm_insn ("lwz %L0,4(%0)", operands); + return ("lwz %0,0(%0)"); } } default: gcc_unreachable (); } -}" +} [(set_attr "type" "load") (set_attr "length" "4,12")]) @@ -62,18 +61,17 @@ You should have received a copy of the GNU General Public License (mem:DF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b") (match_operand 2 "" ""))))] "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_64BIT" - "* { switch (which_alternative) { case 0: - return \"lfd %0,lo16(%2)(%1)\"; + return "lfd %0,lo16(%2)(%1)"; case 1: - return \"ld %0,lo16(%2)(%1)\"; + return "ld %0,lo16(%2)(%1)"; default: gcc_unreachable (); } -}" +} [(set_attr "type" "load") (set_attr "length" "4,4")]) @@ -173,8 +171,8 @@ You should have received a copy of the GNU General Public License ;; Mach-O PIC trickery. (define_expand "macho_high" - [(set (match_operand 0 "" "") - (high (match_operand 1 "" "")))] + [(set (match_operand 0 "") + (high (match_operand 1 "")))] "TARGET_MACHO" { if (TARGET_64BIT) @@ -199,9 +197,9 @@ You should have received a copy of the GNU General Public License "lis %0,ha16(%1)") (define_expand "macho_low" - [(set (match_operand 0 "" "") - (lo_sum (match_operand 1 "" "") - (match_operand 2 "" "")))] + [(set (match_operand 0 "") + (lo_sum (match_operand 1 "") + (match_operand 2 "")))] "TARGET_MACHO" { if (TARGET_64BIT) @@ -227,10 +225,10 @@ You should have received a copy of the GNU General Public License "la %0,lo16(%2)(%1)") (define_split - [(set (mem:V4SI (plus:DI (match_operand:DI 0 "gpc_reg_operand" "") - (match_operand:DI 1 "short_cint_operand" ""))) - (match_operand:V4SI 2 "register_operand" "")) - (clobber (match_operand:DI 3 "gpc_reg_operand" ""))] + [(set (mem:V4SI (plus:DI (match_operand:DI 0 "gpc_reg_operand") + (match_operand:DI 1 "short_cint_operand"))) + (match_operand:V4SI 2 "register_operand")) + (clobber (match_operand:DI 3 "gpc_reg_operand"))] "TARGET_MACHO && TARGET_64BIT" [(set (match_dup 3) (plus:DI (match_dup 0) (match_dup 1))) (set (mem:V4SI (match_dup 3)) @@ -239,7 +237,7 @@ You should have received a copy of the GNU General Public License (define_expand "load_macho_picbase" [(set (reg:SI LR_REGNO) - (unspec [(match_operand 0 "" "")] + (unspec [(match_operand 0 "")] UNSPEC_LD_MPIC))] "(DEFAULT_ABI == ABI_DARWIN) && flag_pic" { @@ -262,7 +260,7 @@ You should have received a copy of the GNU General Public License #else gcc_unreachable (); #endif - return "bcl 20,31,%0\\n%0:"; + return "bcl 20,31,%0\n%0:"; } [(set_attr "type" "branch") (set_attr "cannot_copy" "yes") @@ -279,17 +277,17 @@ You should have received a copy of the GNU General Public License #else gcc_unreachable (); #endif - return "bcl 20,31,%0\\n%0:"; + return "bcl 20,31,%0\n%0:"; } [(set_attr "type" "branch") (set_attr "cannot_copy" "yes") (set_attr "length" "4")]) (define_expand "macho_correct_pic" - [(set (match_operand 0 "" "") - (plus (match_operand 1 "" "") - (unspec [(match_operand 2 "" "") - (match_operand 3 "" "")] + [(set (match_operand 0 "") + (plus (match_operand 1 "") + (unspec [(match_operand 2 "") + (match_operand 3 "")] UNSPEC_MPIC_CORRECT)))] "DEFAULT_ABI == ABI_DARWIN" { @@ -385,7 +383,7 @@ You should have received a copy of the GNU General Public License (define_expand "reload_macho_picbase" [(set (reg:SI LR_REGNO) - (unspec [(match_operand 0 "" "")] + (unspec [(match_operand 0 "")] UNSPEC_RELD_MPIC))] "(DEFAULT_ABI == ABI_DARWIN) && flag_pic" { @@ -408,14 +406,14 @@ You should have received a copy of the GNU General Public License { static char tmp[64]; const char *cnam = machopic_get_function_picbase (); - snprintf (tmp, 64, "bcl 20,31,%s\\n%s:\\n%%0:", cnam, cnam); + snprintf (tmp, 64, "bcl 20,31,%s\n%s:\n%%0:", cnam, cnam); return tmp; } else #else gcc_unreachable (); #endif - return "bcl 20,31,%0\\n%0:"; + return "bcl 20,31,%0\n%0:"; } [(set_attr "type" "branch") (set_attr "cannot_copy" "yes") @@ -432,14 +430,14 @@ You should have received a copy of the GNU General Public License { static char tmp[64]; const char *cnam = machopic_get_function_picbase (); - snprintf (tmp, 64, "bcl 20,31,%s\\n%s:\\n%%0:", cnam, cnam); + snprintf (tmp, 64, "bcl 20,31,%s\n%s:\n%%0:", cnam, cnam); return tmp; } else #else gcc_unreachable (); #endif - return "bcl 20,31,%0\\n%0:"; + return "bcl 20,31,%0\n%0:"; } [(set_attr "type" "branch") (set_attr "cannot_copy" "yes") diff --git a/gcc/config/rs6000/dfp.md b/gcc/config/rs6000/dfp.md index 216251f69f0..cd15aa81bfd 100644 --- a/gcc/config/rs6000/dfp.md +++ b/gcc/config/rs6000/dfp.md @@ -344,11 +344,11 @@ [(set (match_dup 3) (compare:CCFP (unspec:D64_D128 - [(match_operand:SI 1 "const_int_operand" "n") - (match_operand:D64_D128 2 "gpc_reg_operand" "d")] + [(match_operand:SI 1 "const_int_operand") + (match_operand:D64_D128 2 "gpc_reg_operand")] UNSPEC_DTSTSFI) (match_dup 4))) - (set (match_operand:SI 0 "register_operand" "") + (set (match_operand:SI 0 "register_operand") (DFP_TEST:SI (match_dup 3) (const_int 0))) ] diff --git a/gcc/config/rs6000/rs6000-builtin.def b/gcc/config/rs6000/rs6000-builtin.def index 86604da46fa..f9548a0c405 100644 --- a/gcc/config/rs6000/rs6000-builtin.def +++ b/gcc/config/rs6000/rs6000-builtin.def @@ -403,6 +403,14 @@ | RS6000_BTC_UNARY), \ CODE_FOR_ ## ICODE) /* ICODE */ +#define BU_P8V_VSX_2(ENUM, NAME, ATTR, ICODE) \ + RS6000_BUILTIN_2 (P8V_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_vsx_" NAME, /* NAME */ \ + RS6000_BTM_P8_VECTOR, /* MASK */ \ + (RS6000_BTC_ ## ATTR /* ATTR */ \ + | RS6000_BTC_BINARY), \ + CODE_FOR_ ## ICODE) /* ICODE */ + #define BU_P8V_OVERLOAD_1(ENUM, NAME) \ RS6000_BUILTIN_1 (P8V_BUILTIN_VEC_ ## ENUM, /* ENUM */ \ "__builtin_vec_" NAME, /* NAME */ \ @@ -1154,14 +1162,6 @@ BU_ALTIVEC_A (NABS_V16QI, "nabs_v16qi", CONST, nabsv16qi2) BU_ALTIVEC_A (NABS_V4SF, "nabs_v4sf", CONST, vsx_nabsv4sf2) BU_ALTIVEC_A (NABS_V2DF, "nabs_v2df", CONST, vsx_nabsv2df2) -/* Altivec NEG functions. */ -BU_ALTIVEC_A (NEG_V2DI, "neg_v2di", CONST, negv2di2) -BU_ALTIVEC_A (NEG_V4SI, "neg_v4si", CONST, negv4si2) -BU_ALTIVEC_A (NEG_V8HI, "neg_v8hi", CONST, negv8hi2) -BU_ALTIVEC_A (NEG_V16QI, "neg_v16qi", CONST, negv16qi2) -BU_ALTIVEC_A (NEG_V4SF, "neg_v4sf", CONST, negv4sf2) -BU_ALTIVEC_A (NEG_V2DF, "neg_v2df", CONST, negv2df2) - /* 1 argument Altivec builtin functions. */ BU_ALTIVEC_1 (VEXPTEFP, "vexptefp", FP, altivec_vexptefp) BU_ALTIVEC_1 (VLOGEFP, "vlogefp", FP, altivec_vlogefp) @@ -1461,7 +1461,6 @@ BU_ALTIVEC_OVERLOAD_1 (FLOOR, "floor") BU_ALTIVEC_OVERLOAD_1 (LOGE, "loge") BU_ALTIVEC_OVERLOAD_1 (MTVSCR, "mtvscr") BU_ALTIVEC_OVERLOAD_1 (NEARBYINT, "nearbyint") -BU_ALTIVEC_OVERLOAD_1 (NEG, "neg") BU_ALTIVEC_OVERLOAD_1 (RE, "re") BU_ALTIVEC_OVERLOAD_1 (RINT, "rint") BU_ALTIVEC_OVERLOAD_1 (ROUND, "round") @@ -1659,12 +1658,6 @@ BU_VSX_2 (CMPLE_U16QI, "cmple_u16qi", CONST, vector_ngtuv16qi) BU_VSX_2 (CMPLE_U8HI, "cmple_u8hi", CONST, vector_ngtuv8hi) BU_VSX_2 (CMPLE_U4SI, "cmple_u4si", CONST, vector_ngtuv4si) BU_VSX_2 (CMPLE_U2DI, "cmple_u2di", CONST, vector_ngtuv2di) -BU_VSX_2 (FLOAT2_V2DF, "float2_v2df", CONST, float2_v2df) -BU_VSX_2 (FLOAT2_V2DI, "float2_v2di", CONST, float2_v2di) -BU_VSX_2 (UNS_FLOAT2_V2DI, "uns_float2_v2di", CONST, uns_float2_v2di) - -BU_VSX_2 (VEC_VSIGNED2_V2DF, "vsigned2_v2df", CONST, vsigned2_v2df) -BU_VSX_2 (VEC_VUNSIGNED2_V2DF, "vunsigned2_v2df", CONST, vunsigned2_v2df) /* VSX abs builtin functions. */ BU_VSX_A (XVABSDP, "xvabsdp", CONST, absv2df2) @@ -1856,10 +1849,6 @@ BU_VSX_OVERLOAD_2 (XXMRGHW, "xxmrghw") BU_VSX_OVERLOAD_2 (XXMRGLW, "xxmrglw") BU_VSX_OVERLOAD_2 (XXSPLTD, "xxspltd") BU_VSX_OVERLOAD_2 (XXSPLTW, "xxspltw") -BU_VSX_OVERLOAD_2 (FLOAT2, "float2") -BU_VSX_OVERLOAD_2 (UNS_FLOAT2, "uns_float2") -BU_VSX_OVERLOAD_2 (VSIGNED2, "vsigned2") -BU_VSX_OVERLOAD_2 (VUNSIGNED2, "vunsigned2") /* 1 argument VSX overloaded builtin functions. */ BU_VSX_OVERLOAD_1 (DOUBLE, "double") @@ -1910,6 +1899,23 @@ BU_P8V_VSX_1 (REVB_V16QI, "revb_v16qi", CONST, revb_v16qi) BU_P8V_VSX_1 (REVB_V2DF, "revb_v2df", CONST, revb_v2df) BU_P8V_VSX_1 (REVB_V4SF, "revb_v4sf", CONST, revb_v4sf) +/* Power 8 Altivec NEG functions. */ +BU_P8V_AV_1 (NEG_V2DI, "neg_v2di", CONST, negv2di2) +BU_P8V_AV_1 (NEG_V4SI, "neg_v4si", CONST, negv4si2) +BU_P8V_AV_1 (NEG_V8HI, "neg_v8hi", CONST, negv8hi2) +BU_P8V_AV_1 (NEG_V16QI, "neg_v16qi", CONST, negv16qi2) +BU_P8V_AV_1 (NEG_V4SF, "neg_v4sf", CONST, negv4sf2) +BU_P8V_AV_1 (NEG_V2DF, "neg_v2df", CONST, negv2df2) + + +/* 2 argument VSX instructions added in ISA 2.07. */ +BU_P8V_VSX_2 (FLOAT2_V2DF, "float2_v2df", CONST, float2_v2df) +BU_P8V_VSX_2 (FLOAT2_V2DI, "float2_v2di", CONST, float2_v2di) +BU_P8V_VSX_2 (UNS_FLOAT2_V2DI, "uns_float2_v2di", CONST, uns_float2_v2di) +BU_P8V_VSX_2 (VEC_VSIGNED2_V2DF, "vsigned2_v2df", CONST, vsigned2_v2df) +BU_P8V_VSX_2 (VEC_VUNSIGNED2_V2DF, "vunsigned2_v2df", CONST, vunsigned2_v2df) + + /* 1 argument altivec instructions added in ISA 2.07. */ BU_P8V_AV_1 (ABS_V2DI, "abs_v2di", CONST, absv2di2) BU_P8V_AV_1 (VUPKHSW, "vupkhsw", CONST, altivec_vupkhsw) @@ -2025,6 +2031,7 @@ BU_P8V_OVERLOAD_1 (VPOPCNTUW, "vpopcntuw") BU_P8V_OVERLOAD_1 (VPOPCNTUD, "vpopcntud") BU_P8V_OVERLOAD_1 (VGBBD, "vgbbd") BU_P8V_OVERLOAD_1 (REVB, "revb") +BU_P8V_OVERLOAD_1 (NEG, "neg") /* ISA 2.07 vector overloaded 2 argument functions. */ BU_P8V_OVERLOAD_2 (EQV, "eqv") @@ -2052,6 +2059,10 @@ BU_P8V_OVERLOAD_2 (VSRD, "vsrd") BU_P8V_OVERLOAD_2 (VSUBCUQ, "vsubcuq") BU_P8V_OVERLOAD_2 (VSUBUDM, "vsubudm") BU_P8V_OVERLOAD_2 (VSUBUQM, "vsubuqm") +BU_P8V_OVERLOAD_2 (FLOAT2, "float2") +BU_P8V_OVERLOAD_2 (UNS_FLOAT2, "uns_float2") +BU_P8V_OVERLOAD_2 (VSIGNED2, "vsigned2") +BU_P8V_OVERLOAD_2 (VUNSIGNED2, "vunsigned2") /* ISA 2.07 vector overloaded 3 argument functions. */ BU_P8V_OVERLOAD_3 (VADDECUQ, "vaddecuq") @@ -2226,9 +2237,8 @@ BU_P9V_AV_2 (VEXTUWLX, "vextuwlx", CONST, vextuwlx) BU_P9V_AV_2 (VEXTUWRX, "vextuwrx", CONST, vextuwrx) /* Insert/extract 4 byte word into a vector. */ -BU_P9V_VSX_2 (VEXTRACT4B, "vextract4b", CONST, vextract4b) -BU_P9V_VSX_3 (VINSERT4B, "vinsert4b", CONST, vinsert4b) -BU_P9V_VSX_3 (VINSERT4B_DI, "vinsert4b_di", CONST, vinsert4b_di) +BU_P9V_VSX_3 (INSERT4B, "insert4b", CONST, insert4b) +BU_P9V_VSX_2 (EXTRACT4B, "extract4b", CONST, extract4b) /* Hardware IEEE 128-bit floating point round to odd instrucitons added in ISA 3.0 (power9). */ @@ -2290,12 +2300,12 @@ BU_P9V_OVERLOAD_2 (LXVL, "lxvl") BU_P9V_OVERLOAD_2 (XL_LEN_R, "xl_len_r") BU_P9V_OVERLOAD_2 (VEXTULX, "vextulx") BU_P9V_OVERLOAD_2 (VEXTURX, "vexturx") -BU_P9V_OVERLOAD_2 (VEXTRACT4B, "vextract4b") +BU_P9V_OVERLOAD_2 (EXTRACT4B, "extract4b") /* ISA 3.0 Vector scalar overloaded 3 argument functions */ BU_P9V_OVERLOAD_3 (STXVL, "stxvl") BU_P9V_OVERLOAD_3 (XST_LEN_R, "xst_len_r") -BU_P9V_OVERLOAD_3 (VINSERT4B, "vinsert4b") +BU_P9V_OVERLOAD_3 (INSERT4B, "insert4b") /* Overloaded CMPNE support was implemented prior to Power 9, so is not mentioned here. */ diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c index a68be511c40..cc8e4e1b569 100644 --- a/gcc/config/rs6000/rs6000-c.c +++ b/gcc/config/rs6000/rs6000-c.c @@ -1542,11 +1542,11 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_V4SF, RS6000_BTI_V4SI, 0, 0 }, { VSX_BUILTIN_VEC_FLOAT, VSX_BUILTIN_XVCVUXWSP_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, 0, 0 }, - { VSX_BUILTIN_VEC_FLOAT2, VSX_BUILTIN_FLOAT2_V2DF, + { P8V_BUILTIN_VEC_FLOAT2, P8V_BUILTIN_FLOAT2_V2DF, RS6000_BTI_V4SF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, - { VSX_BUILTIN_VEC_FLOAT2, VSX_BUILTIN_FLOAT2_V2DI, + { P8V_BUILTIN_VEC_FLOAT2, P8V_BUILTIN_FLOAT2_V2DI, RS6000_BTI_V4SF, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, - { VSX_BUILTIN_VEC_FLOAT2, VSX_BUILTIN_UNS_FLOAT2_V2DI, + { P8V_BUILTIN_VEC_FLOAT2, P8V_BUILTIN_UNS_FLOAT2_V2DI, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, { VSX_BUILTIN_VEC_FLOATE, VSX_BUILTIN_FLOATE_V2DF, @@ -2291,19 +2291,6 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { { ALTIVEC_BUILTIN_VEC_NEARBYINT, VSX_BUILTIN_XVRSPI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_NEG, ALTIVEC_BUILTIN_NEG_V16QI, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_NEG, ALTIVEC_BUILTIN_NEG_V8HI, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_NEG, ALTIVEC_BUILTIN_NEG_V4SI, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_NEG, ALTIVEC_BUILTIN_NEG_V2DI, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_NEG, ALTIVEC_BUILTIN_NEG_V4SF, - RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_NEG, ALTIVEC_BUILTIN_NEG_V2DF, - RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, @@ -2429,6 +2416,19 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_VPKUDUM, RS6000_BTI_V4SF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, + { P8V_BUILTIN_VEC_NEG, P8V_BUILTIN_NEG_V16QI, + RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, + { P8V_BUILTIN_VEC_NEG, P8V_BUILTIN_NEG_V8HI, + RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 }, + { P8V_BUILTIN_VEC_NEG, P8V_BUILTIN_NEG_V4SI, + RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 }, + { P8V_BUILTIN_VEC_NEG, P8V_BUILTIN_NEG_V2DI, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 }, + { P8V_BUILTIN_VEC_NEG, P8V_BUILTIN_NEG_V4SF, + RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, + { P8V_BUILTIN_VEC_NEG, P8V_BUILTIN_NEG_V2DF, + RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, + { P9V_BUILTIN_VEC_CONVERT_4F32_8I16, P9V_BUILTIN_CONVERT_4F32_8I16, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, @@ -3656,60 +3656,61 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI }, { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_4SF, - RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_NOT_OPAQUE }, + RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_INTSI }, { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_4SI, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_NOT_OPAQUE }, + RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI }, { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_4SI, - RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_NOT_OPAQUE }, + RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI }, { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_4SI, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_NOT_OPAQUE }, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI }, { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_8HI, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_NOT_OPAQUE }, + RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_INTSI }, { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_8HI, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_NOT_OPAQUE }, + RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI }, { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_8HI, - RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_NOT_OPAQUE }, + RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI }, { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_8HI, - RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_NOT_OPAQUE }, + RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI }, { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_16QI, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_NOT_OPAQUE }, + RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_INTSI }, { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_16QI, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_NOT_OPAQUE }, + RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI }, { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_16QI, - RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_NOT_OPAQUE }, + RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI }, { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_2DF, - RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_NOT_OPAQUE }, + RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_INTSI }, { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_2DI, - RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_NOT_OPAQUE }, + RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI }, { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_2DI, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_NOT_OPAQUE }, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_INTSI }, { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_2DI, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_NOT_OPAQUE }, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI }, { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, - RS6000_BTI_NOT_OPAQUE }, + RS6000_BTI_INTSI }, { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_NOT_OPAQUE }, + RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI }, { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, - RS6000_BTI_NOT_OPAQUE }, + RS6000_BTI_INTSI }, { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_NOT_OPAQUE }, + RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI }, { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, - RS6000_BTI_NOT_OPAQUE }, + RS6000_BTI_INTSI }, { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_NOT_OPAQUE }, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI }, { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, - RS6000_BTI_NOT_OPAQUE }, + RS6000_BTI_INTSI }, { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_NOT_OPAQUE }, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI }, + { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DF, RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF }, { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI, @@ -4154,53 +4155,54 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_16QI, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_NOT_OPAQUE }, + RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_INTSI }, { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, - RS6000_BTI_NOT_OPAQUE }, + RS6000_BTI_INTSI }, { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_8HI, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_NOT_OPAQUE }, + RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_INTSI }, { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, - RS6000_BTI_NOT_OPAQUE }, + RS6000_BTI_INTSI }, { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_4SI, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_NOT_OPAQUE }, + RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI }, { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, - RS6000_BTI_NOT_OPAQUE }, + RS6000_BTI_INTSI }, { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_2DI, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_NOT_OPAQUE }, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_INTSI }, { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, - RS6000_BTI_NOT_OPAQUE }, + RS6000_BTI_INTSI }, { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_4SF, - RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_NOT_OPAQUE }, + RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_INTSI }, { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_2DF, - RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_NOT_OPAQUE }, + RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_INTSI }, + { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_2DF, - RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_NOT_OPAQUE }, + RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_INTSI }, { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_2DI, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_NOT_OPAQUE }, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_INTSI }, { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, - RS6000_BTI_NOT_OPAQUE }, + RS6000_BTI_INTSI }, { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_4SF, - RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_NOT_OPAQUE }, + RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_INTSI }, { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_4SI, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_NOT_OPAQUE }, + RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI }, { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, - RS6000_BTI_NOT_OPAQUE }, + RS6000_BTI_INTSI }, { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_8HI, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_NOT_OPAQUE }, + RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_INTSI }, { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, - RS6000_BTI_NOT_OPAQUE }, + RS6000_BTI_INTSI }, { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_16QI, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_NOT_OPAQUE }, + RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_INTSI }, { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, - RS6000_BTI_NOT_OPAQUE }, + RS6000_BTI_INTSI }, { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DF, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 }, @@ -5429,10 +5431,8 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { { P9V_BUILTIN_VEC_VCTZLSBB, P9V_BUILTIN_VCTZLSBB_V4SI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, 0, 0 }, - { P9V_BUILTIN_VEC_VEXTRACT4B, P9V_BUILTIN_VEXTRACT4B, - RS6000_BTI_INTDI, RS6000_BTI_V16QI, RS6000_BTI_UINTSI, 0 }, - { P9V_BUILTIN_VEC_VEXTRACT4B, P9V_BUILTIN_VEXTRACT4B, - RS6000_BTI_INTDI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTSI, 0 }, + { P9V_BUILTIN_VEC_EXTRACT4B, P9V_BUILTIN_EXTRACT4B, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, 0 }, { P9V_BUILTIN_VEC_VEXTRACT_FP_FROM_SHORTH, P9V_BUILTIN_VEXTRACT_FP_FROM_SHORTH, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V8HI, 0, 0 }, @@ -5492,27 +5492,12 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 }, - { P9V_BUILTIN_VEC_VINSERT4B, P9V_BUILTIN_VINSERT4B, - RS6000_BTI_V16QI, RS6000_BTI_V4SI, - RS6000_BTI_V16QI, RS6000_BTI_UINTSI }, - { P9V_BUILTIN_VEC_VINSERT4B, P9V_BUILTIN_VINSERT4B, - RS6000_BTI_V16QI, RS6000_BTI_unsigned_V4SI, - RS6000_BTI_V16QI, RS6000_BTI_UINTSI }, - { P9V_BUILTIN_VEC_VINSERT4B, P9V_BUILTIN_VINSERT4B, + { P9V_BUILTIN_VEC_INSERT4B, P9V_BUILTIN_INSERT4B, + RS6000_BTI_unsigned_V16QI, RS6000_BTI_V4SI, + RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI }, + { P9V_BUILTIN_VEC_INSERT4B, P9V_BUILTIN_INSERT4B, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTSI }, - { P9V_BUILTIN_VEC_VINSERT4B, P9V_BUILTIN_VINSERT4B_DI, - RS6000_BTI_V16QI, RS6000_BTI_INTDI, - RS6000_BTI_V16QI, RS6000_BTI_UINTDI }, - { P9V_BUILTIN_VEC_VINSERT4B, P9V_BUILTIN_VINSERT4B_DI, - RS6000_BTI_V16QI, RS6000_BTI_UINTDI, - RS6000_BTI_V16QI, RS6000_BTI_UINTDI }, - { P9V_BUILTIN_VEC_VINSERT4B, P9V_BUILTIN_VINSERT4B_DI, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTDI, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTDI }, - { P9V_BUILTIN_VEC_VINSERT4B, P9V_BUILTIN_VINSERT4B_DI, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTDI, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTDI }, + RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI }, { P8V_BUILTIN_VEC_VADDECUQ, P8V_BUILTIN_VADDECUQ, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI }, @@ -5891,7 +5876,7 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_V4SI, RS6000_BTI_V2DF, 0, 0 }, { VSX_BUILTIN_VEC_VSIGNEDO, VSX_BUILTIN_VEC_VSIGNEDO_V2DF, RS6000_BTI_V4SI, RS6000_BTI_V2DF, 0, 0 }, - { VSX_BUILTIN_VEC_VSIGNED2, VSX_BUILTIN_VEC_VSIGNED2_V2DF, + { P8V_BUILTIN_VEC_VSIGNED2, P8V_BUILTIN_VEC_VSIGNED2_V2DF, RS6000_BTI_V4SI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, { VSX_BUILTIN_VEC_VUNSIGNED, VSX_BUILTIN_VEC_VUNSIGNED_V4SF, @@ -5902,7 +5887,7 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DF, 0, 0 }, { VSX_BUILTIN_VEC_VUNSIGNEDO, VSX_BUILTIN_VEC_VUNSIGNEDO_V2DF, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DF, 0, 0 }, - { VSX_BUILTIN_VEC_VUNSIGNED2, VSX_BUILTIN_VEC_VUNSIGNED2_V2DF, + { P8V_BUILTIN_VEC_VUNSIGNED2, P8V_BUILTIN_VEC_VUNSIGNED2_V2DF, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 6a6801aad9b..d0de4b5224d 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -4028,6 +4028,13 @@ rs6000_option_override_internal (bool global_init_p) if (global_init_p) rs6000_isa_flags_explicit = global_options_set.x_rs6000_isa_flags; + /* We plan to deprecate the -maltivec=be option. For now, just + issue a warning message. */ + if (global_init_p + && rs6000_altivec_element_order == 2) + warning (0, "%qs command-line option is deprecated", + "-maltivec=be"); + /* On 64-bit Darwin, power alignment is ABI-incompatible with some C library functions, so warn about it. The flag may be useful for performance studies from time to time though, so don't disable it @@ -4813,25 +4820,6 @@ rs6000_option_override_internal (bool global_init_p) if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET) rs6000_print_isa_options (stderr, 0, "after subtarget", rs6000_isa_flags); - /* For the E500 family of cores, reset the single/double FP flags to let us - check that they remain constant across attributes or pragmas. */ - - switch (rs6000_cpu) - { - case PROCESSOR_PPC8540: - case PROCESSOR_PPC8548: - case PROCESSOR_PPCE500MC: - case PROCESSOR_PPCE500MC64: - case PROCESSOR_PPCE5500: - case PROCESSOR_PPCE6500: - rs6000_single_float = 0; - rs6000_double_float = 0; - break; - - default: - break; - } - if (main_target_opt) { if (main_target_opt->x_rs6000_single_float != rs6000_single_float) @@ -8220,6 +8208,12 @@ mem_operand_gpr (rtx op, machine_mode mode) int extra; rtx addr = XEXP (op, 0); + /* Don't allow altivec type addresses like (mem (and (plus ...))). + See PR target/84279. */ + + if (GET_CODE (addr) == AND) + return false; + op = address_offset (addr); if (op == NULL_RTX) return true; @@ -15728,8 +15722,7 @@ altivec_expand_builtin (tree exp, rtx target, bool *expandedp) case VSX_BUILTIN_VEC_EXT_V1TI: return altivec_expand_vec_ext_builtin (exp, target); - case P9V_BUILTIN_VEXTRACT4B: - case P9V_BUILTIN_VEC_VEXTRACT4B: + case P9V_BUILTIN_VEC_EXTRACT4B: arg1 = CALL_EXPR_ARG (exp, 1); STRIP_NOPS (arg1); @@ -15744,9 +15737,7 @@ altivec_expand_builtin (tree exp, rtx target, bool *expandedp) } break; - case P9V_BUILTIN_VINSERT4B: - case P9V_BUILTIN_VINSERT4B_DI: - case P9V_BUILTIN_VEC_VINSERT4B: + case P9V_BUILTIN_VEC_INSERT4B: arg2 = CALL_EXPR_ARG (exp, 2); STRIP_NOPS (arg2); diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 5f44d80ef0e..0976d50d845 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -1576,12 +1576,12 @@ "dlmzb. %0,%1,%2") (define_expand "strlensi" - [(set (match_operand:SI 0 "gpc_reg_operand" "") - (unspec:SI [(match_operand:BLK 1 "general_operand" "") - (match_operand:QI 2 "const_int_operand" "") - (match_operand 3 "const_int_operand" "")] + [(set (match_operand:SI 0 "gpc_reg_operand") + (unspec:SI [(match_operand:BLK 1 "general_operand") + (match_operand:QI 2 "const_int_operand") + (match_operand 3 "const_int_operand")] UNSPEC_DLMZB_STRLEN)) - (clobber (match_scratch:CC 4 "=x"))] + (clobber (match_scratch:CC 4))] "TARGET_DLMZB && WORDS_BIG_ENDIAN && !optimize_size" { rtx result = operands[0]; @@ -1630,9 +1630,9 @@ ;; Fixed-point arithmetic insns. (define_expand "add<mode>3" - [(set (match_operand:SDI 0 "gpc_reg_operand" "") - (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "") - (match_operand:SDI 2 "reg_or_add_cint_operand" "")))] + [(set (match_operand:SDI 0 "gpc_reg_operand") + (plus:SDI (match_operand:SDI 1 "gpc_reg_operand") + (match_operand:SDI 2 "reg_or_add_cint_operand")))] "" { if (<MODE>mode == DImode && !TARGET_POWERPC64) @@ -1805,9 +1805,9 @@ ;; add should be last in case the result gets used in an address. (define_split - [(set (match_operand:GPR 0 "gpc_reg_operand" "") - (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "") - (match_operand:GPR 2 "non_add_cint_operand" "")))] + [(set (match_operand:GPR 0 "gpc_reg_operand") + (plus:GPR (match_operand:GPR 1 "gpc_reg_operand") + (match_operand:GPR 2 "non_add_cint_operand")))] "" [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3))) (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))] @@ -1950,8 +1950,8 @@ (define_expand "one_cmpl<mode>2" - [(set (match_operand:SDI 0 "gpc_reg_operand" "") - (not:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))] + [(set (match_operand:SDI 0 "gpc_reg_operand") + (not:SDI (match_operand:SDI 1 "gpc_reg_operand")))] "" { if (<MODE>mode == DImode && !TARGET_POWERPC64) @@ -2010,9 +2010,9 @@ (define_expand "sub<mode>3" - [(set (match_operand:SDI 0 "gpc_reg_operand" "") - (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "") - (match_operand:SDI 2 "gpc_reg_operand" "")))] + [(set (match_operand:SDI 0 "gpc_reg_operand") + (minus:SDI (match_operand:SDI 1 "reg_or_short_operand") + (match_operand:SDI 2 "gpc_reg_operand")))] "" { if (<MODE>mode == DImode && !TARGET_POWERPC64) @@ -2338,8 +2338,8 @@ (define_expand "popcount<mode>2" - [(set (match_operand:GPR 0 "gpc_reg_operand" "") - (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))] + [(set (match_operand:GPR 0 "gpc_reg_operand") + (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand")))] "TARGET_POPCNTB || TARGET_POPCNTD" { rs6000_emit_popcount (operands[0], operands[1]); @@ -2363,8 +2363,8 @@ (define_expand "parity<mode>2" - [(set (match_operand:GPR 0 "gpc_reg_operand" "") - (parity:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))] + [(set (match_operand:GPR 0 "gpc_reg_operand") + (parity:GPR (match_operand:GPR 1 "gpc_reg_operand")))] "TARGET_POPCNTB" { rs6000_emit_parity (operands[0], operands[1]); @@ -2508,11 +2508,11 @@ ;; complex code. (define_expand "bswapdi2" - [(parallel [(set (match_operand:DI 0 "reg_or_mem_operand" "") + [(parallel [(set (match_operand:DI 0 "reg_or_mem_operand") (bswap:DI - (match_operand:DI 1 "reg_or_mem_operand" ""))) - (clobber (match_scratch:DI 2 "")) - (clobber (match_scratch:DI 3 ""))])] + (match_operand:DI 1 "reg_or_mem_operand"))) + (clobber (match_scratch:DI 2)) + (clobber (match_scratch:DI 3))])] "" { rtx dest = operands[0]; @@ -2589,13 +2589,12 @@ [(set_attr "length" "16,12,36")]) (define_split - [(set (match_operand:DI 0 "gpc_reg_operand" "") - (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" ""))) - (clobber (match_operand:DI 2 "gpc_reg_operand" "")) - (clobber (match_operand:DI 3 "gpc_reg_operand" ""))] + [(set (match_operand:DI 0 "gpc_reg_operand") + (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand"))) + (clobber (match_operand:DI 2 "gpc_reg_operand")) + (clobber (match_operand:DI 3 "gpc_reg_operand"))] "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed" [(const_int 0)] - " { rtx dest = operands[0]; rtx src = operands[1]; @@ -2650,16 +2649,15 @@ emit_insn (gen_ashldi3 (op3, op3, GEN_INT (32))); emit_insn (gen_iordi3 (dest, dest, op3)); DONE; -}") +}) (define_split - [(set (match_operand:DI 0 "indexed_or_indirect_operand" "") - (bswap:DI (match_operand:DI 1 "gpc_reg_operand" ""))) - (clobber (match_operand:DI 2 "gpc_reg_operand" "")) - (clobber (match_operand:DI 3 "gpc_reg_operand" ""))] + [(set (match_operand:DI 0 "indexed_or_indirect_operand") + (bswap:DI (match_operand:DI 1 "gpc_reg_operand"))) + (clobber (match_operand:DI 2 "gpc_reg_operand")) + (clobber (match_operand:DI 3 "gpc_reg_operand"))] "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed" [(const_int 0)] - " { rtx dest = operands[0]; rtx src = operands[1]; @@ -2713,16 +2711,15 @@ emit_insn (gen_bswapsi2 (word1, op3_si)); } DONE; -}") +}) (define_split - [(set (match_operand:DI 0 "gpc_reg_operand" "") - (bswap:DI (match_operand:DI 1 "gpc_reg_operand" ""))) - (clobber (match_operand:DI 2 "gpc_reg_operand" "")) - (clobber (match_operand:DI 3 "gpc_reg_operand" ""))] + [(set (match_operand:DI 0 "gpc_reg_operand") + (bswap:DI (match_operand:DI 1 "gpc_reg_operand"))) + (clobber (match_operand:DI 2 "gpc_reg_operand")) + (clobber (match_operand:DI 3 "gpc_reg_operand"))] "TARGET_POWERPC64 && !TARGET_P9_VECTOR && reload_completed" [(const_int 0)] - " { rtx dest = operands[0]; rtx src = operands[1]; @@ -2740,7 +2737,7 @@ emit_insn (gen_ashldi3 (dest, dest, GEN_INT (32))); emit_insn (gen_iordi3 (dest, dest, op3)); DONE; -}") +}) (define_insn "bswapdi2_32bit" [(set (match_operand:DI 0 "reg_or_mem_operand" "=r,Z,?&r") @@ -2751,12 +2748,11 @@ [(set_attr "length" "16,12,36")]) (define_split - [(set (match_operand:DI 0 "gpc_reg_operand" "") - (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" ""))) - (clobber (match_operand:SI 2 "gpc_reg_operand" ""))] + [(set (match_operand:DI 0 "gpc_reg_operand") + (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand"))) + (clobber (match_operand:SI 2 "gpc_reg_operand"))] "!TARGET_POWERPC64 && reload_completed" [(const_int 0)] - " { rtx dest = operands[0]; rtx src = operands[1]; @@ -2801,15 +2797,14 @@ thus allowing us to omit an early clobber on the output. */ emit_insn (gen_bswapsi2 (dest1, word2)); DONE; -}") +}) (define_split - [(set (match_operand:DI 0 "indexed_or_indirect_operand" "") - (bswap:DI (match_operand:DI 1 "gpc_reg_operand" ""))) - (clobber (match_operand:SI 2 "gpc_reg_operand" ""))] + [(set (match_operand:DI 0 "indexed_or_indirect_operand") + (bswap:DI (match_operand:DI 1 "gpc_reg_operand"))) + (clobber (match_operand:SI 2 "gpc_reg_operand"))] "!TARGET_POWERPC64 && reload_completed" [(const_int 0)] - " { rtx dest = operands[0]; rtx src = operands[1]; @@ -2850,15 +2845,14 @@ emit_insn (gen_bswapsi2 (word2, src1)); emit_insn (gen_bswapsi2 (word1, src2)); DONE; -}") +}) (define_split - [(set (match_operand:DI 0 "gpc_reg_operand" "") - (bswap:DI (match_operand:DI 1 "gpc_reg_operand" ""))) - (clobber (match_operand:SI 2 "" ""))] + [(set (match_operand:DI 0 "gpc_reg_operand") + (bswap:DI (match_operand:DI 1 "gpc_reg_operand"))) + (clobber (match_operand:SI 2 ""))] "!TARGET_POWERPC64 && reload_completed" [(const_int 0)] - " { rtx dest = operands[0]; rtx src = operands[1]; @@ -2870,7 +2864,7 @@ emit_insn (gen_bswapsi2 (dest1, src2)); emit_insn (gen_bswapsi2 (dest2, src1)); DONE; -}") +}) (define_insn "mul<mode>3" @@ -2883,9 +2877,9 @@ mulli %0,%1,%2" [(set_attr "type" "mul") (set (attr "size") - (cond [(match_operand:GPR 2 "s8bit_cint_operand" "") + (cond [(match_operand:GPR 2 "s8bit_cint_operand") (const_string "8") - (match_operand:GPR 2 "short_cint_operand" "") + (match_operand:GPR 2 "short_cint_operand") (const_string "16")] (const_string "<bits>")))]) @@ -3054,9 +3048,9 @@ ;; modulus. If it isn't a power of two, force operands into register and do ;; a normal divide. (define_expand "div<mode>3" - [(set (match_operand:GPR 0 "gpc_reg_operand" "") - (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "") - (match_operand:GPR 2 "reg_or_cint_operand" "")))] + [(set (match_operand:GPR 0 "gpc_reg_operand") + (div:GPR (match_operand:GPR 1 "gpc_reg_operand") + (match_operand:GPR 2 "reg_or_cint_operand")))] "" { if (CONST_INT_P (operands[2]) @@ -3196,10 +3190,10 @@ ;; after a divide. (define_peephole2 - [(set (match_operand:GPR 0 "gpc_reg_operand" "") - (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "") - (match_operand:GPR 2 "gpc_reg_operand" ""))) - (set (match_operand:GPR 3 "gpc_reg_operand" "") + [(set (match_operand:GPR 0 "gpc_reg_operand") + (div:GPR (match_operand:GPR 1 "gpc_reg_operand") + (match_operand:GPR 2 "gpc_reg_operand"))) + (set (match_operand:GPR 3 "gpc_reg_operand") (mod:GPR (match_dup 1) (match_dup 2)))] "TARGET_MODULO @@ -3218,10 +3212,10 @@ (match_dup 3)))]) (define_peephole2 - [(set (match_operand:GPR 0 "gpc_reg_operand" "") - (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "") - (match_operand:GPR 2 "gpc_reg_operand" ""))) - (set (match_operand:GPR 3 "gpc_reg_operand" "") + [(set (match_operand:GPR 0 "gpc_reg_operand") + (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand") + (match_operand:GPR 2 "gpc_reg_operand"))) + (set (match_operand:GPR 3 "gpc_reg_operand") (umod:GPR (match_dup 1) (match_dup 2)))] "TARGET_MODULO @@ -3247,9 +3241,9 @@ ;; those rotate-and-mask operations. Thus, the AND insns come first. (define_expand "and<mode>3" - [(set (match_operand:SDI 0 "gpc_reg_operand" "") - (and:SDI (match_operand:SDI 1 "gpc_reg_operand" "") - (match_operand:SDI 2 "reg_or_cint_operand" "")))] + [(set (match_operand:SDI 0 "gpc_reg_operand") + (and:SDI (match_operand:SDI 1 "gpc_reg_operand") + (match_operand:SDI 2 "reg_or_cint_operand")))] "" { if (<MODE>mode == DImode && !TARGET_POWERPC64) @@ -3545,9 +3539,9 @@ (define_expand "<code><mode>3" - [(set (match_operand:SDI 0 "gpc_reg_operand" "") - (iorxor:SDI (match_operand:SDI 1 "gpc_reg_operand" "") - (match_operand:SDI 2 "reg_or_cint_operand" "")))] + [(set (match_operand:SDI 0 "gpc_reg_operand") + (iorxor:SDI (match_operand:SDI 1 "gpc_reg_operand") + (match_operand:SDI 2 "reg_or_cint_operand")))] "" { if (<MODE>mode == DImode && !TARGET_POWERPC64) @@ -3576,9 +3570,9 @@ }) (define_split - [(set (match_operand:GPR 0 "gpc_reg_operand" "") - (iorxor:GPR (match_operand:GPR 1 "gpc_reg_operand" "") - (match_operand:GPR 2 "non_logical_cint_operand" "")))] + [(set (match_operand:GPR 0 "gpc_reg_operand") + (iorxor:GPR (match_operand:GPR 1 "gpc_reg_operand") + (match_operand:GPR 2 "non_logical_cint_operand")))] "" [(set (match_dup 3) (iorxor:GPR (match_dup 1) @@ -4479,9 +4473,9 @@ ;; Builtins to replace a division to generate FRE reciprocal estimate ;; instructions and the necessary fixup instructions (define_expand "recip<mode>3" - [(match_operand:RECIPF 0 "gpc_reg_operand" "") - (match_operand:RECIPF 1 "gpc_reg_operand" "") - (match_operand:RECIPF 2 "gpc_reg_operand" "")] + [(match_operand:RECIPF 0 "gpc_reg_operand") + (match_operand:RECIPF 1 "gpc_reg_operand") + (match_operand:RECIPF 2 "gpc_reg_operand")] "RS6000_RECIP_HAVE_RE_P (<MODE>mode)" { rs6000_emit_swdiv (operands[0], operands[1], operands[2], false); @@ -4494,9 +4488,9 @@ ;; We used to also check optimize_insn_for_speed_p () but problems with guessed ;; frequencies (pr68212/pr77536) yields that unreliable so it was removed. (define_split - [(set (match_operand:RECIPF 0 "gpc_reg_operand" "") - (div:RECIPF (match_operand 1 "gpc_reg_operand" "") - (match_operand 2 "gpc_reg_operand" "")))] + [(set (match_operand:RECIPF 0 "gpc_reg_operand") + (div:RECIPF (match_operand 1 "gpc_reg_operand") + (match_operand 2 "gpc_reg_operand")))] "RS6000_RECIP_AUTO_RE_P (<MODE>mode) && can_create_pseudo_p () && flag_finite_math_only && !flag_trapping_math && flag_reciprocal_math" @@ -4509,8 +4503,8 @@ ;; Builtins to replace 1/sqrt(x) with instructions using RSQRTE and the ;; appropriate fixup. (define_expand "rsqrt<mode>2" - [(match_operand:RECIPF 0 "gpc_reg_operand" "") - (match_operand:RECIPF 1 "gpc_reg_operand" "")] + [(match_operand:RECIPF 0 "gpc_reg_operand") + (match_operand:RECIPF 1 "gpc_reg_operand")] "RS6000_RECIP_HAVE_RSQRTE_P (<MODE>mode)" { rs6000_emit_swsqrt (operands[0], operands[1], 1); @@ -4523,8 +4517,8 @@ ;; -mupper-regs-{df,sf} option is enabled. (define_expand "abs<mode>2" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "") - (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))] + [(set (match_operand:SFDF 0 "gpc_reg_operand") + (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand")))] "TARGET_<MODE>_INSN" "") @@ -4551,8 +4545,8 @@ (set_attr "fp_type" "fp_addsub_<Fs>")]) (define_expand "neg<mode>2" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "") - (neg:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))] + [(set (match_operand:SFDF 0 "gpc_reg_operand") + (neg:SFDF (match_operand:SFDF 1 "gpc_reg_operand")))] "TARGET_<MODE>_INSN" "") @@ -4567,9 +4561,9 @@ (set_attr "fp_type" "fp_addsub_<Fs>")]) (define_expand "add<mode>3" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "") - (plus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "") - (match_operand:SFDF 2 "gpc_reg_operand" "")))] + [(set (match_operand:SFDF 0 "gpc_reg_operand") + (plus:SFDF (match_operand:SFDF 1 "gpc_reg_operand") + (match_operand:SFDF 2 "gpc_reg_operand")))] "TARGET_<MODE>_INSN" "") @@ -4585,9 +4579,9 @@ (set_attr "fp_type" "fp_addsub_<Fs>")]) (define_expand "sub<mode>3" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "") - (minus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "") - (match_operand:SFDF 2 "gpc_reg_operand" "")))] + [(set (match_operand:SFDF 0 "gpc_reg_operand") + (minus:SFDF (match_operand:SFDF 1 "gpc_reg_operand") + (match_operand:SFDF 2 "gpc_reg_operand")))] "TARGET_<MODE>_INSN" "") @@ -4603,9 +4597,9 @@ (set_attr "fp_type" "fp_addsub_<Fs>")]) (define_expand "mul<mode>3" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "") - (mult:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "") - (match_operand:SFDF 2 "gpc_reg_operand" "")))] + [(set (match_operand:SFDF 0 "gpc_reg_operand") + (mult:SFDF (match_operand:SFDF 1 "gpc_reg_operand") + (match_operand:SFDF 2 "gpc_reg_operand")))] "TARGET_<MODE>_INSN" "") @@ -4621,9 +4615,9 @@ (set_attr "fp_type" "fp_mul_<Fs>")]) (define_expand "div<mode>3" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "") - (div:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "") - (match_operand:SFDF 2 "gpc_reg_operand" "")))] + [(set (match_operand:SFDF 0 "gpc_reg_operand") + (div:SFDF (match_operand:SFDF 1 "gpc_reg_operand") + (match_operand:SFDF 2 "gpc_reg_operand")))] "TARGET_<MODE>_INSN && !TARGET_SIMPLE_FPU" { if (RS6000_RECIP_AUTO_RE_P (<MODE>mode) @@ -4658,8 +4652,8 @@ (set_attr "fp_type" "fp_sqrt_<Fs>")]) (define_expand "sqrt<mode>2" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "") - (sqrt:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))] + [(set (match_operand:SFDF 0 "gpc_reg_operand") + (sqrt:SFDF (match_operand:SFDF 1 "gpc_reg_operand")))] "TARGET_<MODE>_FPR && !TARGET_SIMPLE_FPU && (TARGET_PPC_GPOPT || (<MODE>mode == SFmode && TARGET_XILINX_FPU))" { @@ -4747,8 +4741,8 @@ [(set_attr "type" "fp")]) (define_expand "truncdfsf2" - [(set (match_operand:SF 0 "gpc_reg_operand" "") - (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))] + [(set (match_operand:SF 0 "gpc_reg_operand") + (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand")))] "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" "") @@ -4766,12 +4760,12 @@ ;; when little-endian. (define_expand "signbit<mode>2" [(set (match_dup 2) - (float_truncate:DF (match_operand:FLOAT128 1 "gpc_reg_operand" ""))) + (float_truncate:DF (match_operand:FLOAT128 1 "gpc_reg_operand"))) (set (match_dup 3) (subreg:DI (match_dup 2) 0)) (set (match_dup 4) (match_dup 5)) - (set (match_operand:SI 0 "gpc_reg_operand" "") + (set (match_operand:SI 0 "gpc_reg_operand") (match_dup 6))] "TARGET_HARD_FLOAT && (!FLOAT128_IEEE_P (<MODE>mode) @@ -4874,11 +4868,11 @@ (define_expand "copysign<mode>3" [(set (match_dup 3) - (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" ""))) + (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand"))) (set (match_dup 4) (neg:SFDF (abs:SFDF (match_dup 1)))) - (set (match_operand:SFDF 0 "gpc_reg_operand" "") - (if_then_else:SFDF (ge (match_operand:SFDF 2 "gpc_reg_operand" "") + (set (match_operand:SFDF 0 "gpc_reg_operand") + (if_then_else:SFDF (ge (match_operand:SFDF 2 "gpc_reg_operand") (match_dup 5)) (match_dup 3) (match_dup 4)))] @@ -4928,9 +4922,9 @@ ;; to allow either DF/SF to use only traditional registers. (define_expand "s<minmax><mode>3" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "") - (fp_minmax:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "") - (match_operand:SFDF 2 "gpc_reg_operand" "")))] + [(set (match_operand:SFDF 0 "gpc_reg_operand") + (fp_minmax:SFDF (match_operand:SFDF 1 "gpc_reg_operand") + (match_operand:SFDF 2 "gpc_reg_operand")))] "TARGET_MINMAX_<MODE>" { rs6000_emit_minmax (operands[0], <SMINMAX>, operands[1], operands[2]); @@ -4954,9 +4948,9 @@ ;; instruction. (define_insn_and_split "*s<minmax><mode>3_fpr" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "") - (fp_minmax:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "") - (match_operand:SFDF 2 "gpc_reg_operand" "")))] + [(set (match_operand:SFDF 0 "gpc_reg_operand") + (fp_minmax:SFDF (match_operand:SFDF 1 "gpc_reg_operand") + (match_operand:SFDF 2 "gpc_reg_operand")))] "!TARGET_VSX && TARGET_MINMAX_<MODE>" "#" "&& 1" @@ -4967,18 +4961,17 @@ }) (define_expand "mov<mode>cc" - [(set (match_operand:GPR 0 "gpc_reg_operand" "") - (if_then_else:GPR (match_operand 1 "comparison_operator" "") - (match_operand:GPR 2 "gpc_reg_operand" "") - (match_operand:GPR 3 "gpc_reg_operand" "")))] + [(set (match_operand:GPR 0 "gpc_reg_operand") + (if_then_else:GPR (match_operand 1 "comparison_operator") + (match_operand:GPR 2 "gpc_reg_operand") + (match_operand:GPR 3 "gpc_reg_operand")))] "TARGET_ISEL" - " { if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3])) DONE; else FAIL; -}") +}) ;; We use the BASE_REGS for the isel input operands because, if rA is ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB @@ -5048,18 +5041,17 @@ ;; Floating point conditional move (define_expand "mov<mode>cc" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "") - (if_then_else:SFDF (match_operand 1 "comparison_operator" "") - (match_operand:SFDF 2 "gpc_reg_operand" "") - (match_operand:SFDF 3 "gpc_reg_operand" "")))] + [(set (match_operand:SFDF 0 "gpc_reg_operand") + (if_then_else:SFDF (match_operand 1 "comparison_operator") + (match_operand:SFDF 2 "gpc_reg_operand") + (match_operand:SFDF 3 "gpc_reg_operand")))] "TARGET_<MODE>_FPR && TARGET_PPC_GFXOPT" - " { if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3])) DONE; else FAIL; -}") +}) (define_insn "*fsel<SFDF:mode><SFDF2:mode>4" [(set (match_operand:SFDF 0 "gpc_reg_operand" "=&<SFDF:rreg2>") @@ -5193,7 +5185,6 @@ "#" "" [(pc)] - " { rtx dest = operands[0]; rtx src = operands[1]; @@ -5221,7 +5212,7 @@ } emit_insn (gen_floatdi<mode>2 (dest, tmp)); DONE; -}" +} [(set_attr "length" "12") (set_attr "type" "fpload")]) @@ -5235,7 +5226,6 @@ "#" "" [(pc)] - " { operands[1] = rs6000_address_for_fpconvert (operands[1]); if (GET_CODE (operands[2]) == SCRATCH) @@ -5246,7 +5236,7 @@ emit_insn (gen_lfiwax (operands[2], operands[1])); emit_insn (gen_floatdi<mode>2 (operands[0], operands[2])); DONE; -}" +} [(set_attr "length" "8") (set_attr "type" "fpload")]) @@ -5270,7 +5260,6 @@ "#" "" [(pc)] - " { rtx dest = operands[0]; rtx src = operands[1]; @@ -5298,7 +5287,7 @@ } emit_insn (gen_floatdi<mode>2 (dest, tmp)); DONE; -}" +} [(set_attr "length" "12") (set_attr "type" "fpload")]) @@ -5312,7 +5301,6 @@ "#" "" [(pc)] - " { operands[1] = rs6000_address_for_fpconvert (operands[1]); if (GET_CODE (operands[2]) == SCRATCH) @@ -5323,7 +5311,7 @@ emit_insn (gen_lfiwzx (operands[2], operands[1])); emit_insn (gen_floatdi<mode>2 (operands[0], operands[2])); DONE; -}" +} [(set_attr "length" "8") (set_attr "type" "fpload")]) @@ -5333,15 +5321,14 @@ ; then to have the insns split later (between sched1 and final). (define_expand "floatsidf2" - [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "") - (float:DF (match_operand:SI 1 "nonimmediate_operand" ""))) + [(parallel [(set (match_operand:DF 0 "gpc_reg_operand") + (float:DF (match_operand:SI 1 "nonimmediate_operand"))) (use (match_dup 2)) (use (match_dup 3)) (clobber (match_dup 4)) (clobber (match_dup 5)) (clobber (match_dup 6))])] "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" - " { if (TARGET_LFIWAX && TARGET_FCFID) { @@ -5365,7 +5352,7 @@ operands[4] = rs6000_allocate_stack_temp (DFmode, true, false); operands[5] = gen_reg_rtx (DFmode); operands[6] = gen_reg_rtx (SImode); -}") +}) (define_insn_and_split "*floatsidf2_internal" [(set (match_operand:DF 0 "gpc_reg_operand" "=&d") @@ -5379,7 +5366,6 @@ "#" "" [(pc)] - " { rtx lowword, highword; gcc_assert (MEM_P (operands[4])); @@ -5395,7 +5381,7 @@ emit_move_insn (operands[5], operands[4]); emit_insn (gen_subdf3 (operands[0], operands[5], operands[3])); DONE; -}" +} [(set_attr "length" "24") (set_attr "type" "fp")]) @@ -5403,13 +5389,12 @@ ;; conversion for 32-bit without fast math, because we don't have the insn to ;; generate the fixup swizzle to avoid double rounding problems. (define_expand "floatunssisf2" - [(set (match_operand:SF 0 "gpc_reg_operand" "") - (unsigned_float:SF (match_operand:SI 1 "nonimmediate_operand" "")))] + [(set (match_operand:SF 0 "gpc_reg_operand") + (unsigned_float:SF (match_operand:SI 1 "nonimmediate_operand")))] "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT && ((TARGET_FCFIDUS && TARGET_LFIWZX) || (TARGET_DOUBLE_FLOAT && TARGET_FCFID && (TARGET_POWERPC64 || flag_unsafe_math_optimizations)))" - " { if (TARGET_LFIWZX && TARGET_FCFIDUS) { @@ -5425,17 +5410,16 @@ emit_insn (gen_floatdisf2 (operands[0], dreg)); DONE; } -}") +}) (define_expand "floatunssidf2" - [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "") - (unsigned_float:DF (match_operand:SI 1 "nonimmediate_operand" ""))) + [(parallel [(set (match_operand:DF 0 "gpc_reg_operand") + (unsigned_float:DF (match_operand:SI 1 "nonimmediate_operand"))) (use (match_dup 2)) (use (match_dup 3)) (clobber (match_dup 4)) (clobber (match_dup 5))])] "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" - " { if (TARGET_LFIWZX && TARGET_FCFID) { @@ -5458,7 +5442,7 @@ operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode)); operands[4] = rs6000_allocate_stack_temp (DFmode, true, false); operands[5] = gen_reg_rtx (DFmode); -}") +}) (define_insn_and_split "*floatunssidf2_internal" [(set (match_operand:DF 0 "gpc_reg_operand" "=&d") @@ -5472,7 +5456,6 @@ "#" "" [(pc)] - " { rtx lowword, highword; gcc_assert (MEM_P (operands[4])); @@ -5486,7 +5469,7 @@ emit_move_insn (operands[5], operands[4]); emit_insn (gen_subdf3 (operands[0], operands[5], operands[3])); DONE; -}" +} [(set_attr "length" "20") (set_attr "type" "fp")]) @@ -5551,9 +5534,9 @@ (define_expand "floatuns<QHI:mode><FP_ISA3:mode>2" [(parallel [(set (match_operand:FP_ISA3 0 "vsx_register_operand") (unsigned_float:FP_ISA3 - (match_operand:QHI 1 "input_operand" ""))) - (clobber (match_scratch:DI 2 "")) - (clobber (match_scratch:DI 3 ""))])] + (match_operand:QHI 1 "input_operand"))) + (clobber (match_scratch:DI 2)) + (clobber (match_scratch:DI 3))])] "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE && TARGET_POWERPC64" { if (MEM_P (operands[1])) @@ -5594,10 +5577,9 @@ }) (define_expand "fix_trunc<mode>si2" - [(set (match_operand:SI 0 "gpc_reg_operand" "") - (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))] + [(set (match_operand:SI 0 "gpc_reg_operand") + (fix:SI (match_operand:SFDF 1 "gpc_reg_operand")))] "TARGET_HARD_FLOAT && <TARGET_FLOAT>" - " { if (!TARGET_P8_VECTOR) { @@ -5614,7 +5596,7 @@ } DONE; } -}") +}) ; Like the convert to float patterns, this insn must be split before ; register allocation so that it can allocate the memory slot if it @@ -5671,7 +5653,6 @@ "#" "" [(pc)] - " { rtx lowword; gcc_assert (MEM_P (operands[3])); @@ -5681,13 +5662,13 @@ emit_move_insn (operands[3], operands[2]); emit_move_insn (operands[0], lowword); DONE; -}" +} [(set_attr "length" "16") (set_attr "type" "fp")]) (define_expand "fix_trunc<mode>di2" - [(set (match_operand:DI 0 "gpc_reg_operand" "") - (fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "")))] + [(set (match_operand:DI 0 "gpc_reg_operand") + (fix:DI (match_operand:SFDF 1 "gpc_reg_operand")))] "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FCFID" "") @@ -5756,17 +5737,16 @@ }) (define_expand "fixuns_trunc<mode>si2" - [(set (match_operand:SI 0 "gpc_reg_operand" "") - (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))] + [(set (match_operand:SI 0 "gpc_reg_operand") + (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand")))] "TARGET_HARD_FLOAT && <TARGET_FLOAT> && TARGET_FCTIWUZ && TARGET_STFIWX" - " { if (!TARGET_P8_VECTOR) { emit_insn (gen_fixuns_trunc<mode>si2_stfiwx (operands[0], operands[1])); DONE; } -}") +}) (define_insn_and_split "fixuns_trunc<mode>si2_stfiwx" [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") @@ -6001,9 +5981,9 @@ (define_expand "lround<mode>di2" [(set (match_dup 2) - (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")] + (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand")] UNSPEC_XSRDPI)) - (set (match_operand:DI 0 "gpc_reg_operand" "") + (set (match_operand:DI 0 "gpc_reg_operand") (unspec:DI [(match_dup 2)] UNSPEC_FCTID))] "TARGET_<MODE>_FPR && TARGET_VSX" @@ -6028,13 +6008,12 @@ ;; conversion for 32-bit without fast math, because we don't have the insn to ;; generate the fixup swizzle to avoid double rounding problems. (define_expand "floatsisf2" - [(set (match_operand:SF 0 "gpc_reg_operand" "") - (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))] + [(set (match_operand:SF 0 "gpc_reg_operand") + (float:SF (match_operand:SI 1 "nonimmediate_operand")))] "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT && ((TARGET_FCFIDS && TARGET_LFIWAX) || (TARGET_DOUBLE_FLOAT && TARGET_FCFID && (TARGET_POWERPC64 || flag_unsafe_math_optimizations)))" - " { if (TARGET_FCFIDS && TARGET_LFIWAX) { @@ -6057,7 +6036,7 @@ emit_insn (gen_floatdisf2 (operands[0], dreg)); DONE; } -}") +}) (define_insn "floatdidf2" [(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws") @@ -6087,9 +6066,9 @@ (set_attr "type" "fpload")]) (define_expand "floatunsdidf2" - [(set (match_operand:DF 0 "gpc_reg_operand" "") + [(set (match_operand:DF 0 "gpc_reg_operand") (unsigned_float:DF - (match_operand:DI 1 "gpc_reg_operand" "")))] + (match_operand:DI 1 "gpc_reg_operand")))] "TARGET_HARD_FLOAT && TARGET_FCFIDU" "") @@ -6117,11 +6096,10 @@ (set_attr "type" "fpload")]) (define_expand "floatdisf2" - [(set (match_operand:SF 0 "gpc_reg_operand" "") - (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))] + [(set (match_operand:SF 0 "gpc_reg_operand") + (float:SF (match_operand:DI 1 "gpc_reg_operand")))] "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT && (TARGET_FCFIDS || TARGET_POWERPC64 || flag_unsafe_math_optimizations)" - " { if (!TARGET_FCFIDS) { @@ -6136,7 +6114,7 @@ emit_insn (gen_floatdisf2_internal1 (operands[0], val)); DONE; } -}") +}) (define_insn "floatdisf2_fcfids" [(set (match_operand:SF 0 "gpc_reg_operand" "=f,wy") @@ -6157,12 +6135,11 @@ "#" "&& reload_completed" [(pc)] - " { emit_move_insn (operands[2], operands[1]); emit_insn (gen_floatdisf2_fcfids (operands[0], operands[2])); DONE; -}" +} [(set_attr "length" "8")]) ;; This is not IEEE compliant if rounding mode is "round to nearest". @@ -6189,11 +6166,11 @@ ;; by a bit that won't be lost at that stage, but is below the SFmode ;; rounding position. (define_expand "floatdisf2_internal2" - [(parallel [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "") + [(parallel [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "") (const_int 53))) (clobber (reg:DI CA_REGNO))]) - (set (match_operand:DI 0 "" "") (and:DI (match_dup 1) - (const_int 2047))) + (set (match_operand:DI 0 "") (and:DI (match_dup 1) + (const_int 2047))) (set (match_dup 3) (plus:DI (match_dup 3) (const_int 1))) (set (match_dup 0) (plus:DI (match_dup 0) @@ -6205,20 +6182,19 @@ (set (match_dup 0) (and:DI (match_dup 0) (const_int -2048))) (set (pc) (if_then_else (geu (match_dup 4) (const_int 0)) - (label_ref (match_operand:DI 2 "" "")) + (label_ref (match_operand:DI 2 "")) (pc))) (set (match_dup 0) (match_dup 1))] "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT && !TARGET_FCFIDS" - " { operands[3] = gen_reg_rtx (DImode); operands[4] = gen_reg_rtx (CCUNSmode); -}") +}) (define_expand "floatunsdisf2" - [(set (match_operand:SF 0 "gpc_reg_operand" "") - (unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand" "")))] + [(set (match_operand:SF 0 "gpc_reg_operand") + (unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand")))] "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS" "") @@ -6242,12 +6218,11 @@ "#" "&& reload_completed" [(pc)] - " { emit_move_insn (operands[2], operands[1]); emit_insn (gen_floatunsdisf2_fcfidus (operands[0], operands[2])); DONE; -}" +} [(set_attr "length" "8") (set_attr "type" "fpload")]) @@ -6258,9 +6233,9 @@ ;; also allow for the output being the same as one of the inputs. (define_expand "addti3" - [(set (match_operand:TI 0 "gpc_reg_operand" "") - (plus:TI (match_operand:TI 1 "gpc_reg_operand" "") - (match_operand:TI 2 "reg_or_short_operand" "")))] + [(set (match_operand:TI 0 "gpc_reg_operand") + (plus:TI (match_operand:TI 1 "gpc_reg_operand") + (match_operand:TI 2 "reg_or_short_operand")))] "TARGET_64BIT" { rtx lo0 = gen_lowpart (DImode, operands[0]); @@ -6281,9 +6256,9 @@ }) (define_expand "subti3" - [(set (match_operand:TI 0 "gpc_reg_operand" "") - (minus:TI (match_operand:TI 1 "reg_or_short_operand" "") - (match_operand:TI 2 "gpc_reg_operand" "")))] + [(set (match_operand:TI 0 "gpc_reg_operand") + (minus:TI (match_operand:TI 1 "reg_or_short_operand") + (match_operand:TI 2 "gpc_reg_operand")))] "TARGET_64BIT" { rtx lo0 = gen_lowpart (DImode, operands[0]); @@ -6306,73 +6281,73 @@ ;; 128-bit logical operations expanders (define_expand "and<mode>3" - [(set (match_operand:BOOL_128 0 "vlogical_operand" "") - (and:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "") - (match_operand:BOOL_128 2 "vlogical_operand" "")))] + [(set (match_operand:BOOL_128 0 "vlogical_operand") + (and:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand") + (match_operand:BOOL_128 2 "vlogical_operand")))] "" "") (define_expand "ior<mode>3" - [(set (match_operand:BOOL_128 0 "vlogical_operand" "") - (ior:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "") - (match_operand:BOOL_128 2 "vlogical_operand" "")))] + [(set (match_operand:BOOL_128 0 "vlogical_operand") + (ior:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand") + (match_operand:BOOL_128 2 "vlogical_operand")))] "" "") (define_expand "xor<mode>3" - [(set (match_operand:BOOL_128 0 "vlogical_operand" "") - (xor:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "") - (match_operand:BOOL_128 2 "vlogical_operand" "")))] + [(set (match_operand:BOOL_128 0 "vlogical_operand") + (xor:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand") + (match_operand:BOOL_128 2 "vlogical_operand")))] "" "") (define_expand "one_cmpl<mode>2" - [(set (match_operand:BOOL_128 0 "vlogical_operand" "") - (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")))] + [(set (match_operand:BOOL_128 0 "vlogical_operand") + (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand")))] "" "") (define_expand "nor<mode>3" - [(set (match_operand:BOOL_128 0 "vlogical_operand" "") + [(set (match_operand:BOOL_128 0 "vlogical_operand") (and:BOOL_128 - (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")) - (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))))] + (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand")) + (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand"))))] "" "") (define_expand "andc<mode>3" - [(set (match_operand:BOOL_128 0 "vlogical_operand" "") + [(set (match_operand:BOOL_128 0 "vlogical_operand") (and:BOOL_128 - (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" "")) - (match_operand:BOOL_128 1 "vlogical_operand" "")))] + (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand")) + (match_operand:BOOL_128 1 "vlogical_operand")))] "" "") ;; Power8 vector logical instructions. (define_expand "eqv<mode>3" - [(set (match_operand:BOOL_128 0 "vlogical_operand" "") + [(set (match_operand:BOOL_128 0 "vlogical_operand") (not:BOOL_128 - (xor:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "") - (match_operand:BOOL_128 2 "vlogical_operand" ""))))] + (xor:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand") + (match_operand:BOOL_128 2 "vlogical_operand"))))] "<MODE>mode == TImode || <MODE>mode == PTImode || TARGET_P8_VECTOR" "") ;; Rewrite nand into canonical form (define_expand "nand<mode>3" - [(set (match_operand:BOOL_128 0 "vlogical_operand" "") + [(set (match_operand:BOOL_128 0 "vlogical_operand") (ior:BOOL_128 - (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")) - (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))))] + (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand")) + (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand"))))] "<MODE>mode == TImode || <MODE>mode == PTImode || TARGET_P8_VECTOR" "") ;; The canonical form is to have the negated element first, so we need to ;; reverse arguments. (define_expand "orc<mode>3" - [(set (match_operand:BOOL_128 0 "vlogical_operand" "") + [(set (match_operand:BOOL_128 0 "vlogical_operand") (ior:BOOL_128 - (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" "")) - (match_operand:BOOL_128 1 "vlogical_operand" "")))] + (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand")) + (match_operand:BOOL_128 1 "vlogical_operand")))] "<MODE>mode == TImode || <MODE>mode == PTImode || TARGET_P8_VECTOR" "") @@ -6666,11 +6641,10 @@ ;; Set up a register with a value from the GOT table (define_expand "movsi_got" - [(set (match_operand:SI 0 "gpc_reg_operand" "") - (unspec:SI [(match_operand:SI 1 "got_operand" "") + [(set (match_operand:SI 0 "gpc_reg_operand") + (unspec:SI [(match_operand:SI 1 "got_operand") (match_dup 2)] UNSPEC_MOVSI_GOT))] "DEFAULT_ABI == ABI_V4 && flag_pic == 1" - " { if (GET_CODE (operands[1]) == CONST) { @@ -6691,7 +6665,7 @@ } operands[2] = rs6000_got_register (operands[1]); -}") +}) (define_insn "*movsi_got_internal" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") @@ -6705,9 +6679,9 @@ ;; Used by sched, shorten_branches and final when the GOT pseudo reg ;; didn't get allocated to a hard register. (define_split - [(set (match_operand:SI 0 "gpc_reg_operand" "") - (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "") - (match_operand:SI 2 "memory_operand" "")] + [(set (match_operand:SI 0 "gpc_reg_operand") + (unspec:SI [(match_operand:SI 1 "got_no_const_operand") + (match_operand:SI 2 "memory_operand")] UNSPEC_MOVSI_GOT))] "DEFAULT_ABI == ABI_V4 && flag_pic == 1 @@ -6966,8 +6940,8 @@ ;; sequence. (define_split - [(set (match_operand:SI 0 "gpc_reg_operand" "") - (match_operand:SI 1 "const_int_operand" ""))] + [(set (match_operand:SI 0 "gpc_reg_operand") + (match_operand:SI 1 "const_int_operand"))] "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000 && (INTVAL (operands[1]) & 0xffff) != 0" [(set (match_dup 0) @@ -6975,13 +6949,12 @@ (set (match_dup 0) (ior:SI (match_dup 0) (match_dup 3)))] - " { if (rs6000_emit_set_const (operands[0], operands[1])) DONE; else FAIL; -}") +}) ;; Split loading -128..127 to use XXSPLITB and VEXTSW2D (define_split @@ -7027,10 +7000,13 @@ "") (define_expand "mov<mode>" - [(set (match_operand:INT 0 "general_operand" "") - (match_operand:INT 1 "any_operand" ""))] + [(set (match_operand:INT 0 "general_operand") + (match_operand:INT 1 "any_operand"))] "" - "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }") +{ + rs6000_emit_move (operands[0], operands[1], <MODE>mode); + DONE; +}) ;; MR LHZ/LBZ LXSI*ZX STH/STB STXSI*X LI ;; XXLOR load 0 load -1 VSPLTI* # MFVSRWZ @@ -7080,8 +7056,8 @@ ;; an integer register or memory, we store just the high-order 4 bits. ;; This lets us not shift in the most common case of CR0. (define_expand "movcc" - [(set (match_operand:CC 0 "nonimmediate_operand" "") - (match_operand:CC 1 "nonimmediate_operand" ""))] + [(set (match_operand:CC 0 "nonimmediate_operand") + (match_operand:CC 1 "nonimmediate_operand"))] "" "") @@ -7134,21 +7110,23 @@ ;; Move 32-bit binary/decimal floating point (define_expand "mov<mode>" - [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "") - (match_operand:FMOVE32 1 "any_operand" ""))] + [(set (match_operand:FMOVE32 0 "nonimmediate_operand") + (match_operand:FMOVE32 1 "any_operand"))] "<fmove_ok>" - "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }") +{ + rs6000_emit_move (operands[0], operands[1], <MODE>mode); + DONE; +}) (define_split - [(set (match_operand:FMOVE32 0 "gpc_reg_operand" "") - (match_operand:FMOVE32 1 "const_double_operand" ""))] + [(set (match_operand:FMOVE32 0 "gpc_reg_operand") + (match_operand:FMOVE32 1 "const_double_operand"))] "reload_completed && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) || (GET_CODE (operands[0]) == SUBREG && GET_CODE (SUBREG_REG (operands[0])) == REG && REGNO (SUBREG_REG (operands[0])) <= 31))" [(set (match_dup 2) (match_dup 3))] - " { long l; @@ -7160,7 +7138,7 @@ operands[2] = gen_lowpart (SImode, operands[0]); operands[3] = gen_int_mode (l, SImode); -}") +}) ;; Originally, we tried to keep movsf and movsd common, but the differences ;; addressing was making it rather difficult to hide with mode attributes. In @@ -7331,14 +7309,17 @@ ;; Move 64-bit binary/decimal floating point (define_expand "mov<mode>" - [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "") - (match_operand:FMOVE64 1 "any_operand" ""))] + [(set (match_operand:FMOVE64 0 "nonimmediate_operand") + (match_operand:FMOVE64 1 "any_operand"))] "" - "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }") +{ + rs6000_emit_move (operands[0], operands[1], <MODE>mode); + DONE; +}) (define_split - [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "") - (match_operand:FMOVE64 1 "const_int_operand" ""))] + [(set (match_operand:FMOVE64 0 "gpc_reg_operand") + (match_operand:FMOVE64 1 "const_int_operand"))] "! TARGET_POWERPC64 && reload_completed && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) || (GET_CODE (operands[0]) == SUBREG @@ -7346,7 +7327,6 @@ && REGNO (SUBREG_REG (operands[0])) <= 31))" [(set (match_dup 2) (match_dup 4)) (set (match_dup 3) (match_dup 1))] - " { int endian = (WORDS_BIG_ENDIAN == 0); HOST_WIDE_INT value = INTVAL (operands[1]); @@ -7355,11 +7335,11 @@ operands[3] = operand_subword (operands[0], 1 - endian, 0, <MODE>mode); operands[4] = GEN_INT (value >> 32); operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000); -}") +}) (define_split - [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "") - (match_operand:FMOVE64 1 "const_double_operand" ""))] + [(set (match_operand:FMOVE64 0 "gpc_reg_operand") + (match_operand:FMOVE64 1 "const_double_operand"))] "! TARGET_POWERPC64 && reload_completed && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) || (GET_CODE (operands[0]) == SUBREG @@ -7367,7 +7347,6 @@ && REGNO (SUBREG_REG (operands[0])) <= 31))" [(set (match_dup 2) (match_dup 4)) (set (match_dup 3) (match_dup 5))] - " { int endian = (WORDS_BIG_ENDIAN == 0); long l[2]; @@ -7378,18 +7357,17 @@ operands[3] = operand_subword (operands[0], 1 - endian, 0, <MODE>mode); operands[4] = gen_int_mode (l[endian], SImode); operands[5] = gen_int_mode (l[1 - endian], SImode); -}") +}) (define_split - [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "") - (match_operand:FMOVE64 1 "const_double_operand" ""))] + [(set (match_operand:FMOVE64 0 "gpc_reg_operand") + (match_operand:FMOVE64 1 "const_double_operand"))] "TARGET_POWERPC64 && reload_completed && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) || (GET_CODE (operands[0]) == SUBREG && GET_CODE (SUBREG_REG (operands[0])) == REG && REGNO (SUBREG_REG (operands[0])) <= 31))" [(set (match_dup 2) (match_dup 3))] - " { int endian = (WORDS_BIG_ENDIAN == 0); long l[2]; @@ -7403,7 +7381,7 @@ | ((HOST_WIDE_INT)(unsigned long)l[1 - endian])); operands[3] = gen_int_mode (val, DImode); -}") +}) ;; Don't have reload use general registers to load a constant. It is ;; less efficient than loading the constant into an FP register, since @@ -7508,10 +7486,13 @@ (set_attr "length" "4,4,4,4,4,8,12,16,4")]) (define_expand "mov<mode>" - [(set (match_operand:FMOVE128 0 "general_operand" "") - (match_operand:FMOVE128 1 "any_operand" ""))] + [(set (match_operand:FMOVE128 0 "general_operand") + (match_operand:FMOVE128 1 "any_operand"))] "" - "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }") +{ + rs6000_emit_move (operands[0], operands[1], <MODE>mode); + DONE; +}) ;; It's important to list Y->r and r->Y before r->r because otherwise ;; reload, given m->r, will try to pick r->r and reload it, which @@ -7574,8 +7555,8 @@ [(set_attr "length" "20,20,16")]) (define_expand "extenddf<mode>2" - [(set (match_operand:FLOAT128 0 "gpc_reg_operand" "") - (float_extend:FLOAT128 (match_operand:DF 1 "gpc_reg_operand" "")))] + [(set (match_operand:FLOAT128 0 "gpc_reg_operand") + (float_extend:FLOAT128 (match_operand:DF 1 "gpc_reg_operand")))] "TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" { if (FLOAT128_IEEE_P (<MODE>mode)) @@ -7643,8 +7624,8 @@ }) (define_expand "extendsf<mode>2" - [(set (match_operand:FLOAT128 0 "gpc_reg_operand" "") - (float_extend:FLOAT128 (match_operand:SF 1 "gpc_reg_operand" "")))] + [(set (match_operand:FLOAT128 0 "gpc_reg_operand") + (float_extend:FLOAT128 (match_operand:SF 1 "gpc_reg_operand")))] "TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" { if (FLOAT128_IEEE_P (<MODE>mode)) @@ -7659,8 +7640,8 @@ }) (define_expand "trunc<mode>df2" - [(set (match_operand:DF 0 "gpc_reg_operand" "") - (float_truncate:DF (match_operand:FLOAT128 1 "gpc_reg_operand" "")))] + [(set (match_operand:DF 0 "gpc_reg_operand") + (float_truncate:DF (match_operand:FLOAT128 1 "gpc_reg_operand")))] "TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" { if (FLOAT128_IEEE_P (<MODE>mode)) @@ -7697,8 +7678,8 @@ (set_attr "fp_type" "fp_addsub_d")]) (define_expand "trunc<mode>sf2" - [(set (match_operand:SF 0 "gpc_reg_operand" "") - (float_truncate:SF (match_operand:FLOAT128 1 "gpc_reg_operand" "")))] + [(set (match_operand:SF 0 "gpc_reg_operand") + (float_truncate:SF (match_operand:FLOAT128 1 "gpc_reg_operand")))] "TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" { if (FLOAT128_IEEE_P (<MODE>mode)) @@ -7769,8 +7750,8 @@ (set_attr "length" "20")]) (define_expand "fix_trunc<mode>si2" - [(set (match_operand:SI 0 "gpc_reg_operand" "") - (fix:SI (match_operand:FLOAT128 1 "gpc_reg_operand" "")))] + [(set (match_operand:SI 0 "gpc_reg_operand") + (fix:SI (match_operand:FLOAT128 1 "gpc_reg_operand")))] "TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" { rtx op0 = operands[0]; @@ -7793,8 +7774,8 @@ }) (define_expand "fix_trunc<mode>si2_fprs" - [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") - (fix:SI (match_operand:IBM128 1 "gpc_reg_operand" ""))) + [(parallel [(set (match_operand:SI 0 "gpc_reg_operand") + (fix:SI (match_operand:IBM128 1 "gpc_reg_operand"))) (clobber (match_dup 2)) (clobber (match_dup 3)) (clobber (match_dup 4)) @@ -7833,8 +7814,8 @@ }) (define_expand "fix_trunc<mode>di2" - [(set (match_operand:DI 0 "gpc_reg_operand" "") - (fix:DI (match_operand:IEEE128 1 "gpc_reg_operand" "")))] + [(set (match_operand:DI 0 "gpc_reg_operand") + (fix:DI (match_operand:IEEE128 1 "gpc_reg_operand")))] "TARGET_FLOAT128_TYPE" { if (!TARGET_FLOAT128_HW) @@ -7845,8 +7826,8 @@ }) (define_expand "fixuns_trunc<IEEE128:mode><SDI:mode>2" - [(set (match_operand:SDI 0 "gpc_reg_operand" "") - (unsigned_fix:SDI (match_operand:IEEE128 1 "gpc_reg_operand" "")))] + [(set (match_operand:SDI 0 "gpc_reg_operand") + (unsigned_fix:SDI (match_operand:IEEE128 1 "gpc_reg_operand")))] "TARGET_FLOAT128_TYPE" { rs6000_expand_float128_convert (operands[0], operands[1], true); @@ -7854,8 +7835,8 @@ }) (define_expand "floatdi<mode>2" - [(set (match_operand:IEEE128 0 "gpc_reg_operand" "") - (float:IEEE128 (match_operand:DI 1 "gpc_reg_operand" "")))] + [(set (match_operand:IEEE128 0 "gpc_reg_operand") + (float:IEEE128 (match_operand:DI 1 "gpc_reg_operand")))] "TARGET_FLOAT128_TYPE" { if (!TARGET_FLOAT128_HW) @@ -7866,8 +7847,8 @@ }) (define_expand "floatunsdi<IEEE128:mode>2" - [(set (match_operand:IEEE128 0 "gpc_reg_operand" "") - (unsigned_float:IEEE128 (match_operand:DI 1 "gpc_reg_operand" "")))] + [(set (match_operand:IEEE128 0 "gpc_reg_operand") + (unsigned_float:IEEE128 (match_operand:DI 1 "gpc_reg_operand")))] "TARGET_FLOAT128_TYPE" { if (!TARGET_FLOAT128_HW) @@ -7878,8 +7859,8 @@ }) (define_expand "floatuns<IEEE128:mode>2" - [(set (match_operand:IEEE128 0 "gpc_reg_operand" "") - (unsigned_float:IEEE128 (match_operand:SI 1 "gpc_reg_operand" "")))] + [(set (match_operand:IEEE128 0 "gpc_reg_operand") + (unsigned_float:IEEE128 (match_operand:SI 1 "gpc_reg_operand")))] "TARGET_FLOAT128_TYPE" { rtx op0 = operands[0]; @@ -7893,11 +7874,10 @@ }) (define_expand "neg<mode>2" - [(set (match_operand:FLOAT128 0 "gpc_reg_operand" "") - (neg:FLOAT128 (match_operand:FLOAT128 1 "gpc_reg_operand" "")))] + [(set (match_operand:FLOAT128 0 "gpc_reg_operand") + (neg:FLOAT128 (match_operand:FLOAT128 1 "gpc_reg_operand")))] "FLOAT128_IEEE_P (<MODE>mode) || (FLOAT128_IBM_P (<MODE>mode) && TARGET_HARD_FLOAT)" - " { if (FLOAT128_IEEE_P (<MODE>mode)) { @@ -7931,28 +7911,26 @@ } DONE; } -}") +}) (define_insn "neg<mode>2_internal" [(set (match_operand:IBM128 0 "gpc_reg_operand" "=d") (neg:IBM128 (match_operand:IBM128 1 "gpc_reg_operand" "d")))] "TARGET_HARD_FLOAT && FLOAT128_IBM_P (TFmode)" - "* { if (REGNO (operands[0]) == REGNO (operands[1]) + 1) - return \"fneg %L0,%L1\;fneg %0,%1\"; + return "fneg %L0,%L1\;fneg %0,%1"; else - return \"fneg %0,%1\;fneg %L0,%L1\"; -}" + return "fneg %0,%1\;fneg %L0,%L1"; +} [(set_attr "type" "fpsimple") (set_attr "length" "8")]) (define_expand "abs<mode>2" - [(set (match_operand:FLOAT128 0 "gpc_reg_operand" "") - (abs:FLOAT128 (match_operand:FLOAT128 1 "gpc_reg_operand" "")))] + [(set (match_operand:FLOAT128 0 "gpc_reg_operand") + (abs:FLOAT128 (match_operand:FLOAT128 1 "gpc_reg_operand")))] "FLOAT128_IEEE_P (<MODE>mode) || (FLOAT128_IBM_P (<MODE>mode) && TARGET_HARD_FLOAT)" - " { rtx label; @@ -7991,20 +7969,19 @@ FAIL; emit_label (label); DONE; -}") +}) (define_expand "abs<mode>2_internal" - [(set (match_operand:IBM128 0 "gpc_reg_operand" "") - (match_operand:IBM128 1 "gpc_reg_operand" "")) + [(set (match_operand:IBM128 0 "gpc_reg_operand") + (match_operand:IBM128 1 "gpc_reg_operand")) (set (match_dup 3) (match_dup 5)) (set (match_dup 5) (abs:DF (match_dup 5))) (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5))) (set (pc) (if_then_else (eq (match_dup 4) (const_int 0)) - (label_ref (match_operand 2 "" "")) + (label_ref (match_operand 2 "")) (pc))) (set (match_dup 6) (neg:DF (match_dup 6)))] "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128" - " { const int hi_word = LONG_DOUBLE_LARGE_FIRST ? 0 : GET_MODE_SIZE (DFmode); const int lo_word = LONG_DOUBLE_LARGE_FIRST ? GET_MODE_SIZE (DFmode) : 0; @@ -8012,14 +7989,14 @@ operands[4] = gen_reg_rtx (CCFPmode); operands[5] = simplify_gen_subreg (DFmode, operands[0], <MODE>mode, hi_word); operands[6] = simplify_gen_subreg (DFmode, operands[0], <MODE>mode, lo_word); -}") +}) ;; Generate IEEE 128-bit -0.0 (0x80000000000000000000000000000000) in a vector ;; register (define_expand "ieee_128bit_negative_zero" - [(set (match_operand:V16QI 0 "register_operand" "") (match_dup 1))] + [(set (match_operand:V16QI 0 "register_operand") (match_dup 1))] "TARGET_FLOAT128_TYPE" { rtvec v = rtvec_alloc (16); @@ -8138,8 +8115,8 @@ ;; We use expand to convert from IBM double double to IEEE 128-bit ;; and trunc for the opposite. (define_expand "extendiftf2" - [(set (match_operand:TF 0 "gpc_reg_operand" "") - (float_extend:TF (match_operand:IF 1 "gpc_reg_operand" "")))] + [(set (match_operand:TF 0 "gpc_reg_operand") + (float_extend:TF (match_operand:IF 1 "gpc_reg_operand")))] "TARGET_FLOAT128_TYPE" { rs6000_expand_float128_convert (operands[0], operands[1], false); @@ -8147,8 +8124,8 @@ }) (define_expand "extendifkf2" - [(set (match_operand:KF 0 "gpc_reg_operand" "") - (float_extend:KF (match_operand:IF 1 "gpc_reg_operand" "")))] + [(set (match_operand:KF 0 "gpc_reg_operand") + (float_extend:KF (match_operand:IF 1 "gpc_reg_operand")))] "TARGET_FLOAT128_TYPE" { rs6000_expand_float128_convert (operands[0], operands[1], false); @@ -8156,8 +8133,8 @@ }) (define_expand "extendtfkf2" - [(set (match_operand:KF 0 "gpc_reg_operand" "") - (float_extend:KF (match_operand:TF 1 "gpc_reg_operand" "")))] + [(set (match_operand:KF 0 "gpc_reg_operand") + (float_extend:KF (match_operand:TF 1 "gpc_reg_operand")))] "TARGET_FLOAT128_TYPE" { rs6000_expand_float128_convert (operands[0], operands[1], false); @@ -8165,8 +8142,8 @@ }) (define_expand "trunciftf2" - [(set (match_operand:IF 0 "gpc_reg_operand" "") - (float_truncate:IF (match_operand:TF 1 "gpc_reg_operand" "")))] + [(set (match_operand:IF 0 "gpc_reg_operand") + (float_truncate:IF (match_operand:TF 1 "gpc_reg_operand")))] "TARGET_FLOAT128_TYPE" { rs6000_expand_float128_convert (operands[0], operands[1], false); @@ -8174,8 +8151,8 @@ }) (define_expand "truncifkf2" - [(set (match_operand:IF 0 "gpc_reg_operand" "") - (float_truncate:IF (match_operand:KF 1 "gpc_reg_operand" "")))] + [(set (match_operand:IF 0 "gpc_reg_operand") + (float_truncate:IF (match_operand:KF 1 "gpc_reg_operand")))] "TARGET_FLOAT128_TYPE" { rs6000_expand_float128_convert (operands[0], operands[1], false); @@ -8183,8 +8160,8 @@ }) (define_expand "trunckftf2" - [(set (match_operand:TF 0 "gpc_reg_operand" "") - (float_truncate:TF (match_operand:KF 1 "gpc_reg_operand" "")))] + [(set (match_operand:TF 0 "gpc_reg_operand") + (float_truncate:TF (match_operand:KF 1 "gpc_reg_operand")))] "TARGET_FLOAT128_TYPE" { rs6000_expand_float128_convert (operands[0], operands[1], false); @@ -8192,8 +8169,8 @@ }) (define_expand "trunctfif2" - [(set (match_operand:IF 0 "gpc_reg_operand" "") - (float_truncate:IF (match_operand:TF 1 "gpc_reg_operand" "")))] + [(set (match_operand:IF 0 "gpc_reg_operand") + (float_truncate:IF (match_operand:TF 1 "gpc_reg_operand")))] "TARGET_FLOAT128_TYPE" { rs6000_expand_float128_convert (operands[0], operands[1], false); @@ -8372,8 +8349,8 @@ (set_attr "type" "three")]) (define_split - [(set (match_operand:FMOVE128_GPR 0 "nonimmediate_operand" "") - (match_operand:FMOVE128_GPR 1 "input_operand" ""))] + [(set (match_operand:FMOVE128_GPR 0 "nonimmediate_operand") + (match_operand:FMOVE128_GPR 1 "input_operand"))] "reload_completed && (int_reg_operand (operands[0], <MODE>mode) || int_reg_operand (operands[1], <MODE>mode)) @@ -8539,14 +8516,13 @@ (set_attr "size" "64")]) (define_split - [(set (match_operand:DI 0 "gpc_reg_operand" "") - (match_operand:DI 1 "const_int_operand" ""))] + [(set (match_operand:DI 0 "gpc_reg_operand") + (match_operand:DI 1 "const_int_operand"))] "! TARGET_POWERPC64 && reload_completed && gpr_or_gpr_p (operands[0], operands[1]) && !direct_move_p (operands[0], operands[1])" [(set (match_dup 2) (match_dup 4)) (set (match_dup 3) (match_dup 1))] - " { HOST_WIDE_INT value = INTVAL (operands[1]); operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0, @@ -8555,11 +8531,11 @@ DImode); operands[4] = GEN_INT (value >> 32); operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000); -}") +}) (define_split - [(set (match_operand:DIFD 0 "nonimmediate_operand" "") - (match_operand:DIFD 1 "input_operand" ""))] + [(set (match_operand:DIFD 0 "nonimmediate_operand") + (match_operand:DIFD 1 "input_operand"))] "reload_completed && !TARGET_POWERPC64 && gpr_or_gpr_p (operands[0], operands[1]) && !direct_move_p (operands[0], operands[1])" @@ -8654,36 +8630,34 @@ ;; When non-easy constants can go in the TOC, this should use ;; easy_fp_constant predicate. (define_split - [(set (match_operand:DI 0 "int_reg_operand_not_pseudo" "") - (match_operand:DI 1 "const_int_operand" ""))] + [(set (match_operand:DI 0 "int_reg_operand_not_pseudo") + (match_operand:DI 1 "const_int_operand"))] "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1" [(set (match_dup 0) (match_dup 2)) (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))] - " { if (rs6000_emit_set_const (operands[0], operands[1])) DONE; else FAIL; -}") +}) (define_split - [(set (match_operand:DI 0 "int_reg_operand_not_pseudo" "") - (match_operand:DI 1 "const_scalar_int_operand" ""))] + [(set (match_operand:DI 0 "int_reg_operand_not_pseudo") + (match_operand:DI 1 "const_scalar_int_operand"))] "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1" [(set (match_dup 0) (match_dup 2)) (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))] - " { if (rs6000_emit_set_const (operands[0], operands[1])) DONE; else FAIL; -}") +}) (define_split - [(set (match_operand:DI 0 "altivec_register_operand" "") - (match_operand:DI 1 "s5bit_cint_operand" ""))] + [(set (match_operand:DI 0 "altivec_register_operand") + (match_operand:DI 1 "s5bit_cint_operand"))] "TARGET_VSX && reload_completed" [(const_int 0)] { @@ -8704,8 +8678,8 @@ ;; Split integer constants that can be loaded with XXSPLTIB and a ;; sign extend operation. (define_split - [(set (match_operand:INT_ISA3 0 "altivec_register_operand" "") - (match_operand:INT_ISA3 1 "xxspltib_constant_split" ""))] + [(set (match_operand:INT_ISA3 0 "altivec_register_operand") + (match_operand:INT_ISA3 1 "xxspltib_constant_split"))] "TARGET_P9_VECTOR && reload_completed" [(const_int 0)] { @@ -8757,14 +8731,13 @@ (set_attr "length" "8")]) (define_split - [(set (match_operand:TI2 0 "int_reg_operand" "") - (match_operand:TI2 1 "const_scalar_int_operand" ""))] + [(set (match_operand:TI2 0 "int_reg_operand") + (match_operand:TI2 1 "const_scalar_int_operand"))] "TARGET_POWERPC64 && (VECTOR_MEM_NONE_P (<MODE>mode) || (reload_completed && INT_REGNO_P (REGNO (operands[0]))))" [(set (match_dup 2) (match_dup 4)) (set (match_dup 3) (match_dup 5))] - " { operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0, <MODE>mode); @@ -8782,11 +8755,11 @@ } else FAIL; -}") +}) (define_split - [(set (match_operand:TI2 0 "nonimmediate_operand" "") - (match_operand:TI2 1 "input_operand" ""))] + [(set (match_operand:TI2 0 "nonimmediate_operand") + (match_operand:TI2 1 "input_operand"))] "reload_completed && gpr_or_gpr_p (operands[0], operands[1]) && !direct_move_p (operands[0], operands[1]) @@ -8795,12 +8768,11 @@ { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }) (define_expand "setmemsi" - [(parallel [(set (match_operand:BLK 0 "" "") - (match_operand 2 "const_int_operand" "")) - (use (match_operand:SI 1 "" "")) - (use (match_operand:SI 3 "" ""))])] + [(parallel [(set (match_operand:BLK 0 "") + (match_operand 2 "const_int_operand")) + (use (match_operand:SI 1 "")) + (use (match_operand:SI 3 ""))])] "" - " { /* If value to set is not zero, use the library routine. */ if (operands[2] != const0_rtx) @@ -8810,7 +8782,7 @@ DONE; else FAIL; -}") +}) ;; String compare N insn. ;; Argument 0 is the target (result) @@ -8886,18 +8858,17 @@ ;; Argument 3 is the alignment (define_expand "movmemsi" - [(parallel [(set (match_operand:BLK 0 "" "") - (match_operand:BLK 1 "" "")) - (use (match_operand:SI 2 "" "")) - (use (match_operand:SI 3 "" ""))])] + [(parallel [(set (match_operand:BLK 0 "") + (match_operand:BLK 1 "")) + (use (match_operand:SI 2 "")) + (use (match_operand:SI 3 ""))])] "" - " { if (expand_block_move (operands)) DONE; else FAIL; -}") +}) ;; Define insns that do load or store with update. Some of these we can ;; get by using pre-decrement or pre-increment, but the hardware can also @@ -9245,18 +9216,18 @@ ;; Also this optimization interferes with scalars going into ;; altivec registers (the code does reloading through the FPRs). (define_peephole2 - [(set (match_operand:DF 0 "gpc_reg_operand" "") - (match_operand:DF 1 "any_operand" "")) - (set (match_operand:DF 2 "gpc_reg_operand" "") + [(set (match_operand:DF 0 "gpc_reg_operand") + (match_operand:DF 1 "any_operand")) + (set (match_operand:DF 2 "gpc_reg_operand") (match_dup 0))] "!TARGET_VSX && peep2_reg_dead_p (2, operands[0])" [(set (match_dup 2) (match_dup 1))]) (define_peephole2 - [(set (match_operand:SF 0 "gpc_reg_operand" "") - (match_operand:SF 1 "any_operand" "")) - (set (match_operand:SF 2 "gpc_reg_operand" "") + [(set (match_operand:SF 0 "gpc_reg_operand") + (match_operand:SF 1 "any_operand")) + (set (match_operand:SF 2 "gpc_reg_operand") (match_dup 0))] "!TARGET_P8_VECTOR && peep2_reg_dead_p (2, operands[0])" @@ -9352,10 +9323,9 @@ (set (match_dup 0) (lo_sum:TLSmode (match_dup 3) (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGD)))] - " { operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode); -}" +} [(set (attr "length") (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL")) (const_int 8) @@ -9489,10 +9459,9 @@ (set (match_dup 0) (lo_sum:TLSmode (match_dup 2) (unspec:TLSmode [(const_int 0) (match_dup 1)] UNSPEC_TLSLD)))] - " { operands[2] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode); -}" +} [(set (attr "length") (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL")) (const_int 8) @@ -9587,10 +9556,9 @@ (set (match_dup 0) (lo_sum:TLSmode (match_dup 3) (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTDTPREL)))] - " { operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode); -}" +} [(set (attr "length") (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL")) (const_int 8) @@ -9657,10 +9625,9 @@ (set (match_dup 0) (lo_sum:TLSmode (match_dup 3) (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTTPREL)))] - " { operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode); -}" +} [(set (attr "length") (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL")) (const_int 8) @@ -9695,15 +9662,14 @@ "add %0,%1,%2@tls") (define_expand "tls_get_tpointer" - [(set (match_operand:SI 0 "gpc_reg_operand" "") + [(set (match_operand:SI 0 "gpc_reg_operand") (unspec:SI [(const_int 0)] UNSPEC_TLSTLS))] "TARGET_XCOFF && HAVE_AS_TLS" - " { emit_insn (gen_tls_get_tpointer_internal ()); emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); DONE; -}") +}) (define_insn "tls_get_tpointer_internal" [(set (reg:SI 3) @@ -9713,18 +9679,17 @@ "bla __get_tpointer") (define_expand "tls_get_addr<mode>" - [(set (match_operand:P 0 "gpc_reg_operand" "") - (unspec:P [(match_operand:P 1 "gpc_reg_operand" "") - (match_operand:P 2 "gpc_reg_operand" "")] UNSPEC_TLSTLS))] + [(set (match_operand:P 0 "gpc_reg_operand") + (unspec:P [(match_operand:P 1 "gpc_reg_operand") + (match_operand:P 2 "gpc_reg_operand")] UNSPEC_TLSTLS))] "TARGET_XCOFF && HAVE_AS_TLS" - " { emit_move_insn (gen_rtx_REG (Pmode, 3), operands[1]); emit_move_insn (gen_rtx_REG (Pmode, 4), operands[2]); emit_insn (gen_tls_get_addr_internal<mode> ()); emit_move_insn (operands[0], gen_rtx_REG (Pmode, 3)); DONE; -}") +}) (define_insn "tls_get_addr_internal<mode>" [(set (reg:P 3) @@ -9754,13 +9719,13 @@ ;; the constant size. The value is forced into a register if necessary. ;; (define_expand "allocate_stack" - [(set (match_operand 0 "gpc_reg_operand" "") - (minus (reg 1) (match_operand 1 "reg_or_cint_operand" ""))) + [(set (match_operand 0 "gpc_reg_operand") + (minus (reg 1) (match_operand 1 "reg_or_cint_operand"))) (set (reg 1) (minus (reg 1) (match_dup 1)))] "" - " -{ rtx chain = gen_reg_rtx (Pmode); +{ + rtx chain = gen_reg_rtx (Pmode); rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx); rtx neg_op0; rtx insn, par, set, mem; @@ -9864,7 +9829,7 @@ emit_move_insn (operands[0], virtual_stack_dynamic_rtx); DONE; -}") +}) ;; These patterns say how to save and restore the stack pointer. We need not ;; save the stack pointer at function level since we are careful to @@ -9876,14 +9841,14 @@ ;; save area is a memory location. (define_expand "save_stack_function" - [(match_operand 0 "any_operand" "") - (match_operand 1 "any_operand" "")] + [(match_operand 0 "any_operand") + (match_operand 1 "any_operand")] "" "DONE;") (define_expand "restore_stack_function" - [(match_operand 0 "any_operand" "") - (match_operand 1 "any_operand" "")] + [(match_operand 0 "any_operand") + (match_operand 1 "any_operand")] "" "DONE;") @@ -9894,10 +9859,9 @@ [(set (match_dup 2) (match_dup 3)) (set (match_dup 4) (match_dup 2)) (match_dup 5) - (set (match_operand 0 "register_operand" "") - (match_operand 1 "register_operand" ""))] + (set (match_operand 0 "register_operand") + (match_operand 1 "register_operand"))] "" - " { rtvec p; @@ -9909,14 +9873,13 @@ RTVEC_ELT (p, 0) = gen_rtx_SET (gen_frame_mem (BLKmode, operands[0]), const0_rtx); operands[5] = gen_rtx_PARALLEL (VOIDmode, p); -}") +}) (define_expand "save_stack_nonlocal" [(set (match_dup 3) (match_dup 4)) - (set (match_operand 0 "memory_operand" "") (match_dup 3)) - (set (match_dup 2) (match_operand 1 "register_operand" ""))] + (set (match_operand 0 "memory_operand") (match_dup 3)) + (set (match_dup 2) (match_operand 1 "register_operand"))] "" - " { int units_per_word = (TARGET_32BIT) ? 4 : 8; @@ -9925,16 +9888,15 @@ operands[2] = adjust_address_nv (operands[0], Pmode, units_per_word); operands[3] = gen_reg_rtx (Pmode); operands[4] = gen_frame_mem (Pmode, operands[1]); -}") +}) (define_expand "restore_stack_nonlocal" - [(set (match_dup 2) (match_operand 1 "memory_operand" "")) + [(set (match_dup 2) (match_operand 1 "memory_operand")) (set (match_dup 3) (match_dup 4)) (set (match_dup 5) (match_dup 2)) (match_dup 6) - (set (match_operand 0 "register_operand" "") (match_dup 3))] + (set (match_operand 0 "register_operand") (match_dup 3))] "" - " { int units_per_word = (TARGET_32BIT) ? 4 : 8; rtvec p; @@ -9949,7 +9911,7 @@ RTVEC_ELT (p, 0) = gen_rtx_SET (gen_frame_mem (BLKmode, operands[0]), const0_rtx); operands[6] = gen_rtx_PARALLEL (VOIDmode, p); -}") +}) ;; TOC register handling. @@ -9960,16 +9922,15 @@ (unspec:SI [(const_int 0)] UNSPEC_TOC)) (use (reg:SI 2))])] "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) && TARGET_32BIT" - "* { char buf[30]; extern int need_toc_init; need_toc_init = 1; - ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1); + ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1); operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); operands[2] = gen_rtx_REG (Pmode, 2); - return \"lwz %0,%1(%2)\"; -}" + return "lwz %0,%1(%2)"; +} [(set_attr "type" "load") (set_attr "update" "no") (set_attr "indexed" "no")]) @@ -9979,19 +9940,18 @@ (unspec:DI [(const_int 0)] UNSPEC_TOC)) (use (reg:DI 2))])] "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) && TARGET_64BIT" - "* { char buf[30]; extern int need_toc_init; need_toc_init = 1; - ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", + ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", !TARGET_ELF || !TARGET_MINIMAL_TOC); if (TARGET_ELF) - strcat (buf, \"@toc\"); + strcat (buf, "@toc"); operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); operands[2] = gen_rtx_REG (Pmode, 2); - return \"ld %0,%1(%2)\"; -}" + return "ld %0,%1(%2)"; +} [(set_attr "type" "load") (set_attr "update" "no") (set_attr "indexed" "no")]) @@ -10018,7 +9978,7 @@ (use (unspec [(match_dup 0)] UNSPEC_TOC))] "!TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))" - "bcl 20,31,%0\\n%0:" + "bcl 20,31,%0\n%0:" [(set_attr "type" "branch") (set_attr "length" "4") (set_attr "cannot_copy" "yes")]) @@ -10029,15 +9989,14 @@ (use (unspec [(match_dup 0)] UNSPEC_TOC))] "TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))" - "* { char name[32]; static char templ[32]; get_ppc476_thunk_name (name); - sprintf (templ, \"bl %s\\n%%0:\", name); + sprintf (templ, "bl %s\n%%0:", name); return templ; -}" +} [(set_attr "type" "branch") (set_attr "length" "4") (set_attr "cannot_copy" "yes")]) @@ -10045,7 +10004,7 @@ (define_expand "load_toc_v4_PIC_1b" [(parallel [(set (reg:SI LR_REGNO) (unspec:SI [(match_operand:SI 0 "immediate_operand" "s") - (label_ref (match_operand 1 "" ""))] + (label_ref (match_operand 1 ""))] UNSPEC_TOCPTR)) (match_dup 1)])] "TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2" @@ -10069,15 +10028,14 @@ UNSPEC_TOCPTR)) (match_dup 1)] "TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2" - "* { char name[32]; static char templ[32]; get_ppc476_thunk_name (name); - sprintf (templ, \"bl %s\\n\\tb $+8\\n\\t.long %%0-$\", name); + sprintf (templ, "bl %s\;b $+8\;.long %%0-$", name); return templ; -}" +} [(set_attr "type" "branch") (set_attr "length" "16")]) @@ -10119,11 +10077,10 @@ ;; On Darwin, we need to reload the picbase. (define_expand "builtin_setjmp_receiver" - [(use (label_ref (match_operand 0 "" "")))] + [(use (label_ref (match_operand 0 "")))] "(DEFAULT_ABI == ABI_V4 && flag_pic == 1) || (TARGET_TOC && TARGET_MINIMAL_TOC) || (DEFAULT_ABI == ABI_DARWIN && flag_pic)" - " { #if TARGET_MACHO if (DEFAULT_ABI == ABI_DARWIN) @@ -10134,7 +10091,7 @@ char tmplab[20]; crtl->uses_pic_offset_table = 1; - ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\", + ASM_GENERATE_INTERNAL_LABEL(tmplab, "LSJR", CODE_LABEL_NUMBER (operands[0])); tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab)); @@ -10146,7 +10103,7 @@ #endif rs6000_emit_load_toc_table (FALSE); DONE; -}") +}) ;; Largetoc support (define_insn "*largetoc_high" @@ -10231,12 +10188,11 @@ ;; Call and call_value insns (define_expand "call" - [(parallel [(call (mem:SI (match_operand 0 "address_operand" "")) - (match_operand 1 "" "")) - (use (match_operand 2 "" "")) + [(parallel [(call (mem:SI (match_operand 0 "address_operand")) + (match_operand 1 "")) + (use (match_operand 2 "")) (clobber (reg:SI LR_REGNO))])] "" - " { #if TARGET_MACHO if (MACHOPIC_INDIRECT) @@ -10271,16 +10227,15 @@ gcc_unreachable (); } } -}") +}) (define_expand "call_value" - [(parallel [(set (match_operand 0 "" "") - (call (mem:SI (match_operand 1 "address_operand" "")) - (match_operand 2 "" ""))) - (use (match_operand 3 "" "")) + [(parallel [(set (match_operand 0 "") + (call (mem:SI (match_operand 1 "address_operand")) + (match_operand 2 ""))) + (use (match_operand 3 "")) (clobber (reg:SI LR_REGNO))])] "" - " { #if TARGET_MACHO if (MACHOPIC_INDIRECT) @@ -10315,7 +10270,7 @@ gcc_unreachable (); } } -}") +}) ;; Call to function in current module. No TOC pointer reload needed. ;; Operand2 is nonzero if we are using the V.4 calling sequence and @@ -10329,16 +10284,15 @@ (use (match_operand:SI 2 "immediate_operand" "O,n")) (clobber (reg:SI LR_REGNO))] "(INTVAL (operands[2]) & CALL_LONG) == 0" - "* { if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) - output_asm_insn (\"crxor 6,6,6\", operands); + output_asm_insn ("crxor 6,6,6", operands); else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) - output_asm_insn (\"creqv 6,6,6\", operands); + output_asm_insn ("creqv 6,6,6", operands); - return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\"; -}" + return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z0@local" : "bl %z0"; +} [(set_attr "type" "branch") (set_attr "length" "4,8")]) @@ -10348,16 +10302,15 @@ (use (match_operand:SI 2 "immediate_operand" "O,n")) (clobber (reg:SI LR_REGNO))] "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0" - "* { if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) - output_asm_insn (\"crxor 6,6,6\", operands); + output_asm_insn ("crxor 6,6,6", operands); else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) - output_asm_insn (\"creqv 6,6,6\", operands); + output_asm_insn ("creqv 6,6,6", operands); - return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\"; -}" + return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z0@local" : "bl %z0"; +} [(set_attr "type" "branch") (set_attr "length" "4,8")]) @@ -10368,16 +10321,15 @@ (use (match_operand:SI 3 "immediate_operand" "O,n")) (clobber (reg:SI LR_REGNO))] "(INTVAL (operands[3]) & CALL_LONG) == 0" - "* { if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) - output_asm_insn (\"crxor 6,6,6\", operands); + output_asm_insn ("crxor 6,6,6", operands); else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) - output_asm_insn (\"creqv 6,6,6\", operands); + output_asm_insn ("creqv 6,6,6", operands); - return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\"; -}" + return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z1@local" : "bl %z1"; +} [(set_attr "type" "branch") (set_attr "length" "4,8")]) @@ -10389,16 +10341,15 @@ (use (match_operand:SI 3 "immediate_operand" "O,n")) (clobber (reg:SI LR_REGNO))] "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0" - "* { if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) - output_asm_insn (\"crxor 6,6,6\", operands); + output_asm_insn ("crxor 6,6,6", operands); else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) - output_asm_insn (\"creqv 6,6,6\", operands); + output_asm_insn ("creqv 6,6,6", operands); - return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\"; -}" + return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z1@local" : "bl %z1"; +} [(set_attr "type" "branch") (set_attr "length" "4,8")]) @@ -10767,12 +10718,11 @@ ;; Call subroutine returning any type. (define_expand "untyped_call" - [(parallel [(call (match_operand 0 "" "") + [(parallel [(call (match_operand 0 "") (const_int 0)) - (match_operand 1 "" "") - (match_operand 2 "" "")])] + (match_operand 1 "") + (match_operand 2 "")])] "" - " { int i; @@ -10791,16 +10741,15 @@ emit_insn (gen_blockage ()); DONE; -}") +}) ;; sibling call patterns (define_expand "sibcall" - [(parallel [(call (mem:SI (match_operand 0 "address_operand" "")) - (match_operand 1 "" "")) - (use (match_operand 2 "" "")) + [(parallel [(call (mem:SI (match_operand 0 "address_operand")) + (match_operand 1 "")) + (use (match_operand 2 "")) (simple_return)])] "" - " { #if TARGET_MACHO if (MACHOPIC_INDIRECT) @@ -10817,16 +10766,15 @@ rs6000_sibcall_aix (NULL_RTX, operands[0], operands[1], operands[2]); DONE; } -}") +}) (define_expand "sibcall_value" - [(parallel [(set (match_operand 0 "register_operand" "") - (call (mem:SI (match_operand 1 "address_operand" "")) - (match_operand 2 "" ""))) - (use (match_operand 3 "" "")) + [(parallel [(set (match_operand 0 "register_operand") + (call (mem:SI (match_operand 1 "address_operand")) + (match_operand 2 ""))) + (use (match_operand 3 "")) (simple_return)])] "" - " { #if TARGET_MACHO if (MACHOPIC_INDIRECT) @@ -10843,7 +10791,7 @@ rs6000_sibcall_aix (operands[0], operands[1], operands[2], operands[3]); DONE; } -}") +}) (define_insn "*sibcall_local32" [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s")) @@ -10851,16 +10799,15 @@ (use (match_operand:SI 2 "immediate_operand" "O,n")) (simple_return)] "(INTVAL (operands[2]) & CALL_LONG) == 0" - "* { if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) - output_asm_insn (\"crxor 6,6,6\", operands); + output_asm_insn ("crxor 6,6,6", operands); else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) - output_asm_insn (\"creqv 6,6,6\", operands); + output_asm_insn ("creqv 6,6,6", operands); - return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\"; -}" + return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "b %z0@local" : "b %z0"; +} [(set_attr "type" "branch") (set_attr "length" "4,8")]) @@ -10870,16 +10817,15 @@ (use (match_operand:SI 2 "immediate_operand" "O,n")) (simple_return)] "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0" - "* { if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) - output_asm_insn (\"crxor 6,6,6\", operands); + output_asm_insn ("crxor 6,6,6", operands); else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) - output_asm_insn (\"creqv 6,6,6\", operands); + output_asm_insn ("creqv 6,6,6", operands); - return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\"; -}" + return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "b %z0@local" : "b %z0"; +} [(set_attr "type" "branch") (set_attr "length" "4,8")]) @@ -10890,16 +10836,15 @@ (use (match_operand:SI 3 "immediate_operand" "O,n")) (simple_return)] "(INTVAL (operands[3]) & CALL_LONG) == 0" - "* { if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) - output_asm_insn (\"crxor 6,6,6\", operands); + output_asm_insn ("crxor 6,6,6", operands); else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) - output_asm_insn (\"creqv 6,6,6\", operands); + output_asm_insn ("creqv 6,6,6", operands); - return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\"; -}" + return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "b %z1@local" : "b %z1"; +} [(set_attr "type" "branch") (set_attr "length" "4,8")]) @@ -10910,16 +10855,15 @@ (use (match_operand:SI 3 "immediate_operand" "O,n")) (simple_return)] "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0" - "* { if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) - output_asm_insn (\"crxor 6,6,6\", operands); + output_asm_insn ("crxor 6,6,6", operands); else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) - output_asm_insn (\"creqv 6,6,6\", operands); + output_asm_insn ("creqv 6,6,6", operands); - return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\"; -}" + return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "b %z1@local" : "b %z1"; +} [(set_attr "type" "branch") (set_attr "length" "4,8")]) @@ -11117,11 +11061,10 @@ (define_expand "cbranch<mode>4" [(use (match_operator 0 "comparison_operator" - [(match_operand:GPR 1 "gpc_reg_operand" "") - (match_operand:GPR 2 "reg_or_short_operand" "")])) - (use (match_operand 3 ""))] + [(match_operand:GPR 1 "gpc_reg_operand") + (match_operand:GPR 2 "reg_or_short_operand")])) + (use (match_operand 3))] "" - " { /* Take care of the possibility that operands[2] might be negative but this might be a logical operation. That insn doesn't exist. */ @@ -11136,19 +11079,18 @@ rs6000_emit_cbranch (<MODE>mode, operands); DONE; -}") +}) (define_expand "cbranch<mode>4" [(use (match_operator 0 "comparison_operator" - [(match_operand:FP 1 "gpc_reg_operand" "") - (match_operand:FP 2 "gpc_reg_operand" "")])) - (use (match_operand 3 ""))] + [(match_operand:FP 1 "gpc_reg_operand") + (match_operand:FP 2 "gpc_reg_operand")])) + (use (match_operand 3))] "" - " { rs6000_emit_cbranch (<MODE>mode, operands); DONE; -}") +}) (define_expand "cstore<mode>4_signed" [(use (match_operator 1 "signed_comparison_operator" @@ -11560,18 +11502,18 @@ (define_peephole2 [(set (match_operand:SI 0 "register_operand") - (match_operand:SI 1 "logical_const_operand" "")) + (match_operand:SI 1 "logical_const_operand")) (set (match_dup 0) (match_operator:SI 3 "boolean_or_operator" [(match_dup 0) - (match_operand:SI 2 "logical_const_operand" "")])) - (set (match_operand:CC 4 "cc_reg_operand" "") - (compare:CC (match_operand:SI 5 "gpc_reg_operand" "") + (match_operand:SI 2 "logical_const_operand")])) + (set (match_operand:CC 4 "cc_reg_operand") + (compare:CC (match_operand:SI 5 "gpc_reg_operand") (match_dup 0))) (set (pc) (if_then_else (match_operator 6 "equality_operator" [(match_dup 4) (const_int 0)]) - (match_operand 7 "" "") - (match_operand 8 "" "")))] + (match_operand 7 "") + (match_operand 8 "")))] "peep2_reg_dead_p (3, operands[0]) && peep2_reg_dead_p (4, operands[4]) && REGNO (operands[0]) != REGNO (operands[5])" @@ -11620,21 +11562,21 @@ [(set_attr "length" "8")]) (define_split - [(set (match_operand:CC 3 "cc_reg_operand" "") - (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "short_cint_operand" ""))) - (set (match_operand:SI 0 "gpc_reg_operand" "") - (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))] + [(set (match_operand:CC 3 "cc_reg_operand") + (compare:CC (match_operand:SI 1 "gpc_reg_operand") + (match_operand:SI 2 "short_cint_operand"))) + (set (match_operand:SI 0 "gpc_reg_operand") + (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand")))] "" [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2))) (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))]) (define_split - [(set (match_operand:CCUNS 3 "cc_reg_operand" "") - (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "u_short_cint_operand" ""))) - (set (match_operand:SI 0 "gpc_reg_operand" "") - (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))] + [(set (match_operand:CCUNS 3 "cc_reg_operand") + (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand") + (match_operand:SI 2 "u_short_cint_operand"))) + (set (match_operand:SI 0 "gpc_reg_operand") + (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand")))] "" [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2))) (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))]) @@ -11773,12 +11715,12 @@ (set_attr "length" "8,16")]) (define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 0 "cc_reg_not_cr0_operand") (compare:CC (match_operator:SI 1 "scc_comparison_operator" - [(match_operand 2 "cc_reg_operand" "") + [(match_operand 2 "cc_reg_operand") (const_int 0)]) (const_int 0))) - (set (match_operand:SI 3 "gpc_reg_operand" "") + (set (match_operand:SI 3 "gpc_reg_operand") (match_op_dup 1 [(match_dup 2) (const_int 0)]))] "TARGET_32BIT && reload_completed" [(set (match_dup 3) @@ -11795,7 +11737,6 @@ (const_int 0)]) (match_operand:SI 3 "const_int_operand" "n")))] "" - "* { int is_bit = ccr_bit (operands[1], 1); int put_bit = 31 - (INTVAL (operands[3]) & 31); @@ -11809,8 +11750,8 @@ operands[4] = GEN_INT (count); operands[5] = GEN_INT (put_bit); - return \"mfcr %0%Q2\;rlwinm %0,%0,%4,%5,%5\"; -}" + return "mfcr %0%Q2\;rlwinm %0,%0,%4,%5,%5"; +} [(set (attr "type") (cond [(match_test "TARGET_MFCRF") (const_string "mfcrf") @@ -11830,7 +11771,6 @@ (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) (match_dup 3)))] "" - "* { int is_bit = ccr_bit (operands[1], 1); int put_bit = 31 - (INTVAL (operands[3]) & 31); @@ -11838,7 +11778,7 @@ /* Force split for non-cc0 compare. */ if (which_alternative == 1) - return \"#\"; + return "#"; if (is_bit >= put_bit) count = is_bit - put_bit; @@ -11848,8 +11788,8 @@ operands[5] = GEN_INT (count); operands[6] = GEN_INT (put_bit); - return \"mfcr %4%Q2\;rlwinm. %4,%4,%5,%6,%6\"; -}" + return "mfcr %4%Q2\;rlwinm. %4,%4,%5,%6,%6"; +} [(set_attr "type" "shift") (set_attr "dot" "yes") (set_attr "length" "8,16")]) @@ -12433,7 +12373,6 @@ "" [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3)) (match_dup 5)))] - " { int positive_1, positive_2; @@ -12469,7 +12408,7 @@ { operands[5] = const1_rtx; } -}") +}) ;; Unconditional branch and return. @@ -12894,7 +12833,6 @@ (match_operand 3 "immediate_operand" "n")] UNSPEC_MOVESI_FROM_CR))])] "TARGET_MFCRF" - "* { int mask = 0; int i; @@ -12902,10 +12840,10 @@ { mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1)); operands[4] = GEN_INT (mask); - output_asm_insn (\"mfcr %1,%4\", operands); + output_asm_insn ("mfcr %1,%4", operands); } - return \"\"; -}" + return ""; +} [(set_attr "type" "mfcrf")]) ;; Don't include the volatile CRs since their values are not used wrt CR save @@ -13064,8 +13002,8 @@ ; faster; for instance, on the 601 and 750. (define_expand "movsi_to_cr_one" - [(set (match_operand:CC 0 "cc_reg_operand" "") - (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "") + [(set (match_operand:CC 0 "cc_reg_operand") + (unspec:CC [(match_operand:SI 1 "gpc_reg_operand") (match_dup 2)] UNSPEC_MOVESI_TO_CR))] "" "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));") @@ -13077,15 +13015,14 @@ (match_operand 3 "immediate_operand" "n")] UNSPEC_MOVESI_TO_CR))])] "" - "* { int mask = 0; int i; for (i = 0; i < XVECLEN (operands[0], 0); i++) mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1)); operands[4] = GEN_INT (mask); - return \"mtcrf %4,%2\"; -}" + return "mtcrf %4,%2"; +} [(set_attr "type" "mtcr")]) (define_insn "*mtcrfsi" @@ -13273,16 +13210,15 @@ ; This is used in compiling the unwind routines. (define_expand "eh_return" - [(use (match_operand 0 "general_operand" ""))] + [(use (match_operand 0 "general_operand"))] "" - " { if (TARGET_32BIT) emit_insn (gen_eh_set_lr_si (operands[0])); else emit_insn (gen_eh_set_lr_di (operands[0])); DONE; -}") +}) ; We can't expand this before we know where the link register is stored. (define_insn "eh_set_lr_<mode>" @@ -13293,27 +13229,25 @@ "#") (define_split - [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR) - (clobber (match_scratch 1 ""))] + [(unspec_volatile [(match_operand 0 "register_operand")] UNSPECV_EH_RR) + (clobber (match_scratch 1))] "reload_completed" [(const_int 0)] - " { rs6000_emit_eh_reg_restore (operands[0], operands[1]); DONE; -}") +}) (define_insn "prefetch" [(prefetch (match_operand 0 "indexed_or_indirect_address" "a") (match_operand:SI 1 "const_int_operand" "n") (match_operand:SI 2 "const_int_operand" "n"))] "" - "* { if (GET_CODE (operands[0]) == REG) - return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\"; - return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\"; -}" + return INTVAL (operands[1]) ? "dcbtst 0,%0" : "dcbt 0,%0"; + return INTVAL (operands[1]) ? "dcbtst %a0" : "dcbt %a0"; +} [(set_attr "type" "load")]) ;; Handle -fsplit-stack. @@ -13397,11 +13331,11 @@ ;; Note that the conditions for expansion are in the FMA_F iterator. (define_expand "fma<mode>4" - [(set (match_operand:FMA_F 0 "gpc_reg_operand" "") + [(set (match_operand:FMA_F 0 "gpc_reg_operand") (fma:FMA_F - (match_operand:FMA_F 1 "gpc_reg_operand" "") - (match_operand:FMA_F 2 "gpc_reg_operand" "") - (match_operand:FMA_F 3 "gpc_reg_operand" "")))] + (match_operand:FMA_F 1 "gpc_reg_operand") + (match_operand:FMA_F 2 "gpc_reg_operand") + (match_operand:FMA_F 3 "gpc_reg_operand")))] "" "") @@ -13421,11 +13355,11 @@ ; Altivec only has fma and nfms. (define_expand "fms<mode>4" - [(set (match_operand:FMA_F 0 "gpc_reg_operand" "") + [(set (match_operand:FMA_F 0 "gpc_reg_operand") (fma:FMA_F - (match_operand:FMA_F 1 "gpc_reg_operand" "") - (match_operand:FMA_F 2 "gpc_reg_operand" "") - (neg:FMA_F (match_operand:FMA_F 3 "gpc_reg_operand" ""))))] + (match_operand:FMA_F 1 "gpc_reg_operand") + (match_operand:FMA_F 2 "gpc_reg_operand") + (neg:FMA_F (match_operand:FMA_F 3 "gpc_reg_operand"))))] "!VECTOR_UNIT_ALTIVEC_P (<MODE>mode)" "") @@ -13445,34 +13379,34 @@ ;; If signed zeros are ignored, -(a * b - c) = -a * b + c. (define_expand "fnma<mode>4" - [(set (match_operand:FMA_F 0 "gpc_reg_operand" "") + [(set (match_operand:FMA_F 0 "gpc_reg_operand") (neg:FMA_F (fma:FMA_F - (match_operand:FMA_F 1 "gpc_reg_operand" "") - (match_operand:FMA_F 2 "gpc_reg_operand" "") - (neg:FMA_F (match_operand:FMA_F 3 "gpc_reg_operand" "")))))] + (match_operand:FMA_F 1 "gpc_reg_operand") + (match_operand:FMA_F 2 "gpc_reg_operand") + (neg:FMA_F (match_operand:FMA_F 3 "gpc_reg_operand")))))] "!HONOR_SIGNED_ZEROS (<MODE>mode)" "") ;; If signed zeros are ignored, -(a * b + c) = -a * b - c. (define_expand "fnms<mode>4" - [(set (match_operand:FMA_F 0 "gpc_reg_operand" "") + [(set (match_operand:FMA_F 0 "gpc_reg_operand") (neg:FMA_F (fma:FMA_F - (match_operand:FMA_F 1 "gpc_reg_operand" "") - (match_operand:FMA_F 2 "gpc_reg_operand" "") - (match_operand:FMA_F 3 "gpc_reg_operand" ""))))] + (match_operand:FMA_F 1 "gpc_reg_operand") + (match_operand:FMA_F 2 "gpc_reg_operand") + (match_operand:FMA_F 3 "gpc_reg_operand"))))] "!HONOR_SIGNED_ZEROS (<MODE>mode) && !VECTOR_UNIT_ALTIVEC_P (<MODE>mode)" "") ; Not an official optab name, but used from builtins. (define_expand "nfma<mode>4" - [(set (match_operand:FMA_F 0 "gpc_reg_operand" "") + [(set (match_operand:FMA_F 0 "gpc_reg_operand") (neg:FMA_F (fma:FMA_F - (match_operand:FMA_F 1 "gpc_reg_operand" "") - (match_operand:FMA_F 2 "gpc_reg_operand" "") - (match_operand:FMA_F 3 "gpc_reg_operand" ""))))] + (match_operand:FMA_F 1 "gpc_reg_operand") + (match_operand:FMA_F 2 "gpc_reg_operand") + (match_operand:FMA_F 3 "gpc_reg_operand"))))] "!VECTOR_UNIT_ALTIVEC_P (<MODE>mode)" "") @@ -13493,12 +13427,12 @@ ; Not an official optab name, but used from builtins. (define_expand "nfms<mode>4" - [(set (match_operand:FMA_F 0 "gpc_reg_operand" "") + [(set (match_operand:FMA_F 0 "gpc_reg_operand") (neg:FMA_F (fma:FMA_F - (match_operand:FMA_F 1 "gpc_reg_operand" "") - (match_operand:FMA_F 2 "gpc_reg_operand" "") - (neg:FMA_F (match_operand:FMA_F 3 "gpc_reg_operand" "")))))] + (match_operand:FMA_F 1 "gpc_reg_operand") + (match_operand:FMA_F 2 "gpc_reg_operand") + (neg:FMA_F (match_operand:FMA_F 3 "gpc_reg_operand")))))] "" "") @@ -13520,7 +13454,7 @@ (define_expand "rs6000_get_timebase" - [(use (match_operand:DI 0 "gpc_reg_operand" ""))] + [(use (match_operand:DI 0 "gpc_reg_operand"))] "" { if (TARGET_POWERPC64) @@ -13618,8 +13552,8 @@ ;; (addis followed by load) even on power8. (define_split - [(set (match_operand:INT1 0 "toc_fusion_or_p9_reg_operand" "") - (match_operand:INT1 1 "toc_fusion_mem_raw" ""))] + [(set (match_operand:INT1 0 "toc_fusion_or_p9_reg_operand") + (match_operand:INT1 1 "toc_fusion_mem_raw"))] "TARGET_TOC_FUSION_INT && can_create_pseudo_p ()" [(parallel [(set (match_dup 0) (match_dup 2)) (unspec [(const_int 0)] UNSPEC_FUSION_ADDIS) @@ -13669,10 +13603,10 @@ ;; insn (define_peephole2 - [(set (match_operand:P 0 "base_reg_operand" "") - (match_operand:P 1 "fusion_gpr_addis" "")) - (set (match_operand:INT1 2 "base_reg_operand" "") - (match_operand:INT1 3 "fusion_gpr_mem_load" ""))] + [(set (match_operand:P 0 "base_reg_operand") + (match_operand:P 1 "fusion_gpr_addis")) + (set (match_operand:INT1 2 "base_reg_operand") + (match_operand:INT1 3 "fusion_gpr_mem_load"))] "TARGET_P8_FUSION && fusion_gpr_load_p (operands[0], operands[1], operands[2], operands[3])" @@ -13700,10 +13634,10 @@ ;; ISA 3.0 (power9) fusion support ;; Merge addis with floating load/store to FPRs (or GPRs). (define_peephole2 - [(set (match_operand:P 0 "base_reg_operand" "") - (match_operand:P 1 "fusion_gpr_addis" "")) - (set (match_operand:SFDF 2 "toc_fusion_or_p9_reg_operand" "") - (match_operand:SFDF 3 "fusion_offsettable_mem_operand" ""))] + [(set (match_operand:P 0 "base_reg_operand") + (match_operand:P 1 "fusion_gpr_addis")) + (set (match_operand:SFDF 2 "toc_fusion_or_p9_reg_operand") + (match_operand:SFDF 3 "fusion_offsettable_mem_operand"))] "TARGET_P9_FUSION && peep2_reg_dead_p (2, operands[0]) && fusion_p9_p (operands[0], operands[1], operands[2], operands[3])" [(const_int 0)] @@ -13713,10 +13647,10 @@ }) (define_peephole2 - [(set (match_operand:P 0 "base_reg_operand" "") - (match_operand:P 1 "fusion_gpr_addis" "")) - (set (match_operand:SFDF 2 "offsettable_mem_operand" "") - (match_operand:SFDF 3 "toc_fusion_or_p9_reg_operand" ""))] + [(set (match_operand:P 0 "base_reg_operand") + (match_operand:P 1 "fusion_gpr_addis")) + (set (match_operand:SFDF 2 "offsettable_mem_operand") + (match_operand:SFDF 3 "toc_fusion_or_p9_reg_operand"))] "TARGET_P9_FUSION && peep2_reg_dead_p (2, operands[0]) && fusion_p9_p (operands[0], operands[1], operands[2], operands[3]) && !rtx_equal_p (operands[0], operands[3])" @@ -13727,22 +13661,22 @@ }) (define_peephole2 - [(set (match_operand:SDI 0 "int_reg_operand" "") - (match_operand:SDI 1 "upper16_cint_operand" "")) + [(set (match_operand:SDI 0 "int_reg_operand") + (match_operand:SDI 1 "upper16_cint_operand")) (set (match_dup 0) (ior:SDI (match_dup 0) - (match_operand:SDI 2 "u_short_cint_operand" "")))] + (match_operand:SDI 2 "u_short_cint_operand")))] "TARGET_P9_FUSION" [(set (match_dup 0) (unspec:SDI [(match_dup 1) (match_dup 2)] UNSPEC_FUSION_P9))]) (define_peephole2 - [(set (match_operand:SDI 0 "int_reg_operand" "") - (match_operand:SDI 1 "upper16_cint_operand" "")) - (set (match_operand:SDI 2 "int_reg_operand" "") + [(set (match_operand:SDI 0 "int_reg_operand") + (match_operand:SDI 1 "upper16_cint_operand")) + (set (match_operand:SDI 2 "int_reg_operand") (ior:SDI (match_dup 0) - (match_operand:SDI 3 "u_short_cint_operand" "")))] + (match_operand:SDI 3 "u_short_cint_operand")))] "TARGET_P9_FUSION && !rtx_equal_p (operands[0], operands[2]) && peep2_reg_dead_p (2, operands[0])" @@ -13958,10 +13892,10 @@ (KF "DI")]) (define_expand "unpack<mode>" - [(set (match_operand:<FP128_64> 0 "nonimmediate_operand" "") + [(set (match_operand:<FP128_64> 0 "nonimmediate_operand") (unspec:<FP128_64> - [(match_operand:FMOVE128 1 "register_operand" "") - (match_operand:QI 2 "const_0_to_1_operand" "")] + [(match_operand:FMOVE128 1 "register_operand") + (match_operand:QI 2 "const_0_to_1_operand")] UNSPEC_UNPACK_128BIT))] "FLOAT128_2REG_P (<MODE>mode)" "") diff --git a/gcc/config/rs6000/sync.md b/gcc/config/rs6000/sync.md index f4f7bc2151d..74bc407b462 100644 --- a/gcc/config/rs6000/sync.md +++ b/gcc/config/rs6000/sync.md @@ -38,7 +38,7 @@ (ior "logical_operand") (xor "logical_operand") (and "and_operand")]) (define_expand "mem_thread_fence" - [(match_operand:SI 0 "const_int_operand" "")] ;; model + [(match_operand:SI 0 "const_int_operand")] ;; model "" { enum memmodel model = memmodel_base (INTVAL (operands[0])); @@ -136,9 +136,9 @@ (set_attr "length" "4")]) (define_expand "atomic_load<mode>" - [(set (match_operand:AINT 0 "register_operand" "") ;; output - (match_operand:AINT 1 "memory_operand" "")) ;; memory - (use (match_operand:SI 2 "const_int_operand" ""))] ;; model + [(set (match_operand:AINT 0 "register_operand") ;; output + (match_operand:AINT 1 "memory_operand")) ;; memory + (use (match_operand:SI 2 "const_int_operand"))] ;; model "" { if (<MODE>mode == TImode && !TARGET_SYNC_TI) @@ -200,9 +200,9 @@ (set_attr "length" "4")]) (define_expand "atomic_store<mode>" - [(set (match_operand:AINT 0 "memory_operand" "") ;; memory - (match_operand:AINT 1 "register_operand" "")) ;; input - (use (match_operand:SI 2 "const_int_operand" ""))] ;; model + [(set (match_operand:AINT 0 "memory_operand") ;; memory + (match_operand:AINT 1 "register_operand")) ;; input + (use (match_operand:SI 2 "const_int_operand"))] ;; model "" { if (<MODE>mode == TImode && !TARGET_SYNC_TI) @@ -287,8 +287,8 @@ ;; is indexed or indirect before register allocation. (define_expand "load_lockedti" - [(use (match_operand:TI 0 "quad_int_reg_operand" "")) - (use (match_operand:TI 1 "memory_operand" ""))] + [(use (match_operand:TI 0 "quad_int_reg_operand")) + (use (match_operand:TI 1 "memory_operand"))] "TARGET_SYNC_TI" { rtx op0 = operands[0]; @@ -341,9 +341,9 @@ ;; is indexed or indirect before register allocation. (define_expand "store_conditionalti" - [(use (match_operand:CC 0 "cc_reg_operand" "")) - (use (match_operand:TI 1 "memory_operand" "")) - (use (match_operand:TI 2 "quad_int_reg_operand" ""))] + [(use (match_operand:CC 0 "cc_reg_operand")) + (use (match_operand:TI 1 "memory_operand")) + (use (match_operand:TI 2 "quad_int_reg_operand"))] "TARGET_SYNC_TI" { rtx op0 = operands[0]; @@ -385,14 +385,14 @@ [(set_attr "type" "store_c")]) (define_expand "atomic_compare_and_swap<mode>" - [(match_operand:SI 0 "int_reg_operand" "") ;; bool out - (match_operand:AINT 1 "int_reg_operand" "") ;; val out - (match_operand:AINT 2 "memory_operand" "") ;; memory - (match_operand:AINT 3 "reg_or_short_operand" "") ;; expected - (match_operand:AINT 4 "int_reg_operand" "") ;; desired - (match_operand:SI 5 "const_int_operand" "") ;; is_weak - (match_operand:SI 6 "const_int_operand" "") ;; model succ - (match_operand:SI 7 "const_int_operand" "")] ;; model fail + [(match_operand:SI 0 "int_reg_operand") ;; bool out + (match_operand:AINT 1 "int_reg_operand") ;; val out + (match_operand:AINT 2 "memory_operand") ;; memory + (match_operand:AINT 3 "reg_or_short_operand") ;; expected + (match_operand:AINT 4 "int_reg_operand") ;; desired + (match_operand:SI 5 "const_int_operand") ;; is_weak + (match_operand:SI 6 "const_int_operand") ;; model succ + (match_operand:SI 7 "const_int_operand")] ;; model fail "" { rs6000_expand_atomic_compare_and_swap (operands); @@ -400,10 +400,10 @@ }) (define_expand "atomic_exchange<mode>" - [(match_operand:AINT 0 "int_reg_operand" "") ;; output - (match_operand:AINT 1 "memory_operand" "") ;; memory - (match_operand:AINT 2 "int_reg_operand" "") ;; input - (match_operand:SI 3 "const_int_operand" "")] ;; model + [(match_operand:AINT 0 "int_reg_operand") ;; output + (match_operand:AINT 1 "memory_operand") ;; memory + (match_operand:AINT 2 "int_reg_operand") ;; input + (match_operand:SI 3 "const_int_operand")] ;; model "" { rs6000_expand_atomic_exchange (operands); @@ -411,10 +411,10 @@ }) (define_expand "atomic_<fetchop_name><mode>" - [(match_operand:AINT 0 "memory_operand" "") ;; memory + [(match_operand:AINT 0 "memory_operand") ;; memory (FETCHOP:AINT (match_dup 0) - (match_operand:AINT 1 "<fetchop_pred>" "")) ;; operand - (match_operand:SI 2 "const_int_operand" "")] ;; model + (match_operand:AINT 1 "<fetchop_pred>")) ;; operand + (match_operand:SI 2 "const_int_operand")] ;; model "" { rs6000_expand_atomic_op (<CODE>, operands[0], operands[1], @@ -423,9 +423,9 @@ }) (define_expand "atomic_nand<mode>" - [(match_operand:AINT 0 "memory_operand" "") ;; memory - (match_operand:AINT 1 "int_reg_operand" "") ;; operand - (match_operand:SI 2 "const_int_operand" "")] ;; model + [(match_operand:AINT 0 "memory_operand") ;; memory + (match_operand:AINT 1 "int_reg_operand") ;; operand + (match_operand:SI 2 "const_int_operand")] ;; model "" { rs6000_expand_atomic_op (NOT, operands[0], operands[1], @@ -434,11 +434,11 @@ }) (define_expand "atomic_fetch_<fetchop_name><mode>" - [(match_operand:AINT 0 "int_reg_operand" "") ;; output - (match_operand:AINT 1 "memory_operand" "") ;; memory + [(match_operand:AINT 0 "int_reg_operand") ;; output + (match_operand:AINT 1 "memory_operand") ;; memory (FETCHOP:AINT (match_dup 1) - (match_operand:AINT 2 "<fetchop_pred>" "")) ;; operand - (match_operand:SI 3 "const_int_operand" "")] ;; model + (match_operand:AINT 2 "<fetchop_pred>")) ;; operand + (match_operand:SI 3 "const_int_operand")] ;; model "" { rs6000_expand_atomic_op (<CODE>, operands[1], operands[2], @@ -447,10 +447,10 @@ }) (define_expand "atomic_fetch_nand<mode>" - [(match_operand:AINT 0 "int_reg_operand" "") ;; output - (match_operand:AINT 1 "memory_operand" "") ;; memory - (match_operand:AINT 2 "int_reg_operand" "") ;; operand - (match_operand:SI 3 "const_int_operand" "")] ;; model + [(match_operand:AINT 0 "int_reg_operand") ;; output + (match_operand:AINT 1 "memory_operand") ;; memory + (match_operand:AINT 2 "int_reg_operand") ;; operand + (match_operand:SI 3 "const_int_operand")] ;; model "" { rs6000_expand_atomic_op (NOT, operands[1], operands[2], @@ -459,11 +459,11 @@ }) (define_expand "atomic_<fetchop_name>_fetch<mode>" - [(match_operand:AINT 0 "int_reg_operand" "") ;; output - (match_operand:AINT 1 "memory_operand" "") ;; memory + [(match_operand:AINT 0 "int_reg_operand") ;; output + (match_operand:AINT 1 "memory_operand") ;; memory (FETCHOP:AINT (match_dup 1) - (match_operand:AINT 2 "<fetchop_pred>" "")) ;; operand - (match_operand:SI 3 "const_int_operand" "")] ;; model + (match_operand:AINT 2 "<fetchop_pred>")) ;; operand + (match_operand:SI 3 "const_int_operand")] ;; model "" { rs6000_expand_atomic_op (<CODE>, operands[1], operands[2], @@ -472,10 +472,10 @@ }) (define_expand "atomic_nand_fetch<mode>" - [(match_operand:AINT 0 "int_reg_operand" "") ;; output - (match_operand:AINT 1 "memory_operand" "") ;; memory - (match_operand:AINT 2 "int_reg_operand" "") ;; operand - (match_operand:SI 3 "const_int_operand" "")] ;; model + [(match_operand:AINT 0 "int_reg_operand") ;; output + (match_operand:AINT 1 "memory_operand") ;; memory + (match_operand:AINT 2 "int_reg_operand") ;; operand + (match_operand:SI 3 "const_int_operand")] ;; model "" { rs6000_expand_atomic_op (NOT, operands[1], operands[2], diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md index 3bcf087d2cd..6e2576ee1d8 100644 --- a/gcc/config/rs6000/vector.md +++ b/gcc/config/rs6000/vector.md @@ -111,8 +111,8 @@ ;; Vector move instructions. Little-endian VSX loads and stores require ;; special handling to circumvent "element endianness." (define_expand "mov<mode>" - [(set (match_operand:VEC_M 0 "nonimmediate_operand" "") - (match_operand:VEC_M 1 "any_operand" ""))] + [(set (match_operand:VEC_M 0 "nonimmediate_operand") + (match_operand:VEC_M 1 "any_operand"))] "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)" { if (can_create_pseudo_p ()) @@ -147,21 +147,21 @@ ;; Generic vector floating point load/store instructions. These will match ;; insns defined in vsx.md or altivec.md depending on the switches. (define_expand "vector_load_<mode>" - [(set (match_operand:VEC_M 0 "vfloat_operand" "") - (match_operand:VEC_M 1 "memory_operand" ""))] + [(set (match_operand:VEC_M 0 "vfloat_operand") + (match_operand:VEC_M 1 "memory_operand"))] "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)" "") (define_expand "vector_store_<mode>" - [(set (match_operand:VEC_M 0 "memory_operand" "") - (match_operand:VEC_M 1 "vfloat_operand" ""))] + [(set (match_operand:VEC_M 0 "memory_operand") + (match_operand:VEC_M 1 "vfloat_operand"))] "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)" "") ;; Splits if a GPR register was chosen for the move (define_split - [(set (match_operand:VEC_L 0 "nonimmediate_operand" "") - (match_operand:VEC_L 1 "input_operand" ""))] + [(set (match_operand:VEC_L 0 "nonimmediate_operand") + (match_operand:VEC_L 1 "input_operand"))] "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode) && reload_completed && gpr_or_gpr_p (operands[0], operands[1]) @@ -178,10 +178,9 @@ ;; instructions silently ignore the bottom 3 bits of the address, and VSX does ;; not. (define_expand "vector_altivec_load_<mode>" - [(set (match_operand:VEC_M 0 "vfloat_operand" "") - (match_operand:VEC_M 1 "memory_operand" ""))] + [(set (match_operand:VEC_M 0 "vfloat_operand") + (match_operand:VEC_M 1 "memory_operand"))] "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)" - " { gcc_assert (VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)); @@ -198,13 +197,12 @@ emit_insn (gen_altivec_lvx_<mode>_1op (operands[0], operands[1])); DONE; } -}") +}) (define_expand "vector_altivec_store_<mode>" - [(set (match_operand:VEC_M 0 "memory_operand" "") - (match_operand:VEC_M 1 "vfloat_operand" ""))] + [(set (match_operand:VEC_M 0 "memory_operand") + (match_operand:VEC_M 1 "vfloat_operand"))] "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)" - " { gcc_assert (VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)); @@ -221,29 +219,29 @@ emit_insn (gen_altivec_stvx_<mode>_1op (operands[1], operands[0])); DONE; } -}") +}) ;; Generic floating point vector arithmetic support (define_expand "add<mode>3" - [(set (match_operand:VEC_F 0 "vfloat_operand" "") - (plus:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "") - (match_operand:VEC_F 2 "vfloat_operand" "")))] + [(set (match_operand:VEC_F 0 "vfloat_operand") + (plus:VEC_F (match_operand:VEC_F 1 "vfloat_operand") + (match_operand:VEC_F 2 "vfloat_operand")))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" "") (define_expand "sub<mode>3" - [(set (match_operand:VEC_F 0 "vfloat_operand" "") - (minus:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "") - (match_operand:VEC_F 2 "vfloat_operand" "")))] + [(set (match_operand:VEC_F 0 "vfloat_operand") + (minus:VEC_F (match_operand:VEC_F 1 "vfloat_operand") + (match_operand:VEC_F 2 "vfloat_operand")))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" "") (define_expand "mul<mode>3" - [(set (match_operand:VEC_F 0 "vfloat_operand" "") - (mult:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "") - (match_operand:VEC_F 2 "vfloat_operand" "")))] + [(set (match_operand:VEC_F 0 "vfloat_operand") + (mult:VEC_F (match_operand:VEC_F 1 "vfloat_operand") + (match_operand:VEC_F 2 "vfloat_operand")))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" { if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode)) @@ -254,9 +252,9 @@ }) (define_expand "div<mode>3" - [(set (match_operand:VEC_F 0 "vfloat_operand" "") - (div:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "") - (match_operand:VEC_F 2 "vfloat_operand" "")))] + [(set (match_operand:VEC_F 0 "vfloat_operand") + (div:VEC_F (match_operand:VEC_F 1 "vfloat_operand") + (match_operand:VEC_F 2 "vfloat_operand")))] "VECTOR_UNIT_VSX_P (<MODE>mode)" { if (RS6000_RECIP_AUTO_RE_P (<MODE>mode) @@ -269,49 +267,47 @@ }) (define_expand "neg<mode>2" - [(set (match_operand:VEC_F 0 "vfloat_operand" "") - (neg:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")))] + [(set (match_operand:VEC_F 0 "vfloat_operand") + (neg:VEC_F (match_operand:VEC_F 1 "vfloat_operand")))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" - " { if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode)) { emit_insn (gen_altivec_negv4sf2 (operands[0], operands[1])); DONE; } -}") +}) (define_expand "abs<mode>2" - [(set (match_operand:VEC_F 0 "vfloat_operand" "") - (abs:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")))] + [(set (match_operand:VEC_F 0 "vfloat_operand") + (abs:VEC_F (match_operand:VEC_F 1 "vfloat_operand")))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" - " { if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode)) { emit_insn (gen_altivec_absv4sf2 (operands[0], operands[1])); DONE; } -}") +}) (define_expand "smin<mode>3" - [(set (match_operand:VEC_F 0 "register_operand" "") - (smin:VEC_F (match_operand:VEC_F 1 "register_operand" "") - (match_operand:VEC_F 2 "register_operand" "")))] + [(set (match_operand:VEC_F 0 "register_operand") + (smin:VEC_F (match_operand:VEC_F 1 "register_operand") + (match_operand:VEC_F 2 "register_operand")))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" "") (define_expand "smax<mode>3" - [(set (match_operand:VEC_F 0 "register_operand" "") - (smax:VEC_F (match_operand:VEC_F 1 "register_operand" "") - (match_operand:VEC_F 2 "register_operand" "")))] + [(set (match_operand:VEC_F 0 "register_operand") + (smax:VEC_F (match_operand:VEC_F 1 "register_operand") + (match_operand:VEC_F 2 "register_operand")))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" "") (define_expand "sqrt<mode>2" - [(set (match_operand:VEC_F 0 "vfloat_operand" "") - (sqrt:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")))] + [(set (match_operand:VEC_F 0 "vfloat_operand") + (sqrt:VEC_F (match_operand:VEC_F 1 "vfloat_operand")))] "VECTOR_UNIT_VSX_P (<MODE>mode)" { if (<MODE>mode == V4SFmode @@ -325,51 +321,50 @@ }) (define_expand "rsqrte<mode>2" - [(set (match_operand:VEC_F 0 "vfloat_operand" "") - (unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand" "")] + [(set (match_operand:VEC_F 0 "vfloat_operand") + (unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand")] UNSPEC_RSQRT))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" "") (define_expand "re<mode>2" - [(set (match_operand:VEC_F 0 "vfloat_operand" "") - (unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand" "f")] + [(set (match_operand:VEC_F 0 "vfloat_operand") + (unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand")] UNSPEC_FRES))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" "") (define_expand "ftrunc<mode>2" - [(set (match_operand:VEC_F 0 "vfloat_operand" "") - (fix:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")))] + [(set (match_operand:VEC_F 0 "vfloat_operand") + (fix:VEC_F (match_operand:VEC_F 1 "vfloat_operand")))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" "") (define_expand "vector_ceil<mode>2" - [(set (match_operand:VEC_F 0 "vfloat_operand" "") - (unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand" "")] + [(set (match_operand:VEC_F 0 "vfloat_operand") + (unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand")] UNSPEC_FRIP))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" "") (define_expand "vector_floor<mode>2" - [(set (match_operand:VEC_F 0 "vfloat_operand" "") - (unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand" "")] + [(set (match_operand:VEC_F 0 "vfloat_operand") + (unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand")] UNSPEC_FRIM))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" "") (define_expand "vector_btrunc<mode>2" - [(set (match_operand:VEC_F 0 "vfloat_operand" "") - (fix:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")))] + [(set (match_operand:VEC_F 0 "vfloat_operand") + (fix:VEC_F (match_operand:VEC_F 1 "vfloat_operand")))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" "") (define_expand "vector_copysign<mode>3" - [(set (match_operand:VEC_F 0 "vfloat_operand" "") - (unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand" "") - (match_operand:VEC_F 2 "vfloat_operand" "")] UNSPEC_COPYSIGN))] + [(set (match_operand:VEC_F 0 "vfloat_operand") + (unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand") + (match_operand:VEC_F 2 "vfloat_operand")] UNSPEC_COPYSIGN))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" - " { if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode)) { @@ -377,27 +372,26 @@ operands[2])); DONE; } -}") +}) ;; Vector comparisons (define_expand "vcond<mode><mode>" - [(set (match_operand:VEC_F 0 "vfloat_operand" "") + [(set (match_operand:VEC_F 0 "vfloat_operand") (if_then_else:VEC_F (match_operator 3 "comparison_operator" - [(match_operand:VEC_F 4 "vfloat_operand" "") - (match_operand:VEC_F 5 "vfloat_operand" "")]) - (match_operand:VEC_F 1 "vfloat_operand" "") - (match_operand:VEC_F 2 "vfloat_operand" "")))] + [(match_operand:VEC_F 4 "vfloat_operand") + (match_operand:VEC_F 5 "vfloat_operand")]) + (match_operand:VEC_F 1 "vfloat_operand") + (match_operand:VEC_F 2 "vfloat_operand")))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" - " { if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2], operands[3], operands[4], operands[5])) DONE; else FAIL; -}") +}) (define_expand "vcond<mode><mode>" [(set (match_operand:VEC_I 0 "vint_operand") @@ -408,52 +402,49 @@ (match_operand:VEC_I 1 "vector_int_reg_or_same_bit") (match_operand:VEC_I 2 "vector_int_reg_or_same_bit")))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" - " { if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2], operands[3], operands[4], operands[5])) DONE; else FAIL; -}") +}) (define_expand "vcondv4sfv4si" - [(set (match_operand:V4SF 0 "vfloat_operand" "") + [(set (match_operand:V4SF 0 "vfloat_operand") (if_then_else:V4SF (match_operator 3 "comparison_operator" - [(match_operand:V4SI 4 "vint_operand" "") - (match_operand:V4SI 5 "vint_operand" "")]) - (match_operand:V4SF 1 "vfloat_operand" "") - (match_operand:V4SF 2 "vfloat_operand" "")))] + [(match_operand:V4SI 4 "vint_operand") + (match_operand:V4SI 5 "vint_operand")]) + (match_operand:V4SF 1 "vfloat_operand") + (match_operand:V4SF 2 "vfloat_operand")))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode) && VECTOR_UNIT_ALTIVEC_P (V4SImode)" - " { if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2], operands[3], operands[4], operands[5])) DONE; else FAIL; -}") +}) (define_expand "vcondv4siv4sf" - [(set (match_operand:V4SI 0 "vint_operand" "") + [(set (match_operand:V4SI 0 "vint_operand") (if_then_else:V4SI (match_operator 3 "comparison_operator" - [(match_operand:V4SF 4 "vfloat_operand" "") - (match_operand:V4SF 5 "vfloat_operand" "")]) - (match_operand:V4SI 1 "vint_operand" "") - (match_operand:V4SI 2 "vint_operand" "")))] + [(match_operand:V4SF 4 "vfloat_operand") + (match_operand:V4SF 5 "vfloat_operand")]) + (match_operand:V4SI 1 "vint_operand") + (match_operand:V4SI 2 "vint_operand")))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode) && VECTOR_UNIT_ALTIVEC_P (V4SImode)" - " { if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2], operands[3], operands[4], operands[5])) DONE; else FAIL; -}") +}) (define_expand "vcondv2dfv2di" [(set (match_operand:V2DF 0 "vfloat_operand") @@ -500,33 +491,31 @@ (match_operand:VEC_I 1 "vector_int_reg_or_same_bit") (match_operand:VEC_I 2 "vector_int_reg_or_same_bit")))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" - " { if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2], operands[3], operands[4], operands[5])) DONE; else FAIL; -}") +}) (define_expand "vconduv4sfv4si" - [(set (match_operand:V4SF 0 "vfloat_operand" "") + [(set (match_operand:V4SF 0 "vfloat_operand") (if_then_else:V4SF (match_operator 3 "comparison_operator" - [(match_operand:V4SI 4 "vint_operand" "") - (match_operand:V4SI 5 "vint_operand" "")]) - (match_operand:V4SF 1 "vfloat_operand" "") - (match_operand:V4SF 2 "vfloat_operand" "")))] + [(match_operand:V4SI 4 "vint_operand") + (match_operand:V4SI 5 "vint_operand")]) + (match_operand:V4SF 1 "vfloat_operand") + (match_operand:V4SF 2 "vfloat_operand")))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode) && VECTOR_UNIT_ALTIVEC_P (V4SImode)" - " { if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2], operands[3], operands[4], operands[5])) DONE; else FAIL; -}") +}) (define_expand "vconduv2dfv2di" [(set (match_operand:V2DF 0 "vfloat_operand") @@ -547,95 +536,91 @@ }) (define_expand "vector_eq<mode>" - [(set (match_operand:VEC_C 0 "vlogical_operand" "") - (eq:VEC_C (match_operand:VEC_C 1 "vlogical_operand" "") - (match_operand:VEC_C 2 "vlogical_operand" "")))] + [(set (match_operand:VEC_C 0 "vlogical_operand") + (eq:VEC_C (match_operand:VEC_C 1 "vlogical_operand") + (match_operand:VEC_C 2 "vlogical_operand")))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" "") (define_expand "vector_gt<mode>" - [(set (match_operand:VEC_C 0 "vlogical_operand" "") - (gt:VEC_C (match_operand:VEC_C 1 "vlogical_operand" "") - (match_operand:VEC_C 2 "vlogical_operand" "")))] + [(set (match_operand:VEC_C 0 "vlogical_operand") + (gt:VEC_C (match_operand:VEC_C 1 "vlogical_operand") + (match_operand:VEC_C 2 "vlogical_operand")))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" "") (define_expand "vector_ge<mode>" - [(set (match_operand:VEC_F 0 "vlogical_operand" "") - (ge:VEC_F (match_operand:VEC_F 1 "vlogical_operand" "") - (match_operand:VEC_F 2 "vlogical_operand" "")))] + [(set (match_operand:VEC_F 0 "vlogical_operand") + (ge:VEC_F (match_operand:VEC_F 1 "vlogical_operand") + (match_operand:VEC_F 2 "vlogical_operand")))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" "") ; >= for integer vectors: swap operands and apply not-greater-than (define_expand "vector_nlt<mode>" - [(set (match_operand:VEC_I 3 "vlogical_operand" "") - (gt:VEC_I (match_operand:VEC_I 2 "vlogical_operand" "") - (match_operand:VEC_I 1 "vlogical_operand" ""))) - (set (match_operand:VEC_I 0 "vlogical_operand" "") + [(set (match_operand:VEC_I 3 "vlogical_operand") + (gt:VEC_I (match_operand:VEC_I 2 "vlogical_operand") + (match_operand:VEC_I 1 "vlogical_operand"))) + (set (match_operand:VEC_I 0 "vlogical_operand") (not:VEC_I (match_dup 3)))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" - " { operands[3] = gen_reg_rtx_and_attrs (operands[0]); -}") +}) (define_expand "vector_gtu<mode>" - [(set (match_operand:VEC_I 0 "vint_operand" "") - (gtu:VEC_I (match_operand:VEC_I 1 "vint_operand" "") - (match_operand:VEC_I 2 "vint_operand" "")))] + [(set (match_operand:VEC_I 0 "vint_operand") + (gtu:VEC_I (match_operand:VEC_I 1 "vint_operand") + (match_operand:VEC_I 2 "vint_operand")))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" "") ; >= for integer vectors: swap operands and apply not-greater-than (define_expand "vector_nltu<mode>" - [(set (match_operand:VEC_I 3 "vlogical_operand" "") - (gtu:VEC_I (match_operand:VEC_I 2 "vlogical_operand" "") - (match_operand:VEC_I 1 "vlogical_operand" ""))) - (set (match_operand:VEC_I 0 "vlogical_operand" "") + [(set (match_operand:VEC_I 3 "vlogical_operand") + (gtu:VEC_I (match_operand:VEC_I 2 "vlogical_operand") + (match_operand:VEC_I 1 "vlogical_operand"))) + (set (match_operand:VEC_I 0 "vlogical_operand") (not:VEC_I (match_dup 3)))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" - " { operands[3] = gen_reg_rtx_and_attrs (operands[0]); -}") +}) (define_expand "vector_geu<mode>" - [(set (match_operand:VEC_I 0 "vint_operand" "") - (geu:VEC_I (match_operand:VEC_I 1 "vint_operand" "") - (match_operand:VEC_I 2 "vint_operand" "")))] + [(set (match_operand:VEC_I 0 "vint_operand") + (geu:VEC_I (match_operand:VEC_I 1 "vint_operand") + (match_operand:VEC_I 2 "vint_operand")))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" "") ; <= for integer vectors: apply not-greater-than (define_expand "vector_ngt<mode>" - [(set (match_operand:VEC_I 3 "vlogical_operand" "") - (gt:VEC_I (match_operand:VEC_I 1 "vlogical_operand" "") - (match_operand:VEC_I 2 "vlogical_operand" ""))) - (set (match_operand:VEC_I 0 "vlogical_operand" "") + [(set (match_operand:VEC_I 3 "vlogical_operand") + (gt:VEC_I (match_operand:VEC_I 1 "vlogical_operand") + (match_operand:VEC_I 2 "vlogical_operand"))) + (set (match_operand:VEC_I 0 "vlogical_operand") (not:VEC_I (match_dup 3)))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" - " { operands[3] = gen_reg_rtx_and_attrs (operands[0]); -}") +}) (define_expand "vector_ngtu<mode>" - [(set (match_operand:VEC_I 3 "vlogical_operand" "") - (gtu:VEC_I (match_operand:VEC_I 1 "vlogical_operand" "") - (match_operand:VEC_I 2 "vlogical_operand" ""))) - (set (match_operand:VEC_I 0 "vlogical_operand" "") + [(set (match_operand:VEC_I 3 "vlogical_operand") + (gtu:VEC_I (match_operand:VEC_I 1 "vlogical_operand") + (match_operand:VEC_I 2 "vlogical_operand"))) + (set (match_operand:VEC_I 0 "vlogical_operand") (not:VEC_I (match_dup 3)))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" - " { operands[3] = gen_reg_rtx_and_attrs (operands[0]); -}") +}) (define_insn_and_split "*vector_uneq<mode>" - [(set (match_operand:VEC_F 0 "vfloat_operand" "") - (uneq:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "") - (match_operand:VEC_F 2 "vfloat_operand" "")))] + [(set (match_operand:VEC_F 0 "vfloat_operand") + (uneq:VEC_F (match_operand:VEC_F 1 "vfloat_operand") + (match_operand:VEC_F 2 "vfloat_operand")))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" "#" "" @@ -654,9 +639,9 @@ }) (define_insn_and_split "*vector_ltgt<mode>" - [(set (match_operand:VEC_F 0 "vfloat_operand" "") - (ltgt:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "") - (match_operand:VEC_F 2 "vfloat_operand" "")))] + [(set (match_operand:VEC_F 0 "vfloat_operand") + (ltgt:VEC_F (match_operand:VEC_F 1 "vfloat_operand") + (match_operand:VEC_F 2 "vfloat_operand")))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" "#" "" @@ -669,16 +654,15 @@ (set (match_dup 0) (ior:VEC_F (match_dup 3) (match_dup 4)))] - " { operands[3] = gen_reg_rtx (<MODE>mode); operands[4] = gen_reg_rtx (<MODE>mode); -}") +}) (define_insn_and_split "*vector_ordered<mode>" - [(set (match_operand:VEC_F 0 "vfloat_operand" "") - (ordered:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "") - (match_operand:VEC_F 2 "vfloat_operand" "")))] + [(set (match_operand:VEC_F 0 "vfloat_operand") + (ordered:VEC_F (match_operand:VEC_F 1 "vfloat_operand") + (match_operand:VEC_F 2 "vfloat_operand")))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" "#" "" @@ -691,16 +675,15 @@ (set (match_dup 0) (ior:VEC_F (match_dup 3) (match_dup 4)))] - " { operands[3] = gen_reg_rtx (<MODE>mode); operands[4] = gen_reg_rtx (<MODE>mode); -}") +}) (define_insn_and_split "*vector_unordered<mode>" - [(set (match_operand:VEC_F 0 "vfloat_operand" "") - (unordered:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "") - (match_operand:VEC_F 2 "vfloat_operand" "")))] + [(set (match_operand:VEC_F 0 "vfloat_operand") + (unordered:VEC_F (match_operand:VEC_F 1 "vfloat_operand") + (match_operand:VEC_F 2 "vfloat_operand")))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" "#" "" @@ -713,31 +696,30 @@ (set (match_dup 0) (and:VEC_F (not:VEC_F (match_dup 3)) (not:VEC_F (match_dup 4))))] - " { operands[3] = gen_reg_rtx (<MODE>mode); operands[4] = gen_reg_rtx (<MODE>mode); -}") +}) ;; Note the arguments for __builtin_altivec_vsel are op2, op1, mask ;; which is in the reverse order that we want (define_expand "vector_select_<mode>" - [(set (match_operand:VEC_L 0 "vlogical_operand" "") + [(set (match_operand:VEC_L 0 "vlogical_operand") (if_then_else:VEC_L - (ne:CC (match_operand:VEC_L 3 "vlogical_operand" "") + (ne:CC (match_operand:VEC_L 3 "vlogical_operand") (match_dup 4)) - (match_operand:VEC_L 2 "vlogical_operand" "") - (match_operand:VEC_L 1 "vlogical_operand" "")))] + (match_operand:VEC_L 2 "vlogical_operand") + (match_operand:VEC_L 1 "vlogical_operand")))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" "operands[4] = CONST0_RTX (<MODE>mode);") (define_expand "vector_select_<mode>_uns" - [(set (match_operand:VEC_L 0 "vlogical_operand" "") + [(set (match_operand:VEC_L 0 "vlogical_operand") (if_then_else:VEC_L - (ne:CCUNS (match_operand:VEC_L 3 "vlogical_operand" "") + (ne:CCUNS (match_operand:VEC_L 3 "vlogical_operand") (match_dup 4)) - (match_operand:VEC_L 2 "vlogical_operand" "") - (match_operand:VEC_L 1 "vlogical_operand" "")))] + (match_operand:VEC_L 2 "vlogical_operand") + (match_operand:VEC_L 1 "vlogical_operand")))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" "operands[4] = CONST0_RTX (<MODE>mode);") @@ -746,10 +728,10 @@ (define_expand "vector_eq_<mode>_p" [(parallel [(set (reg:CC CR6_REGNO) - (unspec:CC [(eq:CC (match_operand:VEC_A 1 "vlogical_operand" "") - (match_operand:VEC_A 2 "vlogical_operand" ""))] + (unspec:CC [(eq:CC (match_operand:VEC_A 1 "vlogical_operand") + (match_operand:VEC_A 2 "vlogical_operand"))] UNSPEC_PREDICATE)) - (set (match_operand:VEC_A 0 "vlogical_operand" "") + (set (match_operand:VEC_A 0 "vlogical_operand") (eq:VEC_A (match_dup 1) (match_dup 2)))])] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" @@ -913,10 +895,10 @@ (define_expand "vector_gt_<mode>_p" [(parallel [(set (reg:CC CR6_REGNO) - (unspec:CC [(gt:CC (match_operand:VEC_A 1 "vlogical_operand" "") - (match_operand:VEC_A 2 "vlogical_operand" ""))] + (unspec:CC [(gt:CC (match_operand:VEC_A 1 "vlogical_operand") + (match_operand:VEC_A 2 "vlogical_operand"))] UNSPEC_PREDICATE)) - (set (match_operand:VEC_A 0 "vlogical_operand" "") + (set (match_operand:VEC_A 0 "vlogical_operand") (gt:VEC_A (match_dup 1) (match_dup 2)))])] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" @@ -925,10 +907,10 @@ (define_expand "vector_ge_<mode>_p" [(parallel [(set (reg:CC CR6_REGNO) - (unspec:CC [(ge:CC (match_operand:VEC_F 1 "vfloat_operand" "") - (match_operand:VEC_F 2 "vfloat_operand" ""))] + (unspec:CC [(ge:CC (match_operand:VEC_F 1 "vfloat_operand") + (match_operand:VEC_F 2 "vfloat_operand"))] UNSPEC_PREDICATE)) - (set (match_operand:VEC_F 0 "vfloat_operand" "") + (set (match_operand:VEC_F 0 "vfloat_operand") (ge:VEC_F (match_dup 1) (match_dup 2)))])] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" @@ -937,10 +919,10 @@ (define_expand "vector_gtu_<mode>_p" [(parallel [(set (reg:CC CR6_REGNO) - (unspec:CC [(gtu:CC (match_operand:VEC_I 1 "vint_operand" "") - (match_operand:VEC_I 2 "vint_operand" ""))] + (unspec:CC [(gtu:CC (match_operand:VEC_I 1 "vint_operand") + (match_operand:VEC_I 2 "vint_operand"))] UNSPEC_PREDICATE)) - (set (match_operand:VEC_I 0 "vlogical_operand" "") + (set (match_operand:VEC_I 0 "vlogical_operand") (gtu:VEC_I (match_dup 1) (match_dup 2)))])] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" @@ -1002,87 +984,83 @@ ;; Vector count leading zeros (define_expand "clz<mode>2" - [(set (match_operand:VEC_I 0 "register_operand" "") - (clz:VEC_I (match_operand:VEC_I 1 "register_operand" "")))] + [(set (match_operand:VEC_I 0 "register_operand") + (clz:VEC_I (match_operand:VEC_I 1 "register_operand")))] "TARGET_P8_VECTOR") ;; Vector count trailing zeros (define_expand "ctz<mode>2" - [(set (match_operand:VEC_I 0 "register_operand" "") - (ctz:VEC_I (match_operand:VEC_I 1 "register_operand" "")))] + [(set (match_operand:VEC_I 0 "register_operand") + (ctz:VEC_I (match_operand:VEC_I 1 "register_operand")))] "TARGET_P9_VECTOR") ;; Vector population count (define_expand "popcount<mode>2" - [(set (match_operand:VEC_I 0 "register_operand" "") - (popcount:VEC_I (match_operand:VEC_I 1 "register_operand" "")))] + [(set (match_operand:VEC_I 0 "register_operand") + (popcount:VEC_I (match_operand:VEC_I 1 "register_operand")))] "TARGET_P8_VECTOR") ;; Vector parity (define_expand "parity<mode>2" - [(set (match_operand:VEC_IP 0 "register_operand" "") - (parity:VEC_IP (match_operand:VEC_IP 1 "register_operand" "")))] + [(set (match_operand:VEC_IP 0 "register_operand") + (parity:VEC_IP (match_operand:VEC_IP 1 "register_operand")))] "TARGET_P9_VECTOR") ;; Same size conversions (define_expand "float<VEC_int><mode>2" - [(set (match_operand:VEC_F 0 "vfloat_operand" "") - (float:VEC_F (match_operand:<VEC_INT> 1 "vint_operand" "")))] + [(set (match_operand:VEC_F 0 "vfloat_operand") + (float:VEC_F (match_operand:<VEC_INT> 1 "vint_operand")))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" - " { if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode)) { emit_insn (gen_altivec_vcfsx (operands[0], operands[1], const0_rtx)); DONE; } -}") +}) (define_expand "floatuns<VEC_int><mode>2" - [(set (match_operand:VEC_F 0 "vfloat_operand" "") - (unsigned_float:VEC_F (match_operand:<VEC_INT> 1 "vint_operand" "")))] + [(set (match_operand:VEC_F 0 "vfloat_operand") + (unsigned_float:VEC_F (match_operand:<VEC_INT> 1 "vint_operand")))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" - " { if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode)) { emit_insn (gen_altivec_vcfux (operands[0], operands[1], const0_rtx)); DONE; } -}") +}) (define_expand "fix_trunc<mode><VEC_int>2" - [(set (match_operand:<VEC_INT> 0 "vint_operand" "") - (fix:<VEC_INT> (match_operand:VEC_F 1 "vfloat_operand" "")))] + [(set (match_operand:<VEC_INT> 0 "vint_operand") + (fix:<VEC_INT> (match_operand:VEC_F 1 "vfloat_operand")))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" - " { if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode)) { emit_insn (gen_altivec_vctsxs (operands[0], operands[1], const0_rtx)); DONE; } -}") +}) (define_expand "fixuns_trunc<mode><VEC_int>2" - [(set (match_operand:<VEC_INT> 0 "vint_operand" "") - (unsigned_fix:<VEC_INT> (match_operand:VEC_F 1 "vfloat_operand" "")))] + [(set (match_operand:<VEC_INT> 0 "vint_operand") + (unsigned_fix:<VEC_INT> (match_operand:VEC_F 1 "vfloat_operand")))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" - " { if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode)) { emit_insn (gen_altivec_vctuxs (operands[0], operands[1], const0_rtx)); DONE; } -}") +}) ;; Vector initialization, set, extract (define_expand "vec_init<mode><VEC_base_l>" - [(match_operand:VEC_E 0 "vlogical_operand" "") - (match_operand:VEC_E 1 "" "")] + [(match_operand:VEC_E 0 "vlogical_operand") + (match_operand:VEC_E 1 "")] "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)" { rs6000_expand_vector_init (operands[0], operands[1]); @@ -1090,9 +1068,9 @@ }) (define_expand "vec_set<mode>" - [(match_operand:VEC_E 0 "vlogical_operand" "") - (match_operand:<VEC_base> 1 "register_operand" "") - (match_operand 2 "const_int_operand" "")] + [(match_operand:VEC_E 0 "vlogical_operand") + (match_operand:<VEC_base> 1 "register_operand") + (match_operand 2 "const_int_operand")] "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)" { rs6000_expand_vector_set (operands[0], operands[1], INTVAL (operands[2])); @@ -1100,9 +1078,9 @@ }) (define_expand "vec_extract<mode><VEC_base_l>" - [(match_operand:<VEC_base> 0 "register_operand" "") - (match_operand:VEC_E 1 "vlogical_operand" "") - (match_operand 2 "const_int_operand" "")] + [(match_operand:<VEC_base> 0 "register_operand") + (match_operand:VEC_E 1 "vlogical_operand") + (match_operand 2 "const_int_operand")] "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)" { rs6000_expand_vector_extract (operands[0], operands[1], operands[2]); @@ -1111,9 +1089,9 @@ ;; Convert double word types to single word types (define_expand "vec_pack_trunc_v2df" - [(match_operand:V4SF 0 "vfloat_operand" "") - (match_operand:V2DF 1 "vfloat_operand" "") - (match_operand:V2DF 2 "vfloat_operand" "")] + [(match_operand:V4SF 0 "vfloat_operand") + (match_operand:V2DF 1 "vfloat_operand") + (match_operand:V2DF 2 "vfloat_operand")] "VECTOR_UNIT_VSX_P (V2DFmode) && TARGET_ALTIVEC" { rtx r1 = gen_reg_rtx (V4SFmode); @@ -1126,9 +1104,9 @@ }) (define_expand "vec_pack_sfix_trunc_v2df" - [(match_operand:V4SI 0 "vint_operand" "") - (match_operand:V2DF 1 "vfloat_operand" "") - (match_operand:V2DF 2 "vfloat_operand" "")] + [(match_operand:V4SI 0 "vint_operand") + (match_operand:V2DF 1 "vfloat_operand") + (match_operand:V2DF 2 "vfloat_operand")] "VECTOR_UNIT_VSX_P (V2DFmode) && TARGET_ALTIVEC" { rtx r1 = gen_reg_rtx (V4SImode); @@ -1141,9 +1119,9 @@ }) (define_expand "vec_pack_ufix_trunc_v2df" - [(match_operand:V4SI 0 "vint_operand" "") - (match_operand:V2DF 1 "vfloat_operand" "") - (match_operand:V2DF 2 "vfloat_operand" "")] + [(match_operand:V4SI 0 "vint_operand") + (match_operand:V2DF 1 "vfloat_operand") + (match_operand:V2DF 2 "vfloat_operand")] "VECTOR_UNIT_VSX_P (V2DFmode) && TARGET_ALTIVEC" { rtx r1 = gen_reg_rtx (V4SImode); @@ -1157,8 +1135,8 @@ ;; Convert single word types to double word (define_expand "vec_unpacks_hi_v4sf" - [(match_operand:V2DF 0 "vfloat_operand" "") - (match_operand:V4SF 1 "vfloat_operand" "")] + [(match_operand:V2DF 0 "vfloat_operand") + (match_operand:V4SF 1 "vfloat_operand")] "VECTOR_UNIT_VSX_P (V2DFmode) && VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)" { rtx reg = gen_reg_rtx (V4SFmode); @@ -1169,8 +1147,8 @@ }) (define_expand "vec_unpacks_lo_v4sf" - [(match_operand:V2DF 0 "vfloat_operand" "") - (match_operand:V4SF 1 "vfloat_operand" "")] + [(match_operand:V2DF 0 "vfloat_operand") + (match_operand:V4SF 1 "vfloat_operand")] "VECTOR_UNIT_VSX_P (V2DFmode) && VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)" { rtx reg = gen_reg_rtx (V4SFmode); @@ -1181,8 +1159,8 @@ }) (define_expand "vec_unpacks_float_hi_v4si" - [(match_operand:V2DF 0 "vfloat_operand" "") - (match_operand:V4SI 1 "vint_operand" "")] + [(match_operand:V2DF 0 "vfloat_operand") + (match_operand:V4SI 1 "vint_operand")] "VECTOR_UNIT_VSX_P (V2DFmode) && VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SImode)" { rtx reg = gen_reg_rtx (V4SImode); @@ -1193,8 +1171,8 @@ }) (define_expand "vec_unpacks_float_lo_v4si" - [(match_operand:V2DF 0 "vfloat_operand" "") - (match_operand:V4SI 1 "vint_operand" "")] + [(match_operand:V2DF 0 "vfloat_operand") + (match_operand:V4SI 1 "vint_operand")] "VECTOR_UNIT_VSX_P (V2DFmode) && VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SImode)" { rtx reg = gen_reg_rtx (V4SImode); @@ -1205,8 +1183,8 @@ }) (define_expand "vec_unpacku_float_hi_v4si" - [(match_operand:V2DF 0 "vfloat_operand" "") - (match_operand:V4SI 1 "vint_operand" "")] + [(match_operand:V2DF 0 "vfloat_operand") + (match_operand:V4SI 1 "vint_operand")] "VECTOR_UNIT_VSX_P (V2DFmode) && VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SImode)" { rtx reg = gen_reg_rtx (V4SImode); @@ -1217,8 +1195,8 @@ }) (define_expand "vec_unpacku_float_lo_v4si" - [(match_operand:V2DF 0 "vfloat_operand" "") - (match_operand:V4SI 1 "vint_operand" "")] + [(match_operand:V2DF 0 "vfloat_operand") + (match_operand:V4SI 1 "vint_operand")] "VECTOR_UNIT_VSX_P (V2DFmode) && VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SImode)" { rtx reg = gen_reg_rtx (V4SImode); @@ -1231,10 +1209,10 @@ ;; Align vector loads with a permute. (define_expand "vec_realign_load_<mode>" - [(match_operand:VEC_K 0 "vlogical_operand" "") - (match_operand:VEC_K 1 "vlogical_operand" "") - (match_operand:VEC_K 2 "vlogical_operand" "") - (match_operand:V16QI 3 "vlogical_operand" "")] + [(match_operand:VEC_K 0 "vlogical_operand") + (match_operand:VEC_K 1 "vlogical_operand") + (match_operand:VEC_K 2 "vlogical_operand") + (match_operand:V16QI 3 "vlogical_operand")] "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)" { if (BYTES_BIG_ENDIAN) @@ -1256,8 +1234,8 @@ ;; Under VSX, vectors of 4/8 byte alignments do not need to be aligned ;; since the load already handles it. (define_expand "movmisalign<mode>" - [(set (match_operand:VEC_N 0 "nonimmediate_operand" "") - (match_operand:VEC_N 1 "any_operand" ""))] + [(set (match_operand:VEC_N 0 "nonimmediate_operand") + (match_operand:VEC_N 1 "any_operand"))] "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_ALLOW_MOVMISALIGN" "") @@ -1269,11 +1247,10 @@ ;; Note that the vec_shr operation is actually defined as ;; 'shift toward element 0' so is a shr for LE and shl for BE. (define_expand "vec_shr_<mode>" - [(match_operand:VEC_L 0 "vlogical_operand" "") - (match_operand:VEC_L 1 "vlogical_operand" "") - (match_operand:QI 2 "reg_or_short_operand" "")] + [(match_operand:VEC_L 0 "vlogical_operand") + (match_operand:VEC_L 1 "vlogical_operand") + (match_operand:QI 2 "reg_or_short_operand")] "TARGET_ALTIVEC" - " { rtx bitshift = operands[2]; rtx shift; @@ -1315,37 +1292,37 @@ emit_insn (insn); DONE; -}") +}) ;; Expanders for rotate each element in a vector (define_expand "vrotl<mode>3" - [(set (match_operand:VEC_I 0 "vint_operand" "") - (rotate:VEC_I (match_operand:VEC_I 1 "vint_operand" "") - (match_operand:VEC_I 2 "vint_operand" "")))] + [(set (match_operand:VEC_I 0 "vint_operand") + (rotate:VEC_I (match_operand:VEC_I 1 "vint_operand") + (match_operand:VEC_I 2 "vint_operand")))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" "") ;; Expanders for arithmetic shift left on each vector element (define_expand "vashl<mode>3" - [(set (match_operand:VEC_I 0 "vint_operand" "") - (ashift:VEC_I (match_operand:VEC_I 1 "vint_operand" "") - (match_operand:VEC_I 2 "vint_operand" "")))] + [(set (match_operand:VEC_I 0 "vint_operand") + (ashift:VEC_I (match_operand:VEC_I 1 "vint_operand") + (match_operand:VEC_I 2 "vint_operand")))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" "") ;; Expanders for logical shift right on each vector element (define_expand "vlshr<mode>3" - [(set (match_operand:VEC_I 0 "vint_operand" "") - (lshiftrt:VEC_I (match_operand:VEC_I 1 "vint_operand" "") - (match_operand:VEC_I 2 "vint_operand" "")))] + [(set (match_operand:VEC_I 0 "vint_operand") + (lshiftrt:VEC_I (match_operand:VEC_I 1 "vint_operand") + (match_operand:VEC_I 2 "vint_operand")))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" "") ;; Expanders for arithmetic shift right on each vector element (define_expand "vashr<mode>3" - [(set (match_operand:VEC_I 0 "vint_operand" "") - (ashiftrt:VEC_I (match_operand:VEC_I 1 "vint_operand" "") - (match_operand:VEC_I 2 "vint_operand" "")))] + [(set (match_operand:VEC_I 0 "vint_operand") + (ashiftrt:VEC_I (match_operand:VEC_I 1 "vint_operand") + (match_operand:VEC_I 2 "vint_operand")))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" "") @@ -1359,8 +1336,8 @@ (define_expand "reduc_<VEC_reduc:VEC_reduc_name>_scal_<VEC_F:mode>" - [(match_operand:<VEC_base> 0 "register_operand" "") - (VEC_reduc:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "") + [(match_operand:<VEC_base> 0 "register_operand") + (VEC_reduc:VEC_F (match_operand:VEC_F 1 "vfloat_operand") (unspec:VEC_F [(const_int 0)] UNSPEC_REDUC))] "VECTOR_UNIT_VSX_P (<VEC_F:MODE>mode)" { diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 6f0bd09e9bb..a65ff756a1e 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -443,7 +443,6 @@ (vec_select:<MODE> (match_dup 2) (parallel [(const_int 1) (const_int 0)])))] - " { rtx mem = operands[1]; @@ -475,7 +474,6 @@ operands[2] = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (operands[0]) : operands[0]; } - " [(set_attr "type" "vecload") (set_attr "length" "8")]) @@ -495,7 +493,6 @@ (match_dup 2) (parallel [(const_int 2) (const_int 3) (const_int 0) (const_int 1)])))] - " { rtx mem = operands[1]; @@ -527,7 +524,6 @@ operands[2] = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (operands[0]) : operands[0]; } - " [(set_attr "type" "vecload") (set_attr "length" "8")]) @@ -551,7 +547,6 @@ (const_int 6) (const_int 7) (const_int 0) (const_int 1) (const_int 2) (const_int 3)])))] - " { rtx mem = operands[1]; @@ -583,7 +578,6 @@ operands[2] = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (operands[0]) : operands[0]; } - " [(set_attr "type" "vecload") (set_attr "length" "8")]) @@ -615,7 +609,6 @@ (const_int 2) (const_int 3) (const_int 4) (const_int 5) (const_int 6) (const_int 7)])))] - " { rtx mem = operands[1]; @@ -647,7 +640,6 @@ operands[2] = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (operands[0]) : operands[0]; } - " [(set_attr "type" "vecload") (set_attr "length" "8")]) @@ -660,8 +652,8 @@ (set_attr "length" "12")]) (define_split - [(set (match_operand:VSX_D 0 "indexed_or_indirect_operand" "") - (match_operand:VSX_D 1 "vsx_register_operand" ""))] + [(set (match_operand:VSX_D 0 "indexed_or_indirect_operand") + (match_operand:VSX_D 1 "vsx_register_operand"))] "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR && !reload_completed" [(set (match_dup 2) (vec_select:<MODE> @@ -704,8 +696,8 @@ ;; The post-reload split requires that we re-permute the source ;; register in case it is still live. (define_split - [(set (match_operand:VSX_D 0 "indexed_or_indirect_operand" "") - (match_operand:VSX_D 1 "vsx_register_operand" ""))] + [(set (match_operand:VSX_D 0 "indexed_or_indirect_operand") + (match_operand:VSX_D 1 "vsx_register_operand"))] "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR && reload_completed" [(set (match_dup 1) (vec_select:<MODE> @@ -730,8 +722,8 @@ (set_attr "length" "12")]) (define_split - [(set (match_operand:VSX_W 0 "indexed_or_indirect_operand" "") - (match_operand:VSX_W 1 "vsx_register_operand" ""))] + [(set (match_operand:VSX_W 0 "indexed_or_indirect_operand") + (match_operand:VSX_W 1 "vsx_register_operand"))] "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR && !reload_completed" [(set (match_dup 2) (vec_select:<MODE> @@ -776,8 +768,8 @@ ;; The post-reload split requires that we re-permute the source ;; register in case it is still live. (define_split - [(set (match_operand:VSX_W 0 "indexed_or_indirect_operand" "") - (match_operand:VSX_W 1 "vsx_register_operand" ""))] + [(set (match_operand:VSX_W 0 "indexed_or_indirect_operand") + (match_operand:VSX_W 1 "vsx_register_operand"))] "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR && reload_completed" [(set (match_dup 1) (vec_select:<MODE> @@ -805,8 +797,8 @@ (set_attr "length" "12")]) (define_split - [(set (match_operand:V8HI 0 "indexed_or_indirect_operand" "") - (match_operand:V8HI 1 "vsx_register_operand" ""))] + [(set (match_operand:V8HI 0 "indexed_or_indirect_operand") + (match_operand:V8HI 1 "vsx_register_operand"))] "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR && !reload_completed" [(set (match_dup 2) (vec_select:V8HI @@ -855,8 +847,8 @@ ;; The post-reload split requires that we re-permute the source ;; register in case it is still live. (define_split - [(set (match_operand:V8HI 0 "indexed_or_indirect_operand" "") - (match_operand:V8HI 1 "vsx_register_operand" ""))] + [(set (match_operand:V8HI 0 "indexed_or_indirect_operand") + (match_operand:V8HI 1 "vsx_register_operand"))] "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR && reload_completed" [(set (match_dup 1) (vec_select:V8HI @@ -890,8 +882,8 @@ (set_attr "length" "12")]) (define_split - [(set (match_operand:V16QI 0 "indexed_or_indirect_operand" "") - (match_operand:V16QI 1 "vsx_register_operand" ""))] + [(set (match_operand:V16QI 0 "indexed_or_indirect_operand") + (match_operand:V16QI 1 "vsx_register_operand"))] "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR && !reload_completed" [(set (match_dup 2) (vec_select:V16QI @@ -948,8 +940,8 @@ ;; The post-reload split requires that we re-permute the source ;; register in case it is still live. (define_split - [(set (match_operand:V16QI 0 "indexed_or_indirect_operand" "") - (match_operand:V16QI 1 "vsx_register_operand" ""))] + [(set (match_operand:V16QI 0 "indexed_or_indirect_operand") + (match_operand:V16QI 1 "vsx_register_operand"))] "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR && reload_completed" [(set (match_dup 1) (vec_select:V16QI @@ -1037,7 +1029,6 @@ #" "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR" [(const_int 0)] - " { rtx tmp = (can_create_pseudo_p () ? gen_reg_rtx_and_attrs (operands[0]) @@ -1046,7 +1037,6 @@ rs6000_emit_le_vsx_permute (operands[0], tmp, <MODE>mode); DONE; } - " [(set_attr "type" "vecload,load") (set_attr "length" "8,8")]) @@ -1061,8 +1051,8 @@ (set_attr "length" "12,8")]) (define_split - [(set (match_operand:VSX_LE_128 0 "memory_operand" "") - (match_operand:VSX_LE_128 1 "vsx_register_operand" ""))] + [(set (match_operand:VSX_LE_128 0 "memory_operand") + (match_operand:VSX_LE_128 1 "vsx_register_operand"))] "!BYTES_BIG_ENDIAN && TARGET_VSX && !reload_completed && !TARGET_P9_VECTOR" [(const_int 0)] { @@ -1103,10 +1093,10 @@ ;; VSX registers on a little endian system. The vector types and IEEE 128-bit ;; floating point are handled by the more generic swap elimination pass. (define_peephole2 - [(set (match_operand:TI 0 "vsx_register_operand" "") - (rotate:TI (match_operand:TI 1 "vsx_register_operand" "") + [(set (match_operand:TI 0 "vsx_register_operand") + (rotate:TI (match_operand:TI 1 "vsx_register_operand") (const_int 64))) - (set (match_operand:TI 2 "vsx_register_operand" "") + (set (match_operand:TI 2 "vsx_register_operand") (rotate:TI (match_dup 0) (const_int 64)))] "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR @@ -1117,8 +1107,8 @@ ;; The post-reload split requires that we re-permute the source ;; register in case it is still live. (define_split - [(set (match_operand:VSX_LE_128 0 "memory_operand" "") - (match_operand:VSX_LE_128 1 "vsx_register_operand" ""))] + [(set (match_operand:VSX_LE_128 0 "memory_operand") + (match_operand:VSX_LE_128 1 "vsx_register_operand"))] "!BYTES_BIG_ENDIAN && TARGET_VSX && reload_completed && !TARGET_P9_VECTOR" [(const_int 0)] { @@ -1266,8 +1256,8 @@ ;; Explicit load/store expanders for the builtin functions (define_expand "vsx_load_<mode>" - [(set (match_operand:VSX_M 0 "vsx_register_operand" "") - (match_operand:VSX_M 1 "memory_operand" ""))] + [(set (match_operand:VSX_M 0 "vsx_register_operand") + (match_operand:VSX_M 1 "memory_operand"))] "VECTOR_MEM_VSX_P (<MODE>mode)" { /* Expand to swaps if needed, prior to swap optimization. */ @@ -1279,8 +1269,8 @@ }) (define_expand "vsx_store_<mode>" - [(set (match_operand:VSX_M 0 "memory_operand" "") - (match_operand:VSX_M 1 "vsx_register_operand" ""))] + [(set (match_operand:VSX_M 0 "memory_operand") + (match_operand:VSX_M 1 "vsx_register_operand"))] "VECTOR_MEM_VSX_P (<MODE>mode)" { /* Expand to swaps if needed, prior to swap optimization. */ @@ -1640,7 +1630,6 @@ "#" "VECTOR_MEM_VSX_P (V2DImode) && !reload_completed" [(const_int 0)] - " { rtx op0 = operands[0]; rtx op1 = operands[1]; @@ -1668,7 +1657,7 @@ } emit_insn (gen_vsx_concat_v2di (op0, op5, op3)); DONE; -}" +} [(set_attr "type" "mul")]) (define_insn "*vsx_div<mode>3" @@ -1690,7 +1679,6 @@ "#" "VECTOR_MEM_VSX_P (V2DImode) && !reload_completed" [(const_int 0)] - " { rtx op0 = operands[0]; rtx op1 = operands[1]; @@ -1726,7 +1714,7 @@ } emit_insn (gen_vsx_concat_v2di (op0, op5, op3)); DONE; -}" +} [(set_attr "type" "div")]) (define_insn_and_split "vsx_udiv_v2di" @@ -1738,7 +1726,6 @@ "#" "VECTOR_MEM_VSX_P (V2DImode) && !reload_completed" [(const_int 0)] - " { rtx op0 = operands[0]; rtx op1 = operands[1]; @@ -1774,16 +1761,16 @@ } emit_insn (gen_vsx_concat_v2di (op0, op5, op3)); DONE; -}" +} [(set_attr "type" "div")]) ;; *tdiv* instruction returning the FG flag (define_expand "vsx_tdiv<mode>3_fg" [(set (match_dup 3) - (unspec:CCFP [(match_operand:VSX_B 1 "vsx_register_operand" "") - (match_operand:VSX_B 2 "vsx_register_operand" "")] + (unspec:CCFP [(match_operand:VSX_B 1 "vsx_register_operand") + (match_operand:VSX_B 2 "vsx_register_operand")] UNSPEC_VSX_TDIV)) - (set (match_operand:SI 0 "gpc_reg_operand" "") + (set (match_operand:SI 0 "gpc_reg_operand") (gt:SI (match_dup 3) (const_int 0)))] "VECTOR_UNIT_VSX_P (<MODE>mode)" @@ -1794,10 +1781,10 @@ ;; *tdiv* instruction returning the FE flag (define_expand "vsx_tdiv<mode>3_fe" [(set (match_dup 3) - (unspec:CCFP [(match_operand:VSX_B 1 "vsx_register_operand" "") - (match_operand:VSX_B 2 "vsx_register_operand" "")] + (unspec:CCFP [(match_operand:VSX_B 1 "vsx_register_operand") + (match_operand:VSX_B 2 "vsx_register_operand")] UNSPEC_VSX_TDIV)) - (set (match_operand:SI 0 "gpc_reg_operand" "") + (set (match_operand:SI 0 "gpc_reg_operand") (eq:SI (match_dup 3) (const_int 0)))] "VECTOR_UNIT_VSX_P (<MODE>mode)" @@ -1888,9 +1875,9 @@ ;; *tsqrt* returning the fg flag (define_expand "vsx_tsqrt<mode>2_fg" [(set (match_dup 2) - (unspec:CCFP [(match_operand:VSX_B 1 "vsx_register_operand" "")] + (unspec:CCFP [(match_operand:VSX_B 1 "vsx_register_operand")] UNSPEC_VSX_TSQRT)) - (set (match_operand:SI 0 "gpc_reg_operand" "") + (set (match_operand:SI 0 "gpc_reg_operand") (gt:SI (match_dup 2) (const_int 0)))] "VECTOR_UNIT_VSX_P (<MODE>mode)" @@ -1901,9 +1888,9 @@ ;; *tsqrt* returning the fe flag (define_expand "vsx_tsqrt<mode>2_fe" [(set (match_dup 2) - (unspec:CCFP [(match_operand:VSX_B 1 "vsx_register_operand" "")] + (unspec:CCFP [(match_operand:VSX_B 1 "vsx_register_operand")] UNSPEC_VSX_TSQRT)) - (set (match_operand:SI 0 "gpc_reg_operand" "") + (set (match_operand:SI 0 "gpc_reg_operand") (eq:SI (match_dup 2) (const_int 0)))] "VECTOR_UNIT_VSX_P (<MODE>mode)" @@ -2303,9 +2290,9 @@ ;; Convert and scale (used by vec_ctf, vec_cts, vec_ctu for double/long long) (define_expand "vsx_xvcvsxddp_scale" - [(match_operand:V2DF 0 "vsx_register_operand" "") - (match_operand:V2DI 1 "vsx_register_operand" "") - (match_operand:QI 2 "immediate_operand" "")] + [(match_operand:V2DF 0 "vsx_register_operand") + (match_operand:V2DI 1 "vsx_register_operand") + (match_operand:QI 2 "immediate_operand")] "VECTOR_UNIT_VSX_P (V2DFmode)" { rtx op0 = operands[0]; @@ -2326,9 +2313,9 @@ [(set_attr "type" "vecdouble")]) (define_expand "vsx_xvcvuxddp_scale" - [(match_operand:V2DF 0 "vsx_register_operand" "") - (match_operand:V2DI 1 "vsx_register_operand" "") - (match_operand:QI 2 "immediate_operand" "")] + [(match_operand:V2DF 0 "vsx_register_operand") + (match_operand:V2DI 1 "vsx_register_operand") + (match_operand:QI 2 "immediate_operand")] "VECTOR_UNIT_VSX_P (V2DFmode)" { rtx op0 = operands[0]; @@ -2349,9 +2336,9 @@ [(set_attr "type" "vecdouble")]) (define_expand "vsx_xvcvdpsxds_scale" - [(match_operand:V2DI 0 "vsx_register_operand" "") - (match_operand:V2DF 1 "vsx_register_operand" "") - (match_operand:QI 2 "immediate_operand" "")] + [(match_operand:V2DI 0 "vsx_register_operand") + (match_operand:V2DF 1 "vsx_register_operand") + (match_operand:QI 2 "immediate_operand")] "VECTOR_UNIT_VSX_P (V2DFmode)" { rtx op0 = operands[0]; @@ -2392,9 +2379,9 @@ ;; convert vector of 64-bit floating point numbers to vector of ;; 64-bit unsigned integer (define_expand "vsx_xvcvdpuxds_scale" - [(match_operand:V2DI 0 "vsx_register_operand" "") - (match_operand:V2DF 1 "vsx_register_operand" "") - (match_operand:QI 2 "immediate_operand" "")] + [(match_operand:V2DI 0 "vsx_register_operand") + (match_operand:V2DF 1 "vsx_register_operand") + (match_operand:QI 2 "immediate_operand")] "VECTOR_UNIT_VSX_P (V2DFmode)" { rtx op0 = operands[0]; @@ -3161,10 +3148,10 @@ ;; Convert a TImode value into V1TImode (define_expand "vsx_set_v1ti" - [(match_operand:V1TI 0 "nonimmediate_operand" "") - (match_operand:V1TI 1 "nonimmediate_operand" "") - (match_operand:TI 2 "input_operand" "") - (match_operand:QI 3 "u5bit_cint_operand" "")] + [(match_operand:V1TI 0 "nonimmediate_operand") + (match_operand:V1TI 1 "nonimmediate_operand") + (match_operand:TI 2 "input_operand") + (match_operand:QI 3 "u5bit_cint_operand")] "VECTOR_MEM_VSX_P (V1TImode)" { if (operands[3] != const0_rtx) @@ -4078,9 +4065,9 @@ ;; Expanders for builtins (define_expand "vsx_mergel_<mode>" - [(use (match_operand:VSX_D 0 "vsx_register_operand" "")) - (use (match_operand:VSX_D 1 "vsx_register_operand" "")) - (use (match_operand:VSX_D 2 "vsx_register_operand" ""))] + [(use (match_operand:VSX_D 0 "vsx_register_operand")) + (use (match_operand:VSX_D 1 "vsx_register_operand")) + (use (match_operand:VSX_D 2 "vsx_register_operand"))] "VECTOR_MEM_VSX_P (<MODE>mode)" { rtvec v; @@ -4104,9 +4091,9 @@ }) (define_expand "vsx_mergeh_<mode>" - [(use (match_operand:VSX_D 0 "vsx_register_operand" "")) - (use (match_operand:VSX_D 1 "vsx_register_operand" "")) - (use (match_operand:VSX_D 2 "vsx_register_operand" ""))] + [(use (match_operand:VSX_D 0 "vsx_register_operand")) + (use (match_operand:VSX_D 1 "vsx_register_operand")) + (use (match_operand:VSX_D 2 "vsx_register_operand"))] "VECTOR_MEM_VSX_P (<MODE>mode)" { rtvec v; @@ -4328,7 +4315,6 @@ "#" "" [(const_int 0)] - " { rtx tmp = (GET_CODE (operands[2]) == SCRATCH) ? gen_reg_rtx (V2DFmode) @@ -4336,7 +4322,7 @@ emit_insn (gen_vsx_xxsldwi_v2df (tmp, operands[1], operands[1], const2_rtx)); emit_insn (gen_<VEC_reduc_rtx>v2df3 (operands[0], tmp, operands[1])); DONE; -}" +} [(set_attr "length" "8") (set_attr "type" "veccomplex")]) @@ -4351,7 +4337,6 @@ "#" "" [(const_int 0)] - " { rtx op0 = operands[0]; rtx op1 = operands[1]; @@ -4375,7 +4360,7 @@ emit_insn (gen_vsx_xxsldwi_v4sf (tmp4, tmp3, tmp3, GEN_INT (3))); emit_insn (gen_<VEC_reduc_rtx>v4sf3 (op0, tmp4, tmp3)); DONE; -}" +} [(set_attr "length" "16") (set_attr "type" "veccomplex")]) @@ -4400,7 +4385,6 @@ "#" "" [(const_int 0)] - " { rtx hi = gen_highpart (DFmode, operands[1]); rtx lo = (GET_CODE (operands[2]) == SCRATCH) @@ -4410,7 +4394,7 @@ emit_insn (gen_vsx_extract_v2df (lo, operands[1], const1_rtx)); emit_insn (gen_<VEC_reduc_rtx>df3 (operands[0], hi, lo)); DONE; -}" +} [(set_attr "length" "8") (set_attr "type" "veccomplex")]) @@ -4428,7 +4412,6 @@ "#" "" [(const_int 0)] - " { rtx op0 = operands[0]; rtx op1 = operands[1]; @@ -4455,28 +4438,28 @@ emit_insn (gen_<VEC_reduc_rtx>v4sf3 (tmp5, tmp4, tmp3)); emit_insn (gen_vsx_xscvspdp_scalar2 (op0, tmp5)); DONE; -}" +} [(set_attr "length" "20") (set_attr "type" "veccomplex")]) ;; Power8 Vector fusion. The fused ops must be physically adjacent. (define_peephole - [(set (match_operand:P 0 "base_reg_operand" "") - (match_operand:P 1 "short_cint_operand" "")) - (set (match_operand:VSX_M 2 "vsx_register_operand" "") + [(set (match_operand:P 0 "base_reg_operand") + (match_operand:P 1 "short_cint_operand")) + (set (match_operand:VSX_M 2 "vsx_register_operand") (mem:VSX_M (plus:P (match_dup 0) - (match_operand:P 3 "int_reg_operand" ""))))] + (match_operand:P 3 "int_reg_operand"))))] "TARGET_VSX && TARGET_P8_FUSION && !TARGET_P9_VECTOR" "li %0,%1\;lx<VSX_M:VSm>x %x2,%0,%3\t\t\t# vector load fusion" [(set_attr "length" "8") (set_attr "type" "vecload")]) (define_peephole - [(set (match_operand:P 0 "base_reg_operand" "") - (match_operand:P 1 "short_cint_operand" "")) - (set (match_operand:VSX_M 2 "vsx_register_operand" "") - (mem:VSX_M (plus:P (match_operand:P 3 "int_reg_operand" "") + [(set (match_operand:P 0 "base_reg_operand") + (match_operand:P 1 "short_cint_operand")) + (set (match_operand:VSX_M 2 "vsx_register_operand") + (mem:VSX_M (plus:P (match_operand:P 3 "int_reg_operand") (match_dup 0))))] "TARGET_VSX && TARGET_P8_FUSION && !TARGET_P9_VECTOR" "li %0,%1\;lx<VSX_M:VSm>x %x2,%0,%3\t\t\t# vector load fusion" @@ -5204,45 +5187,20 @@ ;; Vector insert/extract word at arbitrary byte values. Note, the little ;; endian version needs to adjust the byte number, and the V4SI element in ;; vinsert4b. -(define_expand "vextract4b" - [(set (match_operand:DI 0 "gpc_reg_operand") - (unspec:DI [(match_operand:V16QI 1 "vsx_register_operand") - (match_operand:QI 2 "const_0_to_12_operand")] - UNSPEC_XXEXTRACTUW))] +(define_insn "extract4b" + [(set (match_operand:V2DI 0 "vsx_register_operand") + (unspec:V2DI [(match_operand:V16QI 1 "vsx_register_operand" "wa") + (match_operand:QI 2 "const_0_to_12_operand" "n")] + UNSPEC_XXEXTRACTUW))] "TARGET_P9_VECTOR" { if (!VECTOR_ELT_ORDER_BIG) operands[2] = GEN_INT (12 - INTVAL (operands[2])); -}) - -(define_insn_and_split "*vextract4b_internal" - [(set (match_operand:DI 0 "gpc_reg_operand" "=wj,r") - (unspec:DI [(match_operand:V16QI 1 "vsx_register_operand" "wa,v") - (match_operand:QI 2 "const_0_to_12_operand" "n,n")] - UNSPEC_XXEXTRACTUW))] - "TARGET_P9_VECTOR" - "@ - xxextractuw %x0,%x1,%2 - #" - "&& reload_completed && int_reg_operand (operands[0], DImode)" - [(const_int 0)] -{ - rtx op0 = operands[0]; - rtx op1 = operands[1]; - rtx op2 = operands[2]; - rtx op0_si = gen_rtx_REG (SImode, REGNO (op0)); - rtx op1_v4si = gen_rtx_REG (V4SImode, REGNO (op1)); - emit_move_insn (op0, op2); - if (VECTOR_ELT_ORDER_BIG) - emit_insn (gen_vextuwlx (op0_si, op0_si, op1_v4si)); - else - emit_insn (gen_vextuwrx (op0_si, op0_si, op1_v4si)); - DONE; -} - [(set_attr "type" "vecperm")]) + return "xxextractuw %x0,%x1,%2"; +}) -(define_expand "vinsert4b" +(define_expand "insert4b" [(set (match_operand:V16QI 0 "vsx_register_operand") (unspec:V16QI [(match_operand:V4SI 1 "vsx_register_operand") (match_operand:V16QI 2 "vsx_register_operand") @@ -5260,7 +5218,7 @@ } }) -(define_insn "*vinsert4b_internal" +(define_insn "*insert4b_internal" [(set (match_operand:V16QI 0 "vsx_register_operand" "=wa") (unspec:V16QI [(match_operand:V4SI 1 "vsx_register_operand" "wa") (match_operand:V16QI 2 "vsx_register_operand" "0") @@ -5270,27 +5228,6 @@ "xxinsertw %x0,%x1,%3" [(set_attr "type" "vecperm")]) -(define_expand "vinsert4b_di" - [(set (match_operand:V16QI 0 "vsx_register_operand") - (unspec:V16QI [(match_operand:DI 1 "vsx_register_operand") - (match_operand:V16QI 2 "vsx_register_operand") - (match_operand:QI 3 "const_0_to_12_operand")] - UNSPEC_XXINSERTW))] - "TARGET_P9_VECTOR" -{ - if (!VECTOR_ELT_ORDER_BIG) - operands[3] = GEN_INT (12 - INTVAL (operands[3])); -}) - -(define_insn "*vinsert4b_di_internal" - [(set (match_operand:V16QI 0 "vsx_register_operand" "=wa") - (unspec:V16QI [(match_operand:DI 1 "vsx_register_operand" "wj") - (match_operand:V16QI 2 "vsx_register_operand" "0") - (match_operand:QI 3 "const_0_to_12_operand" "n")] - UNSPEC_XXINSERTW))] - "TARGET_P9_VECTOR" - "xxinsertw %x0,%x1,%3" - [(set_attr "type" "vecperm")]) ;; Generate vector extract four float 32 values from left four elements ;; of eight element vector of float 16 values. diff --git a/gcc/config/rx/rx-protos.h b/gcc/config/rx/rx-protos.h index b3c5bfc7a7f..0bb885d2da1 100644 --- a/gcc/config/rx/rx-protos.h +++ b/gcc/config/rx/rx-protos.h @@ -63,6 +63,112 @@ extern void rx_notice_update_cc (rtx, rtx); extern void rx_split_cbranch (machine_mode, enum rtx_code, rtx, rtx, rtx); extern machine_mode rx_select_cc_mode (enum rtx_code, rtx, rtx); + +extern bool rx_reg_dead_or_unused_after_insn (const rtx_insn* i, int regno); +extern void rx_copy_reg_dead_or_unused_notes (rtx reg, const rtx_insn* src, + rtx_insn* dst); + +extern bool rx_fuse_in_memory_bitop (rtx* operands, rtx_insn* curr_insn, + rtx (*gen_insn)(rtx, rtx)); + +/* Result value of rx_find_set_of_reg. */ +struct set_of_reg +{ + /* The insn where sh_find_set_of_reg stopped looking. + Can be NULL_RTX if the end of the insn list was reached. */ + rtx_insn* insn; + + /* The set rtx of the specified reg if found, NULL_RTX otherwise. */ + const_rtx set_rtx; + + /* The set source rtx of the specified reg if found, NULL_RTX otherwise. + Usually, this is the most interesting return value. */ + rtx set_src; +}; + +/* FIXME: Copy-pasta from SH. Move to rtl.h. + Given a reg rtx and a start insn, try to find the insn that sets + the specified reg by using the specified insn stepping function, + such as 'prev_nonnote_nondebug_insn_bb'. When the insn is found, + try to extract the rtx of the reg set. */ +template <typename F> inline set_of_reg +rx_find_set_of_reg (rtx reg, rtx_insn* insn, F stepfunc, + bool ignore_reg_reg_copies = false) +{ + set_of_reg result; + result.insn = insn; + result.set_rtx = NULL_RTX; + result.set_src = NULL_RTX; + + if (!REG_P (reg) || insn == NULL_RTX) + return result; + + for (rtx_insn* i = stepfunc (insn); i != NULL_RTX; i = stepfunc (i)) + { + if (BARRIER_P (i)) + break; + if (!INSN_P (i) || DEBUG_INSN_P (i)) + continue; + if (reg_set_p (reg, i)) + { + if (CALL_P (i)) + break; + + result.insn = i; + result.set_rtx = set_of (reg, i); + + if (result.set_rtx == NULL_RTX || GET_CODE (result.set_rtx) != SET) + break; + + result.set_src = XEXP (result.set_rtx, 1); + + if (ignore_reg_reg_copies && REG_P (result.set_src)) + { + reg = result.set_src; + continue; + } + if (ignore_reg_reg_copies && SUBREG_P (result.set_src) + && REG_P (SUBREG_REG (result.set_src))) + { + reg = SUBREG_REG (result.set_src); + continue; + } + + break; + } + } + + /* If the searched reg is found inside a (mem (post_inc:SI (reg))), set_of + will return NULL and set_rtx will be NULL. + In this case report a 'not found'. result.insn will always be non-null + at this point, so no need to check it. */ + if (result.set_src != NULL && result.set_rtx == NULL) + result.set_src = NULL; + + return result; +} + +/* FIXME: Move to rtlh.h. */ +template <typename F> inline rtx_insn* +rx_find_use_of_reg (rtx reg, rtx_insn* insn, F stepfunc) +{ + if (!REG_P (reg) || insn == NULL_RTX) + return NULL; + + for (rtx_insn* i = stepfunc (insn); i != NULL_RTX; i = stepfunc (i)) + { + if (BARRIER_P (i)) + break; + if (!INSN_P (i) || DEBUG_INSN_P (i)) + continue; + if (reg_overlap_mentioned_p (reg, PATTERN (i)) + || (CALL_P (i) && find_reg_fusage (i, USE, reg))) + return i; + } + + return NULL; +} + #endif #endif /* GCC_RX_PROTOS_H */ diff --git a/gcc/config/rx/rx.c b/gcc/config/rx/rx.c index be8229818ae..fe467f7bd3a 100644 --- a/gcc/config/rx/rx.c +++ b/gcc/config/rx/rx.c @@ -1644,6 +1644,20 @@ mark_frame_related (rtx insn) } } +/* Create CFI notes for register pops. */ +static void +add_pop_cfi_notes (rtx_insn *insn, unsigned int high, unsigned int low) +{ + rtx t = plus_constant (Pmode, stack_pointer_rtx, + (high - low + 1) * UNITS_PER_WORD); + t = gen_rtx_SET (stack_pointer_rtx, t); + add_reg_note (insn, REG_CFA_ADJUST_CFA, t); + RTX_FRAME_RELATED_P (insn) = 1; + for (unsigned int i = low; i <= high; i++) + add_reg_note (insn, REG_CFA_RESTORE, gen_rtx_REG (word_mode, i)); +} + + static bool ok_for_max_constant (HOST_WIDE_INT val) { @@ -2029,11 +2043,14 @@ rx_can_use_simple_return (void) static void pop_regs (unsigned int high, unsigned int low) { + rtx_insn *insn; if (high == low) - emit_insn (gen_stack_pop (gen_rtx_REG (SImode, low))); + insn = emit_insn (gen_stack_pop (gen_rtx_REG (SImode, low))); else - emit_insn (gen_stack_popm (GEN_INT (((high - low) + 1) * UNITS_PER_WORD), - gen_rx_popm_vector (low, high))); + insn = emit_insn (gen_stack_popm (GEN_INT (((high - low) + 1) + * UNITS_PER_WORD), + gen_rx_popm_vector (low, high))); + add_pop_cfi_notes (insn, high, low); } void @@ -2976,6 +2993,62 @@ rx_address_cost (rtx addr, machine_mode mode ATTRIBUTE_UNUSED, } static bool +rx_rtx_costs (rtx x, machine_mode mode, int outer_code ATTRIBUTE_UNUSED, + int opno ATTRIBUTE_UNUSED, int* total, bool speed) +{ + if (x == const0_rtx) + { + *total = 0; + return true; + } + + switch (GET_CODE (x)) + { + case MULT: + if (mode == DImode) + { + *total = COSTS_N_INSNS (2); + return true; + } + /* fall through */ + + case PLUS: + case MINUS: + case AND: + case COMPARE: + case IOR: + case XOR: + *total = COSTS_N_INSNS (1); + return true; + + case DIV: + if (speed) + /* This is the worst case for a division. Pessimize divisions when + not optimizing for size and allow reciprocal optimizations which + produce bigger code. */ + *total = COSTS_N_INSNS (20); + else + *total = COSTS_N_INSNS (3); + return true; + + case UDIV: + if (speed) + /* This is the worst case for a division. Pessimize divisions when + not optimizing for size and allow reciprocal optimizations which + produce bigger code. */ + *total = COSTS_N_INSNS (18); + else + *total = COSTS_N_INSNS (3); + return true; + + default: + break; + } + + return false; +} + +static bool rx_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to) { /* We can always eliminate to the frame pointer. @@ -3439,6 +3512,88 @@ rx_atomic_sequence::~rx_atomic_sequence (void) emit_insn (gen_mvtc (GEN_INT (CTRLREG_PSW), m_prev_psw_reg)); } +/* Given an insn and a reg number, tell whether the reg dies or is unused + after the insn. */ +bool +rx_reg_dead_or_unused_after_insn (const rtx_insn* i, int regno) +{ + return find_regno_note (i, REG_DEAD, regno) != NULL + || find_regno_note (i, REG_UNUSED, regno) != NULL; +} + +/* Copy dead and unused notes from SRC to DST for the specified REGNO. */ +void +rx_copy_reg_dead_or_unused_notes (rtx reg, const rtx_insn* src, rtx_insn* dst) +{ + int regno = REGNO (SUBREG_P (reg) ? SUBREG_REG (reg) : reg); + + if (rtx note = find_regno_note (src, REG_DEAD, regno)) + add_shallow_copy_of_reg_note (dst, note); + + if (rtx note = find_regno_note (src, REG_UNUSED, regno)) + add_shallow_copy_of_reg_note (dst, note); +} + +/* Try to fuse the current bit-operation insn with the surrounding memory load + and store. */ +bool +rx_fuse_in_memory_bitop (rtx* operands, rtx_insn* curr_insn, + rtx (*gen_insn)(rtx, rtx)) +{ + rtx op2_reg = SUBREG_P (operands[2]) ? SUBREG_REG (operands[2]) : operands[2]; + + set_of_reg op2_def = rx_find_set_of_reg (op2_reg, curr_insn, + prev_nonnote_nondebug_insn_bb); + if (op2_def.set_src == NULL_RTX + || !MEM_P (op2_def.set_src) + || GET_MODE (op2_def.set_src) != QImode + || !rx_is_restricted_memory_address (XEXP (op2_def.set_src, 0), + GET_MODE (op2_def.set_src)) + || reg_used_between_p (operands[2], op2_def.insn, curr_insn) + || !rx_reg_dead_or_unused_after_insn (curr_insn, REGNO (op2_reg)) + ) + return false; + + /* The register operand originates from a memory load and the memory load + could be fused with the bitop insn. + Look for the following memory store with the same memory operand. */ + rtx mem = op2_def.set_src; + + /* If the memory is an auto-mod address, it can't be fused. */ + if (GET_CODE (XEXP (mem, 0)) == POST_INC + || GET_CODE (XEXP (mem, 0)) == PRE_INC + || GET_CODE (XEXP (mem, 0)) == POST_DEC + || GET_CODE (XEXP (mem, 0)) == PRE_DEC) + return false; + + rtx_insn* op0_use = rx_find_use_of_reg (operands[0], curr_insn, + next_nonnote_nondebug_insn_bb); + if (op0_use == NULL + || !(GET_CODE (PATTERN (op0_use)) == SET + && RX_REG_P (XEXP (PATTERN (op0_use), 1)) + && reg_overlap_mentioned_p (operands[0], XEXP (PATTERN (op0_use), 1)) + && rtx_equal_p (mem, XEXP (PATTERN (op0_use), 0))) + || !rx_reg_dead_or_unused_after_insn (op0_use, REGNO (operands[0])) + || reg_set_between_p (operands[2], curr_insn, op0_use)) + return false; + + /* If the load-modify-store operation is fused it could potentially modify + load/store ordering if there are other memory accesses between the load + and the store for this insn. If there are volatile mems between the load + and store it's better not to change the ordering. If there is a call + between the load and store, it's also not safe to fuse it. */ + for (rtx_insn* i = next_nonnote_nondebug_insn_bb (op2_def.insn); + i != NULL && i != op0_use; + i = next_nonnote_nondebug_insn_bb (i)) + if (volatile_insn_p (PATTERN (i)) || CALL_P (i)) + return false; + + emit_insn (gen_insn (mem, gen_lowpart (QImode, operands[1]))); + set_insn_deleted (op2_def.insn); + set_insn_deleted (op0_use); + return true; +} + /* Implement TARGET_HARD_REGNO_NREGS. */ static unsigned int @@ -3627,6 +3782,9 @@ rx_modes_tieable_p (machine_mode mode1, machine_mode mode2) #undef TARGET_MODES_TIEABLE_P #define TARGET_MODES_TIEABLE_P rx_modes_tieable_p +#undef TARGET_RTX_COSTS +#define TARGET_RTX_COSTS rx_rtx_costs + struct gcc_target targetm = TARGET_INITIALIZER; #include "gt-rx.h" diff --git a/gcc/config/rx/rx.md b/gcc/config/rx/rx.md index 3fb2ac854b0..116d4d4a939 100644 --- a/gcc/config/rx/rx.md +++ b/gcc/config/rx/rx.md @@ -1094,7 +1094,7 @@ DONE; }) -(define_insn "andsi3" +(define_insn_and_split "andsi3" [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r,r") (and:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0,r,r,0") (match_operand:SI 2 "rx_source_operand" "r,Uint04,Sint08,Sint16,Sint24,i,0,r,Q"))) @@ -1110,6 +1110,21 @@ and\t%1, %0 and\t%2, %1, %0 and\t%Q2, %0" + "&& RX_REG_P (operands[1]) && CONST_INT_P (operands[2]) + && pow2p_hwi (~UINTVAL (operands[2]))" + [(const_int 0)] +{ + /* For negated single bit constants use the bclr insn for smaller code. */ + + if (!rx_reg_dead_or_unused_after_insn (curr_insn, CC_REG)) + FAIL; + + rx_copy_reg_dead_or_unused_notes (operands[1], curr_insn, + emit_insn (gen_bitclr (operands[0], + GEN_INT (exact_log2 (~UINTVAL (operands[2]))), + operands[1]))); + DONE; +} [(set_attr "timings" "11,11,11,11,11,11,11,11,33") (set_attr "length" "2,2,3,4,5,6,2,5,5")] ) @@ -1383,7 +1398,7 @@ [(set_attr "length" "2,3")] ) -(define_insn "iorsi3" +(define_insn_and_split "iorsi3" [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r,r") (ior:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0,r,r,0") (match_operand:SI 2 "rx_source_operand" "r,Uint04,Sint08,Sint16,Sint24,i,0,r,Q"))) @@ -1399,6 +1414,21 @@ or\t%1, %0 or\t%2, %1, %0 or\t%Q2, %0" + "&& RX_REG_P (operands[1]) && CONST_INT_P (operands[2]) + && pow2p_hwi (UINTVAL (operands[2]))" + [(const_int 0)] +{ + /* For single bit constants use the bset insn for smaller code. */ + + if (!rx_reg_dead_or_unused_after_insn (curr_insn, CC_REG)) + FAIL; + + rx_copy_reg_dead_or_unused_notes (operands[1], curr_insn, + emit_insn (gen_bitset (operands[0], + GEN_INT (exact_log2 (UINTVAL (operands[2]))), + operands[1]))); + DONE; +} [(set_attr "timings" "11,11,11,11,11,11,11,11,33") (set_attr "length" "2,2,3,4,5,6,2,3,5")] ) @@ -1704,7 +1734,7 @@ DONE; }) -(define_insn "xorsi3" +(define_insn_and_split "xorsi3" [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r") (xor:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0") (match_operand:SI 2 "rx_source_operand" @@ -1712,6 +1742,21 @@ (clobber (reg:CC CC_REG))] "" "xor\t%Q2, %0" + "&& RX_REG_P (operands[1]) && CONST_INT_P (operands[2]) + && pow2p_hwi (UINTVAL (operands[2]))" + [(const_int 0)] +{ + /* For single bit constants use the bnot insn for smaller code. */ + + if (!rx_reg_dead_or_unused_after_insn (curr_insn, CC_REG)) + FAIL; + + rx_copy_reg_dead_or_unused_notes (operands[1], curr_insn, + emit_insn (gen_bitinvert (operands[0], + GEN_INT (exact_log2 (UINTVAL (operands[2]))), + operands[1]))); + DONE; +} [(set_attr "timings" "11,11,11,11,11,33") (set_attr "length" "3,4,5,6,7,6")] ) @@ -1960,50 +2005,63 @@ ;; Bit manipulation instructions. -;; ??? The *_in_memory patterns will not be matched without further help. -;; At one time we had the insv expander generate them, but I suspect that -;; in general we get better performance by exposing the register load to -;; the optimizers. -;; -;; An alternate solution would be to re-organize these patterns such -;; that allow both register and memory operands. This would allow the -;; register allocator to spill and not load the register operand. This -;; would be possible only for operations for which we have a constant -;; bit offset, so that we can adjust the address by ofs/8 and replace -;; the offset in the insn by ofs%8. - -(define_insn "*bitset" +;; The *_in_memory patterns will not be matched automatically, not even with +;; combiner bridge patterns. Especially when the memory operands have a +;; displacement, the resulting patterns look too complex. +;; Instead we manually look around the matched insn to see if there is a +;; preceeding memory load and a following memory store of the modified register +;; which can be fused into the single *_in_memory insn. +;; Do that before register allocation, as it can eliminate one temporary +;; register that needs to be allocated. + +(define_insn_and_split "bitset" [(set (match_operand:SI 0 "register_operand" "=r") (ior:SI (ashift:SI (const_int 1) (match_operand:SI 1 "rx_shift_operand" "ri")) (match_operand:SI 2 "register_operand" "0")))] "" "bset\t%1, %0" + "&& can_create_pseudo_p ()" + [(const_int 0)] +{ + if (rx_fuse_in_memory_bitop (operands, curr_insn, &gen_bitset_in_memory)) + DONE; + else + FAIL; +} [(set_attr "length" "3")] ) -(define_insn "*bitset_in_memory" +(define_insn "bitset_in_memory" [(set (match_operand:QI 0 "rx_restricted_mem_operand" "+Q") (ior:QI (ashift:QI (const_int 1) (match_operand:QI 1 "nonmemory_operand" "ri")) (match_dup 0)))] "" "bset\t%1, %0.B" - [(set_attr "length" "3") + [(set_attr "length" "5") (set_attr "timings" "33")] ) -(define_insn "*bitinvert" +(define_insn_and_split "bitinvert" [(set (match_operand:SI 0 "register_operand" "=r") (xor:SI (ashift:SI (const_int 1) (match_operand:SI 1 "rx_shift_operand" "ri")) (match_operand:SI 2 "register_operand" "0")))] "" "bnot\t%1, %0" + "&& can_create_pseudo_p ()" + [(const_int 0)] +{ + if (rx_fuse_in_memory_bitop (operands, curr_insn, &gen_bitinvert_in_memory)) + DONE; + else + FAIL; +} [(set_attr "length" "3")] ) -(define_insn "*bitinvert_in_memory" +(define_insn "bitinvert_in_memory" [(set (match_operand:QI 0 "rx_restricted_mem_operand" "+Q") (xor:QI (ashift:QI (const_int 1) (match_operand:QI 1 "nonmemory_operand" "ri")) @@ -2014,7 +2072,7 @@ (set_attr "timings" "33")] ) -(define_insn "*bitclr" +(define_insn_and_split "bitclr" [(set (match_operand:SI 0 "register_operand" "=r") (and:SI (not:SI (ashift:SI @@ -2023,10 +2081,18 @@ (match_operand:SI 2 "register_operand" "0")))] "" "bclr\t%1, %0" + "&& can_create_pseudo_p ()" + [(const_int 0)] +{ + if (rx_fuse_in_memory_bitop (operands, curr_insn, &gen_bitclr_in_memory)) + DONE; + else + FAIL; +} [(set_attr "length" "3")] ) -(define_insn "*bitclr_in_memory" +(define_insn "bitclr_in_memory" [(set (match_operand:QI 0 "rx_restricted_mem_operand" "+Q") (and:QI (not:QI (ashift:QI @@ -2035,7 +2101,7 @@ (match_dup 0)))] "" "bclr\t%1, %0.B" - [(set_attr "length" "3") + [(set_attr "length" "5") (set_attr "timings" "33")] ) diff --git a/gcc/config/s390/s390.c b/gcc/config/s390/s390.c index 298fdd16490..51adb0df480 100644 --- a/gcc/config/s390/s390.c +++ b/gcc/config/s390/s390.c @@ -9259,7 +9259,6 @@ s390_chunkify_start (void) section_switch_p = true; break; case NOTE_INSN_VAR_LOCATION: - case NOTE_INSN_CALL_ARG_LOCATION: continue; default: break; @@ -9330,8 +9329,7 @@ s390_chunkify_start (void) } while (next && NOTE_P (next) - && (NOTE_KIND (next) == NOTE_INSN_VAR_LOCATION - || NOTE_KIND (next) == NOTE_INSN_CALL_ARG_LOCATION)); + && NOTE_KIND (next) == NOTE_INSN_VAR_LOCATION); } else { diff --git a/gcc/config/sh/sh.c b/gcc/config/sh/sh.c index 90d6c733d33..ced66408265 100644 --- a/gcc/config/sh/sh.c +++ b/gcc/config/sh/sh.c @@ -5225,21 +5225,13 @@ find_barrier (int num_mova, rtx_insn *mova, rtx_insn *from) around the constant pool table will be hit. Putting it before a jump makes it more likely that the bra delay slot will be filled. */ - while (NOTE_P (from) || JUMP_P (from) - || LABEL_P (from)) + while (NOTE_P (from) || JUMP_P (from) || LABEL_P (from)) from = PREV_INSN (from); - /* Make sure we do not split between a call and its corresponding - CALL_ARG_LOCATION note. */ if (CALL_P (from)) { bool sibcall_p = SIBLING_CALL_P (from); - rtx_insn *next = NEXT_INSN (from); - if (next && NOTE_P (next) - && NOTE_KIND (next) == NOTE_INSN_CALL_ARG_LOCATION) - from = next; - /* If FROM was a sibling call, then we know that control will not return. In fact, we were guaranteed to hit a barrier before another real insn. diff --git a/gcc/config/xtensa/xtensa.c b/gcc/config/xtensa/xtensa.c index 23cdf4d26bf..7cfe64d4289 100644 --- a/gcc/config/xtensa/xtensa.c +++ b/gcc/config/xtensa/xtensa.c @@ -4255,10 +4255,7 @@ hwloop_optimize (hwloop_info loop) entry_after = BB_END (entry_bb); while (DEBUG_INSN_P (entry_after) || (NOTE_P (entry_after) - && NOTE_KIND (entry_after) != NOTE_INSN_BASIC_BLOCK - /* Make sure we don't split a call and its corresponding - CALL_ARG_LOCATION note. */ - && NOTE_KIND (entry_after) != NOTE_INSN_CALL_ARG_LOCATION)) + && NOTE_KIND (entry_after) != NOTE_INSN_BASIC_BLOCK)) entry_after = PREV_INSN (entry_after); emit_insn_after (seq, entry_after); |