diff options
Diffstat (limited to 'gcc/config/rs6000/vector.md')
| -rw-r--r-- | gcc/config/rs6000/vector.md | 473 |
1 files changed, 225 insertions, 248 deletions
diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md index 3bcf087d2cd..6e2576ee1d8 100644 --- a/gcc/config/rs6000/vector.md +++ b/gcc/config/rs6000/vector.md @@ -111,8 +111,8 @@ ;; Vector move instructions. Little-endian VSX loads and stores require ;; special handling to circumvent "element endianness." (define_expand "mov<mode>" - [(set (match_operand:VEC_M 0 "nonimmediate_operand" "") - (match_operand:VEC_M 1 "any_operand" ""))] + [(set (match_operand:VEC_M 0 "nonimmediate_operand") + (match_operand:VEC_M 1 "any_operand"))] "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)" { if (can_create_pseudo_p ()) @@ -147,21 +147,21 @@ ;; Generic vector floating point load/store instructions. These will match ;; insns defined in vsx.md or altivec.md depending on the switches. (define_expand "vector_load_<mode>" - [(set (match_operand:VEC_M 0 "vfloat_operand" "") - (match_operand:VEC_M 1 "memory_operand" ""))] + [(set (match_operand:VEC_M 0 "vfloat_operand") + (match_operand:VEC_M 1 "memory_operand"))] "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)" "") (define_expand "vector_store_<mode>" - [(set (match_operand:VEC_M 0 "memory_operand" "") - (match_operand:VEC_M 1 "vfloat_operand" ""))] + [(set (match_operand:VEC_M 0 "memory_operand") + (match_operand:VEC_M 1 "vfloat_operand"))] "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)" "") ;; Splits if a GPR register was chosen for the move (define_split - [(set (match_operand:VEC_L 0 "nonimmediate_operand" "") - (match_operand:VEC_L 1 "input_operand" ""))] + [(set (match_operand:VEC_L 0 "nonimmediate_operand") + (match_operand:VEC_L 1 "input_operand"))] "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode) && reload_completed && gpr_or_gpr_p (operands[0], operands[1]) @@ -178,10 +178,9 @@ ;; instructions silently ignore the bottom 3 bits of the address, and VSX does ;; not. (define_expand "vector_altivec_load_<mode>" - [(set (match_operand:VEC_M 0 "vfloat_operand" "") - (match_operand:VEC_M 1 "memory_operand" ""))] + [(set (match_operand:VEC_M 0 "vfloat_operand") + (match_operand:VEC_M 1 "memory_operand"))] "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)" - " { gcc_assert (VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)); @@ -198,13 +197,12 @@ emit_insn (gen_altivec_lvx_<mode>_1op (operands[0], operands[1])); DONE; } -}") +}) (define_expand "vector_altivec_store_<mode>" - [(set (match_operand:VEC_M 0 "memory_operand" "") - (match_operand:VEC_M 1 "vfloat_operand" ""))] + [(set (match_operand:VEC_M 0 "memory_operand") + (match_operand:VEC_M 1 "vfloat_operand"))] "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)" - " { gcc_assert (VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)); @@ -221,29 +219,29 @@ emit_insn (gen_altivec_stvx_<mode>_1op (operands[1], operands[0])); DONE; } -}") +}) ;; Generic floating point vector arithmetic support (define_expand "add<mode>3" - [(set (match_operand:VEC_F 0 "vfloat_operand" "") - (plus:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "") - (match_operand:VEC_F 2 "vfloat_operand" "")))] + [(set (match_operand:VEC_F 0 "vfloat_operand") + (plus:VEC_F (match_operand:VEC_F 1 "vfloat_operand") + (match_operand:VEC_F 2 "vfloat_operand")))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" "") (define_expand "sub<mode>3" - [(set (match_operand:VEC_F 0 "vfloat_operand" "") - (minus:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "") - (match_operand:VEC_F 2 "vfloat_operand" "")))] + [(set (match_operand:VEC_F 0 "vfloat_operand") + (minus:VEC_F (match_operand:VEC_F 1 "vfloat_operand") + (match_operand:VEC_F 2 "vfloat_operand")))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" "") (define_expand "mul<mode>3" - [(set (match_operand:VEC_F 0 "vfloat_operand" "") - (mult:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "") - (match_operand:VEC_F 2 "vfloat_operand" "")))] + [(set (match_operand:VEC_F 0 "vfloat_operand") + (mult:VEC_F (match_operand:VEC_F 1 "vfloat_operand") + (match_operand:VEC_F 2 "vfloat_operand")))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" { if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode)) @@ -254,9 +252,9 @@ }) (define_expand "div<mode>3" - [(set (match_operand:VEC_F 0 "vfloat_operand" "") - (div:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "") - (match_operand:VEC_F 2 "vfloat_operand" "")))] + [(set (match_operand:VEC_F 0 "vfloat_operand") + (div:VEC_F (match_operand:VEC_F 1 "vfloat_operand") + (match_operand:VEC_F 2 "vfloat_operand")))] "VECTOR_UNIT_VSX_P (<MODE>mode)" { if (RS6000_RECIP_AUTO_RE_P (<MODE>mode) @@ -269,49 +267,47 @@ }) (define_expand "neg<mode>2" - [(set (match_operand:VEC_F 0 "vfloat_operand" "") - (neg:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")))] + [(set (match_operand:VEC_F 0 "vfloat_operand") + (neg:VEC_F (match_operand:VEC_F 1 "vfloat_operand")))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" - " { if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode)) { emit_insn (gen_altivec_negv4sf2 (operands[0], operands[1])); DONE; } -}") +}) (define_expand "abs<mode>2" - [(set (match_operand:VEC_F 0 "vfloat_operand" "") - (abs:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")))] + [(set (match_operand:VEC_F 0 "vfloat_operand") + (abs:VEC_F (match_operand:VEC_F 1 "vfloat_operand")))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" - " { if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode)) { emit_insn (gen_altivec_absv4sf2 (operands[0], operands[1])); DONE; } -}") +}) (define_expand "smin<mode>3" - [(set (match_operand:VEC_F 0 "register_operand" "") - (smin:VEC_F (match_operand:VEC_F 1 "register_operand" "") - (match_operand:VEC_F 2 "register_operand" "")))] + [(set (match_operand:VEC_F 0 "register_operand") + (smin:VEC_F (match_operand:VEC_F 1 "register_operand") + (match_operand:VEC_F 2 "register_operand")))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" "") (define_expand "smax<mode>3" - [(set (match_operand:VEC_F 0 "register_operand" "") - (smax:VEC_F (match_operand:VEC_F 1 "register_operand" "") - (match_operand:VEC_F 2 "register_operand" "")))] + [(set (match_operand:VEC_F 0 "register_operand") + (smax:VEC_F (match_operand:VEC_F 1 "register_operand") + (match_operand:VEC_F 2 "register_operand")))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" "") (define_expand "sqrt<mode>2" - [(set (match_operand:VEC_F 0 "vfloat_operand" "") - (sqrt:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")))] + [(set (match_operand:VEC_F 0 "vfloat_operand") + (sqrt:VEC_F (match_operand:VEC_F 1 "vfloat_operand")))] "VECTOR_UNIT_VSX_P (<MODE>mode)" { if (<MODE>mode == V4SFmode @@ -325,51 +321,50 @@ }) (define_expand "rsqrte<mode>2" - [(set (match_operand:VEC_F 0 "vfloat_operand" "") - (unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand" "")] + [(set (match_operand:VEC_F 0 "vfloat_operand") + (unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand")] UNSPEC_RSQRT))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" "") (define_expand "re<mode>2" - [(set (match_operand:VEC_F 0 "vfloat_operand" "") - (unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand" "f")] + [(set (match_operand:VEC_F 0 "vfloat_operand") + (unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand")] UNSPEC_FRES))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" "") (define_expand "ftrunc<mode>2" - [(set (match_operand:VEC_F 0 "vfloat_operand" "") - (fix:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")))] + [(set (match_operand:VEC_F 0 "vfloat_operand") + (fix:VEC_F (match_operand:VEC_F 1 "vfloat_operand")))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" "") (define_expand "vector_ceil<mode>2" - [(set (match_operand:VEC_F 0 "vfloat_operand" "") - (unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand" "")] + [(set (match_operand:VEC_F 0 "vfloat_operand") + (unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand")] UNSPEC_FRIP))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" "") (define_expand "vector_floor<mode>2" - [(set (match_operand:VEC_F 0 "vfloat_operand" "") - (unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand" "")] + [(set (match_operand:VEC_F 0 "vfloat_operand") + (unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand")] UNSPEC_FRIM))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" "") (define_expand "vector_btrunc<mode>2" - [(set (match_operand:VEC_F 0 "vfloat_operand" "") - (fix:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")))] + [(set (match_operand:VEC_F 0 "vfloat_operand") + (fix:VEC_F (match_operand:VEC_F 1 "vfloat_operand")))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" "") (define_expand "vector_copysign<mode>3" - [(set (match_operand:VEC_F 0 "vfloat_operand" "") - (unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand" "") - (match_operand:VEC_F 2 "vfloat_operand" "")] UNSPEC_COPYSIGN))] + [(set (match_operand:VEC_F 0 "vfloat_operand") + (unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand") + (match_operand:VEC_F 2 "vfloat_operand")] UNSPEC_COPYSIGN))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" - " { if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode)) { @@ -377,27 +372,26 @@ operands[2])); DONE; } -}") +}) ;; Vector comparisons (define_expand "vcond<mode><mode>" - [(set (match_operand:VEC_F 0 "vfloat_operand" "") + [(set (match_operand:VEC_F 0 "vfloat_operand") (if_then_else:VEC_F (match_operator 3 "comparison_operator" - [(match_operand:VEC_F 4 "vfloat_operand" "") - (match_operand:VEC_F 5 "vfloat_operand" "")]) - (match_operand:VEC_F 1 "vfloat_operand" "") - (match_operand:VEC_F 2 "vfloat_operand" "")))] + [(match_operand:VEC_F 4 "vfloat_operand") + (match_operand:VEC_F 5 "vfloat_operand")]) + (match_operand:VEC_F 1 "vfloat_operand") + (match_operand:VEC_F 2 "vfloat_operand")))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" - " { if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2], operands[3], operands[4], operands[5])) DONE; else FAIL; -}") +}) (define_expand "vcond<mode><mode>" [(set (match_operand:VEC_I 0 "vint_operand") @@ -408,52 +402,49 @@ (match_operand:VEC_I 1 "vector_int_reg_or_same_bit") (match_operand:VEC_I 2 "vector_int_reg_or_same_bit")))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" - " { if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2], operands[3], operands[4], operands[5])) DONE; else FAIL; -}") +}) (define_expand "vcondv4sfv4si" - [(set (match_operand:V4SF 0 "vfloat_operand" "") + [(set (match_operand:V4SF 0 "vfloat_operand") (if_then_else:V4SF (match_operator 3 "comparison_operator" - [(match_operand:V4SI 4 "vint_operand" "") - (match_operand:V4SI 5 "vint_operand" "")]) - (match_operand:V4SF 1 "vfloat_operand" "") - (match_operand:V4SF 2 "vfloat_operand" "")))] + [(match_operand:V4SI 4 "vint_operand") + (match_operand:V4SI 5 "vint_operand")]) + (match_operand:V4SF 1 "vfloat_operand") + (match_operand:V4SF 2 "vfloat_operand")))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode) && VECTOR_UNIT_ALTIVEC_P (V4SImode)" - " { if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2], operands[3], operands[4], operands[5])) DONE; else FAIL; -}") +}) (define_expand "vcondv4siv4sf" - [(set (match_operand:V4SI 0 "vint_operand" "") + [(set (match_operand:V4SI 0 "vint_operand") (if_then_else:V4SI (match_operator 3 "comparison_operator" - [(match_operand:V4SF 4 "vfloat_operand" "") - (match_operand:V4SF 5 "vfloat_operand" "")]) - (match_operand:V4SI 1 "vint_operand" "") - (match_operand:V4SI 2 "vint_operand" "")))] + [(match_operand:V4SF 4 "vfloat_operand") + (match_operand:V4SF 5 "vfloat_operand")]) + (match_operand:V4SI 1 "vint_operand") + (match_operand:V4SI 2 "vint_operand")))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode) && VECTOR_UNIT_ALTIVEC_P (V4SImode)" - " { if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2], operands[3], operands[4], operands[5])) DONE; else FAIL; -}") +}) (define_expand "vcondv2dfv2di" [(set (match_operand:V2DF 0 "vfloat_operand") @@ -500,33 +491,31 @@ (match_operand:VEC_I 1 "vector_int_reg_or_same_bit") (match_operand:VEC_I 2 "vector_int_reg_or_same_bit")))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" - " { if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2], operands[3], operands[4], operands[5])) DONE; else FAIL; -}") +}) (define_expand "vconduv4sfv4si" - [(set (match_operand:V4SF 0 "vfloat_operand" "") + [(set (match_operand:V4SF 0 "vfloat_operand") (if_then_else:V4SF (match_operator 3 "comparison_operator" - [(match_operand:V4SI 4 "vint_operand" "") - (match_operand:V4SI 5 "vint_operand" "")]) - (match_operand:V4SF 1 "vfloat_operand" "") - (match_operand:V4SF 2 "vfloat_operand" "")))] + [(match_operand:V4SI 4 "vint_operand") + (match_operand:V4SI 5 "vint_operand")]) + (match_operand:V4SF 1 "vfloat_operand") + (match_operand:V4SF 2 "vfloat_operand")))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode) && VECTOR_UNIT_ALTIVEC_P (V4SImode)" - " { if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2], operands[3], operands[4], operands[5])) DONE; else FAIL; -}") +}) (define_expand "vconduv2dfv2di" [(set (match_operand:V2DF 0 "vfloat_operand") @@ -547,95 +536,91 @@ }) (define_expand "vector_eq<mode>" - [(set (match_operand:VEC_C 0 "vlogical_operand" "") - (eq:VEC_C (match_operand:VEC_C 1 "vlogical_operand" "") - (match_operand:VEC_C 2 "vlogical_operand" "")))] + [(set (match_operand:VEC_C 0 "vlogical_operand") + (eq:VEC_C (match_operand:VEC_C 1 "vlogical_operand") + (match_operand:VEC_C 2 "vlogical_operand")))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" "") (define_expand "vector_gt<mode>" - [(set (match_operand:VEC_C 0 "vlogical_operand" "") - (gt:VEC_C (match_operand:VEC_C 1 "vlogical_operand" "") - (match_operand:VEC_C 2 "vlogical_operand" "")))] + [(set (match_operand:VEC_C 0 "vlogical_operand") + (gt:VEC_C (match_operand:VEC_C 1 "vlogical_operand") + (match_operand:VEC_C 2 "vlogical_operand")))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" "") (define_expand "vector_ge<mode>" - [(set (match_operand:VEC_F 0 "vlogical_operand" "") - (ge:VEC_F (match_operand:VEC_F 1 "vlogical_operand" "") - (match_operand:VEC_F 2 "vlogical_operand" "")))] + [(set (match_operand:VEC_F 0 "vlogical_operand") + (ge:VEC_F (match_operand:VEC_F 1 "vlogical_operand") + (match_operand:VEC_F 2 "vlogical_operand")))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" "") ; >= for integer vectors: swap operands and apply not-greater-than (define_expand "vector_nlt<mode>" - [(set (match_operand:VEC_I 3 "vlogical_operand" "") - (gt:VEC_I (match_operand:VEC_I 2 "vlogical_operand" "") - (match_operand:VEC_I 1 "vlogical_operand" ""))) - (set (match_operand:VEC_I 0 "vlogical_operand" "") + [(set (match_operand:VEC_I 3 "vlogical_operand") + (gt:VEC_I (match_operand:VEC_I 2 "vlogical_operand") + (match_operand:VEC_I 1 "vlogical_operand"))) + (set (match_operand:VEC_I 0 "vlogical_operand") (not:VEC_I (match_dup 3)))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" - " { operands[3] = gen_reg_rtx_and_attrs (operands[0]); -}") +}) (define_expand "vector_gtu<mode>" - [(set (match_operand:VEC_I 0 "vint_operand" "") - (gtu:VEC_I (match_operand:VEC_I 1 "vint_operand" "") - (match_operand:VEC_I 2 "vint_operand" "")))] + [(set (match_operand:VEC_I 0 "vint_operand") + (gtu:VEC_I (match_operand:VEC_I 1 "vint_operand") + (match_operand:VEC_I 2 "vint_operand")))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" "") ; >= for integer vectors: swap operands and apply not-greater-than (define_expand "vector_nltu<mode>" - [(set (match_operand:VEC_I 3 "vlogical_operand" "") - (gtu:VEC_I (match_operand:VEC_I 2 "vlogical_operand" "") - (match_operand:VEC_I 1 "vlogical_operand" ""))) - (set (match_operand:VEC_I 0 "vlogical_operand" "") + [(set (match_operand:VEC_I 3 "vlogical_operand") + (gtu:VEC_I (match_operand:VEC_I 2 "vlogical_operand") + (match_operand:VEC_I 1 "vlogical_operand"))) + (set (match_operand:VEC_I 0 "vlogical_operand") (not:VEC_I (match_dup 3)))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" - " { operands[3] = gen_reg_rtx_and_attrs (operands[0]); -}") +}) (define_expand "vector_geu<mode>" - [(set (match_operand:VEC_I 0 "vint_operand" "") - (geu:VEC_I (match_operand:VEC_I 1 "vint_operand" "") - (match_operand:VEC_I 2 "vint_operand" "")))] + [(set (match_operand:VEC_I 0 "vint_operand") + (geu:VEC_I (match_operand:VEC_I 1 "vint_operand") + (match_operand:VEC_I 2 "vint_operand")))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" "") ; <= for integer vectors: apply not-greater-than (define_expand "vector_ngt<mode>" - [(set (match_operand:VEC_I 3 "vlogical_operand" "") - (gt:VEC_I (match_operand:VEC_I 1 "vlogical_operand" "") - (match_operand:VEC_I 2 "vlogical_operand" ""))) - (set (match_operand:VEC_I 0 "vlogical_operand" "") + [(set (match_operand:VEC_I 3 "vlogical_operand") + (gt:VEC_I (match_operand:VEC_I 1 "vlogical_operand") + (match_operand:VEC_I 2 "vlogical_operand"))) + (set (match_operand:VEC_I 0 "vlogical_operand") (not:VEC_I (match_dup 3)))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" - " { operands[3] = gen_reg_rtx_and_attrs (operands[0]); -}") +}) (define_expand "vector_ngtu<mode>" - [(set (match_operand:VEC_I 3 "vlogical_operand" "") - (gtu:VEC_I (match_operand:VEC_I 1 "vlogical_operand" "") - (match_operand:VEC_I 2 "vlogical_operand" ""))) - (set (match_operand:VEC_I 0 "vlogical_operand" "") + [(set (match_operand:VEC_I 3 "vlogical_operand") + (gtu:VEC_I (match_operand:VEC_I 1 "vlogical_operand") + (match_operand:VEC_I 2 "vlogical_operand"))) + (set (match_operand:VEC_I 0 "vlogical_operand") (not:VEC_I (match_dup 3)))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" - " { operands[3] = gen_reg_rtx_and_attrs (operands[0]); -}") +}) (define_insn_and_split "*vector_uneq<mode>" - [(set (match_operand:VEC_F 0 "vfloat_operand" "") - (uneq:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "") - (match_operand:VEC_F 2 "vfloat_operand" "")))] + [(set (match_operand:VEC_F 0 "vfloat_operand") + (uneq:VEC_F (match_operand:VEC_F 1 "vfloat_operand") + (match_operand:VEC_F 2 "vfloat_operand")))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" "#" "" @@ -654,9 +639,9 @@ }) (define_insn_and_split "*vector_ltgt<mode>" - [(set (match_operand:VEC_F 0 "vfloat_operand" "") - (ltgt:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "") - (match_operand:VEC_F 2 "vfloat_operand" "")))] + [(set (match_operand:VEC_F 0 "vfloat_operand") + (ltgt:VEC_F (match_operand:VEC_F 1 "vfloat_operand") + (match_operand:VEC_F 2 "vfloat_operand")))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" "#" "" @@ -669,16 +654,15 @@ (set (match_dup 0) (ior:VEC_F (match_dup 3) (match_dup 4)))] - " { operands[3] = gen_reg_rtx (<MODE>mode); operands[4] = gen_reg_rtx (<MODE>mode); -}") +}) (define_insn_and_split "*vector_ordered<mode>" - [(set (match_operand:VEC_F 0 "vfloat_operand" "") - (ordered:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "") - (match_operand:VEC_F 2 "vfloat_operand" "")))] + [(set (match_operand:VEC_F 0 "vfloat_operand") + (ordered:VEC_F (match_operand:VEC_F 1 "vfloat_operand") + (match_operand:VEC_F 2 "vfloat_operand")))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" "#" "" @@ -691,16 +675,15 @@ (set (match_dup 0) (ior:VEC_F (match_dup 3) (match_dup 4)))] - " { operands[3] = gen_reg_rtx (<MODE>mode); operands[4] = gen_reg_rtx (<MODE>mode); -}") +}) (define_insn_and_split "*vector_unordered<mode>" - [(set (match_operand:VEC_F 0 "vfloat_operand" "") - (unordered:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "") - (match_operand:VEC_F 2 "vfloat_operand" "")))] + [(set (match_operand:VEC_F 0 "vfloat_operand") + (unordered:VEC_F (match_operand:VEC_F 1 "vfloat_operand") + (match_operand:VEC_F 2 "vfloat_operand")))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" "#" "" @@ -713,31 +696,30 @@ (set (match_dup 0) (and:VEC_F (not:VEC_F (match_dup 3)) (not:VEC_F (match_dup 4))))] - " { operands[3] = gen_reg_rtx (<MODE>mode); operands[4] = gen_reg_rtx (<MODE>mode); -}") +}) ;; Note the arguments for __builtin_altivec_vsel are op2, op1, mask ;; which is in the reverse order that we want (define_expand "vector_select_<mode>" - [(set (match_operand:VEC_L 0 "vlogical_operand" "") + [(set (match_operand:VEC_L 0 "vlogical_operand") (if_then_else:VEC_L - (ne:CC (match_operand:VEC_L 3 "vlogical_operand" "") + (ne:CC (match_operand:VEC_L 3 "vlogical_operand") (match_dup 4)) - (match_operand:VEC_L 2 "vlogical_operand" "") - (match_operand:VEC_L 1 "vlogical_operand" "")))] + (match_operand:VEC_L 2 "vlogical_operand") + (match_operand:VEC_L 1 "vlogical_operand")))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" "operands[4] = CONST0_RTX (<MODE>mode);") (define_expand "vector_select_<mode>_uns" - [(set (match_operand:VEC_L 0 "vlogical_operand" "") + [(set (match_operand:VEC_L 0 "vlogical_operand") (if_then_else:VEC_L - (ne:CCUNS (match_operand:VEC_L 3 "vlogical_operand" "") + (ne:CCUNS (match_operand:VEC_L 3 "vlogical_operand") (match_dup 4)) - (match_operand:VEC_L 2 "vlogical_operand" "") - (match_operand:VEC_L 1 "vlogical_operand" "")))] + (match_operand:VEC_L 2 "vlogical_operand") + (match_operand:VEC_L 1 "vlogical_operand")))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" "operands[4] = CONST0_RTX (<MODE>mode);") @@ -746,10 +728,10 @@ (define_expand "vector_eq_<mode>_p" [(parallel [(set (reg:CC CR6_REGNO) - (unspec:CC [(eq:CC (match_operand:VEC_A 1 "vlogical_operand" "") - (match_operand:VEC_A 2 "vlogical_operand" ""))] + (unspec:CC [(eq:CC (match_operand:VEC_A 1 "vlogical_operand") + (match_operand:VEC_A 2 "vlogical_operand"))] UNSPEC_PREDICATE)) - (set (match_operand:VEC_A 0 "vlogical_operand" "") + (set (match_operand:VEC_A 0 "vlogical_operand") (eq:VEC_A (match_dup 1) (match_dup 2)))])] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" @@ -913,10 +895,10 @@ (define_expand "vector_gt_<mode>_p" [(parallel [(set (reg:CC CR6_REGNO) - (unspec:CC [(gt:CC (match_operand:VEC_A 1 "vlogical_operand" "") - (match_operand:VEC_A 2 "vlogical_operand" ""))] + (unspec:CC [(gt:CC (match_operand:VEC_A 1 "vlogical_operand") + (match_operand:VEC_A 2 "vlogical_operand"))] UNSPEC_PREDICATE)) - (set (match_operand:VEC_A 0 "vlogical_operand" "") + (set (match_operand:VEC_A 0 "vlogical_operand") (gt:VEC_A (match_dup 1) (match_dup 2)))])] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" @@ -925,10 +907,10 @@ (define_expand "vector_ge_<mode>_p" [(parallel [(set (reg:CC CR6_REGNO) - (unspec:CC [(ge:CC (match_operand:VEC_F 1 "vfloat_operand" "") - (match_operand:VEC_F 2 "vfloat_operand" ""))] + (unspec:CC [(ge:CC (match_operand:VEC_F 1 "vfloat_operand") + (match_operand:VEC_F 2 "vfloat_operand"))] UNSPEC_PREDICATE)) - (set (match_operand:VEC_F 0 "vfloat_operand" "") + (set (match_operand:VEC_F 0 "vfloat_operand") (ge:VEC_F (match_dup 1) (match_dup 2)))])] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" @@ -937,10 +919,10 @@ (define_expand "vector_gtu_<mode>_p" [(parallel [(set (reg:CC CR6_REGNO) - (unspec:CC [(gtu:CC (match_operand:VEC_I 1 "vint_operand" "") - (match_operand:VEC_I 2 "vint_operand" ""))] + (unspec:CC [(gtu:CC (match_operand:VEC_I 1 "vint_operand") + (match_operand:VEC_I 2 "vint_operand"))] UNSPEC_PREDICATE)) - (set (match_operand:VEC_I 0 "vlogical_operand" "") + (set (match_operand:VEC_I 0 "vlogical_operand") (gtu:VEC_I (match_dup 1) (match_dup 2)))])] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" @@ -1002,87 +984,83 @@ ;; Vector count leading zeros (define_expand "clz<mode>2" - [(set (match_operand:VEC_I 0 "register_operand" "") - (clz:VEC_I (match_operand:VEC_I 1 "register_operand" "")))] + [(set (match_operand:VEC_I 0 "register_operand") + (clz:VEC_I (match_operand:VEC_I 1 "register_operand")))] "TARGET_P8_VECTOR") ;; Vector count trailing zeros (define_expand "ctz<mode>2" - [(set (match_operand:VEC_I 0 "register_operand" "") - (ctz:VEC_I (match_operand:VEC_I 1 "register_operand" "")))] + [(set (match_operand:VEC_I 0 "register_operand") + (ctz:VEC_I (match_operand:VEC_I 1 "register_operand")))] "TARGET_P9_VECTOR") ;; Vector population count (define_expand "popcount<mode>2" - [(set (match_operand:VEC_I 0 "register_operand" "") - (popcount:VEC_I (match_operand:VEC_I 1 "register_operand" "")))] + [(set (match_operand:VEC_I 0 "register_operand") + (popcount:VEC_I (match_operand:VEC_I 1 "register_operand")))] "TARGET_P8_VECTOR") ;; Vector parity (define_expand "parity<mode>2" - [(set (match_operand:VEC_IP 0 "register_operand" "") - (parity:VEC_IP (match_operand:VEC_IP 1 "register_operand" "")))] + [(set (match_operand:VEC_IP 0 "register_operand") + (parity:VEC_IP (match_operand:VEC_IP 1 "register_operand")))] "TARGET_P9_VECTOR") ;; Same size conversions (define_expand "float<VEC_int><mode>2" - [(set (match_operand:VEC_F 0 "vfloat_operand" "") - (float:VEC_F (match_operand:<VEC_INT> 1 "vint_operand" "")))] + [(set (match_operand:VEC_F 0 "vfloat_operand") + (float:VEC_F (match_operand:<VEC_INT> 1 "vint_operand")))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" - " { if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode)) { emit_insn (gen_altivec_vcfsx (operands[0], operands[1], const0_rtx)); DONE; } -}") +}) (define_expand "floatuns<VEC_int><mode>2" - [(set (match_operand:VEC_F 0 "vfloat_operand" "") - (unsigned_float:VEC_F (match_operand:<VEC_INT> 1 "vint_operand" "")))] + [(set (match_operand:VEC_F 0 "vfloat_operand") + (unsigned_float:VEC_F (match_operand:<VEC_INT> 1 "vint_operand")))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" - " { if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode)) { emit_insn (gen_altivec_vcfux (operands[0], operands[1], const0_rtx)); DONE; } -}") +}) (define_expand "fix_trunc<mode><VEC_int>2" - [(set (match_operand:<VEC_INT> 0 "vint_operand" "") - (fix:<VEC_INT> (match_operand:VEC_F 1 "vfloat_operand" "")))] + [(set (match_operand:<VEC_INT> 0 "vint_operand") + (fix:<VEC_INT> (match_operand:VEC_F 1 "vfloat_operand")))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" - " { if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode)) { emit_insn (gen_altivec_vctsxs (operands[0], operands[1], const0_rtx)); DONE; } -}") +}) (define_expand "fixuns_trunc<mode><VEC_int>2" - [(set (match_operand:<VEC_INT> 0 "vint_operand" "") - (unsigned_fix:<VEC_INT> (match_operand:VEC_F 1 "vfloat_operand" "")))] + [(set (match_operand:<VEC_INT> 0 "vint_operand") + (unsigned_fix:<VEC_INT> (match_operand:VEC_F 1 "vfloat_operand")))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" - " { if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode)) { emit_insn (gen_altivec_vctuxs (operands[0], operands[1], const0_rtx)); DONE; } -}") +}) ;; Vector initialization, set, extract (define_expand "vec_init<mode><VEC_base_l>" - [(match_operand:VEC_E 0 "vlogical_operand" "") - (match_operand:VEC_E 1 "" "")] + [(match_operand:VEC_E 0 "vlogical_operand") + (match_operand:VEC_E 1 "")] "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)" { rs6000_expand_vector_init (operands[0], operands[1]); @@ -1090,9 +1068,9 @@ }) (define_expand "vec_set<mode>" - [(match_operand:VEC_E 0 "vlogical_operand" "") - (match_operand:<VEC_base> 1 "register_operand" "") - (match_operand 2 "const_int_operand" "")] + [(match_operand:VEC_E 0 "vlogical_operand") + (match_operand:<VEC_base> 1 "register_operand") + (match_operand 2 "const_int_operand")] "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)" { rs6000_expand_vector_set (operands[0], operands[1], INTVAL (operands[2])); @@ -1100,9 +1078,9 @@ }) (define_expand "vec_extract<mode><VEC_base_l>" - [(match_operand:<VEC_base> 0 "register_operand" "") - (match_operand:VEC_E 1 "vlogical_operand" "") - (match_operand 2 "const_int_operand" "")] + [(match_operand:<VEC_base> 0 "register_operand") + (match_operand:VEC_E 1 "vlogical_operand") + (match_operand 2 "const_int_operand")] "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)" { rs6000_expand_vector_extract (operands[0], operands[1], operands[2]); @@ -1111,9 +1089,9 @@ ;; Convert double word types to single word types (define_expand "vec_pack_trunc_v2df" - [(match_operand:V4SF 0 "vfloat_operand" "") - (match_operand:V2DF 1 "vfloat_operand" "") - (match_operand:V2DF 2 "vfloat_operand" "")] + [(match_operand:V4SF 0 "vfloat_operand") + (match_operand:V2DF 1 "vfloat_operand") + (match_operand:V2DF 2 "vfloat_operand")] "VECTOR_UNIT_VSX_P (V2DFmode) && TARGET_ALTIVEC" { rtx r1 = gen_reg_rtx (V4SFmode); @@ -1126,9 +1104,9 @@ }) (define_expand "vec_pack_sfix_trunc_v2df" - [(match_operand:V4SI 0 "vint_operand" "") - (match_operand:V2DF 1 "vfloat_operand" "") - (match_operand:V2DF 2 "vfloat_operand" "")] + [(match_operand:V4SI 0 "vint_operand") + (match_operand:V2DF 1 "vfloat_operand") + (match_operand:V2DF 2 "vfloat_operand")] "VECTOR_UNIT_VSX_P (V2DFmode) && TARGET_ALTIVEC" { rtx r1 = gen_reg_rtx (V4SImode); @@ -1141,9 +1119,9 @@ }) (define_expand "vec_pack_ufix_trunc_v2df" - [(match_operand:V4SI 0 "vint_operand" "") - (match_operand:V2DF 1 "vfloat_operand" "") - (match_operand:V2DF 2 "vfloat_operand" "")] + [(match_operand:V4SI 0 "vint_operand") + (match_operand:V2DF 1 "vfloat_operand") + (match_operand:V2DF 2 "vfloat_operand")] "VECTOR_UNIT_VSX_P (V2DFmode) && TARGET_ALTIVEC" { rtx r1 = gen_reg_rtx (V4SImode); @@ -1157,8 +1135,8 @@ ;; Convert single word types to double word (define_expand "vec_unpacks_hi_v4sf" - [(match_operand:V2DF 0 "vfloat_operand" "") - (match_operand:V4SF 1 "vfloat_operand" "")] + [(match_operand:V2DF 0 "vfloat_operand") + (match_operand:V4SF 1 "vfloat_operand")] "VECTOR_UNIT_VSX_P (V2DFmode) && VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)" { rtx reg = gen_reg_rtx (V4SFmode); @@ -1169,8 +1147,8 @@ }) (define_expand "vec_unpacks_lo_v4sf" - [(match_operand:V2DF 0 "vfloat_operand" "") - (match_operand:V4SF 1 "vfloat_operand" "")] + [(match_operand:V2DF 0 "vfloat_operand") + (match_operand:V4SF 1 "vfloat_operand")] "VECTOR_UNIT_VSX_P (V2DFmode) && VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)" { rtx reg = gen_reg_rtx (V4SFmode); @@ -1181,8 +1159,8 @@ }) (define_expand "vec_unpacks_float_hi_v4si" - [(match_operand:V2DF 0 "vfloat_operand" "") - (match_operand:V4SI 1 "vint_operand" "")] + [(match_operand:V2DF 0 "vfloat_operand") + (match_operand:V4SI 1 "vint_operand")] "VECTOR_UNIT_VSX_P (V2DFmode) && VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SImode)" { rtx reg = gen_reg_rtx (V4SImode); @@ -1193,8 +1171,8 @@ }) (define_expand "vec_unpacks_float_lo_v4si" - [(match_operand:V2DF 0 "vfloat_operand" "") - (match_operand:V4SI 1 "vint_operand" "")] + [(match_operand:V2DF 0 "vfloat_operand") + (match_operand:V4SI 1 "vint_operand")] "VECTOR_UNIT_VSX_P (V2DFmode) && VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SImode)" { rtx reg = gen_reg_rtx (V4SImode); @@ -1205,8 +1183,8 @@ }) (define_expand "vec_unpacku_float_hi_v4si" - [(match_operand:V2DF 0 "vfloat_operand" "") - (match_operand:V4SI 1 "vint_operand" "")] + [(match_operand:V2DF 0 "vfloat_operand") + (match_operand:V4SI 1 "vint_operand")] "VECTOR_UNIT_VSX_P (V2DFmode) && VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SImode)" { rtx reg = gen_reg_rtx (V4SImode); @@ -1217,8 +1195,8 @@ }) (define_expand "vec_unpacku_float_lo_v4si" - [(match_operand:V2DF 0 "vfloat_operand" "") - (match_operand:V4SI 1 "vint_operand" "")] + [(match_operand:V2DF 0 "vfloat_operand") + (match_operand:V4SI 1 "vint_operand")] "VECTOR_UNIT_VSX_P (V2DFmode) && VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SImode)" { rtx reg = gen_reg_rtx (V4SImode); @@ -1231,10 +1209,10 @@ ;; Align vector loads with a permute. (define_expand "vec_realign_load_<mode>" - [(match_operand:VEC_K 0 "vlogical_operand" "") - (match_operand:VEC_K 1 "vlogical_operand" "") - (match_operand:VEC_K 2 "vlogical_operand" "") - (match_operand:V16QI 3 "vlogical_operand" "")] + [(match_operand:VEC_K 0 "vlogical_operand") + (match_operand:VEC_K 1 "vlogical_operand") + (match_operand:VEC_K 2 "vlogical_operand") + (match_operand:V16QI 3 "vlogical_operand")] "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)" { if (BYTES_BIG_ENDIAN) @@ -1256,8 +1234,8 @@ ;; Under VSX, vectors of 4/8 byte alignments do not need to be aligned ;; since the load already handles it. (define_expand "movmisalign<mode>" - [(set (match_operand:VEC_N 0 "nonimmediate_operand" "") - (match_operand:VEC_N 1 "any_operand" ""))] + [(set (match_operand:VEC_N 0 "nonimmediate_operand") + (match_operand:VEC_N 1 "any_operand"))] "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_ALLOW_MOVMISALIGN" "") @@ -1269,11 +1247,10 @@ ;; Note that the vec_shr operation is actually defined as ;; 'shift toward element 0' so is a shr for LE and shl for BE. (define_expand "vec_shr_<mode>" - [(match_operand:VEC_L 0 "vlogical_operand" "") - (match_operand:VEC_L 1 "vlogical_operand" "") - (match_operand:QI 2 "reg_or_short_operand" "")] + [(match_operand:VEC_L 0 "vlogical_operand") + (match_operand:VEC_L 1 "vlogical_operand") + (match_operand:QI 2 "reg_or_short_operand")] "TARGET_ALTIVEC" - " { rtx bitshift = operands[2]; rtx shift; @@ -1315,37 +1292,37 @@ emit_insn (insn); DONE; -}") +}) ;; Expanders for rotate each element in a vector (define_expand "vrotl<mode>3" - [(set (match_operand:VEC_I 0 "vint_operand" "") - (rotate:VEC_I (match_operand:VEC_I 1 "vint_operand" "") - (match_operand:VEC_I 2 "vint_operand" "")))] + [(set (match_operand:VEC_I 0 "vint_operand") + (rotate:VEC_I (match_operand:VEC_I 1 "vint_operand") + (match_operand:VEC_I 2 "vint_operand")))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" "") ;; Expanders for arithmetic shift left on each vector element (define_expand "vashl<mode>3" - [(set (match_operand:VEC_I 0 "vint_operand" "") - (ashift:VEC_I (match_operand:VEC_I 1 "vint_operand" "") - (match_operand:VEC_I 2 "vint_operand" "")))] + [(set (match_operand:VEC_I 0 "vint_operand") + (ashift:VEC_I (match_operand:VEC_I 1 "vint_operand") + (match_operand:VEC_I 2 "vint_operand")))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" "") ;; Expanders for logical shift right on each vector element (define_expand "vlshr<mode>3" - [(set (match_operand:VEC_I 0 "vint_operand" "") - (lshiftrt:VEC_I (match_operand:VEC_I 1 "vint_operand" "") - (match_operand:VEC_I 2 "vint_operand" "")))] + [(set (match_operand:VEC_I 0 "vint_operand") + (lshiftrt:VEC_I (match_operand:VEC_I 1 "vint_operand") + (match_operand:VEC_I 2 "vint_operand")))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" "") ;; Expanders for arithmetic shift right on each vector element (define_expand "vashr<mode>3" - [(set (match_operand:VEC_I 0 "vint_operand" "") - (ashiftrt:VEC_I (match_operand:VEC_I 1 "vint_operand" "") - (match_operand:VEC_I 2 "vint_operand" "")))] + [(set (match_operand:VEC_I 0 "vint_operand") + (ashiftrt:VEC_I (match_operand:VEC_I 1 "vint_operand") + (match_operand:VEC_I 2 "vint_operand")))] "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)" "") @@ -1359,8 +1336,8 @@ (define_expand "reduc_<VEC_reduc:VEC_reduc_name>_scal_<VEC_F:mode>" - [(match_operand:<VEC_base> 0 "register_operand" "") - (VEC_reduc:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "") + [(match_operand:<VEC_base> 0 "register_operand") + (VEC_reduc:VEC_F (match_operand:VEC_F 1 "vfloat_operand") (unspec:VEC_F [(const_int 0)] UNSPEC_REDUC))] "VECTOR_UNIT_VSX_P (<VEC_F:MODE>mode)" { |