Weekly merge from trunk. No regressions.reload-v2a

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/reload-v2a@181834 138bc75d-0d04-0410-961f-82ee72b054a4

6 files changed, 61 insertions, 9 deletions

diff --git a/gcc/doc/contrib.texi b/gcc/doc/contrib.texi
index f76cce8d234..ffefecc8607 100644
--- a/gcc/doc/contrib.texi
+++ b/gcc/doc/contrib.texi
@@ -66,6 +66,10 @@ improved alias analysis, plus migrating GCC to Bugzilla.
 Geoff Berry for his Java object serialization work and various patches.
 
 @item
+David Binderman tests weekly snapshots of GCC trunk against Fedora Rawhide
+for several architectures.
+
+@item
 Uros Bizjak for the implementation of x87 math built-in functions and
 for various middle end and i386 back end improvements and bug fixes.
 
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index 15238c1b39e..d52f9a0cf29 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -8594,11 +8594,41 @@ implements
 void __builtin_avr_delay_cycles (unsigned long ticks)
 @end smallexample
 
+@noindent
 @code{ticks} is the number of ticks to delay execution. Note that this
 built-in does not take into account the effect of interrupts which
 might increase delay time. @code{ticks} must be a compile time
 integer constant; delays with a variable number of cycles are not supported.
 
+@smallexample
+     unsigned char __builtin_avr_map8 (unsigned long map, unsigned char val)
+@end smallexample
+
+@noindent
+Each bit of the result is copied from a specific bit of @code{val}.
+@code{map} is a compile time constant that represents a map composed
+of 8 nibbles (4-bit groups):
+The @var{n}-th nibble of @code{map} specifies which bit of @code{val}
+is to be moved to the @var{n}-th bit of the result.
+For example, @code{map = 0x76543210} represents identity: The MSB of
+the result is read from the 7-th bit of @code{val}, the LSB is
+read from the 0-th bit to @code{val}, etc.
+Two more examples: @code{0x01234567} reverses the bit order and
+@code{0x32107654} is equivalent to a @code{swap} instruction.
+
+@noindent
+One typical use case for this and the following built-in is adjusting input and
+output values to non-contiguous port layouts.
+
+@smallexample
+     unsigned int __builtin_avr_map16 (unsigned long long map, unsigned int val)
+@end smallexample
+
+@noindent
+Similar to the previous built-in except that it operates on @code{int}
+and thus 16 bits are involved.  Again, @code{map} must be a compile
+time constant.
+
 @node Blackfin Built-in Functions
 @subsection Blackfin Built-in Functions
 
@@ -9384,6 +9414,7 @@ v2df __builtin_ia32_loadlpd (v2df, double const *)
 int __builtin_ia32_movmskpd (v2df)
 int __builtin_ia32_pmovmskb128 (v16qi)
 void __builtin_ia32_movnti (int *, int)
+void __builtin_ia32_movnti64 (long long int *, long long int)
 void __builtin_ia32_movntpd (double *, v2df)
 void __builtin_ia32_movntdq (v2df *, v2df)
 v4si __builtin_ia32_pshufd (v4si, int)
diff --git a/gcc/doc/install.texi b/gcc/doc/install.texi
index 1daddb865e4..46c5824cc71 100644
--- a/gcc/doc/install.texi
+++ b/gcc/doc/install.texi
@@ -1298,8 +1298,7 @@ experimental option which may become the default in a later release.
 @item --enable-build-poststage1-with-cxx
 When bootstrapping, build stages 2 and 3 of GCC using a C++ compiler
 rather than a C compiler.  Stage 1 is still built with a C compiler.
-This is an experimental option which may become the default in a later
-release.  This is enabled by default and may be disabled using
+This is enabled by default and may be disabled using
 @option{--disable-build-poststage1-with-cxx}.
 
 @item --enable-maintainer-mode
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 1fc44372e32..4e6edb9414e 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -6731,13 +6731,16 @@ rule generates a better code.
 Use specified regions for the integrated register allocator.  The
 @var{region} argument should be one of @code{all}, @code{mixed}, or
 @code{one}.  The first value means using all loops as register
-allocation regions, the second value which is the default means using
-all loops except for loops with small register pressure as the
-regions, and third one means using all function as a single region.
-The first value can give best result for machines with small size and
-irregular register set, the third one results in faster and generates
-decent code and the smallest size code, and the default value usually
-give the best results in most cases and for most architectures.
+allocation regions, the second value which is enabled by default when
+compiling with optimization for speed (@option{-O}, @option{-O2},
+@dots{}) means using all loops except for loops with small register
+pressure as the regions, and third one which is enabled by default for
+@option{-Os} or @option{-O0} means using all function as a single
+region.  The first value can give best result for machines with small
+size and irregular register set, the third one results in faster and
+generates decent code and the smallest size code, and the second value
+usually give the best results in most cases and for most
+architectures.
 
 @item -fira-loop-pressure
 @opindex fira-loop-pressure
@@ -12803,6 +12806,15 @@ Improved versions of k8, opteron and athlon64 with SSE3 instruction set support.
 AMD Family 10h core based CPUs with x86-64 instruction set support.  (This
 supersets MMX, SSE, SSE2, SSE3, SSE4A, 3DNow!, enhanced 3DNow!, ABM and 64-bit
 instruction set extensions.)
+@item bdver1
+AMD Family 15h core based CPUs with x86-64 instruction set support.  (This
+supersets FMA4, AVX, XOP, LWP, AES, PCL_MUL, CX16, MMX, SSE, SSE2, SSE3, SSE4A,
+SSSE3, SSE4.1, SSE4.2, 3DNow!, enhanced 3DNow!, ABM and 64-bit
+instruction set extensions.)
+@item btver1
+AMD Family 14h core based CPUs with x86-64 instruction set support.  (This
+supersets MMX, SSE, SSE2, SSE3, SSSE3, SSE4A, CX16, ABM and 64-bit
+instruction set extensions.)
 @item winchip-c6
 IDT Winchip C6 CPU, dealt in same way as i486 with additional MMX instruction
 set support.
diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi
index 10fd876fd09..c079ce29b7e 100644
--- a/gcc/doc/tm.texi
+++ b/gcc/doc/tm.texi
@@ -7090,6 +7090,10 @@ section names for mergeable constant data.  Define this macro to override
 the string if a different section name should be used.
 @end deftypevr
 
+@deftypefn {Target Hook} {section *} TARGET_ASM_TM_CLONE_TABLE_SECTION (void)
+Return the section that should be used for transactional memory clone  tables.
+@end deftypefn
+
 @deftypefn {Target Hook} {section *} TARGET_ASM_SELECT_RTX_SECTION (enum machine_mode @var{mode}, rtx @var{x}, unsigned HOST_WIDE_INT @var{align})
 Return the section into which a constant @var{x}, of mode @var{mode},
 should be placed.  You can assume that @var{x} is some kind of
diff --git a/gcc/doc/tm.texi.in b/gcc/doc/tm.texi.in
index cebeb1fa777..d03d7f656a2 100644
--- a/gcc/doc/tm.texi.in
+++ b/gcc/doc/tm.texi.in
@@ -7013,6 +7013,8 @@ otherwise.
 
 @hook TARGET_ASM_MERGEABLE_RODATA_PREFIX
 
+@hook TARGET_ASM_TM_CLONE_TABLE_SECTION
+
 @hook TARGET_ASM_SELECT_RTX_SECTION
 Return the section into which a constant @var{x}, of mode @var{mode},
 should be placed.  You can assume that @var{x} is some kind of