RISC-V: Introduce rounding mode operand into fixed-point intrinsics

According to new comming fixed-point API:
https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/222

Introduce vxrm argument:
- vint32m1_t __riscv_vsadd_vv_i32m1 (vint32m1_t op1, vint32m1_t op2, size_t vl);
+ vint32m1_t __riscv_vsadd_vv_i32m1 (vint32m1_t op1, vint32m1_t op2, size_t vxrm, size_t vl);

This patch doesn't insert vxrm csrw configuration instruction yet.
Will support automatically insert csrw vxrm instruction in the next patch.

This patch does this following:
1. Only extend the vxrm argument.
2. Check vxrm argument is invalid immediate and report error message if it is invalid.

gcc/ChangeLog:

	* config/riscv/riscv-vector-builtins-bases.cc: Introduce rounding mode.
	* config/riscv/riscv-vector-builtins-shapes.cc (struct alu_def): Ditto.
	(struct narrow_alu_def): Ditto.
	* config/riscv/riscv-vector-builtins.cc (function_builder::apply_predication): Ditto.
	(function_expander::use_exact_insn): Ditto.
	* config/riscv/riscv-vector-builtins.h (function_checker::arg_num): New function.
	(function_base::has_rounding_mode_operand_p): New function.

gcc/testsuite/ChangeLog:

	* g++.target/riscv/rvv/base/bug-11.C: Adapt testcase.
	* g++.target/riscv/rvv/base/bug-12.C: Ditto.
	* g++.target/riscv/rvv/base/bug-14.C: Ditto.
	* g++.target/riscv/rvv/base/bug-15.C: Ditto.
	* g++.target/riscv/rvv/base/bug-16.C: Ditto.
	* g++.target/riscv/rvv/base/bug-17.C: Ditto.
	* g++.target/riscv/rvv/base/bug-18.C: Ditto.
	* g++.target/riscv/rvv/base/bug-19.C: Ditto.
	* g++.target/riscv/rvv/base/bug-20.C: Ditto.
	* g++.target/riscv/rvv/base/bug-21.C: Ditto.
	* g++.target/riscv/rvv/base/bug-22.C: Ditto.
	* g++.target/riscv/rvv/base/bug-23.C: Ditto.
	* g++.target/riscv/rvv/base/bug-3.C: Ditto.
	* g++.target/riscv/rvv/base/bug-5.C: Ditto.
	* g++.target/riscv/rvv/base/bug-6.C: Ditto.
	* g++.target/riscv/rvv/base/bug-8.C: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-100.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-101.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-102.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-103.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-104.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-105.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-106.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-107.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-108.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-109.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-110.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-111.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-112.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-113.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-114.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-115.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-116.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-117.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-118.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-119.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-122.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-97.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-98.c: Ditto.
	* gcc.target/riscv/rvv/base/merge_constraint-1.c: Ditto.
	* gcc.target/riscv/rvv/base/narrow_constraint-6.c: Ditto.
	* gcc.target/riscv/rvv/base/narrow_constraint-7.c: Ditto.
	* gcc.target/riscv/rvv/base/narrow_constraint-8.c: Ditto.
	* gcc.target/riscv/rvv/base/narrow_constraint-9.c: Ditto.
	* gcc.target/riscv/rvv/base/vxrm-2.c: New test.
	* gcc.target/riscv/rvv/base/vxrm-3.c: New test.
	* gcc.target/riscv/rvv/base/vxrm-4.c: New test.
	* gcc.target/riscv/rvv/base/vxrm-5.c: New test.

4 files changed, 72 insertions, 1 deletions

diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index ab5b4dc9515..a8113f6602b 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -260,6 +260,12 @@ template<rtx_code CODE>
 class binop : public function_base
 {
 public:
+  bool has_rounding_mode_operand_p () const override
+  {
+    return CODE == SS_PLUS || CODE == SS_MINUS || CODE == US_PLUS
+	   || CODE == US_MINUS;
+  }
+
   rtx expand (function_expander &e) const override
   {
     switch (e.op_info->op)
@@ -596,6 +602,8 @@ template<int UNSPEC>
 class sat_op : public function_base
 {
 public:
+  bool has_rounding_mode_operand_p () const override { return true; }
+
   rtx expand (function_expander &e) const override
   {
     switch (e.op_info->op)
@@ -616,6 +624,8 @@ template<int UNSPEC>
 class vnclip : public function_base
 {
 public:
+  bool has_rounding_mode_operand_p () const override { return true; }
+
   rtx expand (function_expander &e) const override
   {
     switch (e.op_info->op)
diff --git a/gcc/config/riscv/riscv-vector-builtins-shapes.cc b/gcc/config/riscv/riscv-vector-builtins-shapes.cc
index 822588c7b6e..76262f07ce4 100644
--- a/gcc/config/riscv/riscv-vector-builtins-shapes.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-shapes.cc
@@ -211,6 +211,19 @@ struct alu_def : public build_base
     b.append_name (predication_suffixes[instance.pred]);
     return b.finish_name ();
   }
+
+  bool check (function_checker &c) const override
+  {
+    /* Check whether rounding mode argument is a valid immediate.  */
+    if (c.base->has_rounding_mode_operand_p ())
+      {
+	if (!c.any_type_float_p ())
+	  return c.require_immediate (c.arg_num () - 2, VXRM_RNU, VXRM_ROD);
+	/* TODO: We will support floating-point intrinsic modeling
+	   rounding mode in the future.  */
+      }
+    return true;
+  }
 };
 
 /* widen_alu_def class. Handle vwadd/vwsub. Unlike
@@ -313,6 +326,19 @@ struct narrow_alu_def : public build_base
     b.append_name (predication_suffixes[instance.pred]);
     return b.finish_name ();
   }
+
+  bool check (function_checker &c) const override
+  {
+    /* Check whether rounding mode argument is a valid immediate.  */
+    if (c.base->has_rounding_mode_operand_p ())
+      {
+	if (!c.any_type_float_p ())
+	  return c.require_immediate (c.arg_num () - 2, VXRM_RNU, VXRM_ROD);
+	/* TODO: We will support floating-point intrinsic modeling
+	   rounding mode in the future.  */
+      }
+    return true;
+  }
 };
 
 /* move_def class. Handle vmv.v.v/vmv.v.x.  */
diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc
index e88eb275a1c..dd714bfcee2 100644
--- a/gcc/config/riscv/riscv-vector-builtins.cc
+++ b/gcc/config/riscv/riscv-vector-builtins.cc
@@ -2998,6 +2998,10 @@ function_builder::apply_predication (const function_instance &instance,
       || instance.pred == PRED_TYPE_tumu || instance.pred == PRED_TYPE_mu)
     argument_types.quick_insert (0, mask_type);
 
+  /* check if rounding mode parameter need  */
+  if (instance.base->has_rounding_mode_operand_p ())
+    argument_types.quick_push (unsigned_type_node);
+
   /* check if vl parameter need  */
   if (instance.base->apply_vl_p ())
     argument_types.quick_push (size_type_node);
@@ -3297,7 +3301,17 @@ function_expander::use_exact_insn (insn_code icode)
     }
 
   for (int argno = arg_offset; argno < call_expr_nargs (exp); argno++)
-    add_input_operand (argno);
+    {
+      if (base->has_rounding_mode_operand_p ()
+	  && argno == call_expr_nargs (exp) - 2)
+	{
+	  /* Since the rounding mode argument position is not consistent with
+	     the instruction pattern, we need to skip rounding mode argument
+	     here.  */
+	  continue;
+	}
+      add_input_operand (argno);
+    }
 
   if (base->apply_tail_policy_p ())
     add_input_operand (Pmode, get_tail_policy_for_pred (pred));
@@ -3307,6 +3321,9 @@ function_expander::use_exact_insn (insn_code icode)
   if (base->apply_vl_p ())
     add_input_operand (Pmode, get_avl_type_rtx (avl_type::NONVLMAX));
 
+  if (base->has_rounding_mode_operand_p ())
+    add_input_operand (call_expr_nargs (exp) - 2);
+
   /* TODO: Currently, we don't support intrinsic that is modeling rounding mode.
      We add default rounding mode for the intrinsics that didn't model rounding
      mode yet.  */
diff --git a/gcc/config/riscv/riscv-vector-builtins.h b/gcc/config/riscv/riscv-vector-builtins.h
index b024731e37a..5d434579131 100644
--- a/gcc/config/riscv/riscv-vector-builtins.h
+++ b/gcc/config/riscv/riscv-vector-builtins.h
@@ -413,6 +413,9 @@ public:
   /* Return true if intrinsics has merge operand.  */
   virtual bool has_merge_operand_p () const;
 
+  /* Return true if intrinsics has rounding mode operand.  */
+  virtual bool has_rounding_mode_operand_p () const;
+
   /* Try to fold the given gimple call.  Return the new gimple statement
      on success, otherwise return null.  */
   virtual gimple *fold (gimple_folder &) const { return NULL; }
@@ -434,6 +437,7 @@ public:
 
   machine_mode arg_mode (unsigned int) const;
   machine_mode ret_mode (void) const;
+  unsigned int arg_num (void) const;
   bool check (void);
 
   bool require_immediate (unsigned int, HOST_WIDE_INT, HOST_WIDE_INT) const;
@@ -600,6 +604,12 @@ function_checker::ret_mode () const
   return TYPE_MODE (TREE_TYPE (TREE_TYPE (fndecl)));
 }
 
+inline unsigned int
+function_checker::arg_num () const
+{
+  return m_nargs;
+}
+
 /* Default implementation of function_base::call_properties, with conservatively
    correct behavior for floating-point instructions.  */
 inline unsigned int
@@ -651,6 +661,14 @@ function_base::has_merge_operand_p () const
   return true;
 }
 
+/* We choose to return false by default since most of the intrinsics does
+   not have rounding mode operand.  */
+inline bool
+function_base::has_rounding_mode_operand_p () const
+{
+  return false;
+}
+
 /* Since most of intrinsics can be overloaded, we set it true by default.  */
 inline bool
 function_base::can_be_overloaded_p (enum predication_type_index) const