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| author | Jeffrey Walton <noloader@gmail.com> | 2021-02-03 04:12:33 -0500 |
|---|---|---|
| committer | Jeffrey Walton <noloader@gmail.com> | 2021-02-03 04:12:33 -0500 |
| commit | 02f990cdc121db395988d7f3a84d87b707a75e7e (patch) | |
| tree | 059b3aab61a79119d6a8d1364c3b9ae5490099c0 /ppc_simd.h | |
| parent | 95e867dc6dfbbf9bdac995a43d91e25bc2249053 (diff) | |
| download | cryptopp-git-02f990cdc121db395988d7f3a84d87b707a75e7e.tar.gz | |
Fix typos
Diffstat (limited to 'ppc_simd.h')
| -rw-r--r-- | ppc_simd.h | 8 |
1 files changed, 4 insertions, 4 deletions
@@ -2510,7 +2510,7 @@ inline uint64x2_p VecPolyMultiply(const uint64x2_p& a, const uint64x2_p& b) /// The <tt>0x00</tt> indicates the low 64-bits of <tt>a</tt> and <tt>b</tt>
/// are multiplied.
/// \note An Intel XMM register is composed of 128-bits. The leftmost bit
-/// is MSB and numbered 127, while the the rightmost bit is LSB and numbered 0.
+/// is MSB and numbered 127, while the rightmost bit is LSB and numbered 0.
/// \par Wraps
/// __vpmsumd, __builtin_altivec_crypto_vpmsumd and __builtin_crypto_vpmsumd.
/// \since Crypto++ 8.0
@@ -2532,7 +2532,7 @@ inline uint64x2_p VecIntelMultiply00(const uint64x2_p& a, const uint64x2_p& b) /// The <tt>0x01</tt> indicates the low 64-bits of <tt>a</tt> and high
/// 64-bits of <tt>b</tt> are multiplied.
/// \note An Intel XMM register is composed of 128-bits. The leftmost bit
-/// is MSB and numbered 127, while the the rightmost bit is LSB and numbered 0.
+/// is MSB and numbered 127, while the rightmost bit is LSB and numbered 0.
/// \par Wraps
/// __vpmsumd, __builtin_altivec_crypto_vpmsumd and __builtin_crypto_vpmsumd.
/// \since Crypto++ 8.0
@@ -2554,7 +2554,7 @@ inline uint64x2_p VecIntelMultiply01(const uint64x2_p& a, const uint64x2_p& b) /// The <tt>0x10</tt> indicates the high 64-bits of <tt>a</tt> and low
/// 64-bits of <tt>b</tt> are multiplied.
/// \note An Intel XMM register is composed of 128-bits. The leftmost bit
-/// is MSB and numbered 127, while the the rightmost bit is LSB and numbered 0.
+/// is MSB and numbered 127, while the rightmost bit is LSB and numbered 0.
/// \par Wraps
/// __vpmsumd, __builtin_altivec_crypto_vpmsumd and __builtin_crypto_vpmsumd.
/// \since Crypto++ 8.0
@@ -2576,7 +2576,7 @@ inline uint64x2_p VecIntelMultiply10(const uint64x2_p& a, const uint64x2_p& b) /// The <tt>0x11</tt> indicates the high 64-bits of <tt>a</tt> and <tt>b</tt>
/// are multiplied.
/// \note An Intel XMM register is composed of 128-bits. The leftmost bit
-/// is MSB and numbered 127, while the the rightmost bit is LSB and numbered 0.
+/// is MSB and numbered 127, while the rightmost bit is LSB and numbered 0.
/// \par Wraps
/// __vpmsumd, __builtin_altivec_crypto_vpmsumd and __builtin_crypto_vpmsumd.
/// \since Crypto++ 8.0
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