From 02f990cdc121db395988d7f3a84d87b707a75e7e Mon Sep 17 00:00:00 2001 From: Jeffrey Walton Date: Wed, 3 Feb 2021 04:12:33 -0500 Subject: Fix typos --- ppc_simd.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'ppc_simd.h') diff --git a/ppc_simd.h b/ppc_simd.h index 65008066..84085618 100644 --- a/ppc_simd.h +++ b/ppc_simd.h @@ -2510,7 +2510,7 @@ inline uint64x2_p VecPolyMultiply(const uint64x2_p& a, const uint64x2_p& b) /// The 0x00 indicates the low 64-bits of a and b /// are multiplied. /// \note An Intel XMM register is composed of 128-bits. The leftmost bit -/// is MSB and numbered 127, while the the rightmost bit is LSB and numbered 0. +/// is MSB and numbered 127, while the rightmost bit is LSB and numbered 0. /// \par Wraps /// __vpmsumd, __builtin_altivec_crypto_vpmsumd and __builtin_crypto_vpmsumd. /// \since Crypto++ 8.0 @@ -2532,7 +2532,7 @@ inline uint64x2_p VecIntelMultiply00(const uint64x2_p& a, const uint64x2_p& b) /// The 0x01 indicates the low 64-bits of a and high /// 64-bits of b are multiplied. /// \note An Intel XMM register is composed of 128-bits. The leftmost bit -/// is MSB and numbered 127, while the the rightmost bit is LSB and numbered 0. +/// is MSB and numbered 127, while the rightmost bit is LSB and numbered 0. /// \par Wraps /// __vpmsumd, __builtin_altivec_crypto_vpmsumd and __builtin_crypto_vpmsumd. /// \since Crypto++ 8.0 @@ -2554,7 +2554,7 @@ inline uint64x2_p VecIntelMultiply01(const uint64x2_p& a, const uint64x2_p& b) /// The 0x10 indicates the high 64-bits of a and low /// 64-bits of b are multiplied. /// \note An Intel XMM register is composed of 128-bits. The leftmost bit -/// is MSB and numbered 127, while the the rightmost bit is LSB and numbered 0. +/// is MSB and numbered 127, while the rightmost bit is LSB and numbered 0. /// \par Wraps /// __vpmsumd, __builtin_altivec_crypto_vpmsumd and __builtin_crypto_vpmsumd. /// \since Crypto++ 8.0 @@ -2576,7 +2576,7 @@ inline uint64x2_p VecIntelMultiply10(const uint64x2_p& a, const uint64x2_p& b) /// The 0x11 indicates the high 64-bits of a and b /// are multiplied. /// \note An Intel XMM register is composed of 128-bits. The leftmost bit -/// is MSB and numbered 127, while the the rightmost bit is LSB and numbered 0. +/// is MSB and numbered 127, while the rightmost bit is LSB and numbered 0. /// \par Wraps /// __vpmsumd, __builtin_altivec_crypto_vpmsumd and __builtin_crypto_vpmsumd. /// \since Crypto++ 8.0 -- cgit v1.2.1