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| author | Felix Held <felix-coreboot@felixheld.de> | 2023-04-29 01:59:31 +0200 |
|---|---|---|
| committer | Matt DeVillier <matt.devillier@amd.corp-partner.google.com> | 2023-05-03 16:15:45 +0000 |
| commit | 026caf5def38df8cc2dca0e1acd7adc063e03951 (patch) | |
| tree | 3f451922da47c23142656891fe162c99c6a3f3fa /src/soc | |
| parent | 662d7af70bc8e060921f57aaec328619382b4852 (diff) | |
| download | coreboot-026caf5def38df8cc2dca0e1acd7adc063e03951.tar.gz | |
soc/amd/common/block/lpc/lpc: increase size of SPI BAR to 4kByte
The memory map granularity for those devices is 4kByte.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8806128bdce8988f5cd7c8fa8a342fdb01eb7f42
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/amd/common/block/lpc/lpc.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c index b8fb923c72..5b836eac7b 100644 --- a/src/soc/amd/common/block/lpc/lpc.c +++ b/src/soc/amd/common/block/lpc/lpc.c @@ -121,7 +121,7 @@ static void lpc_read_resources(struct device *dev) FLASH_BELOW_4GB_MAPPING_REGION_SIZE); /* Add a memory resource for the SPI BAR. */ - mmio_range(dev, 2, SPI_BASE_ADDRESS, 1 * KiB); + mmio_range(dev, 2, SPI_BASE_ADDRESS, 4 * KiB); res = new_resource(dev, 3); /* IOAPIC */ res->base = IO_APIC_ADDR; |