| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | reset: Log the reason for AP resets. | Jonathan Brandmeyer | 2018-07-26 | 1 | -3/+4 |
| * | intel_x86: Move chipset reset logic to common code | Vijay Hiremath | 2018-03-25 | 1 | -20/+0 |
| * | power: cannonlake: SLP_SUS_L deasserted == S5. | Aseda Aboagye | 2017-12-20 | 1 | -0/+6 |
| * | power: cannonlake: Fix power state tracking. | Aseda Aboagye | 2017-12-12 | 1 | -16/+38 |
| * | cannonlake: Check for hard and soft off in chipset_force_shutdown | Furquan Shaikh | 2017-11-28 | 1 | -1/+1 |
| * | power: Add task-safe API to control 5V rail. | Aseda Aboagye | 2017-10-23 | 1 | -0/+9 |
| * | CNL: Use SYS_RST_L for warm/cold chipset reset. | Aseda Aboagye | 2017-07-25 | 1 | -16/+18 |
| * | zoombini: Add eSPI VW signals support. | Aseda Aboagye | 2017-07-19 | 1 | -0/+1 |
| * | power: Add Cannonlake chipset support. | Aseda Aboagye | 2017-07-11 | 1 | -0/+118 |
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index : delta/coreboot/chrome-ec.git | |
| review.coreboot.org: chrome-ec.git |
| summaryrefslogtreecommitdiff |