Commit message (Expand) | Author | Age | Files | Lines | |
---|---|---|---|---|---|
* | power: Add power sequencing logic for Tigerlake chipset | Vijay Hiremath | 2019-09-05 | 1 | -2/+0 |
* | tglrvpu_ite: Adding VCONN support | Ayushee | 2019-08-23 | 1 | -8/+6 |
* | tglrvp_ite: Add TGL-U/Y RVP base code | Daniel Gonzalez | 2019-08-15 | 1 | -0/+213 |