diff options
Diffstat (limited to 'zephyr/projects')
462 files changed, 46121 insertions, 0 deletions
diff --git a/zephyr/projects/.pylintrc b/zephyr/projects/.pylintrc new file mode 100644 index 0000000000..8bdb6378e4 --- /dev/null +++ b/zephyr/projects/.pylintrc @@ -0,0 +1,28 @@ +[BASIC] +additional-builtins= + here, + register_binman_project, + register_host_project, + register_host_test, + register_mchp_project, + register_npcx_project, + register_raw_project, +good-names=BUILD + +# cros lint doesn't inherit the pylintrc from the parent dir. +# These settings are copied from platform/ec/pylintrc +[MESSAGES CONTROL] + +disable= + bad-continuation, + bad-whitespace, + # These have nothing to do with black, they are just annoying + fixme, + too-many-arguments, + too-many-statements, + too-many-branches, + too-many-locals + +[format] + +string-quote=double diff --git a/zephyr/projects/brya/BUILD.py b/zephyr/projects/brya/BUILD.py new file mode 100644 index 0000000000..9991335ca7 --- /dev/null +++ b/zephyr/projects/brya/BUILD.py @@ -0,0 +1,43 @@ +# Copyright 2021 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +"""Define zmake projects for brya.""" + + +def register_npcx9_variant( + project_name, extra_dts_overlays=(), extra_kconfig_files=() +): + """Register a variant of a brya, even though this is not named as such.""" + return register_npcx_project( + project_name=project_name, + zephyr_board="npcx9m3f", + dts_overlays=[ + "adc.dts", + "battery.dts", + "fan.dts", + "gpio.dts", + "i2c.dts", + "interrupts.dts", + "keyboard.dts", + "motionsense.dts", + "pwm_leds.dts", + "temp_sensors.dts", + "usbc.dts", + # Project-specific DTS customization. + *extra_dts_overlays, + ], + kconfig_files=[ + # Common to all projects. + here / "prj.conf", + # Project-specific KConfig customization. + *extra_kconfig_files, + ], + ) + + +brya = register_npcx9_variant( + project_name="brya", + extra_dts_overlays=[here / "brya.dts"], + extra_kconfig_files=[here / "prj_brya.conf"], +) diff --git a/zephyr/projects/brya/CMakeLists.txt b/zephyr/projects/brya/CMakeLists.txt new file mode 100644 index 0000000000..11c1a8386f --- /dev/null +++ b/zephyr/projects/brya/CMakeLists.txt @@ -0,0 +1,39 @@ +# Copyright 2021 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +cmake_minimum_required(VERSION 3.13.1) + +find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}") +project(brya) + +set(PLATFORM_EC_BOARD "${PLATFORM_EC}/board/brya" CACHE PATH + "Path to the platform/ec board directory") +set(PLATFORM_EC_BASEBOARD "${PLATFORM_EC}/baseboard/brya" CACHE PATH + "Path to the platform/ec baseboard directory") + +# Include board specific header files +zephyr_include_directories( + include + "${PLATFORM_EC}/driver/tcpm" + "${PLATFORM_EC_BASEBOARD}" + "${PLATFORM_EC_BOARD}") + +zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_BATTERY + "${PLATFORM_EC_BASEBOARD}/battery_presence.c") +zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CBI_EEPROM + "${PLATFORM_EC_BASEBOARD}/cbi.c") +zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_PWM_KBLIGHT + "kblight_hooks.c") +zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_BATTERY + "${PLATFORM_EC_BASEBOARD}/battery_presence.c") +zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_BATTERY + "battery_present.c") +zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_POWER_DELIVERY + "${PLATFORM_EC_BASEBOARD}/usb_pd_policy.c") +zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC + "${PLATFORM_EC_BOARD}/usbc_config.c" + "${PLATFORM_EC_BOARD}/fw_config.c") +zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGE_MANAGER + "${PLATFORM_EC_BOARD}/charger.c" + "${PLATFORM_EC}/common/math_util.c") diff --git a/zephyr/projects/brya/Kconfig b/zephyr/projects/brya/Kconfig new file mode 100644 index 0000000000..4dd8e23443 --- /dev/null +++ b/zephyr/projects/brya/Kconfig @@ -0,0 +1,11 @@ +# Copyright 2022 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +config BOARD_BRYA + bool "Google Brya Baseboard" + help + Build Google Brya reference board. The board uses the Nuvuton NPCX9 + chip as the EC. + +source "Kconfig.zephyr" diff --git a/zephyr/projects/brya/adc.dts b/zephyr/projects/brya/adc.dts new file mode 100644 index 0000000000..f3f0d1e064 --- /dev/null +++ b/zephyr/projects/brya/adc.dts @@ -0,0 +1,36 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + named-adc-channels { + compatible = "named-adc-channels"; + + adc_ddr_soc: ddr_soc { + enum-name = "ADC_TEMP_SENSOR_1_DDR_SOC"; + io-channels = <&adc0 0>; + }; + adc_ambient: ambient { + enum-name = "ADC_TEMP_SENSOR_2_AMBIENT"; + io-channels = <&adc0 1>; + }; + adc_charger: charger { + enum-name = "ADC_TEMP_SENSOR_3_CHARGER"; + io-channels = <&adc0 6>; + }; + adc_wwan: wwan { + enum-name = "ADC_TEMP_SENSOR_4_WWAN"; + io-channels = <&adc0 7>; + }; + }; +}; + +&adc0 { + status = "okay"; + pinctrl-0 = <&adc0_chan0_gp45 + &adc0_chan1_gp44 + &adc0_chan6_gp34 + &adc0_chan7_gpe1>; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/brya/battery.dts b/zephyr/projects/brya/battery.dts new file mode 100644 index 0000000000..4844d88d92 --- /dev/null +++ b/zephyr/projects/brya/battery.dts @@ -0,0 +1,15 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + batteries { + default_battery: batgqa05l22 { + compatible = "powertech,batgqa05l22", "battery-smart"; + }; + lgc_ac17a8m { + compatible = "lgc,ac17a8m", "battery-smart"; + }; + }; +}; diff --git a/zephyr/projects/brya/battery_present.c b/zephyr/projects/brya/battery_present.c new file mode 100644 index 0000000000..c487a01f36 --- /dev/null +++ b/zephyr/projects/brya/battery_present.c @@ -0,0 +1,21 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ +#include <zephyr/drivers/gpio.h> + +#include "battery.h" +#include "cbi.h" + +enum battery_present battery_hw_present(void) +{ + const struct gpio_dt_spec *batt_pres; + + if (get_board_id() == 1) + batt_pres = GPIO_DT_FROM_NODELABEL(gpio_id_1_ec_batt_pres_odl); + else + batt_pres = GPIO_DT_FROM_NODELABEL(gpio_ec_batt_pres_odl); + + /* The GPIO is low when the battery is physically present */ + return gpio_pin_get_dt(batt_pres) ? BP_NO : BP_YES; +} diff --git a/zephyr/projects/brya/brya.dts b/zephyr/projects/brya/brya.dts new file mode 100644 index 0000000000..4b0490afa9 --- /dev/null +++ b/zephyr/projects/brya/brya.dts @@ -0,0 +1,24 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + model = "Google Brya Baseboard"; + + chosen { + cros,rtc = &mtc; + }; + + ec-console { + compatible = "ec-console"; + disabled = "events", "lpc", "hostcmd"; + }; +}; + +/* host interface */ +&espi0 { + status = "okay"; + pinctrl-0 = <&espi_lpc_gp46_47_51_52_53_54_55_57>; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/brya/fan.dts b/zephyr/projects/brya/fan.dts new file mode 100644 index 0000000000..aa6dcfde7d --- /dev/null +++ b/zephyr/projects/brya/fan.dts @@ -0,0 +1,39 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + fans { + compatible = "cros-ec,fans"; + + fan_0 { + pwms = <&pwm5 0 PWM_KHZ(1) PWM_POLARITY_NORMAL>; + rpm_min = <2200>; + rpm_start = <2200>; + rpm_max = <4200>; + tach = <&tach1>; + enable_gpio = <&gpio_en_pp5000_fan>; + }; + }; +}; + +/* Tachemeter for fan speed measurement */ +&tach1 { + status = "okay"; + pinctrl-0 = <&ta1_1_in_gp40>; + pinctrl-names = "default"; + port = <NPCX_TACH_PORT_A>; /* port-A is selected */ + sample-clk = <NPCX_TACH_FREQ_LFCLK>; /* Use LFCLK as sampling clock */ + pulses-per-round = <2>; /* number of pulses per round of encoder */ +}; + +&pwm5_gpb7 { + drive-open-drain; +}; + +&pwm5 { + status = "okay"; + pinctrl-0 = <&pwm5_gpb7>; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/brya/gpio.dts b/zephyr/projects/brya/gpio.dts new file mode 100644 index 0000000000..6c6a2ac054 --- /dev/null +++ b/zephyr/projects/brya/gpio.dts @@ -0,0 +1,341 @@ +/* Copyright 2021 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + aliases { + gpio-wp = &gpio_ec_wp_l; + gpio-kbd-kso2 = &gpio_ec_kso_02_inv; + }; + + named-gpios { + compatible = "named-gpios"; + + lid_open: lid_open { + gpios = <&gpiod 2 GPIO_INPUT>; + enum-name = "GPIO_LID_OPEN"; + }; + gsc_ec_pwr_btn_odl: gsc_ec_pwr_btn_odl { + gpios = <&gpio0 1 GPIO_INPUT>; + enum-name = "GPIO_POWER_BUTTON_L"; + }; + gpio_ec_wp_l: ec_wp_odl { + gpios = <&gpioa 1 (GPIO_INPUT | GPIO_ACTIVE_LOW)>; + }; + charger_vap_otg_en { + gpios = <&gpio7 3 GPIO_OUTPUT_LOW>; + }; + gpio_ec_batt_pres_odl: ec_batt_pres_odl { + gpios = <&gpioa 3 GPIO_INPUT>; + enum-name = "GPIO_BATT_PRES_ODL"; + }; + /* + * Same GPIO as gpio_ec_batt_pres_odl, + * but only enabled for board id 1. + */ + gpio_id_1_ec_kb_bl_en: id_1_ec_kb_bl_en { + gpios = <&gpioa 3 GPIO_OUTPUT_LOW>; + no-auto-init; + }; + gpio_id_1_ec_batt_pres_odl: id_1_ec_batt_pres_odl { + gpios = <&gpioe 1 GPIO_INPUT>; + }; + ec_i2c_bat_scl { + gpios = <&gpio3 3 GPIO_INPUT>; + }; + ec_i2c_bat_sda { + gpios = <&gpio3 6 GPIO_INPUT>; + }; + gpio_ec_kb_bl_en_l: ec_kb_bl_en_l { + gpios = <&gpio8 6 GPIO_OUTPUT_HIGH>; + }; + ec_i2c_misc_scl_r { + gpios = <&gpiob 3 GPIO_INPUT>; + }; + ec_i2c_misc_sda_r { + gpios = <&gpiob 2 GPIO_INPUT>; + }; + ec_i2c_sensor_scl { + gpios = <&gpiob 5 GPIO_INPUT>; + }; + ec_i2c_sensor_sda { + gpios = <&gpiob 4 GPIO_INPUT>; + }; + ec_i2c_usb_c0_c2_ppc_bc_scl { + gpios = <&gpio9 2 GPIO_INPUT>; + }; + ec_i2c_usb_c0_c2_ppc_bc_sda { + gpios = <&gpio9 1 GPIO_INPUT>; + }; + ec_i2c_usb_c0_c2_rt_scl { + gpios = <&gpiod 1 GPIO_INPUT>; + }; + ec_i2c_usb_c0_c2_rt_sda { + gpios = <&gpiod 0 GPIO_INPUT>; + }; + ec_i2c_usb_c0_c2_tcpc_scl { + gpios = <&gpio9 0 GPIO_INPUT>; + }; + ec_i2c_usb_c0_c2_tcpc_sda { + gpios = <&gpio8 7 GPIO_INPUT>; + }; + ec_i2c_usb_c1_mix_scl { + gpios = <&gpioe 4 GPIO_INPUT>; + }; + ec_i2c_usb_c1_mix_sda { + gpios = <&gpioe 3 GPIO_INPUT>; + }; + ec_i2c_usb_c1_tcpc_scl { + gpios = <&gpiof 3 GPIO_INPUT>; + }; + ec_i2c_usb_c1_tcpc_sda { + gpios = <&gpiof 2 GPIO_INPUT>; + }; + ec_chg_led_y_c1 { + gpios = <&gpioc 3 GPIO_OUTPUT_LOW>; + }; + ec_chg_led_b_c1 { + gpios = <&gpioc 4 GPIO_OUTPUT_LOW>; + }; + ec_gsc_packet_mode { + gpios = <&gpio7 5 GPIO_OUTPUT_LOW>; + enum-name = "GPIO_PACKET_MODE_EN"; + }; + gpio_ec_accel_int_l: ec_accel_int_l { + gpios = <&gpio8 1 GPIO_INPUT>; + }; + gpio_ec_imu_int_l: gpio_ec_imu_int_l { + gpios = <&gpio5 6 GPIO_INPUT>; + }; + gpio_ec_als_rgb_int_l: gpio_ec_als_rgb_int_l { + gpios = <&gpiod 4 GPIO_INPUT>; + }; + gpio_tablet_mode_l: tablet_mode_l { + gpios = <&gpio9 5 GPIO_INPUT>; + enum-name = "GPIO_TABLET_MODE_L"; + }; + acok_od: acok_od { + gpios = <&gpio0 0 GPIO_INPUT>; + enum-name = "GPIO_AC_PRESENT"; + }; + gpio_ec_kso_02_inv: ec_kso_02_inv { + gpios = <&gpio1 7 (GPIO_OUTPUT_LOW | GPIO_ACTIVE_LOW)>; + }; + gpio_ec_pch_wake_odl: ec_pch_wake_r_odl { + gpios = <&gpioc 0 GPIO_ODR_HIGH>; + }; + ec_pch_int_odl { + gpios = <&gpiob 0 GPIO_ODR_HIGH>; + enum-name = "GPIO_EC_INT_L"; + }; + gpio_pg_ec_dsw_pwrok: pg_ec_dsw_pwrok { + gpios = <&gpioc 7 GPIO_INPUT>; + enum-name = "GPIO_PG_EC_DSW_PWROK"; + alias = "GPIO_SEQ_EC_DSW_PWROK"; + }; + en_s5_rails { + gpios = <&gpiob 6 GPIO_OUTPUT_LOW>; + enum-name = "GPIO_EN_S5_RAILS"; + alias = "GPIO_TEMP_SENSOR_POWER"; + }; + sys_rst_odl { + gpios = <&gpioc 5 GPIO_ODR_HIGH>; + enum-name = "GPIO_SYS_RESET_L"; + }; + gpio_pg_ec_rsmrst_odl: pg_ec_rsmrst_odl { + gpios = <&gpioe 2 GPIO_INPUT>; + enum-name = "GPIO_PG_EC_RSMRST_ODL"; + }; + ec_pch_rsmrst_odl { + gpios = <&gpioa 6 GPIO_OUTPUT_LOW>; + enum-name = "GPIO_PCH_RSMRST_L"; + }; + gpio_pg_ec_all_sys_pwrgd: pg_ec_all_sys_pwrgd { + gpios = <&gpiof 4 GPIO_INPUT>; + enum-name = "GPIO_PG_EC_ALL_SYS_PWRGD"; + }; + gpio_slp_s0_l: slp_s0_l { + gpios = <&gpiod 5 GPIO_INPUT>; + enum-name = "GPIO_PCH_SLP_S0_L"; + }; + gpio_slp_s3_l: slp_s3_l { + gpios = <&gpioa 5 GPIO_INPUT>; + enum-name = "GPIO_PCH_SLP_S3_L"; + }; + vccst_pwrgd_od { + gpios = <&gpioa 4 GPIO_ODR_LOW>; + enum-name = "GPIO_VCCST_PWRGD_OD"; + }; + ec_prochot_odl { + gpios = <&gpio6 3 GPIO_ODR_HIGH>; + enum-name = "GPIO_CPU_PROCHOT"; + }; + ec_pch_pwr_btn_odl { + gpios = <&gpioc 1 GPIO_ODR_HIGH>; + enum-name = "GPIO_PCH_PWRBTN_L"; + }; + gpio_slp_sus_l: slp_sus_l { + gpios = <&gpiof 1 GPIO_INPUT>; + enum-name = "GPIO_SLP_SUS_L"; + }; + pch_pwrok { + gpios = <&gpio7 2 GPIO_OUTPUT_LOW>; + enum-name = "GPIO_PCH_PWROK"; + }; + ec_pch_sys_pwrok { + gpios = <&gpio3 7 GPIO_OUTPUT_LOW>; + enum-name = "GPIO_EC_PCH_SYS_PWROK"; + }; + imvp9_vrrdy_od { + gpios = <&gpio4 3 GPIO_INPUT>; + enum-name = "GPIO_IMVP9_VRRDY_OD"; + }; + ec_edp_bl_en { + gpios = <&gpiod 3 GPIO_OUTPUT_HIGH>; + enum-name = "GPIO_ENABLE_BACKLIGHT"; + }; + gpio_ec_prochot_in_l: ec_prochot_in_l { + gpios = <&gpiof 0 GPIO_INPUT>; + }; + gpio_en_pp5000_fan: en_pp5000_fan { + gpios = <&gpio6 1 GPIO_OUTPUT_HIGH>; + }; + gpio_ec_voldn_btn_odl: ec_voldn_btn_odl { + gpios = <&gpio9 3 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_VOLUME_DOWN_L"; + }; + gpio_ec_volup_btn_odl: ec_volup_btn_odl { + gpios = <&gpio9 7 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_VOLUME_UP_L"; + }; + gpio_usb_c0_c2_tcpc_int_odl: usb_c0_c2_tcpc_int_odl { + gpios = <&gpioe 0 GPIO_INPUT>; + enum-name = "GPIO_USB_C0_C2_TCPC_INT_ODL"; + }; + gpio_usb_c1_tcpc_int_odl: usb_c1_tcpc_int_odl { + gpios = <&gpioa 2 GPIO_INPUT>; + enum-name = "GPIO_USB_C1_TCPC_INT_ODL"; + }; + gpio_usb_c0_ppc_int_odl: usb_c0_ppc_int_odl { + gpios = <&gpio6 2 GPIO_INPUT>; + enum-name = "GPIO_USB_C0_PPC_INT_ODL"; + }; + gpio_usb_c1_ppc_int_odl: usb_c1_ppc_int_odl { + gpios = <&gpiof 5 GPIO_INPUT>; + enum-name = "GPIO_USB_C1_PPC_INT_ODL"; + }; + gpio_usb_c2_ppc_int_odl: usb_c2_ppc_int_odl { + gpios = <&gpio7 0 GPIO_INPUT>; + enum-name = "GPIO_USB_C2_PPC_INT_ODL"; + }; + gpio_usb_c0_bc12_int_odl: usb_c0_bc12_int_odl { + gpios = <&gpioc 6 GPIO_INPUT>; + enum-name = "GPIO_USB_C0_BC12_INT_ODL"; + }; + gpio_usb_c1_bc12_int_odl: usb_c1_bc12_int_odl { + gpios = <&gpio5 0 GPIO_INPUT>; + enum-name = "GPIO_USB_C1_BC12_INT_ODL"; + }; + gpio_usb_c2_bc12_int_odl: usb_c2_bc12_int_odl { + gpios = <&gpio8 3 GPIO_INPUT>; + enum-name = "GPIO_USB_C2_BC12_INT_ODL"; + }; + gpio_en_pp5000_usba_r: en_pp5000_usba_r { + gpios = <&gpiod 7 GPIO_OUTPUT_LOW>; + enum-name = "GPIO_EN_PP5000_USBA_R"; + }; + usb_c1_rt_rst_r_odl { + gpios = <&gpio0 2 GPIO_ODR_LOW>; + enum-name = "GPIO_USB_C1_RT_RST_R_ODL"; + }; + usb_c1_rst_odl { + gpios = <&gpio9 6 GPIO_ODR_LOW>; + enum-name = "GPIO_USB_C1_RST_ODL"; + }; + usb_c0_c2_tcpc_rst_odl { + gpios = <&gpioa 7 GPIO_ODR_HIGH>; + enum-name = "GPIO_USB_C0_C2_TCPC_RST_ODL"; + }; + id_1_usb_c0_c2_tcpc_rst_odl { + gpios = <&gpio3 4 GPIO_ODR_LOW>; + }; + usb_c0_int_odl { + gpios = <&gpiob 1 GPIO_INPUT>; + }; + usb_c2_int_odl { + gpios = <&gpio4 1 GPIO_INPUT>; + }; + usb_c0_rt_int_odl: usb_c0_rt_int_odl { + gpios = <&gpiob 1 GPIO_INPUT>; + }; + usb_c2_rt_int_odl: usb_c2_rt_int_odl { + gpios = <&gpio4 1 GPIO_INPUT>; + }; + usb_c0_oc_odl { + gpios = <&ioex_port1 4 GPIO_ODR_HIGH>; + no-auto-init; + }; + usb_c0_frs_en: usb_c0_frs_en { + gpios = <&ioex_port1 6 GPIO_OUTPUT_LOW>; + enum-name = "IOEX_USB_C0_FRS_EN"; + no-auto-init; + }; + usb_c0_rt_rst_odl: usb_c0_rt_rst_odl { + gpios = <&ioex_port1 7 GPIO_ODR_LOW>; + no-auto-init; + }; + usb_c2_rt_rst_odl: usb_c2_rt_rst_odl { + gpios = <&ioex_port2 2 GPIO_ODR_LOW>; + no-auto-init; + }; + usb_c1_oc_odl { + gpios = <&ioex_port2 3 GPIO_ODR_HIGH>; + no-auto-init; + }; + usb_c2_oc_odl { + gpios = <&ioex_port2 4 GPIO_ODR_HIGH>; + no-auto-init; + }; + usb_c2_frs_en: usb_c2_frs_en { + gpios = <&ioex_port2 6 GPIO_OUTPUT_LOW>; + enum-name = "IOEX_USB_C2_FRS_EN"; + no-auto-init; + }; + /* unimplemented GPIOs */ + entering-rw { + enum-name = "GPIO_ENTERING_RW"; + }; + }; + + usba-port-enable-list { + compatible = "cros-ec,usba-port-enable-pins"; + enable-pins = <&gpio_en_pp5000_usba_r>; + }; +}; + +/* Power switch logic input pads */ +/* LID_OPEN_OD */ +&psl_in1_gpd2 { + psl-in-mode = "edge"; + psl-in-pol = "high-rising"; +}; + +/* ACOK_EC_OD */ +&psl_in2_gp00 { + psl-in-mode = "edge"; + psl-in-pol = "high-rising"; +}; + +/* GSC_EC_PWR_BTN_ODL */ +&psl_in3_gp01 { + psl-in-mode = "edge"; + psl-in-pol = "high-rising"; +}; + +/* Power domain device controlled by PSL (Power Switch Logic) IO pads */ +&power_ctrl_psl { + status = "okay"; + pinctrl-names = "sleep"; + pinctrl-0 = <&psl_in1_gpd2 &psl_in2_gp00 &psl_in3_gp01>; +}; diff --git a/zephyr/projects/brya/i2c.dts b/zephyr/projects/brya/i2c.dts new file mode 100644 index 0000000000..7284d80870 --- /dev/null +++ b/zephyr/projects/brya/i2c.dts @@ -0,0 +1,285 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + + #include <dt-bindings/usb_pd_tcpm.h> + +/ { + named-i2c-ports { + compatible = "named-i2c-ports"; + i2c_sensor: sensor { + i2c-port = <&i2c0_0>; + enum-names = "I2C_PORT_SENSOR"; + }; + tcpc0_2: tcpc0_2 { + i2c-port = <&i2c1_0>; + enum-names = "I2C_PORT_USB_C0_C2_TCPC"; + }; + tcpc1: tcpc1 { + i2c-port = <&i2c4_1>; + enum-names = "I2C_PORT_USB_C1_TCPC"; + dynamic-speed; + }; + c0_c2_bc12: c0_c2_bc12 { + i2c-port = <&i2c2_0>; + enum-names = "I2C_PORT_USB_C0_C2_PPC", + "I2C_PORT_USB_C0_C2_BC12"; + }; + c1_bc12: c1_bc12 { + i2c-port = <&i2c6_1>; + enum-names = "I2C_PORT_USB_C1_PPC", + "I2C_PORT_USB_C1_BC12"; + dynamic-speed; + }; + retimer0_2: retimer0_2 { + i2c-port = <&i2c3_0>; + enum-names = "I2C_PORT_USB_C0_C2_MUX"; + }; + battery { + i2c-port = <&i2c5_0>; + enum-names = "I2C_PORT_BATTERY"; + }; + i2c_charger: charger { + i2c-port = <&i2c7_0>; + enum-names = "I2C_PORT_CHARGER", + "I2C_PORT_EEPROM", + "I2C_PORT_MP2964"; + }; + }; +}; + +&i2c0_0 { + status = "okay"; + clock-frequency = <I2C_BITRATE_FAST>; + pinctrl-0 = <&i2c0_0_sda_scl_gpb4_b5>; + pinctrl-names = "default"; +}; + +&i2c_ctrl0 { + status = "okay"; +}; + +&i2c1_0 { + status = "okay"; + clock-frequency = <I2C_BITRATE_FAST_PLUS>; + pinctrl-0 = <&i2c1_0_sda_scl_gp87_90>; + pinctrl-names = "default"; + + tcpc_port0: nct38xx@70 { + compatible = "nuvoton,nct38xx"; + reg = <0x70>; + gpio-dev = <&nct3808_0_P1>; + tcpc-flags = <( + TCPC_FLAGS_TCPCI_REV2_0 | + TCPC_FLAGS_NO_DEBUG_ACC_CONTROL)>; + }; + + nct3808_0_P1: nct3808_0_P1@70 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nuvoton,nct38xx-gpio"; + reg = <0x70>; + label = "NCT3808_0_P1"; + + ioex_port1: gpio@0 { + compatible = "nuvoton,nct38xx-gpio-port"; + reg = <0x0>; + label = "NCT3808_0_P1_GPIO0"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + pin_mask = <0xdc>; + pinmux_mask = <0xff>; + }; + }; + + tcpc_port2: nct38xx@74 { + compatible = "nuvoton,nct38xx"; + reg = <0x74>; + gpio-dev = <&nct3808_0_P2>; + tcpc-flags = <(TCPC_FLAGS_TCPCI_REV2_0)>; + }; + + nct3808_0_P2: nct3808_0_P2@74 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nuvoton,nct38xx-gpio"; + reg = <0x74>; + label = "NCT3808_0_P2"; + + ioex_port2: gpio@0 { + compatible = "nuvoton,nct38xx-gpio-port"; + reg = <0x0>; + label = "NCT3808_0_P2_GPIO0"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + pin_mask = <0xdc>; + pinmux_mask = <0xff>; + }; + }; + + nct3808_alert_1 { + compatible = "nuvoton,nct38xx-gpio-alert"; + irq-gpios = <&gpioe 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + nct38xx-dev = <&nct3808_0_P1 &nct3808_0_P2>; + label = "NCT3808_ALERT_1"; + }; +}; + +&i2c_ctrl1 { + status = "okay"; +}; + +&i2c2_0 { + status = "okay"; + clock-frequency = <I2C_BITRATE_FAST_PLUS>; + pinctrl-0 = <&i2c2_0_sda_scl_gp91_92>; + pinctrl-names = "default"; + + ppc_port0: syv682x@40 { + compatible = "silergy,syv682x"; + status = "okay"; + reg = <0x40>; + frs_en_gpio = <&usb_c0_frs_en>; + }; + + bc12_port0: pi3usb9201@5f { + compatible = "pericom,pi3usb9201"; + status = "okay"; + reg = <0x5f>; + irq = <&int_usb_c0_bc12>; + }; + + ppc_port2: syv682x@42 { + compatible = "silergy,syv682x"; + status = "okay"; + reg = <0x42>; + frs_en_gpio = <&usb_c2_frs_en>; + }; + + bc12_port2: pi3usb9201@5d { + compatible = "pericom,pi3usb9201"; + status = "okay"; + reg = <0x5d>; + irq = <&int_usb_c2_bc12>; + }; +}; + +&i2c_ctrl2 { + status = "okay"; +}; + +&i2c3_0 { + status = "okay"; + clock-frequency = <I2C_BITRATE_FAST_PLUS>; + pinctrl-0 = <&i2c3_0_sda_scl_gpd0_d1>; + pinctrl-names = "default"; + + usb_c0_bb_retimer: jhl8040r-c0@56 { + compatible = "intel,jhl8040r"; + reg = <0x56>; + int-pin = <&usb_c0_rt_int_odl>; + reset-pin = <&usb_c0_rt_rst_odl>; + }; + + usb_c2_bb_retimer: jhl8040r-c2@57 { + compatible = "intel,jhl8040r"; + reg = <0x57>; + int-pin = <&usb_c2_rt_int_odl>; + reset-pin = <&usb_c2_rt_rst_odl>; + }; +}; + +&i2c_ctrl3 { + status = "okay"; +}; + +&i2c4_1 { + status = "okay"; + clock-frequency = <I2C_BITRATE_FAST>; + pinctrl-0 = <&i2c4_1_sda_scl_gpf2_f3>; + pinctrl-names = "default"; + + tcpc_port1: ps8xxx@b { + compatible = "parade,ps8xxx"; + reg = <0xb>; + tcpc-flags = <( + TCPC_FLAGS_TCPCI_REV2_0 | + TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V | + TCPC_FLAGS_CONTROL_VCONN | + TCPC_FLAGS_CONTROL_FRS)>; + }; +}; + +&i2c_ctrl4 { + status = "okay"; +}; + +&i2c5_0 { + status = "okay"; + clock-frequency = <I2C_BITRATE_STANDARD>; + pinctrl-0 = <&i2c5_0_sda_scl_gp33_36>; + pinctrl-names = "default"; +}; + +&i2c_ctrl5 { + status = "okay"; +}; + +&i2c6_1 { + status = "okay"; + clock-frequency = <I2C_BITRATE_FAST>; + pinctrl-0 = <&i2c6_1_sda_scl_gpe3_e4>; + pinctrl-names = "default"; + + ppc_port1: nx20p348x@72 { + compatible = "nxp,nx20p348x"; + status = "okay"; + reg = <0x72>; + }; + + bc12_port1: pi3usb9201@5f { + compatible = "pericom,pi3usb9201"; + status = "okay"; + reg = <0x5f>; + irq = <&int_usb_c1_bc12>; + }; +}; + +&i2c_ctrl6 { + status = "okay"; +}; + +&i2c7_0 { + status = "okay"; + clock-frequency = <I2C_BITRATE_FAST>; + pinctrl-0 = <&i2c7_0_sda_scl_gpb2_b3>; + pinctrl-names = "default"; + + pmic_mp2964: pmic_mp2964@20 { + compatible = "mps,mp2964"; + reg = <0x20>; + label = "I2C_ADDR_MP2964_FLAGS"; + }; + + charger: bq25710@9 { + compatible = "ti,bq25710"; + status = "okay"; + reg = <0x9>; + }; + + cbi_eeprom: eeprom@50 { + compatible = "atmel,at24"; + reg = <0x50>; + size = <2048>; + pagesize = <16>; + address-width = <8>; + timeout = <5>; + }; +}; + +&i2c_ctrl7 { + status = "okay"; +}; diff --git a/zephyr/projects/brya/interrupts.dts b/zephyr/projects/brya/interrupts.dts new file mode 100644 index 0000000000..1adca3e035 --- /dev/null +++ b/zephyr/projects/brya/interrupts.dts @@ -0,0 +1,150 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + aliases { + int-wp = &int_wp; + }; + + gpio-interrupts { + compatible = "cros-ec,gpio-interrupts"; + + int_tablet_mode: tablet_mode { + irq-pin = <&gpio_tablet_mode_l>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "gmr_tablet_switch_isr"; + }; + int_lid_open: lid_open { + irq-pin = <&lid_open>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "lid_interrupt"; + }; + int_power_button: power_button { + irq-pin = <&gsc_ec_pwr_btn_odl>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "power_button_interrupt"; + }; + int_wp: wp { + irq-pin = <&gpio_ec_wp_l>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "switch_interrupt"; + }; + int_ac_present: ac_present { + irq-pin = <&acok_od>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "extpower_interrupt"; + }; + int_volume_up: volume_up { + irq-pin = <&gpio_ec_volup_btn_odl>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "button_interrupt"; + }; + int_volume_down: volume_down { + irq-pin = <&gpio_ec_voldn_btn_odl>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "button_interrupt"; + }; + int_accel: accel { + irq-pin = <&gpio_ec_accel_int_l>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "lis2dw12_interrupt"; + }; + int_imu: imu { + irq-pin = <&gpio_ec_imu_int_l>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "lsm6dso_interrupt"; + }; + int_slp_s0: slp_s0 { + irq-pin = <&gpio_slp_s0_l>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "power_signal_interrupt"; + }; + int_slp_s3: slp_s3 { + irq-pin = <&gpio_slp_s3_l>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "power_signal_interrupt"; + }; + int_slp_sus: slp_sus { + irq-pin = <&gpio_slp_sus_l>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "power_signal_interrupt"; + }; + int_pg_dsw_pwrok: pg_dsw_pwrok { + irq-pin = <&gpio_pg_ec_dsw_pwrok>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "power_signal_interrupt"; + }; + int_pg_rsmrst_odl: pg_rsmrst_odl { + irq-pin = <&gpio_pg_ec_rsmrst_odl>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "power_signal_interrupt"; + }; + int_pg_all_sys_pwrgd: pg_all_sys_pwrgd { + irq-pin = <&gpio_pg_ec_all_sys_pwrgd>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "power_signal_interrupt"; + }; + int_als_rgb: als_rgb { + irq-pin = <&gpio_ec_als_rgb_int_l>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "tcs3400_interrupt"; + }; + int_prochot: prochot { + irq-pin = <&gpio_ec_prochot_in_l>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "throttle_ap_prochot_input_interrupt"; + }; + int_usb_c0_c2_tcpc: usb_c0_c2_tcpc { + irq-pin = <&gpio_usb_c0_c2_tcpc_int_odl>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "tcpc_alert_event"; + }; + int_usb_c1_tcpc: usb_c1_tcpc { + irq-pin = <&gpio_usb_c1_tcpc_int_odl>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "tcpc_alert_event"; + }; + int_usb_c0_ppc: usb_c0_ppc { + irq-pin = <&gpio_usb_c0_ppc_int_odl>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "ppc_interrupt"; + }; + int_usb_c1_ppc: usb_c1_ppc { + irq-pin = <&gpio_usb_c1_ppc_int_odl>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "ppc_interrupt"; + }; + int_usb_c2_ppc: usb_c2_ppc { + irq-pin = <&gpio_usb_c2_ppc_int_odl>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "ppc_interrupt"; + }; + int_usb_c0_bc12: usb_c0_bc12 { + irq-pin = <&gpio_usb_c0_bc12_int_odl>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "bc12_interrupt"; + }; + int_usb_c1_bc12: usb_c1_bc12 { + irq-pin = <&gpio_usb_c1_bc12_int_odl>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "bc12_interrupt"; + }; + int_usb_c2_bc12: usb_c2_bc12 { + irq-pin = <&gpio_usb_c2_bc12_int_odl>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "bc12_interrupt"; + }; + int_usb_c0_rt: usb_c0_rt { + irq-pin = <&usb_c0_rt_int_odl>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "retimer_interrupt"; + }; + int_usb_c2_rt: usb_c2_rt { + irq-pin = <&usb_c2_rt_int_odl>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "retimer_interrupt"; + }; + }; +}; diff --git a/zephyr/projects/brya/kblight_hooks.c b/zephyr/projects/brya/kblight_hooks.c new file mode 100644 index 0000000000..d6d795f28e --- /dev/null +++ b/zephyr/projects/brya/kblight_hooks.c @@ -0,0 +1,67 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <zephyr/drivers/gpio.h> +#include <stdbool.h> + +#include <ap_power/ap_power.h> +#include "cbi.h" +#include "hooks.h" + +/* Enable/Disable keyboard backlight gpio */ +static inline void kbd_backlight_enable(bool enable) +{ + if (get_board_id() == 1) + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_id_1_ec_kb_bl_en), + enable); + else + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_kb_bl_en_l), + !enable); +} + +static void board_backlight_handler(struct ap_power_ev_callback *cb, + struct ap_power_ev_data data) +{ + bool enable; + + switch (data.event) { + default: + return; + + case AP_POWER_RESUME: + /* Called on AP S3 -> S0 transition */ + enable = true; + break; + + case AP_POWER_SUSPEND: + /* Called on AP S0 -> S3 transition */ + enable = false; + break; + } + kbd_backlight_enable(enable); +} + +/* + * Explicitly apply the board ID 1 *gpio.inc settings to pins that + * were reassigned on current boards. + */ +static void set_board_id_1_gpios(void) +{ + static struct ap_power_ev_callback cb; + + /* + * Add a callback for suspend/resume to + * control the keyboard backlight. + */ + ap_power_ev_init_callback(&cb, board_backlight_handler, + AP_POWER_RESUME | AP_POWER_SUSPEND); + ap_power_ev_add_callback(&cb); + + if (get_board_id() != 1) + return; + gpio_pin_configure_dt(GPIO_DT_FROM_NODELABEL(gpio_id_1_ec_kb_bl_en), + GPIO_OUTPUT_LOW); +} +DECLARE_HOOK(HOOK_INIT, set_board_id_1_gpios, HOOK_PRIO_FIRST); diff --git a/zephyr/projects/brya/keyboard.dts b/zephyr/projects/brya/keyboard.dts new file mode 100644 index 0000000000..91fad2db92 --- /dev/null +++ b/zephyr/projects/brya/keyboard.dts @@ -0,0 +1,47 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + kblight { + compatible = "cros-ec,kblight-pwm"; + pwms = <&pwm3 0 PWM_HZ(2400) PWM_POLARITY_NORMAL>; + }; +}; + +&pwm3 { + status = "okay"; + pinctrl-0 = <&pwm3_gp80>; + pinctrl-names = "default"; +}; + +&cros_kb_raw { + status = "okay"; + /* No KSO2 (it's inverted and implemented by GPIO) */ + pinctrl-0 = < + &ksi0_gp31 + &ksi1_gp30 + &ksi2_gp27 + &ksi3_gp26 + &ksi4_gp25 + &ksi5_gp24 + &ksi6_gp23 + &ksi7_gp22 + &kso00_gp21 + &kso01_gp20 + &kso03_gp16 + &kso04_gp15 + &kso05_gp14 + &kso06_gp13 + &kso07_gp12 + &kso08_gp11 + &kso09_gp10 + &kso10_gp07 + &kso11_gp06 + &kso12_gp05 + &kso13_gp04 + &kso14_gp82 + >; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/brya/motionsense.dts b/zephyr/projects/brya/motionsense.dts new file mode 100644 index 0000000000..08994e30cc --- /dev/null +++ b/zephyr/projects/brya/motionsense.dts @@ -0,0 +1,257 @@ +/* + * Copyright 2022 The ChromiumOS Authors + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include <dt-bindings/motionsense/utils.h> + + +/ { + aliases { + /* + * motion sense's <>_INT_EVENT is handled + * by alias. Using the alias, each driver creates + * its own <>_INT_EVENT. + */ + lsm6dso-int = &base_accel; + lis2dw12-int = &lid_accel; + tcs3400-int = &als_clear; + }; + + /* + * Declare mutexes used by sensor drivers. + * A mutex node is used to create an instance of mutex_t. + * A mutex node is referenced by a sensor node if the + * corresponding sensor driver needs to use the + * instance of the mutex. + */ + motionsense-mutex { + compatible = "cros-ec,motionsense-mutex"; + mutex_lis2dw12: lis2dw12-mutex { + }; + + mutex_lsm6dso: lsm6dso-mutex { + }; + }; + + /* Rotation matrix used by drivers. */ + motionsense-rotation-ref { + compatible = "cros-ec,motionsense-rotation-ref"; + lid_rot_ref: lid-rotation-ref { + mat33 = <0 1 0 + 1 0 0 + 0 0 (-1)>; + }; + base_rot_ref: base-rotation-ref { + mat33 = <1 0 0 + 0 (-1) 0 + 0 0 (-1)>; + }; + }; + + /* + * Driver specific data. A driver-specific data can be shared with + * different motion sensors while they are using the same driver. + * + * If a node's compatible starts with "cros-ec,accelgyro-", it is for + * a common structure defined in accelgyro.h. + * e.g) compatible = "cros-ec,accelgyro-als-drv-data" is for + * "struct als_drv_data_t" in accelgyro.h + */ + motionsense-sensor-data { + lis2dw12_data: lis2dw12-drv-data { + compatible = "cros-ec,drvdata-lis2dw12"; + status = "okay"; + }; + + lsm6dso_accel_data: lsm6dso-accel-drv-data { + compatible = "cros-ec,drvdata-lsm6dso"; + status = "okay"; + }; + + lsm6dso_gyro_data: lsm6dso-gyro-drv-data { + compatible = "cros-ec,drvdata-lsm6dso"; + status = "okay"; + }; + + tcs_clear_data: tcs3400-clear-drv-data { + compatible = "cros-ec,drvdata-tcs3400-clear"; + status = "okay"; + + als-drv-data { + compatible = "cros-ec,accelgyro-als-drv-data"; + als-cal { + scale = <1>; + uscale = <0>; + offset = <0>; + als-channel-scale { + compatible = + "cros-ec,accelgyro-als-channel-scale"; + k-channel-scale = <1>; + cover-scale = <1>; + }; + }; + }; + }; + + tcs_rgb_data: tcs3400-rgb-drv-data { + compatible = "cros-ec,drvdata-tcs3400-rgb"; + status = "okay"; + + /* node for rgb_calibration_t defined in accelgyro.h */ + rgb_calibration { + compatible = + "cros-ec,accelgyro-rgb-calibration"; + + irt = <1>; + + rgb-cal-x { + offset = <0>; + coeff = <0 0 0 1>; + als-channel-scale { + compatible = + "cros-ec,accelgyro-als-channel-scale"; + k-channel-scale = <1>; + cover-scale = <1>; + }; + }; + rgb-cal-y { + offset = <0>; + coeff = <0 0 0 1>; + als-channel-scale { + compatible = + "cros-ec,accelgyro-als-channel-scale"; + k-channel-scale = <1>; + cover-scale = <1>; + }; + }; + rgb-cal-z { + offset = <0>; + coeff = <0 0 0 1>; + als-channel-scale { + compatible = + "cros-ec,accelgyro-als-channel-scale"; + k-channel-scale = <1>; + cover-scale = <1>; + }; + }; + }; + }; + }; + + /* + * List of motion sensors that creates motion_sensors array. + * The nodelabel "lid_accel" and "base_accel" are used to indicate + * motion sensor IDs for lid angle calculation. + */ + motionsense-sensor { + lid_accel: lid-accel { + compatible = "cros-ec,lis2dw12"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_LID"; + mutex = <&mutex_lis2dw12>; + port = <&i2c_sensor>; + rot-standard-ref = <&lid_rot_ref>; + default-range = <2>; + drv-data = <&lis2dw12_data>; + i2c-spi-addr-flags = "LIS2DWL_ADDR0_FLAGS"; + configs { + compatible = + "cros-ec,motionsense-sensor-config"; + ec-s0 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + ec-s3 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + }; + }; + + base_accel: base-accel { + compatible = "cros-ec,lsm6dso-accel"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_BASE"; + mutex = <&mutex_lsm6dso>; + port = <&i2c_sensor>; + rot-standard-ref = <&base_rot_ref>; + default-range = <4>; + drv-data = <&lsm6dso_accel_data>; + i2c-spi-addr-flags = "LSM6DSO_ADDR0_FLAGS"; + configs { + compatible = + "cros-ec,motionsense-sensor-config"; + ec-s0 { + odr = <(13000 | ROUND_UP_FLAG)>; + ec-rate = <(100 * USEC_PER_MSEC)>; + }; + ec-s3 { + odr = <(10000 | ROUND_UP_FLAG)>; + ec-rate = <(100 * USEC_PER_MSEC)>; + }; + }; + }; + + base-gyro { + compatible = "cros-ec,lsm6dso-gyro"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_BASE"; + mutex = <&mutex_lsm6dso>; + port = <&i2c_sensor>; + rot-standard-ref = <&base_rot_ref>; + default-range = <(1000 | ROUND_UP_FLAG)>; /* dps */ + drv-data = <&lsm6dso_gyro_data>; + i2c-spi-addr-flags = "LSM6DSO_ADDR0_FLAGS"; + }; + + als_clear: base-als-clear { + compatible = "cros-ec,tcs3400-clear"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_CAMERA"; + port = <&i2c_sensor>; + default-range = <0x10000>; + drv-data = <&tcs_clear_data>; + i2c-spi-addr-flags = "TCS3400_I2C_ADDR_FLAGS"; + configs { + compatible = + "cros-ec,motionsense-sensor-config"; + ec-s0 { + /* Run ALS sensor in S0 */ + odr = <1000>; + }; + }; + }; + + base-als-rgb { + compatible = "cros-ec,tcs3400-rgb"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_CAMERA"; + default-range = <0x10000>; /* scale = 1x, uscale = 0 */ + drv-data = <&tcs_rgb_data>; + }; + }; + + motionsense-sensor-info { + compatible = "cros-ec,motionsense-sensor-info"; + + /* list of entries for motion_als_sensors */ + als-sensors = <&als_clear>; + /* + * list of GPIO interrupts that have to + * be enabled at initial stage + */ + sensor-irqs = <&int_imu &int_als_rgb &int_accel>; + /* list of sensors in force mode */ + accel-force-mode-sensors = <&lid_accel &als_clear>; + }; +}; diff --git a/zephyr/projects/brya/prj.conf b/zephyr/projects/brya/prj.conf new file mode 100644 index 0000000000..422f862809 --- /dev/null +++ b/zephyr/projects/brya/prj.conf @@ -0,0 +1,200 @@ +# Copyright 2021 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +CONFIG_CROS_EC=y +CONFIG_PLATFORM_EC=y +CONFIG_SHIMMED_TASKS=y +CONFIG_PLATFORM_EC_POWER_BUTTON=y +CONFIG_PLATFORM_EC_LID_SWITCH=y +CONFIG_PLATFORM_EC_SWITCH=y +CONFIG_LTO=y +CONFIG_CROS_FLASH_NPCX=y +CONFIG_CROS_SYSTEM_NPCX=y +CONFIG_PLATFORM_EC_VBOOT_EFS2=y +CONFIG_PLATFORM_EC_VBOOT_HASH=y +CONFIG_PLATFORM_EC_EXTPOWER_GPIO=y +CONFIG_PLATFORM_EC_CONSOLE_CMD_SYSINFO=y + +CONFIG_PLATFORM_EC_ADC_CHANNELS_RUNTIME_CONFIG=y + +CONFIG_KERNEL_SHELL=y + +# SoC configuration +CONFIG_AP=y +CONFIG_AP_X86_INTEL_ADL=y +CONFIG_FPU=y +CONFIG_ARM_MPU=y + +# CBI +CONFIG_EEPROM=y +CONFIG_EEPROM_AT24=y +CONFIG_EEPROM_SHELL=n +CONFIG_PLATFORM_EC_CBI_EEPROM=y +CONFIG_PLATFORM_EC_BOARD_VERSION_CBI=y + +# eSPI +CONFIG_ESPI=y +CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S4=y +CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S5=y +CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_DEFAULT_VW_WIDTH_US=150 + +# I2C +CONFIG_I2C=y + +# Power Sequencing +CONFIG_PLATFORM_EC_POWERSEQ=y +CONFIG_PLATFORM_EC_POWERSEQ_RTC_RESET=y +CONFIG_PLATFORM_EC_POWERSEQ_S0IX=y +CONFIG_PLATFORM_EC_POWERSEQ_S4=y +CONFIG_PLATFORM_EC_POWER_SLEEP_FAILURE_DETECTION=y +CONFIG_PLATFORM_EC_THROTTLE_AP=y + +# Host command +CONFIG_PLATFORM_EC_HOSTCMD=y +CONFIG_PLATFORM_EC_HOSTCMD_AP_RESET=y + +# Console command +CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCELS=y +CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCEL_INFO=y +CONFIG_PLATFORM_EC_CONSOLE_CMD_I2C_SPEED=y + +# Sensors +CONFIG_SENSOR=y +CONFIG_SENSOR_SHELL=n +CONFIG_PLATFORM_EC_MOTIONSENSE=y +CONFIG_PLATFORM_EC_ACCEL_FIFO=y +CONFIG_PLATFORM_EC_ALS=y +CONFIG_PLATFORM_EC_DYNAMIC_MOTION_SENSOR_COUNT=y +CONFIG_PLATFORM_EC_GMR_TABLET_MODE=y +CONFIG_PLATFORM_EC_LID_ANGLE=y +CONFIG_PLATFORM_EC_LID_ANGLE_UPDATE=y +CONFIG_PLATFORM_EC_SENSOR_TIGHT_TIMESTAMPS=y +CONFIG_PLATFORM_EC_TABLET_MODE=y +CONFIG_PLATFORM_EC_TABLET_MODE_SWITCH=y + +# Sensor Drivers +CONFIG_PLATFORM_EC_ACCELGYRO_LSM6DSO=y +CONFIG_PLATFORM_EC_ACCEL_LIS2DW12=y +CONFIG_PLATFORM_EC_ALS_TCS3400=y + +# Fan +CONFIG_TACH_NPCX=y + +# Temperature sensors +CONFIG_PLATFORM_EC_TEMP_SENSOR=y +CONFIG_PLATFORM_EC_THERMISTOR=y +CONFIG_PLATFORM_EC_TEMP_SENSOR_POWER=y + +# MKBP event +CONFIG_PLATFORM_EC_MKBP_EVENT=y +CONFIG_PLATFORM_EC_MKBP_INPUT_DEVICES=y +CONFIG_PLATFORM_EC_MKBP_USE_GPIO_AND_HOST_EVENT=y + +# PMIC +CONFIG_PLATFORM_EC_PMIC=y +CONFIG_PLATFORM_EC_MP2964=y + +# Keyboard +CONFIG_PLATFORM_EC_KEYBOARD=y +CONFIG_PLATFORM_EC_KEYBOARD_PROTOCOL_8042=y +CONFIG_PLATFORM_EC_KEYBOARD_COL2_INVERTED=y +CONFIG_PLATFORM_EC_KEYBOARD_KEYPAD=y +CONFIG_PLATFORM_EC_KEYBOARD_PWRBTN_ASSERTS_KSI3=y +CONFIG_PLATFORM_EC_VOLUME_BUTTONS=y +CONFIG_PLATFORM_EC_CMD_BUTTON=n +CONFIG_CROS_KB_RAW_NPCX=y + +CONFIG_PLATFORM_EC_WORKAROUND_FLASH_DOWNLOAD_API=y + +# Battery +CONFIG_PLATFORM_EC_BATTERY=y +CONFIG_PLATFORM_EC_BATTERY_SMART=y +CONFIG_PLATFORM_EC_BATTERY_FUEL_GAUGE=y +CONFIG_PLATFORM_EC_BATTERY_CUT_OFF=y +CONFIG_PLATFORM_EC_BATTERY_HW_PRESENT_CUSTOM=y +CONFIG_PLATFORM_EC_BATTERY_REVIVE_DISCONNECT=y + +# USB-C and charging +CONFIG_PLATFORM_EC_CHARGER_BQ25720=y +CONFIG_PLATFORM_EC_CHARGER_BQ25720_VSYS_TH2_CUSTOM=y +CONFIG_PLATFORM_EC_CHARGER_BQ25720_VSYS_TH2_DV=70 +CONFIG_PLATFORM_EC_CHARGER_DISCHARGE_ON_AC=y +CONFIG_PLATFORM_EC_CHARGER_DISCHARGE_ON_AC_CHARGER=y +CONFIG_PLATFORM_EC_CHARGER_MIN_BAT_PCT_FOR_POWER_ON=3 +CONFIG_PLATFORM_EC_CHARGER_MIN_BAT_PCT_FOR_POWER_ON_WITH_AC=1 +CONFIG_PLATFORM_EC_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT=15000 +CONFIG_PLATFORM_EC_CHARGER_MIN_POWER_MW_FOR_POWER_ON=15001 +CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR=10 +CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR_AC=10 +CONFIG_PLATFORM_EC_CHARGE_RAMP_SW=y +CONFIG_PLATFORM_EC_BC12_DETECT_PI3USB9201=y +CONFIG_PLATFORM_EC_USB_PID=0x504F +CONFIG_PLATFORM_EC_USBC_PPC_SYV682X=y +CONFIG_PLATFORM_EC_USBC_PPC_NX20P3483=y +CONFIG_PLATFORM_EC_USBC_RETIMER_INTEL_BB=y +CONFIG_PLATFORM_EC_USB_DRP_ACC_TRYSRC=y +CONFIG_PLATFORM_EC_USB_MUX_VIRTUAL=y +CONFIG_PLATFORM_EC_USB_MUX_RUNTIME_CONFIG=n +CONFIG_PLATFORM_EC_USB_MUX_TASK=y +CONFIG_PLATFORM_EC_USB_PD_DEBUG_FIXED_LEVEL=y +CONFIG_PLATFORM_EC_USB_PD_DEBUG_LEVEL=2 +CONFIG_PLATFORM_EC_USB_PD_ALT_MODE_UFP=y +CONFIG_PLATFORM_EC_USB_PD_VBUS_MEASURE_CHARGER=y +CONFIG_PLATFORM_EC_USB_PD_DISCHARGE_PPC=y +CONFIG_PLATFORM_EC_USB_PD_PPC=y +CONFIG_PLATFORM_EC_USB_PD_REV30=y +CONFIG_PLATFORM_EC_USB_PD_USB32_DRD=y +CONFIG_PLATFORM_EC_USB_PD_TBT_COMPAT_MODE=y +CONFIG_PLATFORM_EC_USB_PD_USB4=y +CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_TCPC=y +CONFIG_PLATFORM_EC_USB_PD_TCPM_PS8815=y +CONFIG_PLATFORM_EC_USB_PD_TCPM_RT1715=n +CONFIG_PLATFORM_EC_USB_PD_TCPM_TUSB422=n +CONFIG_PLATFORM_EC_USB_PD_TCPM_NCT38XX=y +CONFIG_PLATFORM_EC_USB_PD_TCPM_MUX=y +CONFIG_PLATFORM_EC_USB_PD_TCPM_TCPCI=y +CONFIG_PLATFORM_EC_USBC_PPC_DEDICATED_INT=y +CONFIG_PLATFORM_EC_USBA=y +CONFIG_PLATFORM_EC_CONSOLE_CMD_PPC_DUMP=n +CONFIG_PLATFORM_EC_CONSOLE_CMD_TCPC_DUMP=n +CONFIG_PLATFORM_EC_USB_PD_TCPC_RUNTIME_CONFIG=n +CONFIG_PLATFORM_EC_USB_PD_REQUIRE_AP_MODE_ENTRY=y +CONFIG_PLATFORM_EC_USB_PD_INT_SHARED=y +CONFIG_PLATFORM_EC_USB_PD_PORT_0_SHARED=y +CONFIG_PLATFORM_EC_USB_PD_PORT_2_SHARED=y + +CONFIG_SYSCON=y + +# LED +CONFIG_PLATFORM_EC_LED_COMMON=y +CONFIG_PLATFORM_EC_LED_PWM=y +CONFIG_PLATFORM_EC_CONSOLE_CMD_LEDTEST=n +CONFIG_PLATFORM_EC_LED_PWM_NEAR_FULL_COLOR=4 +CONFIG_PLATFORM_EC_LED_PWM_SOC_ON_COLOR=4 +CONFIG_PLATFORM_EC_LED_PWM_SOC_SUSPEND_COLOR=4 +CONFIG_PLATFORM_EC_LED_PWM_LOW_BATT_COLOR=5 + +# PWM +CONFIG_PWM=y +CONFIG_PWM_SHELL=n + +#IOEX +CONFIG_GPIO_NCT38XX=y + +# TODO(b/188605676): bring these features up +CONFIG_PLATFORM_EC_BOARD_VERSION_GPIO=n + +# Power Sequencing +CONFIG_PLATFORM_EC_POWERSEQ=y +CONFIG_PLATFORM_EC_POWERSEQ_PP5000_CONTROL=n +CONFIG_CHIPSET_ALDERLAKE_SLG4BD44540=y +CONFIG_PLATFORM_EC_POWERSEQ_RTC_RESET=n +CONFIG_PLATFORM_EC_POWERSEQ_S0IX=y +CONFIG_PLATFORM_EC_POWER_SLEEP_FAILURE_DETECTION=y +# Treat 2nd reset from H1 as Power-On +CONFIG_PLATFORM_EC_BOARD_RESET_AFTER_POWER_ON=y +CONFIG_PLATFORM_EC_THROTTLE_AP=y + +# RTC +CONFIG_PLATFORM_EC_RTC=y diff --git a/zephyr/projects/brya/prj_brya.conf b/zephyr/projects/brya/prj_brya.conf new file mode 100644 index 0000000000..5aaf86a8c9 --- /dev/null +++ b/zephyr/projects/brya/prj_brya.conf @@ -0,0 +1,6 @@ +# Copyright 2022 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +# BRYA-NPCX9 reference-board-specific Kconfig settings. +CONFIG_BOARD_BRYA=y diff --git a/zephyr/projects/brya/pwm_leds.dts b/zephyr/projects/brya/pwm_leds.dts new file mode 100644 index 0000000000..4321b4bd34 --- /dev/null +++ b/zephyr/projects/brya/pwm_leds.dts @@ -0,0 +1,79 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + pwmleds { + compatible = "pwm-leds"; + pwm_led0: pwm_led_0 { + pwms = <&pwm2 0 PWM_HZ(4800) PWM_POLARITY_INVERTED + &pwm0 0 PWM_HZ(4800) PWM_POLARITY_INVERTED>; + }; + pwm_led1: pwm_led_1 { + pwms = <&pwm1 0 PWM_HZ(4800) PWM_POLARITY_INVERTED + &pwm7 0 PWM_HZ(4800) PWM_POLARITY_INVERTED>; + }; + }; + + cros-pwmleds { + compatible = "cros-ec,pwm-leds"; + + leds = <&pwm_led0 &pwm_led1>; + + /*<amber white>*/ + color-map-red = <0 0>; + color-map-green = <0 0>; + color-map-blue = <0 0>; + color-map-yellow = <0 0>; + color-map-white = <0 50>; + color-map-amber = <50 0>; + + brightness-range = <0 0 0 0 100 100>; + + #address-cells = <1>; + #size-cells = <0>; + + pwm_led_0@0 { + reg = <0>; + ec-led-name = "EC_LED_ID_LEFT_LED"; + }; + + pwm_led_1@1 { + reg = <1>; + ec-led-name = "EC_LED_ID_RIGHT_LED"; + }; + }; +}; + +/* LED2 */ +&pwm0 { + status = "okay"; + clock-bus = "NPCX_CLOCK_BUS_LFCLK"; + pinctrl-0 = <&pwm0_gpc3>; + pinctrl-names = "default"; +}; + +/* LED3 */ +&pwm1 { + status = "okay"; + clock-bus = "NPCX_CLOCK_BUS_LFCLK"; + pinctrl-0 = <&pwm1_gpc2>; + pinctrl-names = "default"; +}; + +/* LED1 */ +&pwm2 { + status = "okay"; + clock-bus = "NPCX_CLOCK_BUS_LFCLK"; + pinctrl-0 = <&pwm2_gpc4>; + pinctrl-names = "default"; +}; + +/* LED4 */ +&pwm7 { + status = "okay"; + clock-bus = "NPCX_CLOCK_BUS_LFCLK"; + pinctrl-0 = <&pwm7_gp60>; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/brya/temp_sensors.dts b/zephyr/projects/brya/temp_sensors.dts new file mode 100644 index 0000000000..ae436a2c6b --- /dev/null +++ b/zephyr/projects/brya/temp_sensors.dts @@ -0,0 +1,75 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <cros/thermistor/thermistor.dtsi> + +/ { + temp_ddr_soc: ddr_soc { + compatible = "cros-ec,temp-sensor-thermistor"; + thermistor = <&thermistor_3V3_30K9_47K_4050B>; + adc = <&adc_ddr_soc>; + }; + + temp_ambient: ambient { + compatible = "cros-ec,temp-sensor-thermistor"; + thermistor = <&thermistor_3V3_30K9_47K_4050B>; + adc = <&adc_ambient>; + }; + + temp_charger: charger { + compatible = "cros-ec,temp-sensor-thermistor"; + thermistor = <&thermistor_3V3_30K9_47K_4050B>; + adc = <&adc_charger>; + }; + + temp_wwan: wwan { + compatible = "cros-ec,temp-sensor-thermistor"; + thermistor = <&thermistor_3V3_30K9_47K_4050B>; + adc = <&adc_wwan>; + }; + + named-temp-sensors { + compatible = "cros-ec,temp-sensors"; + ddr_soc { + temp_fan_off = <35>; + temp_fan_max = <60>; + temp_host_high = <85>; + temp_host_halt = <90>; + temp_host_release_high = <80>; + sensor = <&temp_ddr_soc>; + }; + + ambient { + temp_fan_off = <35>; + temp_fan_max = <60>; + temp_host_high = <85>; + temp_host_halt = <90>; + temp_host_release_high = <80>; + sensor = <&temp_ambient>; + }; + + charger { + temp_fan_off = <35>; + temp_fan_max = <65>; + temp_host_high = <105>; + temp_host_halt = <120>; + temp_host_release_high = <90>; + sensor = <&temp_charger>; + }; + + wwan { + temp_fan_off = <35>; + temp_fan_max = <60>; + temp_host_high = <130>; + temp_host_halt = <130>; + temp_host_release_high = <100>; + sensor = <&temp_wwan>; + }; + }; +}; + +&thermistor_3V3_30K9_47K_4050B { + status = "okay"; +}; diff --git a/zephyr/projects/brya/usbc.dts b/zephyr/projects/brya/usbc.dts new file mode 100644 index 0000000000..1be9ac94ac --- /dev/null +++ b/zephyr/projects/brya/usbc.dts @@ -0,0 +1,69 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + usbc { + #address-cells = <1>; + #size-cells = <0>; + + port0@0 { + compatible = "named-usbc-port"; + reg = <0>; + bc12 = <&bc12_port0>; + tcpc = <&tcpc_port0>; + chg = <&charger>; + usb-mux-chain-0 { + compatible = "cros-ec,usb-mux-chain"; + usb-muxes = <&usb_c0_bb_retimer + &virtual_mux_c0>; + }; + ppc = <&ppc_port0>; + }; + port0-muxes { + virtual_mux_c0: virtual-mux-c0 { + compatible = "cros-ec,usbc-mux-virtual"; + }; + }; + + port1@1 { + compatible = "named-usbc-port"; + reg = <1>; + bc12 = <&bc12_port1>; + tcpc = <&tcpc_port1>; + usb-mux-chain-1 { + compatible = "cros-ec,usb-mux-chain"; + usb-muxes = <&virtual_mux_c1 &tcpci_mux_c1>; + }; + ppc = <&ppc_port1>; + }; + port1-muxes { + tcpci_mux_c1: tcpci-mux-c1 { + compatible = "cros-ec,usbc-mux-tcpci"; + hpd-update = "ps8xxx_tcpc_update_hpd_status"; + }; + virtual_mux_c1: virtual-mux-c1 { + compatible = "cros-ec,usbc-mux-virtual"; + }; + }; + + port2@2 { + compatible = "named-usbc-port"; + reg = <2>; + bc12 = <&bc12_port2>; + tcpc = <&tcpc_port2>; + usb-mux-chain-2 { + compatible = "cros-ec,usb-mux-chain"; + usb-muxes = <&usb_c2_bb_retimer + &virtual_mux_c2>; + }; + ppc = <&ppc_port2>; + }; + port2-muxes { + virtual_mux_c2: virtual-mux-c2 { + compatible = "cros-ec,usbc-mux-virtual"; + }; + }; + }; +}; diff --git a/zephyr/projects/corsola/BUILD.py b/zephyr/projects/corsola/BUILD.py new file mode 100644 index 0000000000..4e82ab7926 --- /dev/null +++ b/zephyr/projects/corsola/BUILD.py @@ -0,0 +1,139 @@ +# Copyright 2021 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +"""Define zmake projects for corsola.""" + +# Default chip is it81202bx, some variants will use NPCX9X. + + +def register_corsola_project( + project_name, + chip="it81202bx", + extra_dts_overlays=(), + extra_kconfig_files=(), +): + """Register a variant of corsola.""" + register_func = register_binman_project + if chip.startswith("npcx"): + register_func = register_npcx_project + + register_func( + project_name=project_name, + zephyr_board=chip, + dts_overlays=[ + here / "common.dts", + here / "power_signal.dts", + here / "usba.dts", + *extra_dts_overlays, + ], + kconfig_files=[here / "prj.conf", *extra_kconfig_files], + ) + + +register_corsola_project( + "krabby", + extra_dts_overlays=[ + here / "adc_krabby.dts", + here / "battery_krabby.dts", + here / "gpio_krabby.dts", + here / "i2c_krabby.dts", + here / "interrupts_krabby.dts", + here / "led_krabby.dts", + here / "motionsense_krabby.dts", + here / "usbc_krabby.dts", + ], + extra_kconfig_files=[ + here / "prj_it81202_base.conf", + here / "prj_krabby.conf", + ], +) + +register_corsola_project( + project_name="kingler", + chip="npcx9m3f", + extra_dts_overlays=[ + here / "adc_kingler.dts", + here / "battery_kingler.dts", + here / "host_interface_npcx.dts", + here / "i2c_kingler.dts", + here / "interrupts_kingler.dts", + here / "gpio_kingler.dts", + here / "npcx_keyboard.dts", + here / "led_kingler.dts", + here / "motionsense_kingler.dts", + here / "usbc_kingler.dts", + here / "default_gpio_pinctrl_kingler.dts", + ], + extra_kconfig_files=[ + here / "prj_npcx993_base.conf", + here / "prj_kingler.conf", + ], +) + +register_corsola_project( + project_name="steelix", + chip="npcx9m3f", + extra_dts_overlays=[ + here / "adc_kingler.dts", + here / "battery_steelix.dts", + here / "host_interface_npcx.dts", + here / "i2c_kingler.dts", + here / "interrupts_kingler.dts", + here / "interrupts_steelix.dts", + here / "cbi_steelix.dts", + here / "gpio_steelix.dts", + here / "npcx_keyboard.dts", + here / "keyboard_steelix.dts", + here / "led_steelix.dts", + here / "motionsense_kingler.dts", + here / "motionsense_steelix.dts", + here / "usba_steelix.dts", + here / "usbc_kingler.dts", + here / "default_gpio_pinctrl_kingler.dts", + ], + extra_kconfig_files=[ + here / "prj_npcx993_base.conf", + here / "prj_steelix.conf", + ], +) + + +register_corsola_project( + "tentacruel", + extra_dts_overlays=[ + here / "adc_tentacruel.dts", + here / "battery_tentacruel.dts", + here / "cbi_tentacruel.dts", + here / "gpio_tentacruel.dts", + here / "i2c_tentacruel.dts", + here / "interrupts_tentacruel.dts", + here / "led_tentacruel.dts", + here / "motionsense_tentacruel.dts", + here / "usbc_tentacruel.dts", + here / "thermistor_tentacruel.dts", + ], + extra_kconfig_files=[ + here / "prj_it81202_base.conf", + here / "prj_tentacruel.conf", + ], +) + +register_corsola_project( + "magikarp", + extra_dts_overlays=[ + here / "adc_magikarp.dts", + here / "battery_magikarp.dts", + here / "cbi_magikarp.dts", + here / "gpio_magikarp.dts", + here / "i2c_magikarp.dts", + here / "interrupts_magikarp.dts", + here / "led_magikarp.dts", + here / "motionsense_magikarp.dts", + here / "usbc_magikarp.dts", + ], + extra_kconfig_files=[ + here / "prj_it81202_base.conf", + here / "prj_magikarp.conf", + ], +) diff --git a/zephyr/projects/corsola/CMakeLists.txt b/zephyr/projects/corsola/CMakeLists.txt new file mode 100644 index 0000000000..fa899a0e77 --- /dev/null +++ b/zephyr/projects/corsola/CMakeLists.txt @@ -0,0 +1,81 @@ +# Copyright 2021 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +cmake_minimum_required(VERSION 3.13.1) + +find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}") + +cros_ec_library_include_directories(include) + +# Include selected EC source from the baseboard +zephyr_library_sources( + "src/board.c" + "src/board_chipset.c" + "src/hibernate.c" +) + +zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "src/usbc_config.c") +zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "src/usb_pd_policy.c") +zephyr_library_sources_ifdef(CONFIG_VARIANT_CORSOLA_DB_DETECTION + "src/variant_db_detection.c") + +if(DEFINED CONFIG_BOARD_KRABBY) + project(krabby) + zephyr_library_sources("src/krabby/hooks.c" + "src/krabby/charger_workaround.c" + "src/krabby/ppc_krabby.c") + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_I2C "src/krabby/i2c.c") + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC + "src/krabby/usb_pd_policy.c") + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC + "src/krabby/usbc_config.c") +elseif(DEFINED CONFIG_BOARD_KINGLER) + project(kingler) + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_I2C "src/kingler/i2c.c") + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_LED_COMMON + "src/kingler/led.c") + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC + "src/kingler/usb_pd_policy.c") + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC + "src/kingler/usbc_config.c") + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_BUTTONS_RUNTIME_CONFIG + "src/kingler/button.c") +elseif(DEFINED CONFIG_BOARD_STEELIX) + project(steelix) + zephyr_library_sources("src/kingler/board_steelix.c") + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_I2C "src/kingler/i2c.c") + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_LED_COMMON + "src/kingler/led_steelix.c") + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC + "src/kingler/usb_pd_policy.c") + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC + "src/kingler/usbc_config.c") + +elseif(DEFINED CONFIG_BOARD_TENTACRUEL) + project(tentacruel) + zephyr_library_sources("src/krabby/hooks.c" + "src/krabby/charger_workaround.c" + "src/krabby/sensor_tentacruel.c" + "src/krabby/temp_tentacruel.c" + "src/krabby/ppc_tentacruel.c") + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_I2C "src/krabby/i2c.c") + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC + "src/krabby/usb_pd_policy.c") + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC + "src/krabby/usbc_config.c") + +elseif(DEFINED CONFIG_BOARD_MAGIKARP) + project(magikarp) + zephyr_library_sources("src/krabby/hooks.c" + "src/krabby/sensor_magikarp.c" + "src/krabby/ppc_magikarp.c" + "src/krabby/keyboard_magikarp.c") + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_I2C "src/krabby/i2c.c") + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC + "src/krabby/usb_pd_policy.c") + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC + "src/krabby/usbc_config.c") + +endif() + diff --git a/zephyr/projects/corsola/Kconfig b/zephyr/projects/corsola/Kconfig new file mode 100644 index 0000000000..4f66601c20 --- /dev/null +++ b/zephyr/projects/corsola/Kconfig @@ -0,0 +1,52 @@ +# Copyright 2021 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +config BOARD_KRABBY + bool "Google Krabby Board" + help + Build Google Krabby reference board. Krabby has MediaTek MT8186 SoC + with ITE it81202-bx EC. + +config BOARD_KINGLER + bool "Google Kingler Board" + help + Build Google Kingler reference board. Krabby has MediaTek MT8186 SoC + with NPCX993FA0BX EC. + +config BOARD_STEELIX + bool "Google Steelix Board" + help + Build Google Steelix variant board. Steelix is a variant of Kingler + and has MediaTek MT8186 SoC with NPCX993FA0BX EC. + +config BOARD_TENTACRUEL + bool "Google Tentacruel Board" + help + Build Google Tentacruel variant board. Tentacruel is a variant of Krabby + and has MediaTek MT8186 SoC with ITE it81202-bx EC. + +config BOARD_MAGIKARP + bool "Google Magikarp Board" + help + Build Google Magikarp variant board. Magikarp is a variant of Krabby + and has MediaTek MT8186 SoC with ITE it81202-bx EC. + +config VARIANT_CORSOLA_DB_DETECTION + bool "Corsola Platform Runtime Daughter Board Detection" + depends on PLATFORM_EC_USB_PD_TCPC_RUNTIME_CONFIG + depends on PLATFORM_EC_USB_MUX_RUNTIME_CONFIG + help + Daughter board detection for Type-C subboard or HDMI subboard. This + includes pin configuration and driver loading. + default y + +config VARIANT_CORSOLA_USBA + bool "Corsola Platform USB-A support" + help + Support Corsola USB-A related functions. Enable this function if + it has USB-A ports. + depends on PLATFORM_EC_USBC + default y + +source "Kconfig.zephyr" diff --git a/zephyr/projects/corsola/adc_kingler.dts b/zephyr/projects/corsola/adc_kingler.dts new file mode 100644 index 0000000000..7b69abe48a --- /dev/null +++ b/zephyr/projects/corsola/adc_kingler.dts @@ -0,0 +1,46 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* + * Kingler and Steelix use the same dts, take care of this when modify it. + */ + +/ { + named-adc-channels { + compatible = "named-adc-channels"; + + adc_charger_pmon_r { + enum-name = "ADC_PSYS"; + io-channels = <&adc0 0>; + /* + * ISL9238C PSYS output is 1.44 uA/W over 33K resistor. + */ + mul = <21043>; + }; + adc_ec_id0 { + enum-name = "ADC_ID_0"; + io-channels = <&adc0 1>; + }; + adc_ec_id1 { + enum-name = "ADC_ID_1"; + io-channels = <&adc0 2>; + }; + adc_charger_amon_r { + enum-name = "ADC_AMON_BMON"; + io-channels = <&adc0 3>; + mul = <1000>; + div = <18>; + }; + }; +}; + +&adc0 { + status = "okay"; + pinctrl-0 = <&adc0_chan0_gp45 + &adc0_chan1_gp44 + &adc0_chan2_gp43 + &adc0_chan3_gp42>; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/corsola/adc_krabby.dts b/zephyr/projects/corsola/adc_krabby.dts new file mode 100644 index 0000000000..be65e9eea7 --- /dev/null +++ b/zephyr/projects/corsola/adc_krabby.dts @@ -0,0 +1,38 @@ +/* Copyright 2021 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + named-adc-channels { + compatible = "named-adc-channels"; + + adc_vbus_c0 { + enum-name = "ADC_VBUS_C0"; + io-channels = <&adc0 0>; + mul = <10>; + }; + adc_board_id0 { + enum-name = "ADC_BOARD_ID_0"; + io-channels = <&adc0 1>; + }; + adc_board_id1 { + enum-name = "ADC_BOARD_ID_1"; + io-channels = <&adc0 2>; + }; + adc_vbus_c1 { + enum-name = "ADC_VBUS_C1"; + io-channels = <&adc0 7>; + mul = <10>; + }; + }; +}; + +&adc0 { + status = "okay"; + pinctrl-0 = <&adc0_ch0_gpi0_default + &adc0_ch1_gpi1_default + &adc0_ch2_gpi2_default + &adc0_ch7_gpi7_default>; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/corsola/adc_magikarp.dts b/zephyr/projects/corsola/adc_magikarp.dts new file mode 100644 index 0000000000..358af6f0f4 --- /dev/null +++ b/zephyr/projects/corsola/adc_magikarp.dts @@ -0,0 +1,63 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <cros/thermistor/thermistor.dtsi> + +/ { + named-adc-channels { + compatible = "named-adc-channels"; + adc_vbus_c0 { + enum-name = "ADC_VBUS_C0"; + io-channels = <&adc0 0>; + mul = <10>; + }; + adc_board_id0 { + enum-name = "ADC_BOARD_ID_0"; + io-channels = <&adc0 1>; + }; + adc_board_id1 { + enum-name = "ADC_BOARD_ID_1"; + io-channels = <&adc0 2>; + }; + adc_vbus_c1 { + enum-name = "ADC_VBUS_C1"; + io-channels = <&adc0 7>; + mul = <10>; + }; + adc_ambient: ambient { + enum-name = "ADC_TEMP_SENSOR_2_AMBIENT"; + io-channels = <&adc0 5>; + }; + }; +}; + +&adc0 { + status = "okay"; + pinctrl-0 = <&adc0_ch0_gpi0_default + &adc0_ch1_gpi1_default + &adc0_ch2_gpi2_default + &adc0_ch5_gpi5_default + &adc0_ch7_gpi7_default>; + pinctrl-names = "default"; +}; + +/ { + temp_ambient: ambient { + compatible = "cros-ec,temp-sensor-thermistor"; + thermistor = <&thermistor_3V3_30K9_47K_NCP15WB>; + adc = <&adc_ambient>; + }; + + named-temp-sensors { + compatible = "cros-ec,temp-sensors"; + ambient { + sensor = <&temp_ambient>; + }; + }; +}; + +&thermistor_3V3_30K9_47K_NCP15WB { + status = "okay"; +}; diff --git a/zephyr/projects/corsola/adc_tentacruel.dts b/zephyr/projects/corsola/adc_tentacruel.dts new file mode 100644 index 0000000000..1b5e849589 --- /dev/null +++ b/zephyr/projects/corsola/adc_tentacruel.dts @@ -0,0 +1,66 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <cros/thermistor/thermistor.dtsi> + +/ { + named-adc-channels { + compatible = "named-adc-channels"; + adc_vbus_c0 { + enum-name = "ADC_VBUS_C0"; + io-channels = <&adc0 0>; + mul = <10>; + }; + adc_board_id0 { + enum-name = "ADC_BOARD_ID_0"; + io-channels = <&adc0 1>; + }; + adc_board_id1 { + enum-name = "ADC_BOARD_ID_1"; + io-channels = <&adc0 2>; + }; + adc_vbus_c1 { + enum-name = "ADC_VBUS_C1"; + io-channels = <&adc0 7>; + mul = <10>; + }; + adc_ambient: ambient { + enum-name = "ADC_TEMP_SENSOR_2_AMBIENT"; + io-channels = <&adc0 5>; + }; + }; +}; + +&adc0 { + status = "okay"; + pinctrl-0 = <&adc0_ch0_gpi0_default + &adc0_ch1_gpi1_default + &adc0_ch2_gpi2_default + &adc0_ch5_gpi5_default + &adc0_ch7_gpi7_default>; + pinctrl-names = "default"; +}; + +/ { + temp_ambient: ambient { + compatible = "cros-ec,temp-sensor-thermistor"; + thermistor = <&thermistor_3V3_30K9_47K_NCP15WB>; + adc = <&adc_ambient>; + }; + + named-temp-sensors { + compatible = "cros-ec,temp-sensors"; + ambient { + sensor = <&temp_ambient>; + }; + temp_charger: charger { + sensor = <&charger>; + }; + }; +}; + +&thermistor_3V3_30K9_47K_NCP15WB { + status = "okay"; +}; diff --git a/zephyr/projects/corsola/battery_kingler.dts b/zephyr/projects/corsola/battery_kingler.dts new file mode 100644 index 0000000000..b01fb8a46d --- /dev/null +++ b/zephyr/projects/corsola/battery_kingler.dts @@ -0,0 +1,15 @@ +/* Copyright 2021 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + batteries { + default_battery: smp_l20m3pg2 { + compatible = "smp,l20m3pg2", "battery-smart"; + }; + lgc_l20l3pg2 { + compatible = "lgc,l20l3pg2", "battery-smart"; + }; + }; +}; diff --git a/zephyr/projects/corsola/battery_krabby.dts b/zephyr/projects/corsola/battery_krabby.dts new file mode 100644 index 0000000000..ce41859182 --- /dev/null +++ b/zephyr/projects/corsola/battery_krabby.dts @@ -0,0 +1,12 @@ +/* Copyright 2021 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + batteries { + default_battery: c235 { + compatible = "celxpert,c235-41", "battery-smart"; + }; + }; +}; diff --git a/zephyr/projects/corsola/battery_magikarp.dts b/zephyr/projects/corsola/battery_magikarp.dts new file mode 100644 index 0000000000..bbdd6ac0c5 --- /dev/null +++ b/zephyr/projects/corsola/battery_magikarp.dts @@ -0,0 +1,12 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + batteries { + default_battery: smp_c31n1915 { + compatible = "smp,c31n1915", "battery-smart"; + }; + }; +}; diff --git a/zephyr/projects/corsola/battery_steelix.dts b/zephyr/projects/corsola/battery_steelix.dts new file mode 100644 index 0000000000..594c83478c --- /dev/null +++ b/zephyr/projects/corsola/battery_steelix.dts @@ -0,0 +1,24 @@ +/* Copyright 2021 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + batteries { + default_battery: byd_l22b3pg0 { + compatible = "byd,l22b3pg0", "battery-smart"; + }; + celxpert_l22c3pg0 { + compatible = "celxpert,l22c3pg0", "battery-smart"; + }; + cosmx_l22x3pg0 { + compatible = "cosmx,l22x3pg0", "battery-smart"; + }; + smp_l22m3pg0 { + compatible = "smp,l22m3pg0", "battery-smart"; + }; + sunwoda_l22d3pg0 { + compatible = "sunwoda,l22d3pg0", "battery-smart"; + }; + }; +}; diff --git a/zephyr/projects/corsola/battery_tentacruel.dts b/zephyr/projects/corsola/battery_tentacruel.dts new file mode 100644 index 0000000000..f116c20a51 --- /dev/null +++ b/zephyr/projects/corsola/battery_tentacruel.dts @@ -0,0 +1,12 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + batteries { + default_battery: dynapack_c140254 { + compatible = "dynapack,c140254", "battery-smart"; + }; + }; +}; diff --git a/zephyr/projects/corsola/cbi_magikarp.dts b/zephyr/projects/corsola/cbi_magikarp.dts new file mode 100644 index 0000000000..5eac6b82c6 --- /dev/null +++ b/zephyr/projects/corsola/cbi_magikarp.dts @@ -0,0 +1,36 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + /* magikarp-specific fw_config fields. */ + magikarp-fw-config { + compatible = "cros-ec,cbi-fw-config"; + /* + * FW_CONFIG field to describe mainboard orientation in chassis. + */ + base-gyro { + enum-name = "FW_BASE_GYRO"; + start = <0>; + size = <2>; + + None { + compatible = "cros-ec,cbi-fw-config-value"; + enum-name = "FW_BASE_NONE"; + value = <0>; + }; + icm42607 { + compatible = "cros-ec,cbi-fw-config-value"; + enum-name = "FW_BASE_ICM42607"; + value = <1>; + default; + }; + bmi323 { + compatible = "cros-ec,cbi-fw-config-value"; + enum-name = "FW_BASE_BMI323"; + value = <2>; + }; + }; + }; +}; diff --git a/zephyr/projects/corsola/cbi_steelix.dts b/zephyr/projects/corsola/cbi_steelix.dts new file mode 100644 index 0000000000..f4918b1577 --- /dev/null +++ b/zephyr/projects/corsola/cbi_steelix.dts @@ -0,0 +1,95 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + steelix-fw-config { + compatible = "cros-ec,cbi-fw-config"; + + /* + * FW_CONFIG field to indicate the device is clamshell + * or convertible. + */ + form_factor { + enum-name = "FORM_FACTOR"; + start = <13>; + size = <3>; + + convertible { + compatible = "cros-ec,cbi-fw-config-value"; + enum-name = "CONVERTIBLE"; + value = <1>; + }; + clamshell { + compatible = "cros-ec,cbi-fw-config-value"; + enum-name = "CLAMSHELL"; + value = <0>; + }; + }; + + /* FW_CONFIG field to indicate which DB is attached. */ + db_config: db { + enum-name = "DB"; + start = <0>; + size = <4>; + + sub-board-1 { + compatible = "cros-ec,cbi-fw-config-value"; + enum-name = "DB_NONE"; + value = <0>; + }; + sub-board-2 { + compatible = "cros-ec,cbi-fw-config-value"; + enum-name = "DB_USBA_HDMI"; + value = <1>; + }; + sub-board-3 { + compatible = "cros-ec,cbi-fw-config-value"; + enum-name = "DB_USBA_HDMI_LTE"; + value = <2>; + }; + }; + }; + + /* Steelix-specific ssfc fields. */ + steelix-ssfc { + compatible = "named-cbi-ssfc"; + + /* SSFC field to identify BASE motion sensor. */ + base-sensor { + enum-name = "BASE_SENSOR"; + size = <3>; + + base_sensor_0: bmi323 { + compatible = "named-cbi-ssfc-value"; + status = "okay"; + value = <1>; + default; + }; + base_sensor_1: lsm6dsm { + compatible = "named-cbi-ssfc-value"; + status = "okay"; + value = <2>; + }; + }; + + /* SSFC field to identify LID motion sensor. */ + lid-sensor { + enum-name = "LID_SENSOR"; + size = <3>; + + lid_sensor_0: bma422 { + compatible = "named-cbi-ssfc-value"; + status = "okay"; + value = <1>; + default; + }; + lid_sensor_1: lis2dw12 { + compatible = "named-cbi-ssfc-value"; + status = "okay"; + value = <2>; + }; + }; + }; +}; diff --git a/zephyr/projects/corsola/cbi_tentacruel.dts b/zephyr/projects/corsola/cbi_tentacruel.dts new file mode 100644 index 0000000000..2cd4594417 --- /dev/null +++ b/zephyr/projects/corsola/cbi_tentacruel.dts @@ -0,0 +1,36 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + /* tentacruel-specific fw_config fields. */ + tentacruel-fw-config { + compatible = "cros-ec,cbi-fw-config"; + /* + * FW_CONFIG field to describe mainboard orientation in chassis. + */ + base-gyro { + enum-name = "FW_BASE_GYRO"; + start = <8>; + size = <2>; + + None { + compatible = "cros-ec,cbi-fw-config-value"; + enum-name = "FW_BASE_NONE"; + value = <0>; + }; + icm42607 { + compatible = "cros-ec,cbi-fw-config-value"; + enum-name = "FW_BASE_ICM42607"; + value = <1>; + default; + }; + bmi323 { + compatible = "cros-ec,cbi-fw-config-value"; + enum-name = "FW_BASE_BMI323"; + value = <2>; + }; + }; + }; +}; diff --git a/zephyr/projects/corsola/common.dts b/zephyr/projects/corsola/common.dts new file mode 100644 index 0000000000..001dcc7ce3 --- /dev/null +++ b/zephyr/projects/corsola/common.dts @@ -0,0 +1,25 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <dt-bindings/wake_mask_event_defines.h> + +/ { + ec-mkbp-host-event-wakeup-mask { + compatible = "ec-wake-mask-event"; + wakeup-mask = <( + HOST_EVENT_AC_CONNECTED | + HOST_EVENT_AC_DISCONNECTED | + HOST_EVENT_LID_OPEN | + HOST_EVENT_POWER_BUTTON | + HOST_EVENT_HANG_DETECT | + HOST_EVENT_MODE_CHANGE)>; + }; + + ec-mkbp-event-wakeup-mask { + compatible = "ec-wake-mask-event"; + wakeup-mask = <(MKBP_EVENT_KEY_MATRIX | + MKBP_EVENT_HOST_EVENT)>; + }; +}; diff --git a/zephyr/projects/corsola/default_gpio_pinctrl_kingler.dts b/zephyr/projects/corsola/default_gpio_pinctrl_kingler.dts new file mode 100644 index 0000000000..604658a145 --- /dev/null +++ b/zephyr/projects/corsola/default_gpio_pinctrl_kingler.dts @@ -0,0 +1,44 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Adds the &alt1_no_lpc_espi setting over the NPCX9 default setting. */ +&{/def-io-conf-list} { + pinmux = <&alt0_gpio_no_spip + &alt0_gpio_no_fpip + &alt1_no_pwrgd + &alt1_no_lpc_espi + &alta_no_peci_en + &altd_npsl_in1_sl + &altd_npsl_in2_sl + &altd_psl_in3_sl + &altd_psl_in4_sl + &alt7_no_ksi0_sl + &alt7_no_ksi1_sl + &alt7_no_ksi2_sl + &alt7_no_ksi3_sl + &alt7_no_ksi4_sl + &alt7_no_ksi5_sl + &alt7_no_ksi6_sl + &alt7_no_ksi7_sl + &alt8_no_kso00_sl + &alt8_no_kso01_sl + &alt8_no_kso02_sl + &alt8_no_kso03_sl + &alt8_no_kso04_sl + &alt8_no_kso05_sl + &alt8_no_kso06_sl + &alt8_no_kso07_sl + &alt9_no_kso08_sl + &alt9_no_kso09_sl + &alt9_no_kso10_sl + &alt9_no_kso11_sl + &alt9_no_kso12_sl + &alt9_no_kso13_sl + &alt9_no_kso14_sl + &alt9_no_kso15_sl + &alta_no_kso16_sl + &alta_no_kso17_sl + &altg_psl_gpo_sl>; +}; diff --git a/zephyr/projects/corsola/gpio_kingler.dts b/zephyr/projects/corsola/gpio_kingler.dts new file mode 100644 index 0000000000..9a827a06dd --- /dev/null +++ b/zephyr/projects/corsola/gpio_kingler.dts @@ -0,0 +1,249 @@ +/* Copyright 2021 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + aliases { + gpio-cbi-wp = &gpio_ec_cbi_wp; + gpio-wp = &gpio_ec_wp_l; + gpio-kbd-kso2 = &gpio_ec_kso_02_inv; + }; + + named-gpios { + compatible = "named-gpios"; + + /* + * In npcx9 series, gpio46, gpio47, and the whole gpio5 port + * belong to VHIF power well. On kingler, it is connencted to + * 1.8V. + */ + base_imu_int_l: base_imu_int_l { + gpios = <&gpio5 6 GPIO_INPUT>; + }; + spi_ap_clk_ec { + gpios = <&gpio5 5 GPIO_INPUT>; + }; + spi_ap_cs_ec_l { + gpios = <&gpio5 3 GPIO_INPUT>; + }; + spi_ap_do_ec_di { + gpios = <&gpio4 6 GPIO_INPUT>; + }; + spi_ap_di_ec_do { + gpios = <&gpio4 7 GPIO_INPUT>; + }; + ap_ec_warm_rst_req: ap_ec_warm_rst_req { + gpios = <&gpio5 1 (GPIO_INPUT | GPIO_ACTIVE_HIGH)>; + enum-name = "GPIO_AP_EC_WARM_RST_REQ"; + }; + ap_ec_wdtrst_l: ap_ec_wdtrst_l { + gpios = <&gpio5 2 (GPIO_INPUT | GPIO_ACTIVE_LOW)>; + enum-name = "GPIO_AP_EC_WDTRST_L"; + }; + ap_in_sleep_l: ap_in_sleep_l { + gpios = <&gpio5 4 (GPIO_INPUT | GPIO_ACTIVE_LOW)>; + enum-name = "GPIO_AP_IN_SLEEP_L"; + }; + gpio_en_ulp: en_ulp { + gpios = <&gpioc 6 GPIO_OUTPUT_LOW>; + }; + en_ec_id_odl { + gpios = <&gpio7 6 GPIO_ODR_HIGH>; + }; + sys_rst_odl { + gpios = <&gpioc 5 (GPIO_ODR_LOW | GPIO_VOLTAGE_1P8)>; + enum-name = "GPIO_SYS_RST_ODL"; + }; + ec_i2c_sensor_scl { + gpios = <&gpiob 5 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; + }; + ec_i2c_sensor_sda { + gpios = <&gpiob 4 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; + }; + ec_i2c_usb_c0_scl { + gpios = <&gpio9 0 GPIO_INPUT>; + }; + ec_i2c_usb_c0_sda { + gpios = <&gpio8 7 GPIO_INPUT>; + }; + ec_i2c_usb_c1_scl { + gpios = <&gpio9 2 GPIO_INPUT>; + }; + ec_i2c_usb_c1_sda { + gpios = <&gpio9 1 GPIO_INPUT>; + }; + ec_i2c_pwr_cbi_scl { + gpios = <&gpiod 1 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; + }; + ec_i2c_pwr_cbi_sda { + gpios = <&gpiod 0 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; + }; + ec_i2c_batt_scl { + gpios = <&gpio3 3 GPIO_INPUT>; + }; + ec_i2c_batt_sda { + gpios = <&gpio3 6 GPIO_INPUT>; + }; + ec_pen_chg_dis_odl { + gpios = <&gpioe 4 GPIO_INPUT>; + }; + gpio_ec_cbi_wp: ec_cbi_wp { + gpios = <&gpio8 0 GPIO_OUTPUT_LOW>; + }; + gpio_ec_wp_l: ec_wp_odl { + gpios = <&gpioe 3 (GPIO_INPUT | GPIO_ACTIVE_LOW | + GPIO_VOLTAGE_1P8)>; + }; + lid_accel_int_l { + gpios = <&gpiob 3 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; + }; + gpio_tablet_mode_l: tablet_mode_l { + gpios = <&gpiob 2 GPIO_INPUT>; + enum-name = "GPIO_TABLET_MODE_L"; + }; + ec_ap_int_odl { + gpios = <&gpioc 1 (GPIO_ODR_HIGH | GPIO_VOLTAGE_1P8)>; + enum-name = "GPIO_EC_INT_L"; + }; + gpio_ec_kso_02_inv: ec_kso_02_inv { + gpios = <&gpio1 7 (GPIO_OUTPUT_LOW | GPIO_ACTIVE_LOW)>; + }; + gpio_usb_c0_bc12_int_odl: usb_c0_bc12_int_odl { + gpios = <&gpio8 3 GPIO_INPUT>; + enum-name = "GPIO_USB_C0_BC12_INT_ODL"; + }; + ec_entering_rw { + gpios = <&gpio0 3 GPIO_OUTPUT_LOW>; + }; + charger_prochot_odl { + gpios = <&gpiob 1 GPIO_INPUT>; + }; + ec_rst_odl { + gpios = <&gpio7 7 GPIO_INPUT>; + }; + gpio_lid_open: lid_open { + gpios = <&gpiod 2 GPIO_INPUT>; + enum-name = "GPIO_LID_OPEN"; + }; + gpio_acok_od: acok_od { + gpios = <&gpio0 0 GPIO_INPUT>; + enum-name = "GPIO_AC_PRESENT"; + }; + gpio_gsc_ec_pwr_btn_odl: gsc_ec_pwr_btn_odl { + gpios = <&gpio0 1 GPIO_INPUT>; + enum-name = "GPIO_POWER_BUTTON_L"; + }; + gpio_en_5v_usm: en_5v_usm { + gpios = <&gpio0 2 GPIO_OUTPUT_LOW>; + }; + packet_mode_en { + gpios = <&gpio7 5 GPIO_OUTPUT_LOW>; + enum-name = "GPIO_PACKET_MODE_EN"; + }; + gpio_x_ec_gpio2: x_ec_gpio2 { + gpios = <&gpiod 4 GPIO_INPUT>; + }; + /* + * In npcx9 series, gpio93-97, the whole gpioa port, and gpiob0 + * belong to VSPI power rail. On kingler, it is connencted to + * 1.8V. + */ + ap_sysrst_odl_r: ap_sysrst_odl_r { + gpios = <&gpioa 1 (GPIO_INPUT | GPIO_ACTIVE_LOW)>; + enum-name = "GPIO_AP_EC_SYSRST_ODL"; + }; + gpio_ap_xhci_init_done: ap_xhci_init_done { + gpios = <&gpioa 3 GPIO_INPUT>; + }; + gpio_usb_c0_ppc_int_odl: usb_c0_ppc_int_odl { + gpios = <&gpio6 7 GPIO_INPUT>; + enum-name = "GPIO_USB_C0_PPC_INT_ODL"; + }; + pg_pp5000_z2_od { + gpios = <&gpio7 0 GPIO_INPUT>; + }; + gpio_ec_x_gpio1: ec_x_gpio1 { + gpios = <&gpio6 2 GPIO_OUTPUT_LOW>; + }; + dp_aux_path_sel: dp_aux_path_sel { + gpios = <&gpio6 3 GPIO_OUTPUT_HIGH>; + }; + gpio_ec_bl_en_od: ec_bl_en_od { + gpios = <&gpio4 0 (GPIO_ODR_LOW | GPIO_VOLTAGE_1P8)>; + }; + gpio_ec_x_gpio3: ec_x_gpio3 { + gpios = <&gpiod 3 GPIO_OUTPUT_LOW>; + }; + gpio_usb_c0_tcpc_int_odl: usb_c0_tcpc_int_odl { + gpios = <&gpio7 3 GPIO_INPUT>; + enum-name = "GPIO_USB_C0_TCPC_INT_ODL"; + }; + gpio_usb_c0_tcpc_rst: usb_c0_tcpc_rst { + gpios = <&gpioc 0 GPIO_OUTPUT_LOW>; + }; + en_pp5000_usb_a0_vbus: en_pp5000_usb_a0_vbus { + gpios = <&gpio6 0 GPIO_OUTPUT_LOW>; + }; + gpio_hdmi_prsnt_odl: hdmi_prsnt_odl { + gpios = <&gpio3 7 GPIO_INPUT>; + }; + en_pp5000_z2 { + gpios = <&gpio3 4 GPIO_OUTPUT_HIGH>; + }; + gpio_usb_c1_tcpc_int_odl: usb_c1_tcpc_int_odl { + gpios = <&gpioe 1 GPIO_INPUT>; + }; + ec_batt_pres_odl { + gpios = <&gpioe 0 GPIO_INPUT>; + enum-name = "GPIO_BATT_PRES_ODL"; + }; + usb_a0_fault_odl { + gpios = <&gpioc 7 GPIO_INPUT>; + }; + ec_ap_dp_hpd_odl: ec_ap_dp_hpd_odl { + gpios = <&gpio6 1 GPIO_ODR_HIGH>; + }; + ec_pmic_en_odl { + gpios = <&gpio7 4 (GPIO_ODR_HIGH | GPIO_VOLTAGE_1P8)>; + enum-name = "GPIO_EC_PMIC_EN_ODL"; + }; + gpio_ec_volup_btn_odl: ec_volup_btn_odl { + gpios = <&gpiod 5 GPIO_INPUT>; + enum-name = "GPIO_VOLUME_UP_L"; + }; + gpio_ec_voldn_btn_odl: ec_voldn_btn_odl { + gpios = <&gpioe 2 GPIO_INPUT>; + enum-name = "GPIO_VOLUME_DOWN_L"; + }; + gpio_ccd_mode_odl: ccd_mode_odl { + gpios = <&gpioe 5 GPIO_INPUT>; + enum-name = "GPIO_CCD_MODE_ODL"; + }; + /* unimplemented GPIOs */ + entering-rw { + enum-name = "GPIO_ENTERING_RW"; + }; + }; + + /* + * aliases for sub-board GPIOs + */ + aliases { + gpio-en-hdmi-pwr = &gpio_ec_x_gpio1; + gpio-usb-c1-frs-en = &gpio_ec_x_gpio1; + gpio-usb-c1-ppc-int-odl = &gpio_x_ec_gpio2; + gpio-ps185-ec-dp-hpd = &gpio_x_ec_gpio2; + gpio-usb-c1-dp-in-hpd = &gpio_ec_x_gpio3; + gpio-ps185-pwrdn-odl = &gpio_ec_x_gpio3; + }; + + hibernate-wake-pins { + compatible = "cros-ec,hibernate-wake-pins"; + wakeup-irqs = < + &int_ac_present + &int_power_button + &int_lid_open + >; + }; +}; diff --git a/zephyr/projects/corsola/gpio_krabby.dts b/zephyr/projects/corsola/gpio_krabby.dts new file mode 100644 index 0000000000..5f06609f43 --- /dev/null +++ b/zephyr/projects/corsola/gpio_krabby.dts @@ -0,0 +1,231 @@ +/* Copyright 2021 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <dt-bindings/gpio_defines.h> + +/ { + aliases { + gpio-cbi-wp = &gpio_ec_cbi_wp; + gpio-wp = &ec_flash_wp_odl; + gpio-en-hdmi-pwr = &gpio_ec_x_gpio1; + gpio-usb-c1-frs-en = &gpio_ec_x_gpio1; + gpio-usb-c1-ppc-int-odl = &gpio_x_ec_gpio2; + gpio-ps185-ec-dp-hpd = &gpio_x_ec_gpio2; + gpio-usb-c1-dp-in-hpd = &gpio_ec_x_gpio3; + gpio-ps185-pwrdn-odl = &gpio_ec_x_gpio3; + }; + + named-gpios { + compatible = "named-gpios"; + + power_button_l: power_button_l { + gpios = <&gpioe 4 GPIO_INPUT>; + enum-name = "GPIO_POWER_BUTTON_L"; + }; + lid_open: lid_open { + gpios = <&gpioe 2 GPIO_INPUT>; + enum-name = "GPIO_LID_OPEN"; + }; + tablet_mode_l: tablet_mode_l { + gpios = <&gpioj 7 GPIO_INPUT>; + enum-name = "GPIO_TABLET_MODE_L"; + }; + ap_ec_warm_rst_req: ap_ec_warm_rst_req { + gpios = <&gpiod 3 (GPIO_INPUT | GPIO_VOLTAGE_1P8 | + GPIO_ACTIVE_HIGH)>; + enum-name = "GPIO_AP_EC_WARM_RST_REQ"; + }; + ap_in_sleep_l: ap_in_sleep_l { + gpios = <&gpiob 6 (GPIO_INPUT | GPIO_VOLTAGE_1P8 | + GPIO_ACTIVE_LOW)>; + enum-name = "GPIO_AP_IN_SLEEP_L"; + }; + base_imu_int_l: base_imu_int_l { + gpios = <&gpiom 3 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; + }; + lid_accel_int_l: lid_accel_int_l { + gpios = <&gpiom 2 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; + }; + volume_down_l: volume_down_l { + gpios = <&gpiod 5 GPIO_INPUT>; + enum-name = "GPIO_VOLUME_DOWN_L"; + }; + volume_up_l: volume_up_l { + gpios = <&gpiod 6 GPIO_INPUT>; + enum-name = "GPIO_VOLUME_UP_L"; + }; + gpio_ap_xhci_init_done: ap_xhci_init_done { + gpios = <&gpioj 5 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; + }; + ac_present: ac_present { + gpios = <&gpioe 5 GPIO_INPUT>; + enum-name = "GPIO_AC_PRESENT"; + }; + gpio_ec_cbi_wp: ec_cbi_wp { + gpios = <&gpioc 3 GPIO_OUTPUT_LOW>; + }; + ec_flash_wp_odl: ec_flash_wp_odl { + gpios = <&gpioi 4 (GPIO_INPUT | GPIO_VOLTAGE_1P8 | + GPIO_ACTIVE_LOW)>; + }; + spi0_cs: spi0_cs { + gpios = <&gpiom 5 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; + }; + gpio_x_ec_gpio2: x_ec_gpio2 { + gpios = <&gpiob 2 GPIO_INPUT>; + }; + usb_c0_ppc_bc12_int_odl: usb_c0_ppc_bc12_int_odl { + gpios = <&gpiod 1 GPIO_INPUT>; + }; + usb_c1_bc12_charger_int_odl: usb_c1_bc12_charger_int_odl { + gpios = <&gpioj 4 GPIO_INPUT>; + }; + ec_pmic_en_odl: ec_pmic_en_odl { + gpios = <&gpiod 0 (GPIO_ODR_HIGH | GPIO_VOLTAGE_1P8)>; + enum-name = "GPIO_EC_PMIC_EN_ODL"; + }; + en_pp5000_z2: en_pp5000_z2 { + gpios = <&gpioc 6 GPIO_OUTPUT_HIGH>; + }; + gpio_en_ulp: en_ulp { + gpios = <&gpioe 3 GPIO_OUTPUT_LOW>; + }; + sys_rst_odl: sys_rst_odl { + gpios = <&gpiog 1 GPIO_ODR_LOW>; + enum-name = "GPIO_SYS_RST_ODL"; + }; + gpio_ec_bl_en_od: ec_bl_en_od { + gpios = <&gpiob 5 (GPIO_ODR_LOW | GPIO_VOLTAGE_1P8)>; + }; + ap_sysrst_odl_r: ap_ec_sysrst_odl { + gpios = <&gpioj 2 (GPIO_INPUT | GPIO_VOLTAGE_1P8 | + GPIO_ACTIVE_LOW)>; + enum-name = "GPIO_AP_EC_SYSRST_ODL"; + }; + ap_ec_wdtrst_l: ap_ec_wdtrst_l { + gpios = <&gpioc 7 (GPIO_INPUT | GPIO_VOLTAGE_1P8 | + GPIO_ACTIVE_LOW)>; + enum-name = "GPIO_AP_EC_WDTRST_L"; + }; + ec_int_l: ec_int_l { + gpios = <&gpioe 6 (GPIO_ODR_HIGH | GPIO_VOLTAGE_1P8)>; + enum-name = "GPIO_EC_INT_L"; + }; + dp_aux_path_sel: dp_aux_path_sel { + gpios = <&gpiog 0 GPIO_OUTPUT_HIGH>; + }; + ec_ap_dp_hpd_odl: ec_ap_dp_hpd_odl { + gpios = <&gpioj 0 (GPIO_ODR_HIGH | GPIO_VOLTAGE_1P8)>; + }; + en_pp5000_usb_a0_vbus: en_pp5000_usb_a0_vbus { + gpios = <&gpiob 7 GPIO_OUTPUT_LOW>; + }; + usb_c0_ppc_frsinfo: usb_c0_ppc_frsinfo { + gpios = <&gpiof 0 GPIO_INPUT>; + }; + ec_batt_pres_odl: ec_batt_pres_odl { + gpios = <&gpioc 0 GPIO_INPUT>; + enum-name = "GPIO_BATT_PRES_ODL"; + }; + en_ec_id_odl: en_ec_id_odl { + gpios = <&gpioh 5 GPIO_ODR_HIGH>; + }; + entering_rw: entering_rw { + gpios = <&gpioc 5 GPIO_OUTPUT_LOW>; + enum-name = "GPIO_ENTERING_RW"; + }; + gpio_en_5v_usm: en_5v_usm { + gpios = <&gpiog 3 GPIO_OUTPUT_LOW>; + }; + usb_a0_fault_odl: usb_a0_fault_odl { + gpios = <&gpioj 6 GPIO_INPUT>; + }; + gpio_ec_x_gpio1: ec_x_gpio1 { + gpios = <&gpioh 4 GPIO_OUTPUT_LOW>; + }; + gpio_ec_x_gpio3: ec_x_gpio3 { + gpios = <&gpioj 1 GPIO_OUTPUT_LOW>; + }; + gpio_hdmi_prsnt_odl: hdmi_prsnt_odl { + gpios = <&gpioj 3 GPIO_INPUT>; + }; + gpio_packet_mode_en: packet_mode_en { + gpios = <&gpiod 4 GPIO_OUTPUT_LOW>; + enum-name = "GPIO_PACKET_MODE_EN"; + }; + gpio_ccd_mode_odl: ccd_mode_odl { + gpios = <&gpioc 4 GPIO_INPUT>; + enum-name = "GPIO_CCD_MODE_ODL"; + }; + }; + + hibernate-wake-pins { + compatible = "cros-ec,hibernate-wake-pins"; + wakeup-irqs = <&int_ac_present + &int_power_button + &int_lid_open>; + }; + + unused-pins { + compatible = "unused-gpios"; + + unused-gpios = + /* pg_pp5000_z2_od */ + <&gpiod 2 GPIO_INPUT>, + /* pg_mt6315_proc_b_odl */ + <&gpioe 1 GPIO_INPUT>, + /* ec_pen_chg_dis_odl */ + <&gpioh 3 GPIO_ODR_HIGH>, + /* unnamed nc pins */ + <&gpioa 3 GPIO_INPUT_PULL_DOWN>, + <&gpioa 6 GPIO_INPUT_PULL_DOWN>, + <&gpioa 7 GPIO_INPUT_PULL_DOWN>, + <&gpiod 7 GPIO_INPUT_PULL_DOWN>, + <&gpiof 1 GPIO_INPUT_PULL_DOWN>, + <&gpioh 0 GPIO_INPUT_PULL_DOWN>, + <&gpioh 6 GPIO_INPUT_PULL_DOWN>, + <&gpioi 3 GPIO_INPUT_PULL_DOWN>, + <&gpioi 5 GPIO_INPUT_PULL_DOWN>, + <&gpioi 6 GPIO_INPUT_PULL_DOWN>, + <&gpiom 6 (GPIO_INPUT_PULL_DOWN | GPIO_VOLTAGE_1P8)>, + /* spi_clk_gpg6 */ + <&gpiog 6 GPIO_INPUT_PULL_UP>, + /* spi_mosi_gpg4 */ + <&gpiog 4 GPIO_OUTPUT_LOW>, + /* spi_miso_gpg5 */ + <&gpiog 5 GPIO_OUTPUT_LOW>, + /* spi_cs_gpg7 */ + <&gpiog 7 GPIO_OUTPUT_LOW>; + }; +}; + +&pinctrl { + /* I2C property setting */ + i2c0_clk_gpb3_default: i2c0_clk_gpb3_default { + gpio-voltage = "1v8"; + }; + i2c0_data_gpb4_default: i2c0_data_gpb4_default { + gpio-voltage = "1v8"; + }; + i2c3_clk_gpf2_default: i2c3_clk_gpf2_default { + gpio-voltage = "1v8"; + }; + i2c3_data_gpf3_default: i2c3_data_gpf3_default { + gpio-voltage = "1v8"; + }; + /* SHI property setting */ + shi_mosi_gpm0_default: shi_mosi_gpm0_default { + gpio-voltage = "1v8"; + }; + shi_miso_gpm1_default: shi_miso_gpm1_default { + gpio-voltage = "1v8"; + }; + shi_clk_gpm4_default: shi_clk_gpm4_default { + gpio-voltage = "1v8"; + }; + shi_cs_gpm5_default: shi_cs_gpm5_default { + gpio-voltage = "1v8"; + }; +}; diff --git a/zephyr/projects/corsola/gpio_magikarp.dts b/zephyr/projects/corsola/gpio_magikarp.dts new file mode 100644 index 0000000000..cb9f6f1a0a --- /dev/null +++ b/zephyr/projects/corsola/gpio_magikarp.dts @@ -0,0 +1,237 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <dt-bindings/gpio_defines.h> + +/ { + aliases { + gpio-cbi-wp = &gpio_ec_cbi_wp; + gpio-wp = &ec_flash_wp_odl; + gpio-en-hdmi-pwr = &gpio_ec_x_gpio1; + gpio-usb-c1-frs-en = &gpio_ec_x_gpio1; + gpio-usb-c1-ppc-int-odl = &gpio_x_ec_gpio2; + gpio-ps185-ec-dp-hpd = &gpio_x_ec_gpio2; + gpio-usb-c1-dp-in-hpd = &gpio_ec_x_gpio3; + gpio-ps185-pwrdn-odl = &gpio_ec_x_gpio3; + }; + + named-gpios { + compatible = "named-gpios"; + + power_button_l: power_button_l { + gpios = <&gpioe 4 GPIO_INPUT>; + enum-name = "GPIO_POWER_BUTTON_L"; + }; + lid_open: lid_open { + gpios = <&gpioe 2 GPIO_INPUT>; + enum-name = "GPIO_LID_OPEN"; + }; + tablet_mode_l: tablet_mode_l { + gpios = <&gpioj 7 GPIO_INPUT>; + enum-name = "GPIO_TABLET_MODE_L"; + }; + ap_ec_warm_rst_req: ap_ec_warm_rst_req { + gpios = <&gpiod 3 (GPIO_INPUT | GPIO_VOLTAGE_1P8 | + GPIO_ACTIVE_HIGH)>; + enum-name = "GPIO_AP_EC_WARM_RST_REQ"; + }; + ap_in_sleep_l: ap_in_sleep_l { + gpios = <&gpiob 6 (GPIO_INPUT | GPIO_VOLTAGE_1P8 | + GPIO_ACTIVE_LOW)>; + enum-name = "GPIO_AP_IN_SLEEP_L"; + }; + base_imu_int_l: base_imu_int_l { + gpios = <&gpiom 3 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; + }; + lid_accel_int_l: lid_accel_int_l { + gpios = <&gpiom 2 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; + }; + volume_down_l: volume_down_l { + gpios = <&gpiod 5 GPIO_INPUT>; + enum-name = "GPIO_VOLUME_DOWN_L"; + }; + volume_up_l: volume_up_l { + gpios = <&gpiod 6 GPIO_INPUT>; + enum-name = "GPIO_VOLUME_UP_L"; + }; + gpio_ap_xhci_init_done: ap_xhci_init_done { + gpios = <&gpioj 5 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; + }; + ac_present: ac_present { + gpios = <&gpioe 5 GPIO_INPUT>; + enum-name = "GPIO_AC_PRESENT"; + }; + gpio_ec_cbi_wp: ec_cbi_wp { + gpios = <&gpioc 3 GPIO_OUTPUT_LOW>; + }; + ec_flash_wp_odl: ec_flash_wp_odl { + gpios = <&gpioi 4 (GPIO_INPUT | GPIO_VOLTAGE_1P8 | + GPIO_ACTIVE_LOW)>; + }; + spi0_cs: spi0_cs { + gpios = <&gpiom 5 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; + }; + gpio_x_ec_gpio2: x_ec_gpio2 { + gpios = <&gpiob 2 GPIO_INPUT>; + }; + usb_c0_ppc_int_odl: usb_c0_ppc_int_odl { + gpios = <&gpiod 1 GPIO_INPUT>; + enum-name = "GPIO_USB_C0_PPC_INT_ODL"; + }; + usb_c0_bc12_int_odl: usb_c0_bc12_int_odl { + gpios = <&gpiof 1 GPIO_INPUT>; + enum-name = "GPIO_USB_C0_BC12_INT_ODL"; + }; + usb_c1_bc12_charger_int_odl: usb_c1_bc12_charger_int_odl { + gpios = <&gpioj 4 GPIO_INPUT>; + }; + ec_pmic_en_odl: ec_pmic_en_odl { + gpios = <&gpiod 0 (GPIO_ODR_HIGH | GPIO_VOLTAGE_1P8)>; + enum-name = "GPIO_EC_PMIC_EN_ODL"; + }; + en_pp5000_z2: en_pp5000_z2 { + gpios = <&gpioc 6 GPIO_OUTPUT_HIGH>; + }; + gpio_en_ulp: en_ulp { + gpios = <&gpioe 3 GPIO_OUTPUT_LOW>; + }; + sys_rst_odl: sys_rst_odl { + gpios = <&gpiog 1 GPIO_ODR_LOW>; + enum-name = "GPIO_SYS_RST_ODL"; + }; + gpio_ec_bl_en_od: ec_bl_en_od { + gpios = <&gpiob 5 (GPIO_ODR_LOW | GPIO_VOLTAGE_1P8)>; + }; + ap_sysrst_odl_r: ap_ec_sysrst_odl { + gpios = <&gpioj 2 (GPIO_INPUT | GPIO_VOLTAGE_1P8 | + GPIO_ACTIVE_LOW)>; + enum-name = "GPIO_AP_EC_SYSRST_ODL"; + }; + ap_ec_wdtrst_l: ap_ec_wdtrst_l { + gpios = <&gpioc 7 (GPIO_INPUT | GPIO_VOLTAGE_1P8 | + GPIO_ACTIVE_LOW)>; + enum-name = "GPIO_AP_EC_WDTRST_L"; + }; + ec_int_l: ec_int_l { + gpios = <&gpioe 6 (GPIO_ODR_HIGH | GPIO_VOLTAGE_1P8)>; + enum-name = "GPIO_EC_INT_L"; + }; + dp_aux_path_sel: dp_aux_path_sel { + gpios = <&gpiog 0 GPIO_OUTPUT_HIGH>; + }; + ec_ap_dp_hpd_odl: ec_ap_dp_hpd_odl { + gpios = <&gpioj 0 (GPIO_ODR_HIGH | GPIO_VOLTAGE_1P8)>; + }; + en_pp5000_usb_a0_vbus: en_pp5000_usb_a0_vbus { + gpios = <&gpiob 7 GPIO_OUTPUT_LOW>; + }; + usb_c0_frs_en: usb_c0_frs_en { + gpios = <&gpiof 0 GPIO_OUTPUT_LOW>; + enum-name = "GPIO_USB_C0_FRS_EN"; + }; + ec_batt_pres_odl: ec_batt_pres_odl { + gpios = <&gpioc 0 GPIO_INPUT>; + enum-name = "GPIO_BATT_PRES_ODL"; + }; + en_ec_id_odl: en_ec_id_odl { + gpios = <&gpioh 5 GPIO_ODR_HIGH>; + }; + entering_rw: entering_rw { + gpios = <&gpioc 5 GPIO_OUTPUT_LOW>; + enum-name = "GPIO_ENTERING_RW"; + }; + gpio_en_5v_usm: en_5v_usm { + gpios = <&gpiog 3 GPIO_OUTPUT_LOW>; + }; + usb_a0_fault_odl: usb_a0_fault_odl { + gpios = <&gpioj 6 GPIO_INPUT>; + }; + gpio_ec_x_gpio1: ec_x_gpio1 { + gpios = <&gpioh 4 GPIO_OUTPUT_LOW>; + }; + gpio_ec_x_gpio3: ec_x_gpio3 { + gpios = <&gpioj 1 GPIO_OUTPUT_LOW>; + }; + gpio_hdmi_prsnt_odl: hdmi_prsnt_odl { + gpios = <&gpioj 3 GPIO_INPUT>; + }; + gpio_packet_mode_en: packet_mode_en { + gpios = <&gpiod 4 GPIO_OUTPUT_LOW>; + enum-name = "GPIO_PACKET_MODE_EN"; + }; + gpio_ccd_mode_odl: ccd_mode_odl { + gpios = <&gpioc 4 GPIO_INPUT>; + enum-name = "GPIO_CCD_MODE_ODL"; + }; + }; + + hibernate-wake-pins { + compatible = "cros-ec,hibernate-wake-pins"; + wakeup-irqs = <&int_ac_present + &int_power_button + &int_lid_open>; + }; + + unused-pins { + compatible = "unused-gpios"; + + unused-gpios = + /* pg_pp5000_z2_od */ + <&gpiod 2 GPIO_INPUT>, + /* pg_mt6315_proc_b_odl */ + <&gpioe 1 GPIO_INPUT>, + /* ec_pen_chg_dis_odl */ + <&gpioh 3 GPIO_ODR_HIGH>, + /* unnamed nc pins */ + <&gpioa 3 GPIO_INPUT_PULL_DOWN>, + <&gpioa 6 GPIO_INPUT_PULL_DOWN>, + <&gpioa 7 GPIO_INPUT_PULL_DOWN>, + /* reserved for b:241345809 */ + <&gpiod 7 GPIO_OUTPUT_LOW>, + <&gpiog 2 GPIO_INPUT_PULL_DOWN>, + <&gpioh 0 GPIO_INPUT_PULL_DOWN>, + <&gpioh 6 GPIO_INPUT_PULL_DOWN>, + <&gpioi 3 GPIO_INPUT_PULL_DOWN>, + <&gpioi 6 GPIO_INPUT_PULL_DOWN>, + <&gpiom 6 (GPIO_INPUT_PULL_DOWN | GPIO_VOLTAGE_1P8)>, + /* spi_clk_gpg6 */ + <&gpiog 6 GPIO_INPUT_PULL_UP>, + /* spi_mosi_gpg4 */ + <&gpiog 4 GPIO_OUTPUT_LOW>, + /* spi_miso_gpg5 */ + <&gpiog 5 GPIO_OUTPUT_LOW>, + /* spi_cs_gpg7 */ + <&gpiog 7 GPIO_OUTPUT_LOW>; + }; +}; + +&pinctrl { + /* I2C property setting */ + i2c0_clk_gpb3_default: i2c0_clk_gpb3_default { + gpio-voltage = "1v8"; + }; + i2c0_data_gpb4_default: i2c0_data_gpb4_default { + gpio-voltage = "1v8"; + }; + i2c3_clk_gpf2_default: i2c3_clk_gpf2_default { + gpio-voltage = "1v8"; + }; + i2c3_data_gpf3_default: i2c3_data_gpf3_default { + gpio-voltage = "1v8"; + }; + /* SHI property setting */ + shi_mosi_gpm0_default: shi_mosi_gpm0_default { + gpio-voltage = "1v8"; + }; + shi_miso_gpm1_default: shi_miso_gpm1_default { + gpio-voltage = "1v8"; + }; + shi_clk_gpm4_default: shi_clk_gpm4_default { + gpio-voltage = "1v8"; + }; + shi_cs_gpm5_default: shi_cs_gpm5_default { + gpio-voltage = "1v8"; + }; +}; diff --git a/zephyr/projects/corsola/gpio_steelix.dts b/zephyr/projects/corsola/gpio_steelix.dts new file mode 100644 index 0000000000..14120e6d7d --- /dev/null +++ b/zephyr/projects/corsola/gpio_steelix.dts @@ -0,0 +1,255 @@ +/* Copyright 2021 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + aliases { + gpio-cbi-wp = &gpio_ec_cbi_wp; + gpio-wp = &gpio_ec_wp_l; + gpio-kbd-kso2 = &gpio_ec_kso_02_inv; + }; + + named-gpios { + compatible = "named-gpios"; + + /* + * In npcx9 series, gpio46, gpio47, and the whole gpio5 port + * belong to VHIF power well. On steelix, it is connencted to + * 1.8V. + */ + base_imu_int_l: base_imu_int_l { + gpios = <&gpio5 6 GPIO_INPUT>; + }; + spi_ap_clk_ec { + gpios = <&gpio5 5 GPIO_INPUT>; + }; + spi_ap_cs_ec_l { + gpios = <&gpio5 3 GPIO_INPUT>; + }; + spi_ap_do_ec_di { + gpios = <&gpio4 6 GPIO_INPUT>; + }; + spi_ap_di_ec_do { + gpios = <&gpio4 7 GPIO_INPUT>; + }; + ap_ec_warm_rst_req: ap_ec_warm_rst_req { + gpios = <&gpio5 1 (GPIO_INPUT | GPIO_ACTIVE_HIGH)>; + enum-name = "GPIO_AP_EC_WARM_RST_REQ"; + }; + ap_ec_wdtrst_l: ap_ec_wdtrst_l { + gpios = <&gpio5 2 (GPIO_INPUT | GPIO_ACTIVE_LOW)>; + enum-name = "GPIO_AP_EC_WDTRST_L"; + }; + ap_in_sleep_l: ap_in_sleep_l { + gpios = <&gpio5 4 (GPIO_INPUT | GPIO_ACTIVE_LOW)>; + enum-name = "GPIO_AP_IN_SLEEP_L"; + }; + gpio_en_ulp: en_ulp { + gpios = <&gpioc 6 GPIO_OUTPUT_LOW>; + }; + en_ec_id_odl { + gpios = <&gpio7 6 GPIO_ODR_HIGH>; + }; + sys_rst_odl { + gpios = <&gpioc 5 (GPIO_ODR_LOW | GPIO_VOLTAGE_1P8)>; + enum-name = "GPIO_SYS_RST_ODL"; + }; + ec_i2c_sensor_scl { + gpios = <&gpiob 5 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; + }; + ec_i2c_sensor_sda { + gpios = <&gpiob 4 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; + }; + ec_i2c_usb_c0_scl { + gpios = <&gpio9 0 GPIO_INPUT>; + }; + ec_i2c_usb_c0_sda { + gpios = <&gpio8 7 GPIO_INPUT>; + }; + ec_i2c_usb_c1_scl { + gpios = <&gpio9 2 GPIO_INPUT>; + }; + ec_i2c_usb_c1_sda { + gpios = <&gpio9 1 GPIO_INPUT>; + }; + ec_i2c_pwr_cbi_scl { + gpios = <&gpiod 1 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; + }; + ec_i2c_pwr_cbi_sda { + gpios = <&gpiod 0 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; + }; + ec_i2c_batt_scl { + gpios = <&gpio3 3 GPIO_INPUT>; + }; + ec_i2c_batt_sda { + gpios = <&gpio3 6 GPIO_INPUT>; + }; + en_pp5000_usb_a1_vbus: en_pp5000_usb_a1_vbus_x { + gpios = <&gpiof 5 GPIO_OUTPUT_LOW>; + }; + usb_a1_fault_odl { + gpios = <&gpiof 4 GPIO_INPUT>; + }; + ec_pen_chg_dis_odl { + gpios = <&gpioe 4 GPIO_INPUT>; + }; + gpio_ec_cbi_wp: ec_cbi_wp { + gpios = <&gpio8 0 GPIO_OUTPUT_LOW>; + }; + gpio_ec_wp_l: ec_wp_odl { + gpios = <&gpioe 3 (GPIO_INPUT | GPIO_ACTIVE_LOW | + GPIO_VOLTAGE_1P8)>; + }; + lid_accel_int_l { + gpios = <&gpiob 3 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; + }; + gpio_tablet_mode_l: tablet_mode_l { + gpios = <&gpiob 2 GPIO_INPUT>; + enum-name = "GPIO_TABLET_MODE_L"; + }; + ec_ap_int_odl { + gpios = <&gpioc 1 (GPIO_ODR_HIGH | GPIO_VOLTAGE_1P8)>; + enum-name = "GPIO_EC_INT_L"; + }; + gpio_ec_kso_02_inv: ec_kso_02_inv { + gpios = <&gpio1 7 (GPIO_OUTPUT_LOW | GPIO_ACTIVE_LOW)>; + }; + gpio_usb_c0_bc12_int_odl: usb_c0_bc12_int_odl { + gpios = <&gpio8 3 GPIO_INPUT>; + enum-name = "GPIO_USB_C0_BC12_INT_ODL"; + }; + ec_entering_rw { + gpios = <&gpio0 3 GPIO_OUTPUT_LOW>; + }; + charger_prochot_odl { + gpios = <&gpiob 1 GPIO_INPUT>; + }; + ec_rst_odl { + gpios = <&gpio7 7 GPIO_INPUT>; + }; + gpio_lid_open: lid_open { + gpios = <&gpiod 2 GPIO_INPUT>; + enum-name = "GPIO_LID_OPEN"; + }; + gpio_acok_od: acok_od { + gpios = <&gpio0 0 GPIO_INPUT>; + enum-name = "GPIO_AC_PRESENT"; + }; + gpio_gsc_ec_pwr_btn_odl: gsc_ec_pwr_btn_odl { + gpios = <&gpio0 1 GPIO_INPUT>; + enum-name = "GPIO_POWER_BUTTON_L"; + }; + gpio_en_5v_usm: en_5v_usm { + gpios = <&gpio0 2 GPIO_OUTPUT_LOW>; + }; + packet_mode_en { + gpios = <&gpio7 5 GPIO_OUTPUT_LOW>; + enum-name = "GPIO_PACKET_MODE_EN"; + }; + gpio_x_ec_gpio2: x_ec_gpio2 { + gpios = <&gpiod 4 GPIO_INPUT>; + }; + /* + * In npcx9 series, gpio93-97, the whole gpioa port, and gpiob0 + * belong to VSPI power well. On steelix, it is connencted to + * 1.8V. + */ + ap_sysrst_odl_r: ap_sysrst_odl_r { + gpios = <&gpioa 1 (GPIO_INPUT | GPIO_ACTIVE_LOW)>; + enum-name = "GPIO_AP_EC_SYSRST_ODL"; + }; + gpio_ap_xhci_init_done: ap_xhci_init_done { + gpios = <&gpioa 3 GPIO_INPUT>; + }; + gpio_usb_c0_ppc_int_odl: usb_c0_ppc_int_odl { + gpios = <&gpio6 7 GPIO_INPUT>; + enum-name = "GPIO_USB_C0_PPC_INT_ODL"; + }; + pg_pp5000_z2_od { + gpios = <&gpio7 0 GPIO_INPUT>; + }; + gpio_ec_x_gpio1: ec_x_gpio1 { + gpios = <&gpio6 2 GPIO_OUTPUT_LOW>; + }; + dp_aux_path_sel: dp_aux_path_sel { + gpios = <&gpio6 3 GPIO_OUTPUT_HIGH>; + }; + gpio_ec_bl_en_od: ec_bl_en_od { + gpios = <&gpio4 0 (GPIO_ODR_LOW | GPIO_VOLTAGE_1P8)>; + }; + gpio_ec_x_gpio3: ec_x_gpio3 { + gpios = <&gpiod 3 GPIO_OUTPUT_LOW>; + }; + gpio_usb_c0_tcpc_int_odl: usb_c0_tcpc_int_odl { + gpios = <&gpio7 3 GPIO_INPUT>; + enum-name = "GPIO_USB_C0_TCPC_INT_ODL"; + }; + gpio_usb_c0_tcpc_rst: usb_c0_tcpc_rst { + gpios = <&gpioc 0 GPIO_OUTPUT_LOW>; + }; + en_pp5000_usb_a0_vbus: en_pp5000_usb_a0_vbus { + gpios = <&gpio6 0 GPIO_OUTPUT_LOW>; + }; + gpio_hdmi_prsnt_odl: hdmi_prsnt_odl { + gpios = <&gpio3 7 GPIO_INPUT>; + }; + en_pp5000_z2 { + gpios = <&gpio3 4 GPIO_OUTPUT_HIGH>; + }; + gpio_usb_c1_tcpc_int_odl: usb_c1_tcpc_int_odl { + gpios = <&gpioe 1 GPIO_INPUT>; + }; + ec_batt_pres_odl { + gpios = <&gpioe 0 GPIO_INPUT>; + enum-name = "GPIO_BATT_PRES_ODL"; + }; + usb_a0_fault_odl { + gpios = <&gpioc 7 GPIO_INPUT>; + }; + ec_ap_dp_hpd_odl: ec_ap_dp_hpd_odl { + gpios = <&gpio6 1 GPIO_ODR_HIGH>; + }; + ec_pmic_en_odl { + gpios = <&gpio7 4 (GPIO_ODR_HIGH | GPIO_VOLTAGE_1P8)>; + enum-name = "GPIO_EC_PMIC_EN_ODL"; + }; + gpio_ec_volup_btn_odl: ec_volup_btn_odl { + gpios = <&gpiod 5 GPIO_INPUT>; + enum-name = "GPIO_VOLUME_UP_L"; + }; + gpio_ec_voldn_btn_odl: ec_voldn_btn_odl { + gpios = <&gpioe 2 GPIO_INPUT>; + enum-name = "GPIO_VOLUME_DOWN_L"; + }; + gpio_ccd_mode_odl: ccd_mode_odl { + gpios = <&gpioe 5 GPIO_INPUT>; + enum-name = "GPIO_CCD_MODE_ODL"; + }; + /* unimplemented GPIOs */ + entering-rw { + enum-name = "GPIO_ENTERING_RW"; + }; + }; + + /* + * aliases for sub-board GPIOs + */ + aliases { + gpio-en-hdmi-pwr = &gpio_ec_x_gpio1; + gpio-usb-c1-frs-en = &gpio_ec_x_gpio1; + gpio-usb-c1-ppc-int-odl = &gpio_x_ec_gpio2; + gpio-ps185-ec-dp-hpd = &gpio_x_ec_gpio2; + gpio-usb-c1-dp-in-hpd = &gpio_ec_x_gpio3; + gpio-ps185-pwrdn-odl = &gpio_ec_x_gpio3; + }; + + hibernate-wake-pins { + compatible = "cros-ec,hibernate-wake-pins"; + wakeup-irqs = < + &int_ac_present + &int_power_button + &int_lid_open + >; + }; +}; diff --git a/zephyr/projects/corsola/gpio_tentacruel.dts b/zephyr/projects/corsola/gpio_tentacruel.dts new file mode 100644 index 0000000000..a9ac9e8eac --- /dev/null +++ b/zephyr/projects/corsola/gpio_tentacruel.dts @@ -0,0 +1,235 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <dt-bindings/gpio_defines.h> + +/ { + aliases { + gpio-cbi-wp = &gpio_ec_cbi_wp; + gpio-wp = &ec_flash_wp_odl; + gpio-en-hdmi-pwr = &gpio_ec_x_gpio1; + gpio-usb-c1-frs-en = &gpio_ec_x_gpio1; + gpio-usb-c1-ppc-int-odl = &gpio_x_ec_gpio2; + gpio-ps185-ec-dp-hpd = &gpio_x_ec_gpio2; + gpio-usb-c1-dp-in-hpd = &gpio_ec_x_gpio3; + gpio-ps185-pwrdn-odl = &gpio_ec_x_gpio3; + }; + + named-gpios { + compatible = "named-gpios"; + + power_button_l: power_button_l { + gpios = <&gpioe 4 GPIO_INPUT>; + enum-name = "GPIO_POWER_BUTTON_L"; + }; + lid_open: lid_open { + gpios = <&gpioe 2 GPIO_INPUT>; + enum-name = "GPIO_LID_OPEN"; + }; + tablet_mode_l: tablet_mode_l { + gpios = <&gpioj 7 GPIO_INPUT>; + enum-name = "GPIO_TABLET_MODE_L"; + }; + ap_ec_warm_rst_req: ap_ec_warm_rst_req { + gpios = <&gpiod 3 (GPIO_INPUT | GPIO_VOLTAGE_1P8 | + GPIO_ACTIVE_HIGH)>; + enum-name = "GPIO_AP_EC_WARM_RST_REQ"; + }; + ap_in_sleep_l: ap_in_sleep_l { + gpios = <&gpiob 6 (GPIO_INPUT | GPIO_VOLTAGE_1P8 | + GPIO_ACTIVE_LOW)>; + enum-name = "GPIO_AP_IN_SLEEP_L"; + }; + base_imu_int_l: base_imu_int_l { + gpios = <&gpiom 3 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; + }; + lid_accel_int_l: lid_accel_int_l { + gpios = <&gpiom 2 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; + }; + volume_down_l: volume_down_l { + gpios = <&gpiod 5 GPIO_INPUT>; + enum-name = "GPIO_VOLUME_DOWN_L"; + }; + volume_up_l: volume_up_l { + gpios = <&gpiod 6 GPIO_INPUT>; + enum-name = "GPIO_VOLUME_UP_L"; + }; + gpio_ap_xhci_init_done: ap_xhci_init_done { + gpios = <&gpioj 5 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; + }; + ac_present: ac_present { + gpios = <&gpioe 5 GPIO_INPUT>; + enum-name = "GPIO_AC_PRESENT"; + }; + gpio_ec_cbi_wp: ec_cbi_wp { + gpios = <&gpioc 3 GPIO_OUTPUT_LOW>; + }; + ec_flash_wp_odl: ec_flash_wp_odl { + gpios = <&gpioi 4 (GPIO_INPUT | GPIO_VOLTAGE_1P8 | + GPIO_ACTIVE_LOW)>; + }; + spi0_cs: spi0_cs { + gpios = <&gpiom 5 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; + }; + gpio_x_ec_gpio2: x_ec_gpio2 { + gpios = <&gpiob 2 GPIO_INPUT>; + }; + usb_c0_ppc_int_odl: usb_c0_ppc_int_odl { + gpios = <&gpiod 1 GPIO_INPUT>; + enum-name = "GPIO_USB_C0_PPC_INT_ODL"; + }; + usb_c0_bc12_int_odl: usb_c0_bc12_int_odl { + gpios = <&gpiof 1 GPIO_INPUT>; + enum-name = "GPIO_USB_C0_BC12_INT_ODL"; + }; + usb_c1_bc12_charger_int_odl: usb_c1_bc12_charger_int_odl { + gpios = <&gpioj 4 GPIO_INPUT>; + }; + ec_pmic_en_odl: ec_pmic_en_odl { + gpios = <&gpiod 0 (GPIO_ODR_HIGH | GPIO_VOLTAGE_1P8)>; + enum-name = "GPIO_EC_PMIC_EN_ODL"; + }; + en_pp5000_z2: en_pp5000_z2 { + gpios = <&gpioc 6 GPIO_OUTPUT_HIGH>; + }; + gpio_en_ulp: en_ulp { + gpios = <&gpioe 3 GPIO_OUTPUT_LOW>; + }; + sys_rst_odl: sys_rst_odl { + gpios = <&gpiog 1 GPIO_ODR_LOW>; + enum-name = "GPIO_SYS_RST_ODL"; + }; + gpio_ec_bl_en_od: ec_bl_en_od { + gpios = <&gpiob 5 (GPIO_ODR_LOW | GPIO_VOLTAGE_1P8)>; + }; + ap_sysrst_odl_r: ap_ec_sysrst_odl { + gpios = <&gpioj 2 (GPIO_INPUT | GPIO_VOLTAGE_1P8 | + GPIO_ACTIVE_LOW)>; + enum-name = "GPIO_AP_EC_SYSRST_ODL"; + }; + ap_ec_wdtrst_l: ap_ec_wdtrst_l { + gpios = <&gpioc 7 (GPIO_INPUT | GPIO_VOLTAGE_1P8 | + GPIO_ACTIVE_LOW)>; + enum-name = "GPIO_AP_EC_WDTRST_L"; + }; + ec_int_l: ec_int_l { + gpios = <&gpioe 6 (GPIO_ODR_HIGH | GPIO_VOLTAGE_1P8)>; + enum-name = "GPIO_EC_INT_L"; + }; + dp_aux_path_sel: dp_aux_path_sel { + gpios = <&gpiog 0 GPIO_OUTPUT_HIGH>; + }; + ec_ap_dp_hpd_odl: ec_ap_dp_hpd_odl { + gpios = <&gpioj 0 (GPIO_ODR_HIGH | GPIO_VOLTAGE_1P8)>; + }; + en_pp5000_usb_a0_vbus: en_pp5000_usb_a0_vbus { + gpios = <&gpiob 7 GPIO_OUTPUT_LOW>; + }; + usb_c0_frs_en: usb_c0_frs_en { + gpios = <&gpiof 0 GPIO_OUTPUT_LOW>; + enum-name = "GPIO_USB_C0_FRS_EN"; + }; + ec_batt_pres_odl: ec_batt_pres_odl { + gpios = <&gpioc 0 GPIO_INPUT>; + enum-name = "GPIO_BATT_PRES_ODL"; + }; + en_ec_id_odl: en_ec_id_odl { + gpios = <&gpioh 5 GPIO_ODR_HIGH>; + }; + entering_rw: entering_rw { + gpios = <&gpioc 5 GPIO_OUTPUT_LOW>; + enum-name = "GPIO_ENTERING_RW"; + }; + gpio_en_5v_usm: en_5v_usm { + gpios = <&gpiog 3 GPIO_OUTPUT_LOW>; + }; + usb_a0_fault_odl: usb_a0_fault_odl { + gpios = <&gpioj 6 GPIO_INPUT>; + }; + gpio_ec_x_gpio1: ec_x_gpio1 { + gpios = <&gpioh 4 GPIO_OUTPUT_LOW>; + }; + gpio_ec_x_gpio3: ec_x_gpio3 { + gpios = <&gpioj 1 GPIO_OUTPUT_LOW>; + }; + gpio_hdmi_prsnt_odl: hdmi_prsnt_odl { + gpios = <&gpioj 3 GPIO_INPUT>; + }; + gpio_packet_mode_en: packet_mode_en { + gpios = <&gpiod 4 GPIO_OUTPUT_LOW>; + enum-name = "GPIO_PACKET_MODE_EN"; + }; + gpio_ccd_mode_odl: ccd_mode_odl { + gpios = <&gpioc 4 GPIO_INPUT>; + enum-name = "GPIO_CCD_MODE_ODL"; + }; + }; + + hibernate-wake-pins { + compatible = "cros-ec,hibernate-wake-pins"; + wakeup-irqs = <&int_ac_present + &int_power_button + &int_lid_open>; + }; + + unused-pins { + compatible = "unused-gpios"; + + unused-gpios = + /* pg_pp5000_z2_od */ + <&gpiod 2 GPIO_INPUT>, + /* pg_mt6315_proc_b_odl */ + <&gpioe 1 GPIO_INPUT>, + /* ec_pen_chg_dis_odl */ + <&gpioh 3 GPIO_ODR_HIGH>, + /* unnamed nc pins */ + <&gpioa 3 GPIO_INPUT_PULL_DOWN>, + <&gpioa 6 GPIO_INPUT_PULL_DOWN>, + <&gpioa 7 GPIO_INPUT_PULL_DOWN>, + <&gpiod 7 GPIO_INPUT_PULL_DOWN>, + <&gpioh 0 GPIO_INPUT_PULL_DOWN>, + <&gpioh 6 GPIO_INPUT_PULL_DOWN>, + <&gpioi 3 GPIO_INPUT_PULL_DOWN>, + <&gpioi 6 GPIO_INPUT_PULL_DOWN>, + <&gpiom 6 (GPIO_INPUT_PULL_DOWN | GPIO_VOLTAGE_1P8)>, + /* spi_clk_gpg6 */ + <&gpiog 6 GPIO_INPUT_PULL_UP>, + /* spi_mosi_gpg4 */ + <&gpiog 4 GPIO_OUTPUT_LOW>, + /* spi_miso_gpg5 */ + <&gpiog 5 GPIO_OUTPUT_LOW>, + /* spi_cs_gpg7 */ + <&gpiog 7 GPIO_OUTPUT_LOW>; + }; +}; + +&pinctrl { + /* I2C property setting */ + i2c0_clk_gpb3_default: i2c0_clk_gpb3_default { + gpio-voltage = "1v8"; + }; + i2c0_data_gpb4_default: i2c0_data_gpb4_default { + gpio-voltage = "1v8"; + }; + i2c3_clk_gpf2_default: i2c3_clk_gpf2_default { + gpio-voltage = "1v8"; + }; + i2c3_data_gpf3_default: i2c3_data_gpf3_default { + gpio-voltage = "1v8"; + }; + /* SHI property setting */ + shi_mosi_gpm0_default: shi_mosi_gpm0_default { + gpio-voltage = "1v8"; + }; + shi_miso_gpm1_default: shi_miso_gpm1_default { + gpio-voltage = "1v8"; + }; + shi_clk_gpm4_default: shi_clk_gpm4_default { + gpio-voltage = "1v8"; + }; + shi_cs_gpm5_default: shi_cs_gpm5_default { + gpio-voltage = "1v8"; + }; +}; diff --git a/zephyr/projects/corsola/host_interface_npcx.dts b/zephyr/projects/corsola/host_interface_npcx.dts new file mode 100644 index 0000000000..14efa3c6b2 --- /dev/null +++ b/zephyr/projects/corsola/host_interface_npcx.dts @@ -0,0 +1,12 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* host interface */ +&shi { + status = "okay"; + pinctrl-0 = <&shi_gp46_47_53_55>; + pinctrl-1 = <&shi_gpio_gp46_47_53_55>; + pinctrl-names = "default", "sleep"; +}; diff --git a/zephyr/projects/corsola/i2c_kingler.dts b/zephyr/projects/corsola/i2c_kingler.dts new file mode 100644 index 0000000000..90390ab8a0 --- /dev/null +++ b/zephyr/projects/corsola/i2c_kingler.dts @@ -0,0 +1,169 @@ +/* Copyright 2021 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <dt-bindings/usb_pd_tcpm.h> + +/* + * Kingler and Steelix use the same dts, take care of this when modify it. + */ + +/ { + named-i2c-ports { + compatible = "named-i2c-ports"; + + i2c_sensor: sensor { + i2c-port = <&i2c0_0>; + enum-names = "I2C_PORT_SENSOR"; + }; + i2c_usb_c0: usb-c0 { + i2c-port = <&i2c1_0>; + remote-port = <7>; + enum-names = "I2C_PORT_USB_C0"; + }; + i2c_usb_c1: usb-c1 { + i2c-port = <&i2c2_0>; + enum-names = "I2C_PORT_USB_C1", + "I2C_PORT_USB_C1_TCPC", + "I2C_PORT_USB_C1_PPC"; + }; + i2c_charger: charger { + i2c-port = <&i2c3_0>; + enum-names = "I2C_PORT_POWER", + "I2C_PORT_EEPROM"; + }; + battery { + i2c-port = <&i2c5_0>; + remote-port = <1>; + enum-names = "I2C_PORT_BATTERY", + "I2C_PORT_VIRTUAL_BATTERY"; + }; + }; +}; + +&i2c0_0 { + label = "I2C_SENSOR"; + status = "okay"; + clock-frequency = <I2C_BITRATE_FAST>; + pinctrl-0 = <&i2c0_0_sda_scl_gpb4_b5>; + pinctrl-names = "default"; +}; + +&i2c_ctrl0 { + status = "okay"; +}; + +&i2c1_0 { + label = "I2C_USB_C0"; + status = "okay"; + clock-frequency = <I2C_BITRATE_FAST_PLUS>; + pinctrl-0 = <&i2c1_0_sda_scl_gp87_90>; + pinctrl-names = "default"; + + bc12_port0: pi3usb9201@5f { + compatible = "pericom,pi3usb9201"; + status = "okay"; + reg = <0x5f>; + irq = <&int_usb_c0_bc12>; + }; + + tcpc_port0: anx7447-tcpc@2c { + compatible = "analogix,anx7447-tcpc"; + status = "okay"; + reg = <0x2c>; + tcpc-flags = <( + TCPC_FLAGS_VBUS_MONITOR | + TCPC_FLAGS_ALERT_OD | + TCPC_FLAGS_CONTROL_VCONN | + TCPC_FLAGS_CONTROL_FRS)>; + }; + + ppc_port0: nx20p348x@72 { + compatible = "nxp,nx20p348x"; + status = "okay"; + reg = <0x72>; + }; +}; + +&i2c_ctrl1 { + status = "okay"; +}; + +&i2c2_0 { + label = "I2C_USB_C1"; + status = "okay"; + clock-frequency = <I2C_BITRATE_FAST_PLUS>; + pinctrl-0 = <&i2c2_0_sda_scl_gp91_92>; + pinctrl-names = "default"; + + bc12_port1: rt1718s-bc12@40 { + compatible = "richtek,rt1718s-bc12"; + status = "okay"; + reg = <0x40>; + }; + + tcpc_port1: rt1718s-tcpc@40 { + compatible = "richtek,rt1718s-tcpc"; + reg = <0x40>; + tcpc-flags = <( + TCPC_FLAGS_ALERT_OD | + TCPC_FLAGS_CONTROL_VCONN | + TCPC_FLAGS_CONTROL_FRS)>; + }; + + ppc_port1: nx20p348x@72 { + compatible = "nxp,nx20p348x"; + status = "okay"; + reg = <0x72>; + }; + + ps8743_mux_1: ps8743-mux-1@10 { + compatible = "parade,ps8743"; + reg = <0x10>; + board-init = "ps8743_mux_1_board_init"; + }; +}; + +&i2c_ctrl2 { + status = "okay"; +}; + +&i2c3_0 { + label = "I2C_PWR_CBI"; + status = "okay"; + clock-frequency = <I2C_BITRATE_FAST>; + pinctrl-0 = <&i2c3_0_sda_scl_gpd0_d1>; + pinctrl-names = "default"; + + charger: isl923x@9 { + compatible = "intersil,isl923x"; + status = "okay"; + reg = <0x9>; + }; + + cbi_eeprom: eeprom@50 { + compatible = "atmel,at24"; + reg = <0x50>; + size = <2048>; + pagesize = <16>; + address-width = <8>; + timeout = <5>; + }; +}; + +&i2c_ctrl3 { + status = "okay"; +}; + +&i2c5_0 { + label = "I2C_BATTERY"; + status = "okay"; + clock-frequency = <I2C_BITRATE_STANDARD>; + pinctrl-0 = <&i2c5_0_sda_scl_gp33_36>; + pinctrl-names = "default"; +}; + +&i2c_ctrl5 { + status = "okay"; +}; diff --git a/zephyr/projects/corsola/i2c_krabby.dts b/zephyr/projects/corsola/i2c_krabby.dts new file mode 100644 index 0000000000..a5dc03b655 --- /dev/null +++ b/zephyr/projects/corsola/i2c_krabby.dts @@ -0,0 +1,22 @@ +/* Copyright 2021 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "i2c_krabby_tentacruel.dtsi" + +&i2c0 { + charger: rt9490@53 { + compatible = "richtek,rt9490"; + status = "okay"; + reg = <0x53>; + }; +}; + +&i2c4 { + tusb1064_mux_1: tusb1064-mux-1@44 { + compatible = "ti,tusb1064"; + reg = <0x44>; + board-init = "tusb1064_mux_1_board_init"; + }; +}; diff --git a/zephyr/projects/corsola/i2c_krabby_tentacruel.dtsi b/zephyr/projects/corsola/i2c_krabby_tentacruel.dtsi new file mode 100644 index 0000000000..6fd153e1fa --- /dev/null +++ b/zephyr/projects/corsola/i2c_krabby_tentacruel.dtsi @@ -0,0 +1,138 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + named-i2c-ports { + compatible = "named-i2c-ports"; + + battery { + i2c-port = <&i2c1>; + remote-port = <1>; + enum-names = "I2C_PORT_BATTERY", + "I2C_PORT_VIRTUAL_BATTERY"; + }; + i2c_charger: charger { + i2c-port = <&i2c0>; + enum-names = "I2C_PORT_CHARGER", + "I2C_PORT_EEPROM"; + }; + i2c_sensor: sensor { + i2c-port = <&i2c3>; + enum-names = "I2C_PORT_SENSOR"; + }; + i2c_usb_c0: usb-c0 { + i2c-port = <&i2c2>; + enum-names = "I2C_PORT_USB_C0", + "I2C_PORT_USB_MUX0"; + }; + i2c_usb_c1: usb-c1 { + i2c-port = <&i2c4>; + enum-names = "I2C_PORT_USB_C1", + "I2C_PORT_USB_MUX1"; + }; + }; + +}; + +&pinctrl { + i2c3_clk_gpf2_sleep: i2c3_clk_gpf2_sleep { + pinmuxs = <&pinctrlf 2 IT8XXX2_ALT_DEFAULT>; + }; + i2c3_data_gpf3_sleep: i2c3_data_gpf3_sleep { + pinmuxs = <&pinctrlf 3 IT8XXX2_ALT_DEFAULT>; + }; +}; + +&i2c0 { + /* EC_I2C_PWR_CBI */ + label = "I2C_PWR_CBI"; + status = "okay"; + clock-frequency = <I2C_BITRATE_FAST>; + pinctrl-0 = <&i2c0_clk_gpb3_default + &i2c0_data_gpb4_default>; + pinctrl-names = "default"; + + cbi_eeprom: eeprom@50 { + compatible = "atmel,at24"; + reg = <0x50>; + size = <2048>; + pagesize = <16>; + address-width = <8>; + timeout = <5>; + }; + + bc12_port1: rt9490-bc12@53 { + compatible = "richtek,rt9490-bc12"; + status = "okay"; + reg = <0x53>; + irq = <&int_usb_c1_bc12_charger>; + }; +}; + +&i2c1 { + /* EC_I2C_BATTERY */ + label = "I2C_BATTERY"; + status = "okay"; + clock-frequency = <50000>; + pinctrl-0 = <&i2c1_clk_gpc1_default + &i2c1_data_gpc2_default>; + pinctrl-names = "default"; + fifo-enable; +}; + +&i2c2 { + /* EC_I2C_USB_C0 */ + label = "I2C_USB_C0"; + status = "okay"; + clock-frequency = <I2C_BITRATE_FAST>; + pinctrl-0 = <&i2c2_clk_gpf6_default + &i2c2_data_gpf7_default>; + pinctrl-names = "default"; + /delete-property/ fifo-enable; + + bc12_ppc_port0: rt1739@70 { + compatible = "richtek,rt1739"; + status = "okay"; + reg = <0x70>; + }; + + it5205_mux_0: it5205-mux-0@48 { + compatible = "ite,it5205"; + reg = <0x48>; + }; +}; + +&i2c3 { + /* EC_I2C_SENSOR */ + label = "I2C_SENSOR"; + status = "okay"; + clock-frequency = <I2C_BITRATE_FAST>; + scl-gpios = <&gpiof 2 0>; + sda-gpios = <&gpiof 3 0>; + pinctrl-0 = <&i2c3_clk_gpf2_default + &i2c3_data_gpf3_default>; + pinctrl-1 = <&i2c3_clk_gpf2_sleep + &i2c3_data_gpf3_sleep>; + pinctrl-names = "default", "sleep"; + prescale-scl-low = <1>; +}; + +&i2c4 { + /* EC_I2C_USB_C1 */ + label = "I2C_USB_C1"; + status = "okay"; + clock-frequency = <I2C_BITRATE_FAST>; + pinctrl-0 = <&i2c4_clk_gpe0_default + &i2c4_data_gpe7_default>; + pinctrl-names = "default"; + prescale-scl-low = <1>; + + ppc_port1: syv682x@40 { + compatible = "silergy,syv682x"; + status = "okay"; + reg = <0x40>; + frs_en_gpio = <&gpio_ec_x_gpio1>; + }; +}; diff --git a/zephyr/projects/corsola/i2c_magikarp.dts b/zephyr/projects/corsola/i2c_magikarp.dts new file mode 100644 index 0000000000..fbf5ed6337 --- /dev/null +++ b/zephyr/projects/corsola/i2c_magikarp.dts @@ -0,0 +1,36 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "i2c_krabby_tentacruel.dtsi" + +&i2c0 { + charger: rt9490@53 { + compatible = "richtek,rt9490"; + status = "okay"; + reg = <0x53>; + }; +}; + +&i2c2 { + bc12_port0: pi3usb9201@5f { + compatible = "pericom,pi3usb9201"; + status = "okay"; + reg = <0x5f>; + irq = <&int_usb_c0_bc12>; + }; + ppc_port0: syv682x@40 { + compatible = "silergy,syv682x"; + status = "okay"; + reg = <0x40>; + frs_en_gpio = <&usb_c0_frs_en>; + }; +}; + +&i2c4 { + ps8743_mux_1: ps8743-mux-1@10 { + compatible = "parade,ps8743"; + reg = <0x10>; + }; +}; diff --git a/zephyr/projects/corsola/i2c_tentacruel.dts b/zephyr/projects/corsola/i2c_tentacruel.dts new file mode 100644 index 0000000000..a635adcf5c --- /dev/null +++ b/zephyr/projects/corsola/i2c_tentacruel.dts @@ -0,0 +1,38 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "i2c_krabby_tentacruel.dtsi" + +&i2c0 { + charger: rt9490@53 { + compatible = "richtek,rt9490"; + status = "okay"; + reg = <0x53>; + thermistor = <&thermistor_rt9490>; + }; +}; + +&i2c2 { + bc12_port0: pi3usb9201@5f { + compatible = "pericom,pi3usb9201"; + status = "okay"; + reg = <0x5f>; + irq = <&int_usb_c0_bc12>; + }; + ppc_port0: syv682x@40 { + compatible = "silergy,syv682x"; + status = "okay"; + reg = <0x40>; + frs_en_gpio = <&usb_c0_frs_en>; + }; +}; + +&i2c4 { + ps8743_mux_1: ps8743-mux-1@10 { + compatible = "parade,ps8743"; + reg = <0x10>; + board-init = "ps8743_eq_c1_setting"; + }; +}; diff --git a/zephyr/projects/corsola/include/baseboard_usbc_config.h b/zephyr/projects/corsola/include/baseboard_usbc_config.h new file mode 100644 index 0000000000..66610fec5e --- /dev/null +++ b/zephyr/projects/corsola/include/baseboard_usbc_config.h @@ -0,0 +1,39 @@ +/* Copyright 2021 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Corsola daughter board detection */ + +#ifndef __CROS_EC_BASEBOARD_USBC_CONFIG_H +#define __CROS_EC_BASEBOARD_USBC_CONFIG_H + +#include "gpio.h" + +#ifdef CONFIG_PLATFORM_EC_USB_PD_TCPM_RT1718S +#define GPIO_EN_USB_C1_SINK RT1718S_GPIO1 +#define GPIO_EN_USB_C1_SOURCE RT1718S_GPIO2 +#define GPIO_EN_USB_C1_FRS RT1718S_GPIO3 +#endif + +void ppc_interrupt(enum gpio_signal signal); +void ccd_interrupt(enum gpio_signal signal); + +/* USB-A ports */ +enum usba_port { USBA_PORT_A0 = 0, USBA_PORT_COUNT }; + +/* USB-C ports */ +enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT }; +BUILD_ASSERT(USBC_PORT_COUNT == CONFIG_USB_PD_PORT_MAX_COUNT); + +/** + * Is the port fine to be muxed its DisplayPort lines? + * + * Only one port can be muxed to DisplayPort at a time. + * + * @param port Port number of TCPC. + * @return 1 is fine; 0 is bad as other port is already muxed; + */ +int corsola_is_dp_muxable(int port); + +#endif /* __CROS_EC_BASEBOARD_USBC_CONFIG_H */ diff --git a/zephyr/projects/corsola/include/variant_db_detection.h b/zephyr/projects/corsola/include/variant_db_detection.h new file mode 100644 index 0000000000..285ff327f2 --- /dev/null +++ b/zephyr/projects/corsola/include/variant_db_detection.h @@ -0,0 +1,33 @@ +/* Copyright 2021 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Corsola daughter board detection */ + +#ifndef __CROS_EC_CORSOLA_DB_DETECTION_H +#define __CROS_EC_CORSOLA_DB_DETECTION_H + +enum corsola_db_type { + CORSOLA_DB_UNINIT = -1, + CORSOLA_DB_NONE, + CORSOLA_DB_TYPEC, + CORSOLA_DB_HDMI, + CORSOLA_DB_COUNT, +}; + +#ifdef CONFIG_VARIANT_CORSOLA_DB_DETECTION +/* + * Get the connected daughterboard type. + * + * @return The daughterboard type. + */ +enum corsola_db_type corsola_get_db_type(void); +#else +inline enum corsola_db_type corsola_get_db_type(void) +{ + return CORSOLA_DB_NONE; +}; +#endif /* CONFIG_VARIANT_CORSOLA_DB_DETECTION */ + +#endif /* __CROS_EC_CORSOLA_DB_DETECTION_H */ diff --git a/zephyr/projects/corsola/interrupts_kingler.dts b/zephyr/projects/corsola/interrupts_kingler.dts new file mode 100644 index 0000000000..f3da785a60 --- /dev/null +++ b/zephyr/projects/corsola/interrupts_kingler.dts @@ -0,0 +1,114 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* + * Kingler and Steelix use the same dts, take care of this when modify it. + */ + +/ { + aliases { + int-wp = &int_wp; + }; + + gpio-interrupts { + compatible = "cros-ec,gpio-interrupts"; + + int_power_button: power_button { + irq-pin = <&gpio_gsc_ec_pwr_btn_odl>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "power_button_interrupt"; + }; + int_volume_up: volume_up { + irq-pin = <&gpio_ec_volup_btn_odl>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "button_interrupt"; + }; + int_volume_down: volume_down { + irq-pin = <&gpio_ec_voldn_btn_odl>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "button_interrupt"; + }; + int_lid_open: lid_open { + irq-pin = <&gpio_lid_open>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "lid_interrupt"; + }; + int_warm_rst: warm_rst { + irq-pin = <&ap_ec_warm_rst_req>; + flags = <GPIO_INT_EDGE_RISING>; + handler = "chipset_reset_request_interrupt"; + }; + int_ap_in_sleep: ap_in_sleep { + irq-pin = <&ap_in_sleep_l>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "power_signal_interrupt"; + }; + int_ap_in_rst: ap_in_rst { + irq-pin = <&ap_sysrst_odl_r>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "power_signal_interrupt"; + }; + int_ap_wdtrst: ap_wdtrst { + irq-pin = <&ap_ec_wdtrst_l>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "chipset_watchdog_interrupt"; + }; + int_ac_present: ac_present { + irq-pin = <&gpio_acok_od>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "extpower_interrupt"; + }; + int_usba: usba { + irq-pin = <&gpio_ap_xhci_init_done>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "usb_a0_interrupt"; + }; + int_wp: wp { + irq-pin = <&gpio_ec_wp_l>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "switch_interrupt"; + }; + int_usb_c0_tcpc: usb_c0_tcpc { + irq-pin = <&gpio_usb_c0_tcpc_int_odl>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "tcpc_alert_event"; + }; + int_usb_c1_tcpc: usb_c1_tcpc { + irq-pin = <&gpio_usb_c1_tcpc_int_odl>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "tcpc_alert_event"; + }; + int_usb_c0_ppc: usb_c0_ppc { + irq-pin = <&gpio_usb_c0_ppc_int_odl>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "ppc_interrupt"; + }; + int_usb_c0_bc12: usb_c0_bc12 { + irq-pin = <&gpio_usb_c0_bc12_int_odl>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "bc12_interrupt"; + }; + int_x_ec_gpio2: x_ec_gpio2 { + irq-pin = <&gpio_x_ec_gpio2>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "x_ec_interrupt"; + }; + int_base_imu: base_imu { + irq-pin = <&base_imu_int_l>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "bmi3xx_interrupt"; + }; + int_tablet_mode: tablet_mode { + irq-pin = <&gpio_tablet_mode_l>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "gmr_tablet_switch_isr"; + }; + int_ccd_mode_odl: ccd-mode-odl { + irq-pin = <&gpio_ccd_mode_odl>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "ccd_interrupt"; + }; + }; +}; diff --git a/zephyr/projects/corsola/interrupts_krabby.dts b/zephyr/projects/corsola/interrupts_krabby.dts new file mode 100644 index 0000000000..3caf4660ae --- /dev/null +++ b/zephyr/projects/corsola/interrupts_krabby.dts @@ -0,0 +1,110 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + aliases { + int-wp = &int_wp; + }; + + gpio-interrupts { + compatible = "cros-ec,gpio-interrupts"; + + int_power_button: power_button { + irq-pin = <&power_button_l>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "power_button_interrupt"; + }; + int_volume_up: volume_up { + irq-pin = <&volume_up_l>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "button_interrupt"; + }; + int_volume_down: volume_down { + irq-pin = <&volume_down_l>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "button_interrupt"; + }; + int_lid_open: lid_open { + irq-pin = <&lid_open>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "lid_interrupt"; + }; + int_warm_rst: warm_rst { + irq-pin = <&ap_ec_warm_rst_req>; + flags = <GPIO_INT_EDGE_RISING>; + handler = "chipset_reset_request_interrupt"; + }; + int_ap_in_sleep: ap_in_sleep { + irq-pin = <&ap_in_sleep_l>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "power_signal_interrupt"; + }; + int_ap_in_rst: ap_in_rst { + irq-pin = <&ap_sysrst_odl_r>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "power_signal_interrupt"; + }; + int_ap_wdtrst: ap_wdtrst { + irq-pin = <&ap_ec_wdtrst_l>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "chipset_watchdog_interrupt"; + }; + int_tablet_mode: tablet_mode { + irq-pin = <&tablet_mode_l>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "gmr_tablet_switch_isr"; + }; + int_base_imu: base_imu { + irq-pin = <&base_imu_int_l>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "icm42607_interrupt"; + }; + int_lid_imu: lid_imu { + irq-pin = <&lid_accel_int_l>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "lis2dw12_interrupt"; + }; + int_ac_present: ac_present { + irq-pin = <&ac_present>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "extpower_interrupt"; + }; + int_usba: usba { + irq-pin = <&gpio_ap_xhci_init_done>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "usb_a0_interrupt"; + }; + int_wp: wp { + irq-pin = <&ec_flash_wp_odl>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "switch_interrupt"; + }; + int_spi0_cs: spi0_cs { + irq-pin = <&spi0_cs>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "spi_event"; + }; + int_x_ec_gpio2: x_ec_gpio2 { + irq-pin = <&gpio_x_ec_gpio2>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "x_ec_interrupt"; + }; + int_usb_c0_ppc_bc12: usb_c0_ppc_bc12 { + irq-pin = <&usb_c0_ppc_bc12_int_odl>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "c0_bc12_interrupt"; + }; + int_usb_c1_bc12_charger: usb_c1_bc12_charger { + irq-pin = <&usb_c1_bc12_charger_int_odl>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "rt9490_bc12_dt_interrupt"; + }; + int_ccd_mode_odl: ccd-mode-odl { + irq-pin = <&gpio_ccd_mode_odl>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "ccd_interrupt"; + }; + }; +}; diff --git a/zephyr/projects/corsola/interrupts_magikarp.dts b/zephyr/projects/corsola/interrupts_magikarp.dts new file mode 100644 index 0000000000..4f4e0ba100 --- /dev/null +++ b/zephyr/projects/corsola/interrupts_magikarp.dts @@ -0,0 +1,115 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + aliases { + int-wp = &int_wp; + }; + + gpio-interrupts { + compatible = "cros-ec,gpio-interrupts"; + + int_power_button: power_button { + irq-pin = <&power_button_l>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "power_button_interrupt"; + }; + int_volume_up: volume_up { + irq-pin = <&volume_up_l>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "button_interrupt"; + }; + int_volume_down: volume_down { + irq-pin = <&volume_down_l>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "button_interrupt"; + }; + int_lid_open: lid_open { + irq-pin = <&lid_open>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "lid_interrupt"; + }; + int_warm_rst: warm_rst { + irq-pin = <&ap_ec_warm_rst_req>; + flags = <GPIO_INT_EDGE_RISING>; + handler = "chipset_reset_request_interrupt"; + }; + int_ap_in_sleep: ap_in_sleep { + irq-pin = <&ap_in_sleep_l>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "power_signal_interrupt"; + }; + int_ap_in_rst: ap_in_rst { + irq-pin = <&ap_sysrst_odl_r>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "power_signal_interrupt"; + }; + int_ap_wdtrst: ap_wdtrst { + irq-pin = <&ap_ec_wdtrst_l>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "chipset_watchdog_interrupt"; + }; + int_tablet_mode: tablet_mode { + irq-pin = <&tablet_mode_l>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "gmr_tablet_switch_isr"; + }; + int_base_imu: base_imu { + irq-pin = <&base_imu_int_l>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "motion_interrupt"; + }; + int_lid_imu: lid_imu { + irq-pin = <&lid_accel_int_l>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "lis2dw12_interrupt"; + }; + int_ac_present: ac_present { + irq-pin = <&ac_present>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "extpower_interrupt"; + }; + int_usba: usba { + irq-pin = <&gpio_ap_xhci_init_done>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "usb_a0_interrupt"; + }; + int_wp: wp { + irq-pin = <&ec_flash_wp_odl>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "switch_interrupt"; + }; + int_spi0_cs: spi0_cs { + irq-pin = <&spi0_cs>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "spi_event"; + }; + int_x_ec_gpio2: x_ec_gpio2 { + irq-pin = <&gpio_x_ec_gpio2>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "x_ec_interrupt"; + }; + int_usb_c0_bc12: usb_c0_bc12 { + irq-pin = <&usb_c0_bc12_int_odl>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "bc12_interrupt"; + }; + int_usb_c0_ppc: usb_c0_ppc { + irq-pin = <&usb_c0_ppc_int_odl>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "ppc_interrupt"; + }; + int_usb_c1_bc12_charger: usb_c1_bc12_charger { + irq-pin = <&usb_c1_bc12_charger_int_odl>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "rt9490_bc12_dt_interrupt"; + }; + int_ccd_mode_odl: ccd-mode-odl { + irq-pin = <&gpio_ccd_mode_odl>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "ccd_interrupt"; + }; + }; +}; diff --git a/zephyr/projects/corsola/interrupts_steelix.dts b/zephyr/projects/corsola/interrupts_steelix.dts new file mode 100644 index 0000000000..816beb95f4 --- /dev/null +++ b/zephyr/projects/corsola/interrupts_steelix.dts @@ -0,0 +1,10 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +&int_base_imu { + irq-pin = <&base_imu_int_l>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "motion_interrupt"; +}; diff --git a/zephyr/projects/corsola/interrupts_tentacruel.dts b/zephyr/projects/corsola/interrupts_tentacruel.dts new file mode 100644 index 0000000000..11229daf36 --- /dev/null +++ b/zephyr/projects/corsola/interrupts_tentacruel.dts @@ -0,0 +1,115 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + aliases { + int-wp = &int_wp; + }; + + gpio-interrupts { + compatible = "cros-ec,gpio-interrupts"; + + int_power_button: power_button { + irq-pin = <&power_button_l>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "power_button_interrupt"; + }; + int_volume_up: volume_up { + irq-pin = <&volume_up_l>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "button_interrupt"; + }; + int_volume_down: volume_down { + irq-pin = <&volume_down_l>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "button_interrupt"; + }; + int_lid_open: lid_open { + irq-pin = <&lid_open>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "lid_interrupt"; + }; + int_warm_rst: warm_rst { + irq-pin = <&ap_ec_warm_rst_req>; + flags = <GPIO_INT_EDGE_RISING>; + handler = "chipset_reset_request_interrupt"; + }; + int_ap_in_sleep: ap_in_sleep { + irq-pin = <&ap_in_sleep_l>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "power_signal_interrupt"; + }; + int_ap_in_rst: ap_in_rst { + irq-pin = <&ap_sysrst_odl_r>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "power_signal_interrupt"; + }; + int_ap_wdtrst: ap_wdtrst { + irq-pin = <&ap_ec_wdtrst_l>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "chipset_watchdog_interrupt"; + }; + int_tablet_mode: tablet_mode { + irq-pin = <&tablet_mode_l>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "gmr_tablet_switch_isr"; + }; + int_base_imu: base_imu { + irq-pin = <&base_imu_int_l>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "motion_interrupt"; + }; + int_lid_imu: lid_imu { + irq-pin = <&lid_accel_int_l>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "lis2dw12_interrupt"; + }; + int_ac_present: ac_present { + irq-pin = <&ac_present>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "extpower_interrupt"; + }; + int_usba: usba { + irq-pin = <&gpio_ap_xhci_init_done>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "usb_a0_interrupt"; + }; + int_wp: wp { + irq-pin = <&ec_flash_wp_odl>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "switch_interrupt"; + }; + int_spi0_cs: spi0_cs { + irq-pin = <&spi0_cs>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "spi_event"; + }; + int_x_ec_gpio2: x_ec_gpio2 { + irq-pin = <&gpio_x_ec_gpio2>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "x_ec_interrupt"; + }; + int_usb_c0_ppc: usb_c0_ppc { + irq-pin = <&usb_c0_ppc_int_odl>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "ppc_interrupt"; + }; + int_usb_c0_bc12: usb_c0_bc12 { + irq-pin = <&usb_c0_bc12_int_odl>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "bc12_interrupt"; + }; + int_usb_c1_bc12_charger: usb_c1_bc12_charger { + irq-pin = <&usb_c1_bc12_charger_int_odl>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "rt9490_bc12_dt_interrupt"; + }; + int_ccd_mode_odl: ccd-mode-odl { + irq-pin = <&gpio_ccd_mode_odl>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "ccd_interrupt"; + }; + }; +}; diff --git a/zephyr/projects/corsola/keyboard_steelix.dts b/zephyr/projects/corsola/keyboard_steelix.dts new file mode 100644 index 0000000000..9a0dca3e05 --- /dev/null +++ b/zephyr/projects/corsola/keyboard_steelix.dts @@ -0,0 +1,29 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + cros-keyscan { + compatible = "cros-keyscan"; + + debounce-down = <15000>; + debounce-up = <15000>; + + actual-key-mask = < + 0x1c /* C0 */ + 0xff /* C1 */ + 0xff /* C2 */ + 0xff /* C3 */ + 0xff /* C4 */ + 0xf5 /* C5 */ + 0xff /* C6 */ + 0xa4 /* C7 */ + 0xff /* C8 */ + 0xfe /* C9 */ + 0x55 /* C10 */ + 0xfa /* C11 */ + 0xca /* C12 */ + >; + }; +}; diff --git a/zephyr/projects/corsola/led_it81202_base.dtsi b/zephyr/projects/corsola/led_it81202_base.dtsi new file mode 100644 index 0000000000..dce7bb4f95 --- /dev/null +++ b/zephyr/projects/corsola/led_it81202_base.dtsi @@ -0,0 +1,184 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ +#include <dt-bindings/battery.h> + +/ { + led_colors: led-colors { + compatible = "cros-ec,led-policy"; + + bat-power-state-charge { + charge-state = "PWR_STATE_CHARGE"; + + color-0 { + led-color = <&color_battery_amber>; + }; + }; + + bat-power-state-near-full { + charge-state = "PWR_STATE_CHARGE_NEAR_FULL"; + + color-0 { + led-color = <&color_battery_white>; + }; + }; + + bat-power-state-discharge { + charge-state = "PWR_STATE_DISCHARGE"; + + color-0 { + led-color = <&color_battery_off>; + }; + }; + + bat-power-state-discharge-s0-bat-low { + charge-state = "PWR_STATE_DISCHARGE"; + chipset-state = "POWER_S0"; + batt-lvl = <BATTERY_LEVEL_EMPTY BATTERY_LEVEL_LOW>; + + color-0 { + led-color = <&color_battery_amber>; + period-ms = <1000>; + }; + + color-1 { + led-color = <&color_battery_off>; + period-ms = <3000>; + }; + }; + + bat-power-state-error { + charge-state = "PWR_STATE_ERROR"; + + color-0 { + led-color = <&color_battery_amber>; + period-ms = <1000>; + }; + + color-1 { + led-color = <&color_battery_off>; + period-ms = <1000>; + }; + }; + + pwr-power-state-off { + color-0 { + led-color = <&color_power_off>; + }; + }; + + pwr-power-state-on { + chipset-state = "POWER_S0"; + + color-0 { + led-color = <&color_power_white>; + }; + }; + + pwr-power-state-s3 { + chipset-state = "POWER_S3"; + + color-0 { + led-color = <&color_power_white>; + period-ms = <1000>; + }; + + color-1 { + led-color = <&color_power_off>; + period-ms = <3000>; + }; + }; + }; + + pwmleds { + compatible = "cros-ec,pwm-pin-config"; + + /* NOTE: &pwm number needs same with channel number */ + led_power_white: ec_led1_odl { + #led-pin-cells = <1>; + pwms = <&pwm0 + PWM_CHANNEL_0 + PWM_HZ(324) + PWM_POLARITY_INVERTED>; + }; + led_battery_amber: ec_led2_odl { + #led-pin-cells = <1>; + pwms = <&pwm1 + PWM_CHANNEL_1 + PWM_HZ(324) + PWM_POLARITY_INVERTED>; + }; + led_battery_white: ec_led3_odl { + #led-pin-cells = <1>; + pwms = <&pwm2 + PWM_CHANNEL_2 + PWM_HZ(324) + PWM_POLARITY_INVERTED>; + }; + }; + + pwm-led-pins { + compatible = "cros-ec,pwm-led-pins"; + + color_power_off: color-power-off { + led-color = "LED_OFF"; + led-id = "EC_LED_ID_POWER_LED"; + led-pins = <&led_power_white 0>; + }; + + color_power_white: color-power-white { + led-color = "LED_WHITE"; + br-color = "EC_LED_COLOR_WHITE"; + led-id = "EC_LED_ID_POWER_LED"; + led-pins = <&led_power_white 100>; + }; + + color_battery_off: color-battery-off { + led-color = "LED_OFF"; + led-id = "EC_LED_ID_BATTERY_LED"; + led-pins = <&led_battery_amber 0>, + <&led_battery_white 0>; + }; + + color_battery_amber: color-battery-amber { + led-color = "LED_AMBER"; + br-color = "EC_LED_COLOR_AMBER"; + led-id = "EC_LED_ID_BATTERY_LED"; + led-pins = <&led_battery_amber 100>, + <&led_battery_white 0>; + }; + + color_battery_white: color-battery-white { + led-color = "LED_WHITE"; + br-color = "EC_LED_COLOR_WHITE"; + led-id = "EC_LED_ID_BATTERY_LED"; + led-pins = <&led_battery_amber 0>, + <&led_battery_white 100>; + }; + }; +}; + +/* LED1 */ +&pwm0 { + status = "okay"; + prescaler-cx = <PWM_PRESCALER_C4>; + pinctrl-0 = <&pwm0_gpa0_default>; + pinctrl-names = "default"; +}; + +/* LED2 */ +&pwm1 { + status = "okay"; + prescaler-cx = <PWM_PRESCALER_C4>; + pinctrl-0 = <&pwm1_gpa1_default>; + pinctrl-names = "default"; +}; + +/* LED3 */ +&pwm2 { + status = "okay"; + prescaler-cx = <PWM_PRESCALER_C4>; + pinctrl-0 = <&pwm2_gpa2_default>; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/corsola/led_kingler.dts b/zephyr/projects/corsola/led_kingler.dts new file mode 100644 index 0000000000..92f6c4d4fe --- /dev/null +++ b/zephyr/projects/corsola/led_kingler.dts @@ -0,0 +1,71 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + pwmleds { + compatible = "pwm-leds"; + pwm_led0: pwm_led_0 { + pwms = <&pwm0 0 PWM_HZ(100) PWM_POLARITY_INVERTED + &pwm1 0 PWM_HZ(100) PWM_POLARITY_INVERTED + &pwm2 0 PWM_HZ(100) PWM_POLARITY_INVERTED>; + }; + }; + + cros-pwmleds { + compatible = "cros-ec,pwm-leds"; + + leds = <&pwm_led0>; + + color-map-red = <100 0 0>; + color-map-green = < 0 100 0>; + color-map-amber = <100 20 0>; + + brightness-range = <255 255 0 0 0 255>; + + #address-cells = <1>; + #size-cells = <0>; + + pwm_led_0@0 { + reg = <0>; + ec-led-name = "EC_LED_ID_BATTERY_LED"; + }; + }; +}; + +/* Red LED */ +&pwm0_gpc3 { + drive-open-drain; +}; + +&pwm0 { + status = "okay"; + clock-bus = "NPCX_CLOCK_BUS_LFCLK"; + pinctrl-0 = <&pwm0_gpc3>; + pinctrl-names = "default"; +}; + +/* Green LED */ +&pwm1_gpc2 { + drive-open-drain; +}; + +&pwm1 { + status = "okay"; + clock-bus = "NPCX_CLOCK_BUS_LFCLK"; + pinctrl-0 = <&pwm1_gpc2>; + pinctrl-names = "default"; +}; + +/* Blue LED */ +&pwm2_gpc4 { + drive-open-drain; +}; + +&pwm2 { + status = "okay"; + clock-bus = "NPCX_CLOCK_BUS_LFCLK"; + pinctrl-0 = <&pwm2_gpc4>; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/corsola/led_krabby.dts b/zephyr/projects/corsola/led_krabby.dts new file mode 100644 index 0000000000..b16bff3cac --- /dev/null +++ b/zephyr/projects/corsola/led_krabby.dts @@ -0,0 +1,5 @@ +/* Copyright 2021 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ +#include "led_it81202_base.dtsi" diff --git a/zephyr/projects/corsola/led_magikarp.dts b/zephyr/projects/corsola/led_magikarp.dts new file mode 100644 index 0000000000..0e2b0aca52 --- /dev/null +++ b/zephyr/projects/corsola/led_magikarp.dts @@ -0,0 +1,136 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ +#include "led_it81202_base.dtsi" + +/ { + led_colors: led-colors { + compatible = "cros-ec,led-policy"; + + /* Magikarp LED bat charge */ + bat-power-state-charge { + charge-state = "PWR_STATE_CHARGE"; + /* Battery percent range (>= Empty, <= 94%) */ + batt-lvl = <BATTERY_LEVEL_EMPTY + (BATTERY_LEVEL_NEAR_FULL - 3)>; + color-0 { + led-color = <&color_battery_amber>; + }; + }; + + bat-power-state-charge-near-full { + charge-state = "PWR_STATE_CHARGE"; + /* Battery percent range (>= 95%, <= Full) */ + batt-lvl = <(BATTERY_LEVEL_NEAR_FULL - 2) + BATTERY_LEVEL_FULL>; + color-0 { + led-color = <&color_battery_white>; + }; + }; + + /* Magikarp LED bat discharge */ + bat-power-state-discharge-s0 { + charge-state = "PWR_STATE_DISCHARGE"; + chipset-state = "POWER_S0"; + /* Battery percent range (>= 11%, <= Full) */ + batt-lvl = <(BATTERY_LEVEL_LOW + 1) BATTERY_LEVEL_FULL>; + + color-0 { + led-color = <&color_battery_white>; + }; + }; + + + bat-power-state-discharge-s0-bat-low { + charge-state = "PWR_STATE_DISCHARGE"; + chipset-state = "POWER_S0"; + /* Battery percent range (>= Empty, <= 10%) */ + batt-lvl = <BATTERY_LEVEL_EMPTY BATTERY_LEVEL_LOW>; + + color-0 { + led-color = <&color_battery_amber>; + period-ms = <1000>; + }; + + color-1 { + led-color = <&color_battery_off>; + period-ms = <3000>; + }; + }; + + bat-power-state-discharge-s3 { + charge-state = "PWR_STATE_DISCHARGE"; + chipset-state = "POWER_S3"; + + color-0 { + led-color = <&color_battery_white>; + period-ms = <1000>; + }; + + color-1 { + led-color = <&color_battery_off>; + period-ms = <3000>; + }; + }; + + bat-power-state-discharge-s5 { + charge-state = "PWR_STATE_DISCHARGE"; + chipset-state = "POWER_S5"; + color-0 { + led-color = <&color_battery_off>; + }; + }; + + /* Magikarp LED bat error */ + bat-power-state-error { + charge-state = "PWR_STATE_ERROR"; + chipset-state = "POWER_S0"; + + color-0 { + led-color = <&color_battery_amber>; + period-ms = <1000>; + }; + + color-1 { + led-color = <&color_battery_off>; + period-ms = <1000>; + }; + }; + + bat-power-state-error-s3 { + charge-state = "PWR_STATE_ERROR"; + chipset-state = "POWER_S3"; + + color-0 { + led-color = <&color_battery_white>; + period-ms = <1000>; + }; + + color-1 { + led-color = <&color_battery_off>; + period-ms = <3000>; + }; + }; + + bat-power-state-error-s5 { + charge-state = "PWR_STATE_ERROR"; + chipset-state = "POWER_S5"; + + color-0 { + led-color = <&color_battery_off>; + }; + }; + }; + + pwm-led-pins { + compatible = "cros-ec,pwm-led-pins"; + + /* Overwrite Power LED white to off */ + color_power_white: color-power-white { + led-color = "LED_WHITE"; + led-id = "EC_LED_ID_POWER_LED"; + led-pins = <&led_power_white 0>; + }; + }; +}; diff --git a/zephyr/projects/corsola/led_steelix.dts b/zephyr/projects/corsola/led_steelix.dts new file mode 100644 index 0000000000..6a25929327 --- /dev/null +++ b/zephyr/projects/corsola/led_steelix.dts @@ -0,0 +1,55 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + pwmleds { + compatible = "pwm-leds"; + led_battery_red: ec_led1_odl { + pwms = <&pwm0 0 PWM_HZ(100) PWM_POLARITY_INVERTED>; + }; + led_battery_green: ec_led2_odl { + pwms = <&pwm1 0 PWM_HZ(100) PWM_POLARITY_INVERTED>; + }; + led_power_white: ec_led3_odl { + pwms = <&pwm4 0 PWM_HZ(100) PWM_POLARITY_INVERTED>; + }; + }; +}; + +/* Red LED */ +&pwm0_gpc3 { + drive-open-drain; +}; + +&pwm0 { + status = "okay"; + clock-bus = "NPCX_CLOCK_BUS_LFCLK"; + pinctrl-0 = <&pwm0_gpc3>; + pinctrl-names = "default"; +}; + +/* Green LED */ +&pwm1_gpc2 { + drive-open-drain; +}; + +&pwm1 { + status = "okay"; + clock-bus = "NPCX_CLOCK_BUS_LFCLK"; + pinctrl-0 = <&pwm1_gpc2>; + pinctrl-names = "default"; +}; + +/* White LED */ +&pwm4_gpb6 { + drive-open-drain; +}; + +&pwm4 { + status = "okay"; + clock-bus = "NPCX_CLOCK_BUS_LFCLK"; + pinctrl-0 = <&pwm4_gpb6>; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/corsola/led_tentacruel.dts b/zephyr/projects/corsola/led_tentacruel.dts new file mode 100644 index 0000000000..5569a956f6 --- /dev/null +++ b/zephyr/projects/corsola/led_tentacruel.dts @@ -0,0 +1,118 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ +#include "led_it81202_base.dtsi" + +/ { + led_colors: led-colors { + compatible = "cros-ec,led-policy"; + + /* Tentacruel LED bat charge */ + bat-power-state-charge { + charge-state = "PWR_STATE_CHARGE"; + /* Battery percent range (>= Empty, <= 94%) */ + batt-lvl = <BATTERY_LEVEL_EMPTY + (BATTERY_LEVEL_NEAR_FULL - 3)>; + color-0 { + led-color = <&color_battery_amber>; + }; + }; + + bat-power-state-charge-near-full { + charge-state = "PWR_STATE_CHARGE"; + /* Battery percent range (>= 95%, <= Full) */ + batt-lvl = <(BATTERY_LEVEL_NEAR_FULL - 2) + BATTERY_LEVEL_FULL>; + color-0 { + led-color = <&color_battery_white>; + }; + }; + + /* Tentacruel LED bat discharge */ + bat-power-state-discharge { + charge-state = "PWR_STATE_DISCHARGE"; + chipset-state = "POWER_S0"; + /* Battery percent range (>= 11%, <= Full) */ + batt-lvl = <(BATTERY_LEVEL_LOW + 1) BATTERY_LEVEL_FULL>; + + color-0 { + led-color = <&color_battery_white>; + }; + }; + + bat-power-state-discharge-s3 { + charge-state = "PWR_STATE_DISCHARGE"; + chipset-state = "POWER_S3"; + + color-0 { + led-color = <&color_battery_white>; + period-ms = <1000>; + }; + + color-1 { + led-color = <&color_battery_off>; + period-ms = <3000>; + }; + }; + + bat-power-state-discharge-s5 { + charge-state = "PWR_STATE_DISCHARGE"; + chipset-state = "POWER_S5"; + color-0 { + led-color = <&color_battery_off>; + }; + }; + + /* Tentacruel LED bat error */ + bat-power-state-error { + charge-state = "PWR_STATE_ERROR"; + chipset-state = "POWER_S0"; + + color-0 { + led-color = <&color_battery_amber>; + period-ms = <1000>; + }; + + color-1 { + led-color = <&color_battery_off>; + period-ms = <1000>; + }; + }; + + bat-power-state-error-s3 { + charge-state = "PWR_STATE_ERROR"; + chipset-state = "POWER_S3"; + + color-0 { + led-color = <&color_battery_white>; + period-ms = <1000>; + }; + + color-1 { + led-color = <&color_battery_off>; + period-ms = <3000>; + }; + }; + + bat-power-state-error-s5 { + charge-state = "PWR_STATE_ERROR"; + chipset-state = "POWER_S5"; + + color-0 { + led-color = <&color_battery_off>; + }; + }; + }; + + pwm-led-pins { + compatible = "cros-ec,pwm-led-pins"; + + /* Overwrite Power LED white to off */ + color_power_white: color-power-white { + led-color = "LED_WHITE"; + led-id = "EC_LED_ID_POWER_LED"; + led-pins = <&led_power_white 0>; + }; + }; +}; diff --git a/zephyr/projects/corsola/motionsense_kingler.dts b/zephyr/projects/corsola/motionsense_kingler.dts new file mode 100644 index 0000000000..a7f674e01f --- /dev/null +++ b/zephyr/projects/corsola/motionsense_kingler.dts @@ -0,0 +1,150 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* + * Kingler and Steelix use the same dts, take care of this when modify it. + */ + +#include <dt-bindings/motionsense/utils.h> + +/ { + aliases { + /* + * motion sense's <>_INT_EVENT is handled + * by alias. Using the alias, each driver creates + * its own <>_INT_EVENT. + */ + bmi3xx-int = &base_accel; + }; + + /* + * Declare mutexes used by sensor drivers. + * A mutex node is used to create an instance of mutex_t. + * A mutex node is referenced by a sensor node if the + * corresponding sensor driver needs to use the + * instance of the mutex. + */ + motionsense-mutex { + compatible = "cros-ec,motionsense-mutex"; + lid_mutex: lid-mutex { + }; + base_mutex: base-mutex { + }; + }; + + /* Rotation matrix used by drivers. */ + motionsense-rotation-ref { + compatible = "cros-ec,motionsense-rotation-ref"; + lid_rot_ref: lid-rotation-ref { + mat33 = <0 (-1) 0 + (-1) 0 0 + 0 0 (-1)>; + }; + base_rot_ref: base-rotation-ref { + mat33 = <0 (-1) 0 + 1 0 0 + 0 0 1>; + }; + }; + + /* + * Driver specific data. A driver-specific data can be shared with + * different motion sensors while they are using the same driver. + * + * If a node's compatible starts with "cros-ec,accelgyro-", it is for + * a common structure defined in accelgyro.h. + * e.g) compatible = "cros-ec,accelgyro-als-drv-data" is for + * "struct als_drv_data_t" in accelgyro.h + */ + motionsense-sensor-data { + bma4xx_data: bma4xx-drv-data { + compatible = "cros-ec,drvdata-bma4xx"; + status = "okay"; + }; + bmi3xx_data: bmi3xx-drv-data { + compatible = "cros-ec,drvdata-bmi3xx"; + status = "okay"; + }; + }; + + /* + * List of motion sensors that creates motion_sensors array. + * The nodelabel "lid_accel" and "base_accel" are used to indicate + * motion sensor IDs for lid angle calculation. + */ + motionsense-sensor { + lid_accel: lid-accel { + compatible = "cros-ec,bma4xx"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_LID"; + mutex = <&lid_mutex>; + port = <&i2c_sensor>; + rot-standard-ref = <&lid_rot_ref>; + default-range = <2>; + drv-data = <&bma4xx_data>; + configs { + compatible = + "cros-ec,motionsense-sensor-config"; + ec-s0 { + odr = <(12500 | ROUND_UP_FLAG)>; + }; + ec-s3 { + odr = <(12500 | ROUND_UP_FLAG)>; + }; + }; + }; + + base_accel: base-accel { + compatible = "cros-ec,bmi3xx-accel"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_BASE"; + mutex = <&base_mutex>; + port = <&i2c_sensor>; + rot-standard-ref = <&base_rot_ref>; + drv-data = <&bmi3xx_data>; + configs { + compatible = + "cros-ec,motionsense-sensor-config"; + ec-s0 { + odr = <(12500 | ROUND_UP_FLAG)>; + ec-rate = <(100 * USEC_PER_MSEC)>; + }; + ec-s3 { + odr = <(12500 | ROUND_UP_FLAG)>; + ec-rate = <0>; + }; + }; + }; + + base_gyro: base-gyro { + compatible = "cros-ec,bmi3xx-gyro"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_BASE"; + mutex = <&base_mutex>; + port = <&i2c_sensor>; + rot-standard-ref = <&base_rot_ref>; + drv-data = <&bmi3xx_data>; + }; + + }; + + motionsense-sensor-info { + compatible = "cros-ec,motionsense-sensor-info"; + + /* + * list of GPIO interrupts that have to + * be enabled at initial stage + */ + sensor-irqs = <&int_base_imu>; + /* list of sensors in force mode */ + accel-force-mode-sensors = <&lid_accel>; + }; +}; diff --git a/zephyr/projects/corsola/motionsense_krabby.dts b/zephyr/projects/corsola/motionsense_krabby.dts new file mode 100644 index 0000000000..1c7d5b2df4 --- /dev/null +++ b/zephyr/projects/corsola/motionsense_krabby.dts @@ -0,0 +1,146 @@ +/* Copyright 2020 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <dt-bindings/motionsense/utils.h> + + +/ { + aliases { + /* + * motion sense's <>_INT_EVENT is handled + * by alias. Using the alias, each driver creates + * its own <>_INT_EVENT. + */ + icm42607-int = &base_accel; + lis2dw12-int = &lid_accel; + }; + + /* + * Declare mutexes used by sensor drivers. + * A mutex node is used to create an instance of mutex_t. + * A mutex node is referenced by a sensor node if the + * corresponding sensor driver needs to use the + * instance of the mutex. + */ + motionsense-mutex { + compatible = "cros-ec,motionsense-mutex"; + lid_mutex: lid-mutex { + }; + + base_mutex: icm42607-mutex { + }; + }; + + /* Rotation matrix used by drivers. */ + motionsense-rotation-ref { + compatible = "cros-ec,motionsense-rotation-ref"; + lid_rot_ref: lid-rotation-ref { + mat33 = <1 0 0 + 0 1 0 + 0 0 1>; + }; + + base_rot_ref: base-rotation-ref { + mat33 = <1 0 0 + 0 1 0 + 0 0 1>; + }; + }; + + /* + * Driver specific data. A driver-specific data can be shared with + * different motion sensors while they are using the same driver. + * + * If a node's compatible starts with "cros-ec,accelgyro-", it is for + * a common structure defined in accelgyro.h. + * e.g) compatible = "cros-ec,accelgyro-als-drv-data" is for + * "struct als_drv_data_t" in accelgyro.h + */ + motionsense-sensor-data { + icm42607_data: icm42607-drv-data { + compatible = "cros-ec,drvdata-icm42607"; + status = "okay"; + }; + + lis2dw12_data: lis2dw12-drv-data { + compatible = "cros-ec,drvdata-lis2dw12"; + status = "okay"; + }; + }; + + /* + * List of motion sensors that creates motion_sensors array. + * The nodelabel "lid_accel" and "base_accel" are used to indicate + * motion sensor IDs for lid angle calculation. + */ + motionsense-sensor { + lid_accel: lid-accel { + compatible = "cros-ec,lis2dw12"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_LID"; + mutex = <&lid_mutex>; + port = <&i2c_sensor>; + rot-standard-ref = <&lid_rot_ref>; + default-range = <2>; + drv-data = <&lis2dw12_data>; + configs { + compatible = + "cros-ec,motionsense-sensor-config"; + ec-s0 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + ec-s3 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + }; + }; + + base_accel: base-accel { + compatible = "cros-ec,icm42607-accel"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_BASE"; + mutex = <&base_mutex>; + port = <&i2c_sensor>; + rot-standard-ref = <&base_rot_ref>; + drv-data = <&icm42607_data>; + configs { + compatible = + "cros-ec,motionsense-sensor-config"; + ec-s0 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + ec-s3 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + }; + }; + + base_gyro: base-gyro { + compatible = "cros-ec,icm42607-gyro"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_BASE"; + mutex = <&base_mutex>; + port = <&i2c_sensor>; + rot-standard-ref = <&base_rot_ref>; + drv-data = <&icm42607_data>; + }; + }; + + motionsense-sensor-info { + compatible = "cros-ec,motionsense-sensor-info"; + + /* + * list of GPIO interrupts that have to + * be enabled at initial stage + */ + sensor-irqs = <&int_base_imu &int_lid_imu>; + }; +}; diff --git a/zephyr/projects/corsola/motionsense_magikarp.dts b/zephyr/projects/corsola/motionsense_magikarp.dts new file mode 100644 index 0000000000..92e73bd2c6 --- /dev/null +++ b/zephyr/projects/corsola/motionsense_magikarp.dts @@ -0,0 +1,199 @@ +/* Copyright 2020 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <dt-bindings/motionsense/utils.h> + + +/ { + aliases { + /* + * motion sense's <>_INT_EVENT is handled + * by alias. Using the alias, each driver creates + * its own <>_INT_EVENT. + */ + icm42607-int = &base_accel; + lis2dw12-int = &lid_accel; + bmi3xx-int = &base_accel; + }; + + /* + * Declare mutexes used by sensor drivers. + * A mutex node is used to create an instance of mutex_t. + * A mutex node is referenced by a sensor node if the + * corresponding sensor driver needs to use the + * instance of the mutex. + */ + motionsense-mutex { + compatible = "cros-ec,motionsense-mutex"; + lid_mutex: lid-mutex { + }; + + base_mutex: icm42607-mutex { + }; + + base_mutex_bmi323: bmi323-mutex { + }; + }; + + /* Rotation matrix used by drivers. */ + motionsense-rotation-ref { + compatible = "cros-ec,motionsense-rotation-ref"; + lid_rot_ref: lid-rotation-ref { + mat33 = <1 0 0 + 0 1 0 + 0 0 (-1)>; + }; + + base_rot_ref: base-rotation-ref { + mat33 = <1 0 0 + 0 1 0 + 0 0 1>; + }; + + base_rot_ref_bmi: base-rotation-ref-bmi { + mat33 = <0 1 0 + (-1) 0 0 + 0 0 1>; + }; + }; + + /* + * Driver specific data. A driver-specific data can be shared with + * different motion sensors while they are using the same driver. + * + * If a node's compatible starts with "cros-ec,accelgyro-", it is for + * a common structure defined in accelgyro.h. + * e.g) compatible = "cros-ec,accelgyro-als-drv-data" is for + * "struct als_drv_data_t" in accelgyro.h + */ + motionsense-sensor-data { + icm42607_data: icm42607-drv-data { + compatible = "cros-ec,drvdata-icm42607"; + status = "okay"; + }; + + lis2dw12_data: lis2dw12-drv-data { + compatible = "cros-ec,drvdata-lis2dw12"; + status = "okay"; + }; + + bmi323_data: bmi323-drv-data { + compatible = "cros-ec,drvdata-bmi3xx"; + status = "okay"; + }; + }; + + /* + * List of motion sensors that creates motion_sensors array. + * The nodelabel "lid_accel" and "base_accel" are used to indicate + * motion sensor IDs for lid angle calculation. + */ + motionsense-sensor { + lid_accel: lid-accel { + compatible = "cros-ec,lis2dw12"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_LID"; + mutex = <&lid_mutex>; + port = <&i2c_sensor>; + rot-standard-ref = <&lid_rot_ref>; + default-range = <2>; + drv-data = <&lis2dw12_data>; + configs { + compatible = + "cros-ec,motionsense-sensor-config"; + ec-s0 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + ec-s3 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + }; + }; + + base_accel: base-accel { + compatible = "cros-ec,icm42607-accel"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_BASE"; + mutex = <&base_mutex>; + port = <&i2c_sensor>; + rot-standard-ref = <&base_rot_ref>; + drv-data = <&icm42607_data>; + configs { + compatible = + "cros-ec,motionsense-sensor-config"; + ec-s0 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + ec-s3 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + }; + }; + + base_gyro: base-gyro { + compatible = "cros-ec,icm42607-gyro"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_BASE"; + mutex = <&base_mutex>; + port = <&i2c_sensor>; + rot-standard-ref = <&base_rot_ref>; + drv-data = <&icm42607_data>; + }; + }; + + motionsense-sensor-alt { + alt_base_accel: alt-base-accel { + compatible = "cros-ec,bmi3xx-accel"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_BASE"; + mutex = <&base_mutex_bmi323>; + port = <&i2c_sensor>; + rot-standard-ref = <&base_rot_ref_bmi>; + drv-data = <&bmi323_data>; + alternate-for = <&base_accel>; + configs { + compatible = + "cros-ec,motionsense-sensor-config"; + ec-s0 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + ec-s3 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + }; + }; + + alt_base_gyro: alt-base-gyro { + compatible = "cros-ec,bmi3xx-gyro"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_BASE"; + mutex = <&base_mutex_bmi323>; + port = <&i2c_sensor>; + rot-standard-ref = <&base_rot_ref_bmi>; + drv-data = <&bmi323_data>; + alternate-for = <&base_gyro>; + }; + }; + + motionsense-sensor-info { + compatible = "cros-ec,motionsense-sensor-info"; + + /* + * list of GPIO interrupts that have to + * be enabled at initial stage + */ + sensor-irqs = <&int_base_imu &int_lid_imu>; + }; +}; diff --git a/zephyr/projects/corsola/motionsense_steelix.dts b/zephyr/projects/corsola/motionsense_steelix.dts new file mode 100644 index 0000000000..df96fc2e42 --- /dev/null +++ b/zephyr/projects/corsola/motionsense_steelix.dts @@ -0,0 +1,133 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <dt-bindings/motionsense/utils.h> + +/* inherit the rot_ref from Kingler and overwrite it */ +&lid_rot_ref { + mat33 = <0 1 0 + 1 0 0 + 0 0 (-1)>; +}; + +&base_rot_ref { + mat33 = <1 0 0 + 0 (-1) 0 + 0 0 (-1)>; +}; + +/ { + aliases { + /* + * motion sense's <>_INT_EVENT is handled + * by alias. Using the alias, each driver creates + * its own <>_INT_EVENT. + */ + lsm6dsm-int = &base_accel; + }; + + /* Rotation matrix used by drivers. */ + motionsense-rotation-ref { + compatible = "cros-ec,motionsense-rotation-ref"; + base_rot_ref_lsm6dsm: base-rotation-ref-lsm6dsm { + mat33 = <0 1 0 + 1 0 0 + 0 0 (-1)>; + }; + }; + + /* + * Driver specific data. A driver-specific data can be shared with + * different motion sensors while they are using the same driver. + * + * If a node's compatible starts with "cros-ec,accelgyro-", it is for + * a common structure defined in accelgyro.h. + * e.g) compatible = "cros-ec,accelgyro-als-drv-data" is for + * "struct als_drv_data_t" in accelgyro.h + */ + motionsense-sensor-data { + lis2dw12_data: lis2dw12-drv-data { + compatible = "cros-ec,drvdata-lis2dw12"; + status = "okay"; + }; + lsm6dsm_data_accel: lsm6dsm-accel-drv-data { + compatible = "cros-ec,drvdata-lsm6dsm"; + status = "okay"; + }; + lsm6dsm_data_gyro: lsm6dsm-gyro-drv-data { + compatible = "cros-ec,drvdata-lsm6dsm"; + status = "okay"; + }; + }; + + motionsense-sensor-alt { + alt_lid_accel: alt-lid-accel { + compatible = "cros-ec,lis2dw12"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_LID"; + mutex = <&lid_mutex>; + port = <&i2c_sensor>; + rot-standard-ref = <&lid_rot_ref>; + default-range = <2>; + drv-data = <&lis2dw12_data>; + i2c-spi-addr-flags = "LIS2DWL_ADDR0_FLAGS"; + alternate-for = <&lid_accel>; + alternate-ssfc-indicator = <&lid_sensor_1>; + configs { + compatible = + "cros-ec,motionsense-sensor-config"; + ec-s0 { + odr = <(12500 | ROUND_UP_FLAG)>; + }; + ec-s3 { + odr = <(12500 | ROUND_UP_FLAG)>; + }; + }; + }; + + alt_base_accel: alt-base-accel { + compatible = "cros-ec,lsm6dsm-accel"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_BASE"; + mutex = <&base_mutex>; + port = <&i2c_sensor>; + rot-standard-ref = <&base_rot_ref_lsm6dsm>; + drv-data = <&lsm6dsm_data_accel>; + alternate-for = <&base_accel>; + alternate-ssfc-indicator = <&base_sensor_1>; + configs { + compatible = + "cros-ec,motionsense-sensor-config"; + ec-s0 { + odr = <(12500 | ROUND_UP_FLAG)>; + ec-rate = <(100 * USEC_PER_MSEC)>; + }; + ec-s3 { + odr = <(12500 | ROUND_UP_FLAG)>; + ec-rate = <0>; + }; + }; + }; + + alt_base_gyro: alt-base-gyro { + compatible = "cros-ec,lsm6dsm-gyro"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_BASE"; + mutex = <&base_mutex>; + port = <&i2c_sensor>; + rot-standard-ref = <&base_rot_ref_lsm6dsm>; + default-range = <(1000 | ROUND_UP_FLAG)>; /* dps */ + drv-data = <&lsm6dsm_data_gyro>; + alternate-for = <&base_gyro>; + alternate-ssfc-indicator = <&base_sensor_1>; + }; + }; +}; diff --git a/zephyr/projects/corsola/motionsense_tentacruel.dts b/zephyr/projects/corsola/motionsense_tentacruel.dts new file mode 100644 index 0000000000..68b2c023df --- /dev/null +++ b/zephyr/projects/corsola/motionsense_tentacruel.dts @@ -0,0 +1,199 @@ +/* Copyright 2020 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <dt-bindings/motionsense/utils.h> + + +/ { + aliases { + /* + * motion sense's <>_INT_EVENT is handled + * by alias. Using the alias, each driver creates + * its own <>_INT_EVENT. + */ + icm42607-int = &base_accel; + lis2dw12-int = &lid_accel; + bmi3xx-int = &base_accel; + }; + + /* + * Declare mutexes used by sensor drivers. + * A mutex node is used to create an instance of mutex_t. + * A mutex node is referenced by a sensor node if the + * corresponding sensor driver needs to use the + * instance of the mutex. + */ + motionsense-mutex { + compatible = "cros-ec,motionsense-mutex"; + lid_mutex: lid-mutex { + }; + + base_mutex: icm42607-mutex { + }; + + base_mutex_bmi323: bmi323-mutex { + }; + }; + + /* Rotation matrix used by drivers. */ + motionsense-rotation-ref { + compatible = "cros-ec,motionsense-rotation-ref"; + lid_rot_ref: lid-rotation-ref { + mat33 = <1 0 0 + 0 1 0 + 0 0 1>; + }; + + base_rot_ref: base-rotation-ref { + mat33 = <1 0 0 + 0 1 0 + 0 0 1>; + }; + + base_rot_ref_bmi: base-rotation-ref-bmi { + mat33 = <0 1 0 + (-1) 0 0 + 0 0 1>; + }; + }; + + /* + * Driver specific data. A driver-specific data can be shared with + * different motion sensors while they are using the same driver. + * + * If a node's compatible starts with "cros-ec,accelgyro-", it is for + * a common structure defined in accelgyro.h. + * e.g) compatible = "cros-ec,accelgyro-als-drv-data" is for + * "struct als_drv_data_t" in accelgyro.h + */ + motionsense-sensor-data { + icm42607_data: icm42607-drv-data { + compatible = "cros-ec,drvdata-icm42607"; + status = "okay"; + }; + + lis2dw12_data: lis2dw12-drv-data { + compatible = "cros-ec,drvdata-lis2dw12"; + status = "okay"; + }; + + bmi323_data: bmi323-drv-data { + compatible = "cros-ec,drvdata-bmi3xx"; + status = "okay"; + }; + }; + + /* + * List of motion sensors that creates motion_sensors array. + * The nodelabel "lid_accel" and "base_accel" are used to indicate + * motion sensor IDs for lid angle calculation. + */ + motionsense-sensor { + lid_accel: lid-accel { + compatible = "cros-ec,lis2dw12"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_LID"; + mutex = <&lid_mutex>; + port = <&i2c_sensor>; + rot-standard-ref = <&lid_rot_ref>; + default-range = <2>; + drv-data = <&lis2dw12_data>; + configs { + compatible = + "cros-ec,motionsense-sensor-config"; + ec-s0 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + ec-s3 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + }; + }; + + base_accel: base-accel { + compatible = "cros-ec,icm42607-accel"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_BASE"; + mutex = <&base_mutex>; + port = <&i2c_sensor>; + rot-standard-ref = <&base_rot_ref>; + drv-data = <&icm42607_data>; + configs { + compatible = + "cros-ec,motionsense-sensor-config"; + ec-s0 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + ec-s3 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + }; + }; + + base_gyro: base-gyro { + compatible = "cros-ec,icm42607-gyro"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_BASE"; + mutex = <&base_mutex>; + port = <&i2c_sensor>; + rot-standard-ref = <&base_rot_ref>; + drv-data = <&icm42607_data>; + }; + }; + + motionsense-sensor-alt { + alt_base_accel: alt-base-accel { + compatible = "cros-ec,bmi3xx-accel"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_BASE"; + mutex = <&base_mutex_bmi323>; + port = <&i2c_sensor>; + rot-standard-ref = <&base_rot_ref_bmi>; + drv-data = <&bmi323_data>; + alternate-for = <&base_accel>; + configs { + compatible = + "cros-ec,motionsense-sensor-config"; + ec-s0 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + ec-s3 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + }; + }; + + alt_base_gyro: alt-base-gyro { + compatible = "cros-ec,bmi3xx-gyro"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_BASE"; + mutex = <&base_mutex_bmi323>; + port = <&i2c_sensor>; + rot-standard-ref = <&base_rot_ref_bmi>; + drv-data = <&bmi323_data>; + alternate-for = <&base_gyro>; + }; + }; + + motionsense-sensor-info { + compatible = "cros-ec,motionsense-sensor-info"; + + /* + * list of GPIO interrupts that have to + * be enabled at initial stage + */ + sensor-irqs = <&int_base_imu &int_lid_imu>; + }; +}; diff --git a/zephyr/projects/corsola/npcx_keyboard.dts b/zephyr/projects/corsola/npcx_keyboard.dts new file mode 100644 index 0000000000..f9e46de1f2 --- /dev/null +++ b/zephyr/projects/corsola/npcx_keyboard.dts @@ -0,0 +1,32 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +&cros_kb_raw { + status = "okay"; + /* No KSO2 (it's inverted and implemented by GPIO) */ + pinctrl-0 = < + &ksi0_gp31 + &ksi1_gp30 + &ksi2_gp27 + &ksi3_gp26 + &ksi4_gp25 + &ksi5_gp24 + &ksi6_gp23 + &ksi7_gp22 + &kso00_gp21 + &kso01_gp20 + &kso03_gp16 + &kso04_gp15 + &kso05_gp14 + &kso06_gp13 + &kso07_gp12 + &kso08_gp11 + &kso09_gp10 + &kso10_gp07 + &kso11_gp06 + &kso12_gp05 + >; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/corsola/power_signal.dts b/zephyr/projects/corsola/power_signal.dts new file mode 100644 index 0000000000..181d7cf96e --- /dev/null +++ b/zephyr/projects/corsola/power_signal.dts @@ -0,0 +1,26 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + power_signal_list: power-signal-list { + compatible = "mt8186,power-signal-list"; + ap_in_rst { + power-enum-name = "AP_IN_RST"; + power-gpio-pin = <&ap_sysrst_odl_r>; + }; + ap_in_s3 { + power-enum-name = "AP_IN_S3"; + power-gpio-pin = <&ap_in_sleep_l>; + }; + ap_wdt_asserted { + power-enum-name = "AP_WDT_ASSERTED"; + power-gpio-pin = <&ap_ec_wdtrst_l>; + }; + ap_warm_rst_req { + power-enum-name = "AP_WARM_RST_REQ"; + power-gpio-pin = <&ap_ec_warm_rst_req>; + }; + }; +}; diff --git a/zephyr/projects/corsola/prj.conf b/zephyr/projects/corsola/prj.conf new file mode 100644 index 0000000000..110b91bbbb --- /dev/null +++ b/zephyr/projects/corsola/prj.conf @@ -0,0 +1,101 @@ +# Copyright 2021 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. +# + +# http://google3/hardware/standards/usb/ +CONFIG_PLATFORM_EC_USB_PID=0x505C + +# CROS EC +CONFIG_CROS_EC=y +CONFIG_PLATFORM_EC=y +CONFIG_PLATFORM_EC_SWITCH=y +CONFIG_SHIMMED_TASKS=y + +# AP SoC configuration +CONFIG_AP=y +CONFIG_AP_ARM_MTK_MT8186=y + +# Variant config +CONFIG_VARIANT_CORSOLA_DB_DETECTION=y + +# Shell features +CONFIG_KERNEL_SHELL=y +CONFIG_SHELL_HELP=y +CONFIG_SHELL_HISTORY=y +CONFIG_SHELL_TAB=y +CONFIG_SHELL_TAB_AUTOCOMPLETION=y + +# CBI +CONFIG_EEPROM=y +CONFIG_EEPROM_AT24=y +CONFIG_EEPROM_SHELL=n +CONFIG_PLATFORM_EC_BOARD_VERSION_CBI=y +CONFIG_PLATFORM_EC_CBI_EEPROM=y + +# I2C +CONFIG_I2C=y + +# Keyboard +CONFIG_PLATFORM_EC_KEYBOARD=y +CONFIG_PLATFORM_EC_KEYBOARD_PROTOCOL_MKBP=y +CONFIG_PLATFORM_EC_KEYBOARD_COL2_INVERTED=y + +# MKBP +CONFIG_PLATFORM_EC_MKBP_EVENT=y +CONFIG_PLATFORM_EC_MKBP_INPUT_DEVICES=y +CONFIG_PLATFORM_EC_MKBP_USE_GPIO=y + +# EFS2 +CONFIG_PLATFORM_EC_VBOOT_EFS2=y + +# USB +CONFIG_PLATFORM_EC_USB_PD_TBT_COMPAT_MODE=n +CONFIG_PLATFORM_EC_USB_PD_USB32_DRD=n +CONFIG_PLATFORM_EC_USB_PD_USB4=n +CONFIG_PLATFORM_EC_USB_PORT_POWER_DUMB_CUSTOM_HOOK=y + +# USB-C +CONFIG_PLATFORM_EC_USBC=y +CONFIG_PLATFORM_EC_USBC_SS_MUX_DFP_ONLY=y +CONFIG_PLATFORM_EC_USB_PD_DPS=y +CONFIG_PLATFORM_EC_USB_PD_DP_HPD_GPIO=y +CONFIG_PLATFORM_EC_USB_PD_DP_HPD_GPIO_CUSTOM=y +CONFIG_PLATFORM_EC_USB_PD_FRS=y + +# Power Seq +CONFIG_PLATFORM_EC_CHIPSET_RESUME_INIT_HOOK=y +CONFIG_PLATFORM_EC_EXTPOWER_GPIO=y +CONFIG_PLATFORM_EC_POWERSEQ=y +CONFIG_PLATFORM_EC_POWERSEQ_HOST_SLEEP=y +CONFIG_PLATFORM_EC_POWERSEQ_PP5000_CONTROL=n +CONFIG_PLATFORM_EC_POWER_SLEEP_FAILURE_DETECTION=y + +# Optional features +CONFIG_FLASH_SHELL=n + +# EEPROM +CONFIG_PLATFORM_EC_EEPROM_CBI_WP=y + +# Host Commands +CONFIG_PLATFORM_EC_HOSTCMD=y + +# Battery +CONFIG_PLATFORM_EC_BATTERY=y +CONFIG_PLATFORM_EC_BATTERY_CUT_OFF=y +CONFIG_PLATFORM_EC_BATTERY_FUEL_GAUGE=y +CONFIG_PLATFORM_EC_BATTERY_PRESENT_GPIO=y +CONFIG_PLATFORM_EC_BATTERY_SMART=y +CONFIG_PLATFORM_EC_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV=9000 +CONFIG_PLATFORM_EC_I2C_PASSTHRU_RESTRICTED=y +CONFIG_PLATFORM_EC_I2C_VIRTUAL_BATTERY=y + +# Charger +CONFIG_PLATFORM_EC_BC12_CLIENT_MODE_ONLY_PI3USB9201=y +CONFIG_PLATFORM_EC_CHARGER=y +CONFIG_PLATFORM_EC_CHARGE_MANAGER=y + +# Button +CONFIG_PLATFORM_EC_CMD_BUTTON=y +CONFIG_PLATFORM_EC_POWER_BUTTON=y +CONFIG_PLATFORM_EC_VOLUME_BUTTONS=y diff --git a/zephyr/projects/corsola/prj_it81202_base.conf b/zephyr/projects/corsola/prj_it81202_base.conf new file mode 100644 index 0000000000..04283bcf5c --- /dev/null +++ b/zephyr/projects/corsola/prj_it81202_base.conf @@ -0,0 +1,93 @@ +# Copyright 2022 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +# Bring up options +CONFIG_SHELL_HISTORY_BUFFER=256 +CONFIG_PLATFORM_EC_SYSTEM_UNLOCKED=y +CONFIG_PLATFORM_EC_BRINGUP=y + +# Power Sequencing +CONFIG_PLATFORM_EC_CHIPSET_RESET_HOOK=y + +# Lid Switch +CONFIG_PLATFORM_EC_LID_SWITCH=y + +# Charger +CONFIG_PLATFORM_EC_CHARGE_RAMP_HW=y +CONFIG_PLATFORM_EC_CHARGER_DISCHARGE_ON_AC=y +CONFIG_PLATFORM_EC_CHARGER_DISCHARGE_ON_AC_CHARGER=y +CONFIG_PLATFORM_EC_CHARGER_RT9490=y +CONFIG_PLATFORM_EC_CHARGER_MAINTAIN_VBAT=y +CONFIG_PLATFORM_EC_CHARGER_PSYS=y +CONFIG_PLATFORM_EC_CHARGER_PSYS_READ=y +# BOARD_RS2 +CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR=10 +# BOARD_RS1 +CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR_AC=20 +CONFIG_PLATFORM_EC_CONSOLE_CMD_CHARGER_DUMP=y + +# Host Commands +CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCELS=y +CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCEL_INFO=y +CONFIG_PLATFORM_EC_CONSOLE_CMD_CHARGER_ADC_AMON_BMON=y +CONFIG_PLATFORM_EC_CONSOLE_CMD_SYSINFO=y +CONFIG_PLATFORM_EC_HOST_COMMAND_STATUS=y + +# LED +CONFIG_PLATFORM_EC_LED_DT=y + +# PWM +CONFIG_PWM=y +CONFIG_PWM_SHELL=n + +# Sensors +CONFIG_PLATFORM_EC_MOTIONSENSE=y +CONFIG_PLATFORM_EC_ACCEL_FIFO=y +CONFIG_PLATFORM_EC_GMR_TABLET_MODE=y +CONFIG_PLATFORM_EC_LID_ANGLE=y +CONFIG_PLATFORM_EC_LID_ANGLE_UPDATE=y +CONFIG_PLATFORM_EC_SENSOR_TIGHT_TIMESTAMPS=y +CONFIG_PLATFORM_EC_TABLET_MODE=y +CONFIG_PLATFORM_EC_TABLET_MODE_SWITCH=y +CONFIG_PLATFORM_EC_MAX_SENSOR_FREQ_MILLIHZ=100000 + +# Sensor Drivers +CONFIG_PLATFORM_EC_ACCEL_LIS2DW12=y +CONFIG_PLATFORM_EC_ACCELGYRO_ICM42607=y +CONFIG_PLATFORM_EC_ACCELGYRO_ICM_COMM_I2C=y + +# Tasks +CONFIG_TASK_CHARGER_STACK_SIZE=1024 +CONFIG_TASK_CHIPSET_STACK_SIZE=1440 +CONFIG_TASK_MOTIONSENSE_STACK_SIZE=1024 +CONFIG_TASK_PD_STACK_SIZE=1280 + +# USB-A +CONFIG_PLATFORM_EC_USBA=y + +# USB-C +CONFIG_PLATFORM_EC_BC12_SINGLE_DRIVER=n +CONFIG_PLATFORM_EC_USBC_PPC_RT1739=y +CONFIG_PLATFORM_EC_USBC_PPC_SYV682C=y +CONFIG_PLATFORM_EC_USBC_PPC_SYV682X=y +CONFIG_PLATFORM_EC_USB_MUX_IT5205=y +CONFIG_PLATFORM_EC_USB_MUX_TUSB546=y +CONFIG_PLATFORM_EC_USB_MUX_VIRTUAL=y +CONFIG_PLATFORM_EC_USB_PD_DISCHARGE_PPC=y +CONFIG_PLATFORM_EC_USB_PD_FRS_PPC=y +CONFIG_PLATFORM_EC_USB_PD_LOGGING=y +CONFIG_PLATFORM_EC_USB_PD_TCPM_DRIVER_IT8XXX2=y +CONFIG_PLATFORM_EC_USB_PD_TCPM_ITE_ON_CHIP=y +CONFIG_PLATFORM_EC_USB_PD_TCPM_TCPCI=y +CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_PPC=y +CONFIG_PLATFORM_EC_USB_PD_VBUS_MEASURE_ADC_EACH_PORT=y +CONFIG_PLATFORM_EC_USB_PD_DUAL_ROLE_AUTO_TOGGLE=n +CONFIG_PLATFORM_EC_CONFIG_USB_PD_3A_PORTS=0 +CONFIG_PLATFORM_EC_USB_PD_PULLUP=1 + +CONFIG_PLATFORM_EC_SHA256_UNROLLED=y + +# TODO(b/180980668): bring these features up +CONFIG_LTO=n +CONFIG_PLATFORM_EC_BACKLIGHT_LID=n diff --git a/zephyr/projects/corsola/prj_kingler.conf b/zephyr/projects/corsola/prj_kingler.conf new file mode 100644 index 0000000000..d7de991e93 --- /dev/null +++ b/zephyr/projects/corsola/prj_kingler.conf @@ -0,0 +1,12 @@ +# Copyright 2021 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +# Variant config +CONFIG_BOARD_KINGLER=y + +# LED +CONFIG_PLATFORM_EC_LED_PWM=y + +# Keyboard +CONFIG_PLATFORM_EC_KEYBOARD_PWRBTN_ASSERTS_KSI2=y diff --git a/zephyr/projects/corsola/prj_krabby.conf b/zephyr/projects/corsola/prj_krabby.conf new file mode 100644 index 0000000000..c4cde05c16 --- /dev/null +++ b/zephyr/projects/corsola/prj_krabby.conf @@ -0,0 +1,9 @@ +# Copyright 2021 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +# Variant config +CONFIG_BOARD_KRABBY=y + +# Keyboard +CONFIG_PLATFORM_EC_KEYBOARD_PWRBTN_ASSERTS_KSI2=y diff --git a/zephyr/projects/corsola/prj_magikarp.conf b/zephyr/projects/corsola/prj_magikarp.conf new file mode 100644 index 0000000000..a5ec9ede3b --- /dev/null +++ b/zephyr/projects/corsola/prj_magikarp.conf @@ -0,0 +1,27 @@ +# Copyright 2022 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +# Variant config +CONFIG_BOARD_MAGIKARP=y + +# USB-C +CONFIG_PLATFORM_EC_BC12_DETECT_PI3USB9201=y +CONFIG_PLATFORM_EC_USB_MUX_TUSB546=n +CONFIG_PLATFORM_EC_USB_MUX_PS8743=y +CONFIG_PLATFORM_EC_PD_MAX_POWER_MW=45000 + +# Keyboard +CONFIG_PLATFORM_EC_KEYBOARD_REFRESH_ROW3=y +CONFIG_PLATFORM_EC_KEYBOARD_PWRBTN_ASSERTS_KSI3=y + +# Sensor +CONFIG_PLATFORM_EC_ACCELGYRO_BMI3XX=y +CONFIG_PLATFORM_EC_ACCELGYRO_BMI_COMM_I2C=y + +# Temperature sensors +CONFIG_PLATFORM_EC_TEMP_SENSOR=y +CONFIG_PLATFORM_EC_THERMISTOR=y + +# Battery +CONFIG_PLATFORM_EC_BATTERY_REVIVE_DISCONNECT=y diff --git a/zephyr/projects/corsola/prj_npcx993_base.conf b/zephyr/projects/corsola/prj_npcx993_base.conf new file mode 100644 index 0000000000..0642bcd331 --- /dev/null +++ b/zephyr/projects/corsola/prj_npcx993_base.conf @@ -0,0 +1,95 @@ +# Copyright 2022 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + + +# Bring up options +CONFIG_PLATFORM_EC_SYSTEM_UNLOCKED=y + +# Debug options and features; can be disabled to save memory or once bringup +# is complete. +CONFIG_SHELL_MINIMAL=n +CONFIG_LOG=y +CONFIG_LOG_MODE_MINIMAL=y + +# ADC +CONFIG_ADC=y + +# Charger +CONFIG_PLATFORM_EC_CHARGER_DISCHARGE_ON_AC=y +CONFIG_PLATFORM_EC_CHARGER_ISL9238C=y +CONFIG_PLATFORM_EC_CHARGER_PSYS=y +CONFIG_PLATFORM_EC_CHARGER_PSYS_READ=y +CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR=10 +CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR_AC=20 +CONFIG_PLATFORM_EC_CONSOLE_CMD_CHARGER_ADC_AMON_BMON=y + +# PWM +CONFIG_PWM=y +CONFIG_PWM_SHELL=n + +# LED +CONFIG_PLATFORM_EC_LED_COMMON=y +CONFIG_PLATFORM_EC_LED_ONOFF_STATES=y + +# Math +CONFIG_PLATFORM_EC_MATH_UTIL=y + +# Power sequencing +CONFIG_PLATFORM_EC_POWERSEQ_MT8186=y +CONFIG_PLATFORM_EC_POWERSEQ_S4=n + +# Button +CONFIG_PLATFORM_EC_BUTTONS_RUNTIME_CONFIG=y + +# Sensors +CONFIG_PLATFORM_EC_ACCELGYRO_BMI3XX=y +CONFIG_PLATFORM_EC_ACCELGYRO_BMI_COMM_I2C=y +CONFIG_PLATFORM_EC_ACCEL_BMA4XX=y +CONFIG_PLATFORM_EC_ACCEL_FIFO=y +CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCELS=y +CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCEL_INFO=y +CONFIG_PLATFORM_EC_GMR_TABLET_MODE=y +CONFIG_PLATFORM_EC_LID_ANGLE=y +CONFIG_PLATFORM_EC_LID_ANGLE_UPDATE=y +CONFIG_PLATFORM_EC_LID_SWITCH=y +CONFIG_PLATFORM_EC_MOTIONSENSE=y +CONFIG_PLATFORM_EC_SENSOR_TIGHT_TIMESTAMPS=y +CONFIG_PLATFORM_EC_TABLET_MODE=y +CONFIG_PLATFORM_EC_TABLET_MODE_SWITCH=y + +# USBA +CONFIG_PLATFORM_EC_USBA=y + +# USBC +CONFIG_PLATFORM_EC_BC12_DETECT_PI3USB9201=y +CONFIG_PLATFORM_EC_BC12_SINGLE_DRIVER=n +CONFIG_PLATFORM_EC_PD_POWER_SUPPLY_TURN_OFF_DELAY=15000 +CONFIG_PLATFORM_EC_PD_POWER_SUPPLY_TURN_ON_DELAY=15000 +CONFIG_PLATFORM_EC_USBC_PPC=y +CONFIG_PLATFORM_EC_USBC_PPC_NX20P3483=y +CONFIG_PLATFORM_EC_USBC_PPC_RT1718S=y +CONFIG_PLATFORM_EC_USB_MUX_PS8743=y +CONFIG_PLATFORM_EC_USB_MUX_VIRTUAL=y +CONFIG_PLATFORM_EC_USB_PD_DISCHARGE_PPC=y +CONFIG_PLATFORM_EC_USB_PD_FRS_TCPC=y +CONFIG_PLATFORM_EC_USB_PD_LOGGING=y +CONFIG_PLATFORM_EC_USB_PD_DEBUG_FIXED_LEVEL=y +CONFIG_PLATFORM_EC_USB_PD_DEBUG_LEVEL=2 +CONFIG_PLATFORM_EC_USB_PD_TCPM_ANX7447=y +CONFIG_PLATFORM_EC_USB_PD_TCPM_ANX7447_AUX_PU_PD=y +CONFIG_PLATFORM_EC_USB_PD_TCPM_RT1718S=y +CONFIG_PLATFORM_EC_USB_PD_TCPM_SBU=y +CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_TCPC=y +CONFIG_PLATFORM_EC_USB_PD_VBUS_MEASURE_BY_BOARD=y + +# External power +CONFIG_PLATFORM_EC_BACKLIGHT_LID=n + +# Keyboard +CONFIG_CROS_KB_RAW_NPCX=y +CONFIG_CROS_KB_RAW_NPCX_KSO_HIGH_DRIVE=y + +CONFIG_SYSCON=y + +CONFIG_PLATFORM_EC_BOARD_VERSION_GPIO=n diff --git a/zephyr/projects/corsola/prj_steelix.conf b/zephyr/projects/corsola/prj_steelix.conf new file mode 100644 index 0000000000..7a854b1313 --- /dev/null +++ b/zephyr/projects/corsola/prj_steelix.conf @@ -0,0 +1,32 @@ +# Copyright 2022 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +# Variant config +CONFIG_BOARD_STEELIX=y + +# steelix only use D2, drop the workaround config for H1 +CONFIG_PLATFORM_EC_BOARD_RESET_AFTER_POWER_ON=n + +# Motion sensor +CONFIG_PLATFORM_EC_ACCEL_LIS2DW12=y +CONFIG_PLATFORM_EC_ACCELGYRO_LSM6DSM=y +CONFIG_PLATFORM_EC_DYNAMIC_MOTION_SENSOR_COUNT=y + +# Keyboard +CONFIG_PLATFORM_EC_KEYBOARD_REFRESH_ROW3=y +CONFIG_PLATFORM_EC_KEYBOARD_PWRBTN_ASSERTS_KSI3=y +CONFIG_PLATFORM_EC_KEYBOARD_STRICT_DEBOUNCE=y + +# USBC +CONFIG_PLATFORM_EC_PD_MAX_CURRENT_MA=3250 +CONFIG_PLATFORM_EC_PD_MAX_POWER_MW=65000 + +# Remove bring up options for FW QUAL +CONFIG_PLATFORM_EC_SYSTEM_UNLOCKED=n + +# Remove debug options and features for FW QUAL +CONFIG_LOG=n +CONFIG_LOG_MODE_MINIMAL=n +CONFIG_SHELL_MINIMAL=y +CONFIG_PLATFORM_EC_USB_PD_DEBUG_LEVEL=0 diff --git a/zephyr/projects/corsola/prj_tentacruel.conf b/zephyr/projects/corsola/prj_tentacruel.conf new file mode 100644 index 0000000000..71cc9d9694 --- /dev/null +++ b/zephyr/projects/corsola/prj_tentacruel.conf @@ -0,0 +1,26 @@ +# Copyright 2022 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +# Variant config +CONFIG_BOARD_TENTACRUEL=y + +# USB-C +CONFIG_PLATFORM_EC_BC12_DETECT_PI3USB9201=y +CONFIG_PLATFORM_EC_USB_MUX_TUSB546=n +CONFIG_PLATFORM_EC_USB_MUX_PS8743=y + +# Keyboard +CONFIG_PLATFORM_EC_KEYBOARD_REFRESH_ROW3=y +CONFIG_PLATFORM_EC_KEYBOARD_PWRBTN_ASSERTS_KSI3=y + +# Sensor +CONFIG_PLATFORM_EC_ACCELGYRO_BMI3XX=y +CONFIG_PLATFORM_EC_ACCELGYRO_BMI_COMM_I2C=y + +# Temperature sensors +CONFIG_PLATFORM_EC_TEMP_SENSOR=y +CONFIG_PLATFORM_EC_THERMISTOR=y + +# Battery +CONFIG_PLATFORM_EC_CHARGER_PROFILE_OVERRIDE=y diff --git a/zephyr/projects/corsola/src/board.c b/zephyr/projects/corsola/src/board.c new file mode 100644 index 0000000000..93a2443191 --- /dev/null +++ b/zephyr/projects/corsola/src/board.c @@ -0,0 +1,37 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "console.h" +#include "hooks.h" +#include "typec_control.h" +#include "usb_dp_alt_mode.h" +#include "usb_mux.h" +#include "usb_pd.h" +#include "usbc_ppc.h" + +#include "baseboard_usbc_config.h" + +#define CPRINTS(format, args...) cprints(CC_USB, format, ##args) + +static void ccd_interrupt_deferred(void) +{ + /* + * If CCD_MODE_ODL asserts, it means there's a debug accessory connected + * and we should enable the SBU FETs. + */ + typec_set_sbu(CONFIG_CCD_USBC_PORT_NUMBER, 1); + + /* Mux DP AUX away when CCD enabled to prevent the AUX channel + * interferes the SBU pins. + */ + CPRINTS("CCD Enabled, mux DP_AUX_PATH_SEL to 1"); + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(dp_aux_path_sel), 1); +} +DECLARE_DEFERRED(ccd_interrupt_deferred); + +void ccd_interrupt(enum gpio_signal signal) +{ + hook_call_deferred(&ccd_interrupt_deferred_data, 0); +} diff --git a/zephyr/projects/corsola/src/board_chipset.c b/zephyr/projects/corsola/src/board_chipset.c new file mode 100644 index 0000000000..54e96bc631 --- /dev/null +++ b/zephyr/projects/corsola/src/board_chipset.c @@ -0,0 +1,49 @@ +/* Copyright 2021 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Corsola baseboard-chipset specific configuration */ + +#include <zephyr/init.h> +#include <ap_power/ap_power.h> +#include <zephyr/drivers/gpio.h> +#include "gpio.h" + +static void board_backlight_handler(struct ap_power_ev_callback *cb, + struct ap_power_ev_data data) +{ + int value; + + switch (data.event) { + default: + return; + + case AP_POWER_RESUME: + /* Called on AP S3 -> S0 transition */ + value = 1; + break; + + case AP_POWER_SUSPEND: + /* Called on AP S0 -> S3 transition */ + value = 0; + break; + } + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_bl_en_od), value); +} + +static int install_backlight_handler(const struct device *unused) +{ + static struct ap_power_ev_callback cb; + + /* + * Add a callback for suspend/resume to + * control the keyboard backlight. + */ + ap_power_ev_init_callback(&cb, board_backlight_handler, + AP_POWER_RESUME | AP_POWER_SUSPEND); + ap_power_ev_add_callback(&cb); + return 0; +} + +SYS_INIT(install_backlight_handler, APPLICATION, 1); diff --git a/zephyr/projects/corsola/src/hibernate.c b/zephyr/projects/corsola/src/hibernate.c new file mode 100644 index 0000000000..56c085e077 --- /dev/null +++ b/zephyr/projects/corsola/src/hibernate.c @@ -0,0 +1,22 @@ +/* Copyright 2021 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ +#include <zephyr/drivers/gpio.h> + +#include "charger.h" +#include "driver/charger/isl923x_public.h" +#include "system.h" + +/* Corsola board specific hibernate implementation */ +__override void board_hibernate(void) +{ +#ifdef CONFIG_CHARGER_ISL9238C + isl9238c_hibernate(CHARGER_SOLO); +#endif +} + +__override void board_hibernate_late(void) +{ + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_en_ulp), 1); +} diff --git a/zephyr/projects/corsola/src/kingler/board_steelix.c b/zephyr/projects/corsola/src/kingler/board_steelix.c new file mode 100644 index 0000000000..8b88a6d7c7 --- /dev/null +++ b/zephyr/projects/corsola/src/kingler/board_steelix.c @@ -0,0 +1,76 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Board re-init for Rusty board + * Rusty shares the firmware with Steelix. + * Steelix is convertible but Rusty is clamshell + * so some functions should be disabled for clamshell. + */ +#include <zephyr/logging/log.h> +#include <zephyr/drivers/gpio.h> + +#include "accelgyro.h" +#include "common.h" +#include "cros_cbi.h" +#include "driver/accelgyro_bmi3xx.h" +#include "driver/accelgyro_lsm6dsm.h" +#include "gpio/gpio_int.h" +#include "hooks.h" +#include "motion_sense.h" +#include "motionsense_sensors.h" +#include "tablet_mode.h" + +LOG_MODULE_REGISTER(board_init, LOG_LEVEL_ERR); + +static bool board_is_clamshell; + +static void board_setup_init(void) +{ + int ret; + uint32_t val; + + ret = cros_cbi_get_fw_config(FORM_FACTOR, &val); + if (ret != 0) { + LOG_ERR("Error retrieving CBI FW_CONFIG field %d", FORM_FACTOR); + return; + } + if (val == CLAMSHELL) { + board_is_clamshell = true; + motion_sensor_count = 0; + gmr_tablet_switch_disable(); + } +} +DECLARE_HOOK(HOOK_INIT, board_setup_init, HOOK_PRIO_PRE_DEFAULT); + +static void disable_base_imu_irq(void) +{ + if (board_is_clamshell) { + gpio_disable_dt_interrupt( + GPIO_INT_FROM_NODELABEL(int_base_imu)); + gpio_pin_configure_dt(GPIO_DT_FROM_NODELABEL(base_imu_int_l), + GPIO_INPUT | GPIO_PULL_UP); + } +} +DECLARE_HOOK(HOOK_INIT, disable_base_imu_irq, HOOK_PRIO_POST_DEFAULT); + +static bool base_use_alt_sensor; + +void motion_interrupt(enum gpio_signal signal) +{ + if (base_use_alt_sensor) { + lsm6dsm_interrupt(signal); + } else { + bmi3xx_interrupt(signal); + } +} + +static void alt_sensor_init(void) +{ + base_use_alt_sensor = cros_cbi_ssfc_check_match( + CBI_SSFC_VALUE_ID(DT_NODELABEL(base_sensor_1))); + + motion_sensors_check_ssfc(); +} +DECLARE_HOOK(HOOK_INIT, alt_sensor_init, HOOK_PRIO_POST_I2C); diff --git a/zephyr/projects/corsola/src/kingler/button.c b/zephyr/projects/corsola/src/kingler/button.c new file mode 100644 index 0000000000..920069bef6 --- /dev/null +++ b/zephyr/projects/corsola/src/kingler/button.c @@ -0,0 +1,35 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* kingler button */ + +#include "button.h" +#include "cros_board_info.h" +#include "gpio.h" +#include "hooks.h" + +static void buttons_hook(void) +{ + int version; + + if (cbi_get_board_version(&version)) { + return; + } + + /* b:219891339: drop this workaround when we deprecate rev0 */ + if (version == 0) { + /* swap VOLUP/VOLDN */ + button_reassign_gpio(BUTTON_VOLUME_DOWN, GPIO_VOLUME_UP_L); + button_reassign_gpio(BUTTON_VOLUME_UP, GPIO_VOLUME_DOWN_L); + /* + * button_reassign_gpio will disable the old button interrupt + * and then enable the new button interrupt which cause the + * GPIO_VOLUME_UP_L interrupt disabled after we reassign + * BUTTON_VOLUME_UP, so we need to re-enable it here. + */ + gpio_enable_interrupt(GPIO_VOLUME_UP_L); + } +} +DECLARE_HOOK(HOOK_INIT, buttons_hook, HOOK_PRIO_DEFAULT); diff --git a/zephyr/projects/corsola/src/kingler/i2c.c b/zephyr/projects/corsola/src/kingler/i2c.c new file mode 100644 index 0000000000..f2bbff3749 --- /dev/null +++ b/zephyr/projects/corsola/src/kingler/i2c.c @@ -0,0 +1,21 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "i2c/i2c.h" +#include "i2c.h" + +/* Kingler and Steelix board specific i2c implementation */ + +#ifdef CONFIG_PLATFORM_EC_I2C_PASSTHRU_RESTRICTED +int board_allow_i2c_passthru(const struct i2c_cmd_desc_t *cmd_desc) +{ + return (i2c_get_device_for_port(cmd_desc->port) == + i2c_get_device_for_port(I2C_PORT_VIRTUAL_BATTERY) || + i2c_get_device_for_port(cmd_desc->port) == + i2c_get_device_for_port(I2C_PORT_EEPROM) || + i2c_get_device_for_port(cmd_desc->port) == + i2c_get_device_for_port(I2C_PORT_USB_C0)); +} +#endif diff --git a/zephyr/projects/corsola/src/kingler/led.c b/zephyr/projects/corsola/src/kingler/led.c new file mode 100644 index 0000000000..4e2c5b12fb --- /dev/null +++ b/zephyr/projects/corsola/src/kingler/led.c @@ -0,0 +1,52 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + * + * Battery LED control for Kingler + */ +#include "common.h" +#include "ec_commands.h" +#include "led_common.h" +#include "led_onoff_states.h" +#include "led_pwm.h" + +__override const int led_charge_lvl_1 = 5; +__override const int led_charge_lvl_2 = 97; +__override struct led_descriptor + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED, + LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 3 * LED_ONE_SEC } }, + [STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 2 * LED_ONE_SEC }, + { EC_LED_COLOR_GREEN, + 2 * LED_ONE_SEC } }, + }; + +__override void led_set_color_battery(enum ec_led_colors color) +{ + switch (color) { + case EC_LED_COLOR_RED: + set_pwm_led_color(EC_LED_ID_BATTERY_LED, EC_LED_COLOR_RED); + break; + case EC_LED_COLOR_GREEN: + set_pwm_led_color(EC_LED_ID_BATTERY_LED, EC_LED_COLOR_GREEN); + break; + case EC_LED_COLOR_AMBER: + set_pwm_led_color(EC_LED_ID_BATTERY_LED, EC_LED_COLOR_AMBER); + break; + default: /* LED_OFF and other unsupported colors */ + set_pwm_led_color(EC_LED_ID_BATTERY_LED, -1); + break; + } +} diff --git a/zephyr/projects/corsola/src/kingler/led_steelix.c b/zephyr/projects/corsola/src/kingler/led_steelix.c new file mode 100644 index 0000000000..87b76128e8 --- /dev/null +++ b/zephyr/projects/corsola/src/kingler/led_steelix.c @@ -0,0 +1,181 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + * + * Battery LED control for Steelix + */ + +#include <zephyr/drivers/pwm.h> +#include <zephyr/logging/log.h> + +#include "board_led.h" +#include "common.h" +#include "cros_cbi.h" +#include "led_common.h" +#include "led_onoff_states.h" +#include "util.h" + +LOG_MODULE_REGISTER(board_led, LOG_LEVEL_ERR); + +#define BOARD_LED_PWM_PERIOD_NS BOARD_LED_HZ_TO_PERIOD_NS(100) + +static const struct board_led_pwm_dt_channel board_led_battery_red = + BOARD_LED_PWM_DT_CHANNEL_INITIALIZER(DT_NODELABEL(led_battery_red)); +static const struct board_led_pwm_dt_channel board_led_battery_green = + BOARD_LED_PWM_DT_CHANNEL_INITIALIZER(DT_NODELABEL(led_battery_green)); +static const struct board_led_pwm_dt_channel board_led_power_white = + BOARD_LED_PWM_DT_CHANNEL_INITIALIZER(DT_NODELABEL(led_power_white)); + +__override const int led_charge_lvl_1 = 5; +__override const int led_charge_lvl_2 = 97; +__override struct led_descriptor + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED, + LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S0_BAT_LOW] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 2 * LED_ONE_SEC }, + { EC_LED_COLOR_GREEN, + 2 * LED_ONE_SEC } }, + }; + +__override const struct led_descriptor + led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { + [PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } }, + [PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE, + 3 * LED_ONE_SEC }, + { LED_OFF, 0.5 * LED_ONE_SEC } }, + [PWR_LED_STATE_SUSPEND_NO_AC] = { { EC_LED_COLOR_WHITE, + 3 * LED_ONE_SEC }, + { LED_OFF, + 0.5 * LED_ONE_SEC } }, + [PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } }, + }; + +const enum ec_led_id supported_led_ids[] = { + EC_LED_ID_BATTERY_LED, + EC_LED_ID_POWER_LED, +}; + +const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); + +static void board_led_pwm_set_duty(const struct board_led_pwm_dt_channel *ch, + int percent) +{ + uint32_t pulse_ns; + int rv; + + if (!device_is_ready(ch->dev)) { + LOG_ERR("PWM device %s not ready", ch->dev->name); + return; + } + + pulse_ns = DIV_ROUND_NEAREST(BOARD_LED_PWM_PERIOD_NS * percent, 100); + + LOG_DBG("Board LED PWM %s set percent (%d), pulse %d", ch->dev->name, + percent, pulse_ns); + + rv = pwm_set(ch->dev, ch->channel, BOARD_LED_PWM_PERIOD_NS, pulse_ns, + ch->flags); + if (rv) { + LOG_ERR("pwm_set() failed %s (%d)", ch->dev->name, rv); + } +} + +static bool device_is_clamshell(void) +{ + int ret; + uint32_t val; + + ret = cros_cbi_get_fw_config(FORM_FACTOR, &val); + if (ret != 0) { + LOG_ERR("Error retrieving CBI FW_CONFIG field %d", FORM_FACTOR); + return false; + } + + return val == CLAMSHELL; +} + +__override void led_set_color_battery(enum ec_led_colors color) +{ + switch (color) { + case EC_LED_COLOR_RED: + board_led_pwm_set_duty(&board_led_battery_red, 100); + board_led_pwm_set_duty(&board_led_battery_green, 0); + break; + case EC_LED_COLOR_GREEN: + board_led_pwm_set_duty(&board_led_battery_red, 0); + board_led_pwm_set_duty(&board_led_battery_green, 100); + break; + case EC_LED_COLOR_AMBER: + board_led_pwm_set_duty(&board_led_battery_red, 100); + board_led_pwm_set_duty(&board_led_battery_green, 20); + break; + default: /* LED_OFF and other unsupported colors */ + board_led_pwm_set_duty(&board_led_battery_red, 0); + board_led_pwm_set_duty(&board_led_battery_green, 0); + break; + } +} + +__override void led_set_color_power(enum ec_led_colors color) +{ + if (device_is_clamshell()) { + board_led_pwm_set_duty(&board_led_power_white, 0); + } else { + switch (color) { + case EC_LED_COLOR_WHITE: + board_led_pwm_set_duty(&board_led_power_white, 100); + break; + default: + board_led_pwm_set_duty(&board_led_power_white, 0); + break; + } + } +} + +void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range) +{ + if (led_id == EC_LED_ID_BATTERY_LED) { + brightness_range[EC_LED_COLOR_RED] = 1; + brightness_range[EC_LED_COLOR_GREEN] = 1; + brightness_range[EC_LED_COLOR_AMBER] = 1; + } else if (led_id == EC_LED_ID_POWER_LED) { + if (device_is_clamshell()) { + brightness_range[EC_LED_COLOR_WHITE] = 0; + } else { + brightness_range[EC_LED_COLOR_WHITE] = 1; + } + } +} + +int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness) +{ + if (led_id == EC_LED_ID_BATTERY_LED) { + if (brightness[EC_LED_COLOR_RED] != 0) { + led_set_color_battery(EC_LED_COLOR_RED); + } else if (brightness[EC_LED_COLOR_GREEN] != 0) { + led_set_color_battery(EC_LED_COLOR_GREEN); + } else if (brightness[EC_LED_COLOR_AMBER] != 0) { + led_set_color_battery(EC_LED_COLOR_AMBER); + } else { + led_set_color_battery(LED_OFF); + } + } else if (led_id == EC_LED_ID_POWER_LED) { + if (brightness[EC_LED_COLOR_WHITE] != 0) { + led_set_color_power(EC_LED_COLOR_WHITE); + } else { + led_set_color_power(LED_OFF); + } + } + + return EC_SUCCESS; +} diff --git a/zephyr/projects/corsola/src/kingler/usb_pd_policy.c b/zephyr/projects/corsola/src/kingler/usb_pd_policy.c new file mode 100644 index 0000000000..3de2857ad1 --- /dev/null +++ b/zephyr/projects/corsola/src/kingler/usb_pd_policy.c @@ -0,0 +1,74 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "charge_manager.h" +#include "console.h" +#include "driver/ppc/rt1718s.h" +#include "system.h" +#include "usb_mux.h" +#include "usb_pd.h" +#include "usbc_ppc.h" +#include "util.h" + +#include "baseboard_usbc_config.h" + +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) + +void pd_power_supply_reset(int port) +{ + int prev_en; + + prev_en = ppc_is_sourcing_vbus(port); + + if (port == USBC_PORT_C1) { + rt1718s_gpio_set_level(port, GPIO_EN_USB_C1_SOURCE, 0); + } + + /* Disable VBUS. */ + ppc_vbus_source_enable(port, 0); + + /* Enable discharge if we were previously sourcing 5V */ + if (prev_en) { + pd_set_vbus_discharge(port, 1); + } + + /* Notify host of power info change. */ + pd_send_host_event(PD_EVENT_POWER_CHANGE); +} + +int pd_set_power_supply_ready(int port) +{ + int rv; + + /* Disable charging. */ + rv = ppc_vbus_sink_enable(port, 0); + if (rv) { + return rv; + } + + pd_set_vbus_discharge(port, 0); + + /* Provide Vbus. */ + if (port == USBC_PORT_C1) { + rt1718s_gpio_set_level(port, GPIO_EN_USB_C1_SOURCE, 1); + } + + rv = ppc_vbus_source_enable(port, 1); + if (rv) { + return rv; + } + + /* Notify host of power info change. */ + pd_send_host_event(PD_EVENT_POWER_CHANGE); + + return EC_SUCCESS; +} + +int pd_snk_is_vbus_provided(int port) +{ + /* TODO: use ADC? */ + return tcpm_check_vbus_level(port, VBUS_PRESENT); +} diff --git a/zephyr/projects/corsola/src/kingler/usbc_config.c b/zephyr/projects/corsola/src/kingler/usbc_config.c new file mode 100644 index 0000000000..8c0ca86454 --- /dev/null +++ b/zephyr/projects/corsola/src/kingler/usbc_config.c @@ -0,0 +1,317 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Kingler board-specific USB-C configuration */ + +#include "charger.h" +#include "console.h" +#include "driver/bc12/pi3usb9201_public.h" +#include "driver/charger/isl923x_public.h" +#include "driver/ppc/nx20p348x.h" +#include "driver/ppc/rt1718s.h" +#include "driver/tcpm/anx7447.h" +#include "driver/tcpm/rt1718s.h" +#include "driver/usb_mux/ps8743.h" +#include "gpio/gpio_int.h" +#include "hooks.h" +#include "timer.h" +#include "usb_charge.h" +#include "usb_mux.h" +#include "usb_pd_tcpm.h" +#include "usbc_ppc.h" + +#include "baseboard_usbc_config.h" +#include "variant_db_detection.h" + +/* TODO(b/220196310): Create GPIO driver for RT17181S TCPC */ +#ifdef __REQUIRE_ZEPHYR_GPIOS__ +#undef __REQUIRE_ZEPHYR_GPIOS__ +#endif +#include "gpio.h" + +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) + +/* USB Mux */ + +/* USB Mux C1 : board_init of PS8743 */ +int ps8743_mux_1_board_init(const struct usb_mux *me) +{ + ps8743_tune_usb_eq(me, PS8743_USB_EQ_TX_3_6_DB, + PS8743_USB_EQ_RX_16_0_DB); + + return EC_SUCCESS; +} + +void board_usb_mux_init(void) +{ + if (corsola_get_db_type() == CORSOLA_DB_TYPEC) { + /* Disable DCI function. This is not needed for ARM. */ + ps8743_field_update(usb_muxes[1].mux, PS8743_REG_DCI_CONFIG_2, + PS8743_AUTO_DCI_MODE_MASK, + PS8743_AUTO_DCI_MODE_FORCE_USB); + } +} +DECLARE_HOOK(HOOK_INIT, board_usb_mux_init, HOOK_PRIO_INIT_I2C + 1); + +void board_tcpc_init(void) +{ + /* Only reset TCPC if not sysjump */ + if (!system_jumped_late()) { + /* TODO(crosbug.com/p/61098): How long do we need to wait? */ + board_reset_pd_mcu(); + } + + /* Enable TCPC interrupts */ + gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0_tcpc)); + if (corsola_get_db_type() == CORSOLA_DB_TYPEC) { + gpio_enable_dt_interrupt( + GPIO_INT_FROM_NODELABEL(int_usb_c1_tcpc)); + } + + /* Enable BC1.2 interrupts. */ + gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0_bc12)); + + /* + * Initialize HPD to low; after sysjump SOC needs to see + * HPD pulse to enable video path + */ + for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port) { + usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED | + USB_PD_MUX_HPD_IRQ_DEASSERTED); + } +} +DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_POST_I2C); + +__override int board_rt1718s_init(int port) +{ + static bool gpio_initialized; + + if (!system_jumped_late() && !gpio_initialized) { + /* set GPIO 1~3 as push pull, as output, output low. */ + rt1718s_gpio_set_flags(port, RT1718S_GPIO1, GPIO_OUT_LOW); + rt1718s_gpio_set_flags(port, RT1718S_GPIO2, GPIO_OUT_LOW); + rt1718s_gpio_set_flags(port, RT1718S_GPIO3, GPIO_OUT_LOW); + gpio_initialized = true; + } + + /* gpio1 low, gpio2 output high when receiving frs signal */ + RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_GPIO1_VBUS_CTRL, + RT1718S_GPIO1_VBUS_CTRL_FRS_RX_VBUS, + 0)); + RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_GPIO2_VBUS_CTRL, + RT1718S_GPIO2_VBUS_CTRL_FRS_RX_VBUS, + 0xFF)); + + /* Trigger GPIO 1/2 change when FRS signal received */ + RETURN_ERROR(rt1718s_update_bits8( + port, RT1718S_FRS_CTRL3, + RT1718S_FRS_CTRL3_FRS_RX_WAIT_GPIO2 | + RT1718S_FRS_CTRL3_FRS_RX_WAIT_GPIO1, + RT1718S_FRS_CTRL3_FRS_RX_WAIT_GPIO2 | + RT1718S_FRS_CTRL3_FRS_RX_WAIT_GPIO1)); + /* Set FRS signal detect time to 46.875us */ + RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_FRS_CTRL1, + RT1718S_FRS_CTRL1_FRSWAPRX_MASK, + 0xFF)); + + /* Disable BC1.2 SRC mode */ + RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_RT2_BC12_SRC_FUNC, + RT1718S_RT2_BC12_SRC_FUNC_BC12_SRC_EN, + 0)); + + return EC_SUCCESS; +} + +__override int board_rt1718s_set_frs_enable(int port, int enable) +{ + if (port == USBC_PORT_C1) + /* + * Use set_flags (implemented by a single i2c write) instead + * of set_level (= i2c_update) to save one read operation in + * FRS path. + */ + rt1718s_gpio_set_flags(port, GPIO_EN_USB_C1_FRS, + enable ? GPIO_OUT_HIGH : GPIO_OUT_LOW); + return EC_SUCCESS; +} + +void board_reset_pd_mcu(void) +{ + CPRINTS("Resetting TCPCs..."); + /* reset C0 ANX3447 */ + /* Assert reset */ + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_c0_tcpc_rst), 1); + msleep(1); + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_c0_tcpc_rst), 0); + /* After TEST_R release, anx7447/3447 needs 2ms to finish eFuse + * loading. + */ + msleep(2); + + /* reset C1 RT1718s */ + rt1718s_sw_reset(USBC_PORT_C1); +} + +/* Used by Vbus discharge common code with CONFIG_USB_PD_DISCHARGE */ +int board_vbus_source_enabled(int port) +{ + return ppc_is_sourcing_vbus(port); +} + +__override int board_rt1718s_set_snk_enable(int port, int enable) +{ + if (port == USBC_PORT_C1) { + rt1718s_gpio_set_level(port, GPIO_EN_USB_C1_SINK, enable); + } + + return EC_SUCCESS; +} + +int board_set_active_charge_port(int port) +{ + int i; + bool is_valid_port = + (port >= 0 && port < board_get_usb_pd_port_count()); + + if (!is_valid_port && port != CHARGE_PORT_NONE) { + return EC_ERROR_INVAL; + } + + if (port == CHARGE_PORT_NONE) { + CPRINTS("Disabling all charger ports"); + + /* Disable all ports. */ + for (i = 0; i < board_get_usb_pd_port_count(); i++) { + /* + * Do not return early if one fails otherwise we can + * get into a boot loop assertion failure. + */ + if (ppc_vbus_sink_enable(i, 0)) { + CPRINTS("Disabling C%d as sink failed.", i); + } + } + + return EC_SUCCESS; + } + + /* Check if the port is sourcing VBUS. */ + if (ppc_is_sourcing_vbus(port)) { + CPRINTS("Skip enable C%d", port); + return EC_ERROR_INVAL; + } + + CPRINTS("New charge port: C%d", port); + + /* + * Turn off the other ports' sink path FETs, before enabling the + * requested charge port. + */ + for (i = 0; i < board_get_usb_pd_port_count(); i++) { + if (i == port) { + continue; + } + + if (ppc_vbus_sink_enable(i, 0)) { + CPRINTS("C%d: sink path disable failed.", i); + } + } + + /* Enable requested charge port. */ + if (ppc_vbus_sink_enable(port, 1)) { + CPRINTS("C%d: sink path enable failed.", port); + return EC_ERROR_UNKNOWN; + } + + return EC_SUCCESS; +} + +uint16_t tcpc_get_alert_status(void) +{ + uint16_t status = 0; + + if (!gpio_pin_get_dt( + GPIO_DT_FROM_NODELABEL(gpio_usb_c0_tcpc_int_odl))) { + if (!gpio_pin_get_dt( + GPIO_DT_FROM_NODELABEL(gpio_usb_c0_tcpc_rst))) { + status |= PD_STATUS_TCPC_ALERT_0; + } + } + + if (!gpio_pin_get_dt( + GPIO_DT_FROM_NODELABEL(gpio_usb_c1_tcpc_int_odl))) { + return status |= PD_STATUS_TCPC_ALERT_1; + } + return status; +} + +void tcpc_alert_event(enum gpio_signal signal) +{ + int port; + + switch (signal) { + case GPIO_SIGNAL(DT_NODELABEL(gpio_usb_c0_tcpc_int_odl)): + port = 0; + break; + case GPIO_SIGNAL(DT_NODELABEL(gpio_usb_c1_tcpc_int_odl)): + port = 1; + break; + default: + return; + } + + schedule_deferred_pd_interrupt(port); +} + +void ppc_interrupt(enum gpio_signal signal) +{ + switch (signal) { + case GPIO_SIGNAL(DT_NODELABEL(gpio_usb_c0_ppc_int_odl)): + ppc_chips[0].drv->interrupt(0); + break; + case GPIO_SIGNAL(DT_ALIAS(gpio_usb_c1_ppc_int_odl)): + ppc_chips[1].drv->interrupt(1); + break; + default: + break; + } +} + +void bc12_interrupt(enum gpio_signal signal) +{ + usb_charger_task_set_event(0, USB_CHG_EVENT_BC12); +} + +__override int board_get_vbus_voltage(int port) +{ + int voltage = 0; + int rv; + + switch (port) { + case USBC_PORT_C0: + rv = tcpc_config[USBC_PORT_C0].drv->get_vbus_voltage(port, + &voltage); + if (rv) + return 0; + break; + case USBC_PORT_C1: + rt1718s_get_adc(port, RT1718S_ADC_VBUS1, &voltage); + break; + default: + return 0; + } + return voltage; +} + +__override int board_nx20p348x_init(int port) +{ + int rv; + + rv = i2c_update8(ppc_chips[port].i2c_port, + ppc_chips[port].i2c_addr_flags, + NX20P348X_DEVICE_CONTROL_REG, NX20P348X_CTRL_LDO_SD, + MASK_SET); + return rv; +} diff --git a/zephyr/projects/corsola/src/krabby/charger_workaround.c b/zephyr/projects/corsola/src/krabby/charger_workaround.c new file mode 100644 index 0000000000..d7fd05cc00 --- /dev/null +++ b/zephyr/projects/corsola/src/krabby/charger_workaround.c @@ -0,0 +1,93 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <zephyr/sys/util.h> + +#include "charger.h" +#include "driver/charger/rt9490.h" +#include "hooks.h" +#include "i2c.h" +#include "system.h" + +/* + * This workaround and the board id checks only apply to krabby and early + * tentacruel devices. + * Newer project should have all of these fixed. + */ +BUILD_ASSERT(IS_ENABLED(CONFIG_BOARD_KRABBY) || + IS_ENABLED(CONFIG_BOARD_TENTACRUEL) || IS_ENABLED(CONFIG_TEST)); + +/* b/194967754#comment5: work around for IBUS ADC unstable issue */ +static void ibus_adc_workaround(void) +{ + if (system_get_board_version() != 0) { + return; + } + + i2c_update8(chg_chips[CHARGER_SOLO].i2c_port, + chg_chips[CHARGER_SOLO].i2c_addr_flags, + RT9490_REG_ADC_CHANNEL0, RT9490_VSYS_ADC_DIS, MASK_SET); + + rt9490_enable_hidden_mode(CHARGER_SOLO, true); + /* undocumented registers... */ + i2c_write8(chg_chips[CHARGER_SOLO].i2c_port, + chg_chips[CHARGER_SOLO].i2c_addr_flags, 0x52, 0xC4); + + i2c_update8(chg_chips[CHARGER_SOLO].i2c_port, + chg_chips[CHARGER_SOLO].i2c_addr_flags, + RT9490_REG_ADC_CHANNEL0, RT9490_VSYS_ADC_DIS, MASK_CLR); + rt9490_enable_hidden_mode(CHARGER_SOLO, false); +} + +/* b/214880220#comment44: lock i2c at 400khz */ +static void i2c_speed_workaround(void) +{ + if (system_get_board_version() >= 3) { + return; + } + + rt9490_enable_hidden_mode(CHARGER_SOLO, true); + /* Set to Auto mode, default run at 400kHz */ + i2c_write8(chg_chips[CHARGER_SOLO].i2c_port, + chg_chips[CHARGER_SOLO].i2c_addr_flags, 0x71, 0x22); + /* Manually select for 400kHz, valid only when 0x71[7] == 1 */ + i2c_write8(chg_chips[CHARGER_SOLO].i2c_port, + chg_chips[CHARGER_SOLO].i2c_addr_flags, 0xF7, 0x14); + rt9490_enable_hidden_mode(CHARGER_SOLO, false); +} + +static void eoc_deglitch_workaround(void) +{ + if (system_get_board_version() != 1) { + return; + } + + /* set end-of-charge deglitch time to 2ms */ + i2c_update8(chg_chips[CHARGER_SOLO].i2c_port, + chg_chips[CHARGER_SOLO].i2c_addr_flags, + RT9490_REG_ADD_CTRL0, RT9490_TD_EOC, MASK_CLR); +} + +static void disable_safety_timer(void) +{ + if (system_get_board_version() >= 2) { + return; + } + /* Disable charge timer */ + i2c_write8(chg_chips[CHARGER_SOLO].i2c_port, + chg_chips[CHARGER_SOLO].i2c_addr_flags, + RT9490_REG_SAFETY_TMR_CTRL, + RT9490_EN_TRICHG_TMR | RT9490_EN_PRECHG_TMR | + RT9490_EN_FASTCHG_TMR); +} + +static void board_rt9490_workaround(void) +{ + ibus_adc_workaround(); + i2c_speed_workaround(); + eoc_deglitch_workaround(); + disable_safety_timer(); +} +DECLARE_HOOK(HOOK_INIT, board_rt9490_workaround, HOOK_PRIO_DEFAULT); diff --git a/zephyr/projects/corsola/src/krabby/hooks.c b/zephyr/projects/corsola/src/krabby/hooks.c new file mode 100644 index 0000000000..1eb4f600f2 --- /dev/null +++ b/zephyr/projects/corsola/src/krabby/hooks.c @@ -0,0 +1,90 @@ +/* Copyright 2021 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <zephyr/init.h> +#include <zephyr/drivers/gpio.h> +#include <zephyr/drivers/pinctrl.h> + +#include <ap_power/ap_power.h> +#include "charger.h" +#include "driver/charger/rt9490.h" +#include "extpower.h" +#include "gpio.h" +#include "hooks.h" + +#define I2C3_NODE DT_NODELABEL(i2c3) +PINCTRL_DT_DEFINE(I2C3_NODE); + +static void board_i2c3_ctrl(bool enable) +{ + if (DEVICE_DT_GET( + DT_GPIO_CTLR_BY_IDX(DT_NODELABEL(i2c3), scl_gpios, 0)) == + DEVICE_DT_GET(DT_NODELABEL(gpiof))) { + const struct pinctrl_dev_config *pcfg = + PINCTRL_DT_DEV_CONFIG_GET(I2C3_NODE); + + if (enable) { + pinctrl_apply_state(pcfg, PINCTRL_STATE_DEFAULT); + } else { + pinctrl_apply_state(pcfg, PINCTRL_STATE_SLEEP); + } + } +} + +static void board_enable_i2c3(void) +{ + board_i2c3_ctrl(1); +} +DECLARE_HOOK(HOOK_CHIPSET_PRE_INIT, board_enable_i2c3, HOOK_PRIO_FIRST); + +static void board_disable_i2c3(void) +{ + board_i2c3_ctrl(0); +} +DECLARE_HOOK(HOOK_CHIPSET_HARD_OFF, board_disable_i2c3, HOOK_PRIO_LAST); + +static void board_suspend_handler(struct ap_power_ev_callback *cb, + struct ap_power_ev_data data) +{ + int value; + + switch (data.event) { + default: + return; + + case AP_POWER_RESUME: + value = 1; + break; + + case AP_POWER_SUSPEND: + value = 0; + break; + } + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_en_5v_usm), value); +} + +static int install_suspend_handler(const struct device *unused) +{ + static struct ap_power_ev_callback cb; + + /* + * Add a callback for suspend/resume. + */ + ap_power_ev_init_callback(&cb, board_suspend_handler, + AP_POWER_RESUME | AP_POWER_SUSPEND); + ap_power_ev_add_callback(&cb); + return 0; +} + +SYS_INIT(install_suspend_handler, APPLICATION, 1); + +static void board_hook_ac_change(void) +{ + if (system_get_board_version() >= 1) { + rt9490_enable_adc(CHARGER_SOLO, extpower_is_present()); + } +} +DECLARE_HOOK(HOOK_AC_CHANGE, board_hook_ac_change, HOOK_PRIO_DEFAULT); +DECLARE_HOOK(HOOK_INIT, board_hook_ac_change, HOOK_PRIO_LAST); diff --git a/zephyr/projects/corsola/src/krabby/i2c.c b/zephyr/projects/corsola/src/krabby/i2c.c new file mode 100644 index 0000000000..a83af77dbd --- /dev/null +++ b/zephyr/projects/corsola/src/krabby/i2c.c @@ -0,0 +1,19 @@ +/* Copyright 2021 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "i2c/i2c.h" +#include "i2c.h" + +/* Krabby board specific i2c implementation */ + +#ifdef CONFIG_PLATFORM_EC_I2C_PASSTHRU_RESTRICTED +int board_allow_i2c_passthru(const struct i2c_cmd_desc_t *cmd_desc) +{ + return (i2c_get_device_for_port(cmd_desc->port) == + i2c_get_device_for_port(I2C_PORT_VIRTUAL_BATTERY) || + i2c_get_device_for_port(cmd_desc->port) == + i2c_get_device_for_port(I2C_PORT_EEPROM)); +} +#endif diff --git a/zephyr/projects/corsola/src/krabby/keyboard_magikarp.c b/zephyr/projects/corsola/src/krabby/keyboard_magikarp.c new file mode 100644 index 0000000000..bcb706bba3 --- /dev/null +++ b/zephyr/projects/corsola/src/krabby/keyboard_magikarp.c @@ -0,0 +1,29 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "ec_commands.h" + +static const struct ec_response_keybd_config magikarp_kb_legacy = { + .num_top_row_keys = 10, + .action_keys = { + TK_BACK, /* T1 */ + TK_REFRESH, /* T2 */ + TK_FULLSCREEN, /* T3 */ + TK_OVERVIEW, /* T4 */ + TK_SNAPSHOT, /* T5 */ + TK_BRIGHTNESS_DOWN, /* T6 */ + TK_BRIGHTNESS_UP, /* T7 */ + TK_VOL_MUTE, /* T8 */ + TK_VOL_DOWN, /* T9 */ + TK_VOL_UP, /* T10 */ + }, + .capabilities = KEYBD_CAP_SCRNLOCK_KEY, +}; + +__override const struct ec_response_keybd_config * +board_vivaldi_keybd_config(void) +{ + return &magikarp_kb_legacy; +} diff --git a/zephyr/projects/corsola/src/krabby/ppc_krabby.c b/zephyr/projects/corsola/src/krabby/ppc_krabby.c new file mode 100644 index 0000000000..d4f574a725 --- /dev/null +++ b/zephyr/projects/corsola/src/krabby/ppc_krabby.c @@ -0,0 +1,31 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Krabby PPC/BC12 (RT1739) configuration */ + +#include "baseboard_usbc_config.h" +#include "gpio/gpio_int.h" +#include "driver/ppc/rt1739.h" +#include "driver/ppc/syv682x.h" +#include "hooks.h" +#include "variant_db_detection.h" + +void c0_bc12_interrupt(enum gpio_signal signal) +{ + rt1739_interrupt(0); +} + +static void board_usbc_init(void) +{ + gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0_ppc_bc12)); +} +DECLARE_HOOK(HOOK_INIT, board_usbc_init, HOOK_PRIO_POST_DEFAULT); + +void ppc_interrupt(enum gpio_signal signal) +{ + if (signal == GPIO_SIGNAL(DT_ALIAS(gpio_usb_c1_ppc_int_odl))) { + syv682x_interrupt(1); + } +} diff --git a/zephyr/projects/corsola/src/krabby/ppc_magikarp.c b/zephyr/projects/corsola/src/krabby/ppc_magikarp.c new file mode 100644 index 0000000000..41cce3f73d --- /dev/null +++ b/zephyr/projects/corsola/src/krabby/ppc_magikarp.c @@ -0,0 +1,44 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Tentacruel PPC/BC12 (mixed RT1739 or PI3USB9201+SYV682X) configuration */ + +#include "baseboard_usbc_config.h" +#include "console.h" +#include "cros_board_info.h" +#include "gpio/gpio_int.h" +#include "hooks.h" +#include "usbc/ppc.h" +#include "variant_db_detection.h" + +#include <zephyr/logging/log.h> + +#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args) + +void bc12_interrupt(enum gpio_signal signal) +{ + usb_charger_task_set_event(0, USB_CHG_EVENT_BC12); +} + +static void board_usbc_init(void) +{ + /* Enable PPC interrupts. */ + gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0_ppc)); + + /* Enable BC1.2 interrupts. */ + gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0_bc12)); +} +DECLARE_HOOK(HOOK_INIT, board_usbc_init, HOOK_PRIO_POST_DEFAULT); + +void ppc_interrupt(enum gpio_signal signal) +{ + if (signal == GPIO_SIGNAL(DT_NODELABEL(usb_c0_ppc_int_odl))) { + syv682x_interrupt(0); + } else if (signal == GPIO_SIGNAL(DT_ALIAS(gpio_usb_c1_ppc_int_odl))) { + syv682x_interrupt(1); + } +} diff --git a/zephyr/projects/corsola/src/krabby/ppc_tentacruel.c b/zephyr/projects/corsola/src/krabby/ppc_tentacruel.c new file mode 100644 index 0000000000..877b9940b4 --- /dev/null +++ b/zephyr/projects/corsola/src/krabby/ppc_tentacruel.c @@ -0,0 +1,89 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Tentacruel PPC/BC12 (mixed RT1739 or PI3USB9201+SYV682X) configuration */ + +#include "baseboard_usbc_config.h" +#include "console.h" +#include "cros_board_info.h" +#include "driver/usb_mux/ps8743.h" +#include "gpio/gpio_int.h" +#include "hooks.h" +#include "usb_mux.h" +#include "usbc/ppc.h" +#include "variant_db_detection.h" + +#include <zephyr/logging/log.h> + +#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args) + +LOG_MODULE_REGISTER(alt_dev_replacement); + +#define BOARD_VERSION_UNKNOWN 0xffffffff + +/* Check board version to decide which ppc/bc12 is used. */ +static bool board_has_syv_ppc(void) +{ + static uint32_t board_version = BOARD_VERSION_UNKNOWN; + + if (board_version == BOARD_VERSION_UNKNOWN) { + if (cbi_get_board_version(&board_version) != EC_SUCCESS) { + LOG_ERR("Failed to get board version."); + board_version = 0; + } + } + + return (board_version >= 3); +} + +static void check_alternate_devices(void) +{ + /* Configure the PPC driver */ + if (board_has_syv_ppc()) + /* Arg is the USB port number */ + PPC_ENABLE_ALTERNATE(0); +} +DECLARE_HOOK(HOOK_INIT, check_alternate_devices, HOOK_PRIO_DEFAULT); + +void bc12_interrupt(enum gpio_signal signal) +{ + usb_charger_task_set_event(0, USB_CHG_EVENT_BC12); +} + +/* USB Mux C1 : board_init of PS8743 */ +int ps8743_eq_c1_setting(void) +{ + ps8743_write(usb_muxes[1].mux, PS8743_REG_USB_EQ_RX, 0x90); + return EC_SUCCESS; +} + +static void board_usbc_init(void) +{ + if (board_has_syv_ppc()) { + /* Enable PPC interrupts. */ + gpio_enable_dt_interrupt( + GPIO_INT_FROM_NODELABEL(int_usb_c0_ppc)); + + /* Enable BC1.2 interrupts. */ + gpio_enable_dt_interrupt( + GPIO_INT_FROM_NODELABEL(int_usb_c0_bc12)); + } else { + gpio_enable_dt_interrupt( + GPIO_INT_FROM_NODELABEL(int_usb_c0_ppc)); + } +} +DECLARE_HOOK(HOOK_INIT, board_usbc_init, HOOK_PRIO_POST_DEFAULT); + +void ppc_interrupt(enum gpio_signal signal) +{ + if (signal == GPIO_SIGNAL(DT_NODELABEL(usb_c0_ppc_int_odl))) { + ppc_chips[0].drv->interrupt(0); + } + if (signal == GPIO_SIGNAL(DT_ALIAS(gpio_usb_c1_ppc_int_odl))) { + ppc_chips[1].drv->interrupt(1); + } +} diff --git a/zephyr/projects/corsola/src/krabby/sensor_magikarp.c b/zephyr/projects/corsola/src/krabby/sensor_magikarp.c new file mode 100644 index 0000000000..269bc26fae --- /dev/null +++ b/zephyr/projects/corsola/src/krabby/sensor_magikarp.c @@ -0,0 +1,41 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "common.h" +#include "accelgyro.h" +#include "cros_cbi.h" +#include "driver/accelgyro_bmi323.h" +#include "driver/accelgyro_icm42607.h" +#include "hooks.h" +#include "motionsense_sensors.h" + +void motion_interrupt(enum gpio_signal signal) +{ + uint32_t val; + + cros_cbi_get_fw_config(FW_BASE_GYRO, &val); + if (val == FW_BASE_ICM42607) { + icm42607_interrupt(signal); + } else if (val == FW_BASE_BMI323) { + bmi3xx_interrupt(signal); + } +} + +static void motionsense_init(void) +{ + uint32_t val; + + cros_cbi_get_fw_config(FW_BASE_GYRO, &val); + if (val == FW_BASE_ICM42607) { + ccprints("BASE ACCEL is ICM42607"); + } else if (val == FW_BASE_BMI323) { + MOTIONSENSE_ENABLE_ALTERNATE(alt_base_accel); + MOTIONSENSE_ENABLE_ALTERNATE(alt_base_gyro); + ccprints("BASE ACCEL IS BMI323"); + } else { + ccprints("no motionsense"); + } +} +DECLARE_HOOK(HOOK_INIT, motionsense_init, HOOK_PRIO_DEFAULT); diff --git a/zephyr/projects/corsola/src/krabby/sensor_tentacruel.c b/zephyr/projects/corsola/src/krabby/sensor_tentacruel.c new file mode 100644 index 0000000000..269bc26fae --- /dev/null +++ b/zephyr/projects/corsola/src/krabby/sensor_tentacruel.c @@ -0,0 +1,41 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "common.h" +#include "accelgyro.h" +#include "cros_cbi.h" +#include "driver/accelgyro_bmi323.h" +#include "driver/accelgyro_icm42607.h" +#include "hooks.h" +#include "motionsense_sensors.h" + +void motion_interrupt(enum gpio_signal signal) +{ + uint32_t val; + + cros_cbi_get_fw_config(FW_BASE_GYRO, &val); + if (val == FW_BASE_ICM42607) { + icm42607_interrupt(signal); + } else if (val == FW_BASE_BMI323) { + bmi3xx_interrupt(signal); + } +} + +static void motionsense_init(void) +{ + uint32_t val; + + cros_cbi_get_fw_config(FW_BASE_GYRO, &val); + if (val == FW_BASE_ICM42607) { + ccprints("BASE ACCEL is ICM42607"); + } else if (val == FW_BASE_BMI323) { + MOTIONSENSE_ENABLE_ALTERNATE(alt_base_accel); + MOTIONSENSE_ENABLE_ALTERNATE(alt_base_gyro); + ccprints("BASE ACCEL IS BMI323"); + } else { + ccprints("no motionsense"); + } +} +DECLARE_HOOK(HOOK_INIT, motionsense_init, HOOK_PRIO_DEFAULT); diff --git a/zephyr/projects/corsola/src/krabby/temp_tentacruel.c b/zephyr/projects/corsola/src/krabby/temp_tentacruel.c new file mode 100644 index 0000000000..59c5a989aa --- /dev/null +++ b/zephyr/projects/corsola/src/krabby/temp_tentacruel.c @@ -0,0 +1,129 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "charger.h" +#include "charge_state.h" +#include "common.h" +#include "config.h" +#include "console.h" +#include "driver/charger/rt9490.h" +#include "hooks.h" +#include "temp_sensor/temp_sensor.h" +#include "thermal.h" +#include "util.h" + +#define NUM_CURRENT_LEVELS ARRAY_SIZE(current_table) +#define TEMP_THRESHOLD 55 +#define TEMP_BUFF_SIZE 60 +#define KEEP_TIME 5 + +BUILD_ASSERT(IS_ENABLED(CONFIG_BOARD_TENTACRUEL) || IS_ENABLED(CONFIG_TEST)); +/* calculate current average temperature */ +static int average_tempature(void) +{ + static int temp_history_buffer[TEMP_BUFF_SIZE]; + static int buff_ptr; + static int temp_sum; + static int past_temp; + static int avg_temp; + int cur_temp, t; + + temp_sensor_read(TEMP_SENSOR_ID(DT_NODELABEL(temp_charger)), &t); + cur_temp = K_TO_C(t); + past_temp = temp_history_buffer[buff_ptr]; + temp_history_buffer[buff_ptr] = cur_temp; + temp_sum = temp_sum + temp_history_buffer[buff_ptr] - past_temp; + buff_ptr++; + if (buff_ptr >= TEMP_BUFF_SIZE) { + buff_ptr = 0; + } + /* Calculate per minute temperature. + * It's expected low temperature when the first 60 seconds. + */ + avg_temp = temp_sum / TEMP_BUFF_SIZE; + return avg_temp; +} + +static int current_level; + +/* Limit charging current table : 3600/3000/2400/1800 + * note this should be in descending order. + */ +static uint16_t current_table[] = { + 3600, + 3000, + 2400, + 1800, +}; + +/* Called by hook task every hook second (1 sec) */ +static void current_update(void) +{ + int temp; + static uint8_t uptime; + static uint8_t dntime; + + temp = average_tempature(); +#ifndef CONFIG_TEST + if (charge_get_state() == PWR_STATE_DISCHARGE) { + current_level = 0; + uptime = 0; + dntime = 0; + return; + } +#endif + if (temp >= TEMP_THRESHOLD) { + dntime = 0; + if (uptime < KEEP_TIME) { + uptime++; + } else { + uptime = 0; + current_level++; + } + } else if (current_level != 0 && temp < TEMP_THRESHOLD) { + uptime = 0; + if (dntime < KEEP_TIME) { + dntime++; + } else { + dntime = 0; + current_level--; + } + } else { + uptime = 0; + dntime = 0; + } + if (current_level > NUM_CURRENT_LEVELS) { + current_level = NUM_CURRENT_LEVELS; + } +} +DECLARE_HOOK(HOOK_SECOND, current_update, HOOK_PRIO_DEFAULT); + +int charger_profile_override(struct charge_state_data *curr) +{ + /* + * Precharge must be executed when communication is failed on + * dead battery. + */ + if (!(curr->batt.flags & BATT_FLAG_RESPONSIVE)) + return 0; + if (current_level != 0) { + if (curr->requested_current > current_table[current_level - 1]) + curr->requested_current = + current_table[current_level - 1]; + } + return 0; +} + +enum ec_status charger_profile_override_get_param(uint32_t param, + uint32_t *value) +{ + return EC_RES_INVALID_PARAM; +} + +enum ec_status charger_profile_override_set_param(uint32_t param, + uint32_t value) +{ + return EC_RES_INVALID_PARAM; +} diff --git a/zephyr/projects/corsola/src/krabby/usb_pd_policy.c b/zephyr/projects/corsola/src/krabby/usb_pd_policy.c new file mode 100644 index 0000000000..8f2a2c3515 --- /dev/null +++ b/zephyr/projects/corsola/src/krabby/usb_pd_policy.c @@ -0,0 +1,88 @@ +/* Copyright 2021 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "adc.h" +#include "charge_manager.h" +#include "chipset.h" +#include "usb_charge.h" +#include "usb_pd.h" +#include "usbc_ppc.h" + +int pd_snk_is_vbus_provided(int port) +{ + static atomic_t vbus_prev[CONFIG_USB_PD_PORT_MAX_COUNT]; + int vbus; + + /* + * (b:181203590#comment20) TODO(yllin): use + * PD_VSINK_DISCONNECT_PD for non-5V case. + */ + vbus = adc_read_channel(board_get_vbus_adc(port)) >= + PD_V_SINK_DISCONNECT_MAX; + +#ifdef CONFIG_USB_CHARGER + /* + * There's no PPC to inform VBUS change for usb_charger, so inform + * the usb_charger now. + */ + if (!!(vbus_prev[port] != vbus)) { + usb_charger_vbus_change(port, vbus); + } + + if (vbus) { + atomic_or(&vbus_prev[port], 1); + } else { + atomic_clear(&vbus_prev[port]); + } +#endif + return vbus; +} + +void pd_power_supply_reset(int port) +{ + int prev_en; + + prev_en = ppc_is_sourcing_vbus(port); + + /* Disable VBUS. */ + ppc_vbus_source_enable(port, 0); + + /* Enable discharge if we were previously sourcing 5V */ + if (prev_en) { + pd_set_vbus_discharge(port, 1); + } + + /* Notify host of power info change. */ + pd_send_host_event(PD_EVENT_POWER_CHANGE); +} + +int pd_set_power_supply_ready(int port) +{ + int rv; + + /* Disable charging. */ + rv = ppc_vbus_sink_enable(port, 0); + if (rv) { + return rv; + } + + pd_set_vbus_discharge(port, 0); + + /* Provide Vbus. */ + rv = ppc_vbus_source_enable(port, 1); + if (rv) { + return rv; + } + + /* Notify host of power info change. */ + pd_send_host_event(PD_EVENT_POWER_CHANGE); + + return EC_SUCCESS; +} + +int board_vbus_source_enabled(int port) +{ + return ppc_is_sourcing_vbus(port); +} diff --git a/zephyr/projects/corsola/src/krabby/usbc_config.c b/zephyr/projects/corsola/src/krabby/usbc_config.c new file mode 100644 index 0000000000..7a7f710804 --- /dev/null +++ b/zephyr/projects/corsola/src/krabby/usbc_config.c @@ -0,0 +1,141 @@ +/* Copyright 2021 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Krabby board-specific USB-C configuration */ + +#include "adc.h" +#include "baseboard_usbc_config.h" +#include "charge_manager.h" +#include "console.h" +#include "driver/tcpm/it83xx_pd.h" +#include "driver/usb_mux/tusb1064.h" +#include "i2c.h" +#include "usb_pd.h" +#include "usbc_ppc.h" + +#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args) + +int tusb1064_mux_1_board_init(const struct usb_mux *me) +{ + int rv; + + rv = i2c_write8(me->i2c_port, me->i2c_addr_flags, + TUSB1064_REG_DP1DP3EQ_SEL, + TUSB1064_DP1EQ(TUSB1064_DP_EQ_RX_8_9_DB) | + TUSB1064_DP3EQ(TUSB1064_DP_EQ_RX_5_4_DB)); + if (rv) + return rv; + + /* Enable EQ_OVERRIDE so the gain registers are used */ + return i2c_update8(me->i2c_port, me->i2c_addr_flags, + TUSB1064_REG_GENERAL, REG_GENERAL_EQ_OVERRIDE, + MASK_SET); +} + +#ifdef CONFIG_USB_PD_TCPM_ITE_ON_CHIP +const struct cc_para_t *board_get_cc_tuning_parameter(enum usbpd_port port) +{ + const static struct cc_para_t + cc_parameter[CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT] = { + { + .rising_time = + IT83XX_TX_PRE_DRIVING_TIME_1_UNIT, + .falling_time = + IT83XX_TX_PRE_DRIVING_TIME_2_UNIT, + }, + { + .rising_time = + IT83XX_TX_PRE_DRIVING_TIME_1_UNIT, + .falling_time = + IT83XX_TX_PRE_DRIVING_TIME_2_UNIT, + }, + }; + + return &cc_parameter[port]; +} +#endif + +void board_reset_pd_mcu(void) +{ + /* + * C0 & C1: TCPC is embedded in the EC and processes interrupts in the + * chip code (it83xx/intc.c) + */ +} + +#ifndef CONFIG_TEST +int board_set_active_charge_port(int port) +{ + int i; + int is_valid_port = (port >= 0 && port < board_get_usb_pd_port_count()); + + if (!is_valid_port && port != CHARGE_PORT_NONE) { + return EC_ERROR_INVAL; + } + + if (port == CHARGE_PORT_NONE) { + CPRINTS("Disabling all charger ports"); + + /* Disable all ports. */ + for (i = 0; i < ppc_cnt; i++) { + /* + * Do not return early if one fails otherwise we can + * get into a boot loop assertion failure. + */ + if (ppc_vbus_sink_enable(i, 0)) { + CPRINTS("Disabling C%d as sink failed.", i); + } + } + + return EC_SUCCESS; + } + + /* Check if the port is sourcing VBUS. */ + if (ppc_is_sourcing_vbus(port)) { + CPRINTS("Skip enable C%d", port); + return EC_ERROR_INVAL; + } + + CPRINTS("New charge port: C%d", port); + + /* + * Turn off the other ports' sink path FETs, before enabling the + * requested charge port. + */ + for (i = 0; i < ppc_cnt; i++) { + if (i == port) { + continue; + } + + if (ppc_vbus_sink_enable(i, 0)) { + CPRINTS("C%d: sink path disable failed.", i); + } + } + + /* Enable requested charge port. */ + if (ppc_vbus_sink_enable(port, 1)) { + CPRINTS("C%d: sink path enable failed.", port); + return EC_ERROR_UNKNOWN; + } + + return EC_SUCCESS; +} +#endif + +#ifdef CONFIG_USB_PD_VBUS_MEASURE_ADC_EACH_PORT +enum adc_channel board_get_vbus_adc(int port) +{ + if (port == 0) { + return ADC_VBUS_C0; + } + if (port == 1) { + return ADC_VBUS_C1; + } + CPRINTSUSB("Unknown vbus adc port id: %d", port); + return ADC_VBUS_C0; +} +#endif /* CONFIG_USB_PD_VBUS_MEASURE_ADC_EACH_PORT */ diff --git a/zephyr/projects/corsola/src/usb_pd_policy.c b/zephyr/projects/corsola/src/usb_pd_policy.c new file mode 100644 index 0000000000..a885362c61 --- /dev/null +++ b/zephyr/projects/corsola/src/usb_pd_policy.c @@ -0,0 +1,226 @@ +/* Copyright 2021 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "atomic.h" +#include "console.h" +#include "chipset.h" +#include "hooks.h" +#include "timer.h" +#include "typec_control.h" +#include "usb_dp_alt_mode.h" +#include "usb_mux.h" +#include "usb_pd.h" +#include "usbc_ppc.h" + +#include "baseboard_usbc_config.h" + +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) + +static int active_aux_port = -1; + +int pd_check_vconn_swap(int port) +{ + /* Allow Vconn swap if AP is on. */ + return chipset_in_state(CHIPSET_STATE_SUSPEND | CHIPSET_STATE_ON); +} + +static void set_dp_aux_path_sel(int port) +{ + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(dp_aux_path_sel), port); + CPRINTS("Set DP_AUX_PATH_SEL: %d", port); +} + +int svdm_get_hpd_gpio(int port) +{ + /* HPD is low active, inverse the result */ + return !gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(ec_ap_dp_hpd_odl)); +} + +static void reset_aux_deferred(void) +{ + if (active_aux_port == -1) + /* reset to 1 for lower power consumption. */ + set_dp_aux_path_sel(1); +} +DECLARE_DEFERRED(reset_aux_deferred); + +void svdm_set_hpd_gpio(int port, int en) +{ + /* + * HPD is low active, inverse the en. + * + * Implement FCFS policy: + * 1) Enable hpd if no active port. + * 2) Disable hpd if active port is the given port. + */ + if (en && active_aux_port < 0) { + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(ec_ap_dp_hpd_odl), 0); + active_aux_port = port; + hook_call_deferred(&reset_aux_deferred_data, -1); + } + + if (!en && active_aux_port == port) { + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(ec_ap_dp_hpd_odl), 1); + active_aux_port = -1; + /* + * This might be a HPD debounce to send a HPD IRQ (500us), so + * do not reset the aux path immediately. Defer this call and + * re-check if this is a real disable. + */ + hook_call_deferred(&reset_aux_deferred_data, 1 * MSEC); + } +} + +__override int svdm_dp_config(int port, uint32_t *payload) +{ + int opos = pd_alt_mode(port, TCPCI_MSG_SOP, USB_SID_DISPLAYPORT); + uint8_t pin_mode = get_dp_pin_mode(port); + mux_state_t mux_mode = svdm_dp_get_mux_mode(port); + int mf_pref = PD_VDO_DPSTS_MF_PREF(dp_status[port]); + + if (!pin_mode) { + return 0; + } + + CPRINTS("pin_mode: %x, mf: %d, mux: %d", pin_mode, mf_pref, mux_mode); + /* + * Defer setting the usb_mux until HPD goes high, svdm_dp_attention(). + * The AP only supports one DP phy. An external DP mux switches between + * the two ports. Should switch those muxes when it is really used, + * i.e. HPD high; otherwise, the real use case is preempted, like: + * (1) plug a dongle without monitor connected to port-0, + * (2) plug a dongle without monitor connected to port-1, + * (3) plug a monitor to the port-1 dongle. + */ + + payload[0] = + VDO(USB_SID_DISPLAYPORT, 1, CMD_DP_CONFIG | VDO_OPOS(opos)); + payload[1] = VDO_DP_CFG(pin_mode, /* pin mode */ + 1, /* DPv1.3 signaling */ + 2); /* UFP connected */ + return 2; +}; + +__override void svdm_dp_post_config(int port) +{ + mux_state_t mux_mode = svdm_dp_get_mux_mode(port); + + typec_set_sbu(port, true); + + /* + * Prior to post-config, the mux will be reset to safe mode, and this + * will break mux config and aux path config we did in the first DP + * status command. Only enable this if the port is the current aux-port. + */ + if (port == active_aux_port) { + usb_mux_set(port, mux_mode, USB_SWITCH_CONNECT, + polarity_rm_dts(pd_get_polarity(port))); + usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL | + USB_PD_MUX_HPD_IRQ_DEASSERTED); + } + + dp_flags[port] |= DP_FLAGS_DP_ON; +} + +int corsola_is_dp_muxable(int port) +{ + int i; + + for (i = 0; i < board_get_usb_pd_port_count(); i++) { + if (i != port) { + if (usb_mux_get(i) & USB_PD_MUX_DP_ENABLED) { + return 0; + } + } + } + + return 1; +} + +__override int svdm_dp_attention(int port, uint32_t *payload) +{ + int lvl = PD_VDO_DPSTS_HPD_LVL(payload[1]); + int irq = PD_VDO_DPSTS_HPD_IRQ(payload[1]); +#ifdef CONFIG_USB_PD_DP_HPD_GPIO + int cur_lvl = svdm_get_hpd_gpio(port); +#endif /* CONFIG_USB_PD_DP_HPD_GPIO */ + mux_state_t mux_state; + + dp_status[port] = payload[1]; + + if (!corsola_is_dp_muxable(port)) { + /* TODO(waihong): Info user? */ + CPRINTS("p%d: The other port is already muxed.", port); + return 0; /* nak */ + } + + if (lvl) { + set_dp_aux_path_sel(port); + + usb_mux_set(port, USB_PD_MUX_DOCK, USB_SWITCH_CONNECT, + polarity_rm_dts(pd_get_polarity(port))); + } else { + usb_mux_set(port, USB_PD_MUX_USB_ENABLED, USB_SWITCH_CONNECT, + polarity_rm_dts(pd_get_polarity(port))); + } + + if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) && (irq || lvl)) { + /* + * Wake up the AP. IRQ or level high indicates a DP sink is now + * present. + */ + if (IS_ENABLED(CONFIG_MKBP_EVENT)) { + pd_notify_dp_alt_mode_entry(port); + } + } + +#ifdef CONFIG_USB_PD_DP_HPD_GPIO + if (irq && !lvl) { + /* + * IRQ can only be generated when the level is high, because + * the IRQ is signaled by a short low pulse from the high level. + */ + CPRINTF("ERR:HPD:IRQ&LOW\n"); + return 0; /* nak */ + } + + if (irq && cur_lvl) { + uint64_t now = get_time().val; + /* wait for the minimum spacing between IRQ_HPD if needed */ + if (now < svdm_hpd_deadline[port]) { + usleep(svdm_hpd_deadline[port] - now); + } + + /* generate IRQ_HPD pulse */ + svdm_set_hpd_gpio(port, 0); + /* + * b/171172053#comment14: since the HPD_DSTREAM_DEBOUNCE_IRQ is + * very short (500us), we can use udelay instead of usleep for + * more stable pulse period. + */ + udelay(HPD_DSTREAM_DEBOUNCE_IRQ); + svdm_set_hpd_gpio(port, 1); + } else { + svdm_set_hpd_gpio(port, lvl); + } + + /* set the minimum time delay (2ms) for the next HPD IRQ */ + svdm_hpd_deadline[port] = get_time().val + HPD_USTREAM_DEBOUNCE_LVL; +#endif /* CONFIG_USB_PD_DP_HPD_GPIO */ + + mux_state = (lvl ? USB_PD_MUX_HPD_LVL : USB_PD_MUX_HPD_LVL_DEASSERTED) | + (irq ? USB_PD_MUX_HPD_IRQ : USB_PD_MUX_HPD_IRQ_DEASSERTED); + usb_mux_hpd_update(port, mux_state); + +#ifdef USB_PD_PORT_TCPC_MST + if (port == USB_PD_PORT_TCPC_MST) { + baseboard_mst_enable_control(port, lvl); + } +#endif + + /* ack */ + return 1; +} diff --git a/zephyr/projects/corsola/src/usbc_config.c b/zephyr/projects/corsola/src/usbc_config.c new file mode 100644 index 0000000000..e3a2796de5 --- /dev/null +++ b/zephyr/projects/corsola/src/usbc_config.c @@ -0,0 +1,319 @@ +/* Copyright 2021 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Corsola baseboard-specific USB-C configuration */ + +#include <zephyr/drivers/gpio.h> +#include <ap_power/ap_power.h> + +#include "adc.h" +#include "baseboard_usbc_config.h" +#include "button.h" +#include "charger.h" +#include "charge_state_v2.h" +#include "console.h" +#include "ec_commands.h" +#include "extpower.h" +#include "gpio/gpio_int.h" +#include "hooks.h" +#include "i2c.h" +#include "lid_switch.h" +#include "task.h" +#include "ppc/syv682x_public.h" +#include "power.h" +#include "power_button.h" +#include "spi.h" +#include "switch.h" +#include "tablet_mode.h" +#include "uart.h" +#include "usb_charge.h" +#include "usb_mux.h" +#include "usb_pd_tcpm.h" +#include "usb_tc_sm.h" +#include "usbc/usb_muxes.h" +#include "usbc_ppc.h" + +#include "variant_db_detection.h" + +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args) + +/* a flag for indicating the tasks are inited. */ +static bool tasks_inited; + +/* Baseboard */ +static void baseboard_init(void) +{ +#ifdef CONFIG_VARIANT_CORSOLA_USBA + gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usba)); +#endif + /* If CCD mode has enabled before init, force the ccd_interrupt. */ + if (!gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_ccd_mode_odl))) { + ccd_interrupt(GPIO_CCD_MODE_ODL); + } + gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_ccd_mode_odl)); +} +DECLARE_HOOK(HOOK_INIT, baseboard_init, HOOK_PRIO_PRE_DEFAULT); + +__override uint8_t board_get_usb_pd_port_count(void) +{ + if (corsola_get_db_type() == CORSOLA_DB_HDMI) { + if (tasks_inited) { + return CONFIG_USB_PD_PORT_MAX_COUNT; + } else { + return CONFIG_USB_PD_PORT_MAX_COUNT - 1; + } + } else if (corsola_get_db_type() == CORSOLA_DB_NONE) { + return CONFIG_USB_PD_PORT_MAX_COUNT - 1; + } + + return CONFIG_USB_PD_PORT_MAX_COUNT; +} + +/* USB-A */ +void usb_a0_interrupt(enum gpio_signal signal) +{ + enum usb_charge_mode mode = gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL( + gpio_ap_xhci_init_done)) ? + USB_CHARGE_MODE_ENABLED : + USB_CHARGE_MODE_DISABLED; + + const int xhci_stat = gpio_get_level(signal); + + for (int i = 0; i < USB_PORT_COUNT; i++) { + usb_charge_set_mode(i, mode, USB_ALLOW_SUSPEND_CHARGE); + } + + for (int i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) { + /* + * Enable DRP toggle after XHCI inited. This is used to follow + * USB 3.2 spec 10.3.1.1. + */ + if (xhci_stat) { + pd_set_dual_role(i, PD_DRP_TOGGLE_ON); + } else if (tc_is_attached_src(i)) { + /* + * This is a AP reset S0->S0 transition. + * We should set the role back to sink. + */ + pd_set_dual_role(i, PD_DRP_FORCE_SINK); + } + } +} + +__override enum pd_dual_role_states pd_get_drp_state_in_s0(void) +{ + if (gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_ap_xhci_init_done))) { + return PD_DRP_TOGGLE_ON; + } else { + return PD_DRP_FORCE_SINK; + } +} + +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) +{ + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); +} + +void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled) +{ + /* + * We ignore the cc_pin and PPC vconn because polarity and PPC vconn + * should already be set correctly in the PPC driver via the pd + * state machine. + */ +} + +/** + * Handle PS185 HPD changing state. + */ +int debounced_hpd; + +static void ps185_hdmi_hpd_deferred(void) +{ + const int new_hpd = + gpio_pin_get_dt(GPIO_DT_FROM_ALIAS(gpio_ps185_ec_dp_hpd)); + + /* HPD status not changed, probably a glitch, just return. */ + if (debounced_hpd == new_hpd) { + return; + } + + debounced_hpd = new_hpd; + + if (!corsola_is_dp_muxable(USBC_PORT_C1)) { + if (debounced_hpd) { + CPRINTS("C0 port is already muxed."); + } + return; + } + + if (debounced_hpd) { + dp_status[USBC_PORT_C1] = + VDO_DP_STATUS(0, /* HPD IRQ ... not applicable */ + 0, /* HPD level ... not applicable */ + 0, /* exit DP? ... no */ + 0, /* usb mode? ... no */ + 0, /* multi-function ... no */ + 1, /* DP enabled ... yes */ + 0, /* power low? ... no */ + (!!DP_FLAGS_DP_ON)); + /* update C1 virtual mux */ + usb_mux_set(USBC_PORT_C1, USB_PD_MUX_DP_ENABLED, + USB_SWITCH_DISCONNECT, + 0 /* polarity, don't care */); + + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(dp_aux_path_sel), + debounced_hpd); + CPRINTS("Set DP_AUX_PATH_SEL: %d", 1); + } + svdm_set_hpd_gpio(USBC_PORT_C1, debounced_hpd); + CPRINTS(debounced_hpd ? "HDMI plug" : "HDMI unplug"); +} +DECLARE_DEFERRED(ps185_hdmi_hpd_deferred); + +static void ps185_hdmi_hpd_disconnect_deferred(void) +{ + const int new_hpd = + gpio_pin_get_dt(GPIO_DT_FROM_ALIAS(gpio_ps185_ec_dp_hpd)); + + if (debounced_hpd == new_hpd && !new_hpd) { + dp_status[USBC_PORT_C1] = + VDO_DP_STATUS(0, /* HPD IRQ ... not applicable */ + 0, /* HPD level ... not applicable */ + 0, /* exit DP? ... no */ + 0, /* usb mode? ... no */ + 0, /* multi-function ... no */ + 0, /* DP enabled ... no */ + 0, /* power low? ... no */ + (!DP_FLAGS_DP_ON)); + usb_mux_set(USBC_PORT_C1, USB_PD_MUX_NONE, + USB_SWITCH_DISCONNECT, + 0 /* polarity, don't care */); + } +} +DECLARE_DEFERRED(ps185_hdmi_hpd_disconnect_deferred); + +#define PS185_HPD_DEBOUCE 250 +#define HPD_SINK_ABSENCE_DEBOUNCE (2 * MSEC) + +static void hdmi_hpd_interrupt(enum gpio_signal signal) +{ + hook_call_deferred(&ps185_hdmi_hpd_deferred_data, PS185_HPD_DEBOUCE); + + if (!gpio_pin_get_dt(GPIO_DT_FROM_ALIAS(gpio_ps185_ec_dp_hpd))) { + hook_call_deferred(&ps185_hdmi_hpd_disconnect_deferred_data, + HPD_SINK_ABSENCE_DEBOUNCE); + } else { + hook_call_deferred(&ps185_hdmi_hpd_disconnect_deferred_data, + -1); + } +} + +/* HDMI/TYPE-C function shared subboard interrupt */ +void x_ec_interrupt(enum gpio_signal signal) +{ + int sub = corsola_get_db_type(); + + if (sub == CORSOLA_DB_TYPEC) { + /* C1: PPC interrupt */ + ppc_interrupt(signal); + } else if (sub == CORSOLA_DB_HDMI) { + hdmi_hpd_interrupt(signal); + } else { + CPRINTS("Undetected subboard interrupt."); + } +} + +static void board_hdmi_handler(struct ap_power_ev_callback *cb, + struct ap_power_ev_data data) +{ + int value; + + switch (data.event) { + default: + return; + + case AP_POWER_RESUME: + value = 1; + break; + + case AP_POWER_SUSPEND: + value = 0; + break; + } + gpio_pin_set_dt(GPIO_DT_FROM_ALIAS(gpio_en_hdmi_pwr), value); + gpio_pin_set_dt(GPIO_DT_FROM_ALIAS(gpio_ps185_pwrdn_odl), value); +} + +static void tasks_init_deferred(void) +{ + tasks_inited = true; +} +DECLARE_DEFERRED(tasks_init_deferred); + +static void baseboard_x_ec_gpio2_init(void) +{ + static struct ppc_drv virtual_ppc_drv = { 0 }; + static struct tcpm_drv virtual_tcpc_drv = { 0 }; + static struct bc12_drv virtual_bc12_drv = { 0 }; + + /* no sub board */ + if (corsola_get_db_type() == CORSOLA_DB_NONE) { + return; + } + + /* type-c: USB_C1_PPC_INT_ODL / hdmi: PS185_EC_DP_HPD */ + gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_x_ec_gpio2)); + + if (corsola_get_db_type() == CORSOLA_DB_TYPEC) { + gpio_pin_interrupt_configure_dt( + GPIO_DT_FROM_ALIAS(gpio_usb_c1_ppc_int_odl), + GPIO_INT_EDGE_FALLING); + return; + } + if (corsola_get_db_type() == CORSOLA_DB_HDMI) { + static struct ap_power_ev_callback cb; + + ap_power_ev_init_callback(&cb, board_hdmi_handler, + AP_POWER_RESUME | AP_POWER_SUSPEND); + ap_power_ev_add_callback(&cb); + } + + /* drop related C1 port drivers when it's a HDMI DB. */ + ppc_chips[USBC_PORT_C1] = + (const struct ppc_config_t){ .drv = &virtual_ppc_drv }; + tcpc_config[USBC_PORT_C1] = + (const struct tcpc_config_t){ .drv = &virtual_tcpc_drv }; + bc12_ports[USBC_PORT_C1] = + (const struct bc12_config){ .drv = &virtual_bc12_drv }; + /* Use virtual mux to notify AP the mainlink direction. */ + USB_MUX_ENABLE_ALTERNATIVE(usb_mux_chain_1_hdmi_db); + + /* + * If a HDMI DB is attached, C1 port tasks will be exiting in that + * the port number is larger than board_get_usb_pd_port_count(). + * After C1 port tasks finished, we intentionally increase the port + * count by 1 for usb_mux to access the C1 virtual mux for notifying + * mainlink direction. + */ + hook_call_deferred(&tasks_init_deferred_data, 2 * SECOND); +} +DECLARE_HOOK(HOOK_INIT, baseboard_x_ec_gpio2_init, HOOK_PRIO_DEFAULT); + +__override uint8_t get_dp_pin_mode(int port) +{ + if (corsola_get_db_type() == CORSOLA_DB_HDMI && port == USBC_PORT_C1) { + if (usb_mux_get(USBC_PORT_C1) & USB_PD_MUX_DP_ENABLED) { + return MODE_DP_PIN_E; + } else { + return 0; + } + } + + return pd_dfp_dp_get_pin_mode(port, dp_status[port]); +} diff --git a/zephyr/projects/corsola/src/variant_db_detection.c b/zephyr/projects/corsola/src/variant_db_detection.c new file mode 100644 index 0000000000..6099d86bdd --- /dev/null +++ b/zephyr/projects/corsola/src/variant_db_detection.c @@ -0,0 +1,115 @@ +/* Copyright 2021 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Corsola daughter board detection */ +#include <zephyr/drivers/gpio.h> + +#include "console.h" +#include "cros_cbi.h" +#include "gpio/gpio_int.h" +#include "hooks.h" + +#include "variant_db_detection.h" + +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args) + +static void corsola_db_config(enum corsola_db_type type) +{ + switch (type) { + case CORSOLA_DB_HDMI: + /* EC_X_GPIO1 */ + gpio_pin_configure_dt(GPIO_DT_FROM_ALIAS(gpio_en_hdmi_pwr), + GPIO_OUTPUT_HIGH); + /* X_EC_GPIO2 */ + gpio_pin_configure_dt(GPIO_DT_FROM_ALIAS(gpio_ps185_ec_dp_hpd), + GPIO_INPUT); + gpio_enable_dt_interrupt( + GPIO_INT_FROM_NODELABEL(int_x_ec_gpio2)); + /* EC_X_GPIO3 */ + gpio_pin_configure_dt(GPIO_DT_FROM_ALIAS(gpio_ps185_pwrdn_odl), + GPIO_OUTPUT_HIGH | GPIO_OPEN_DRAIN); + return; + case CORSOLA_DB_TYPEC: + /* EC_X_GPIO1 */ + gpio_pin_configure_dt(GPIO_DT_FROM_ALIAS(gpio_usb_c1_frs_en), + GPIO_OUTPUT_LOW); + /* X_EC_GPIO2 */ + gpio_pin_configure_dt( + GPIO_DT_FROM_ALIAS(gpio_usb_c1_ppc_int_odl), + GPIO_INPUT | GPIO_PULL_UP); + gpio_enable_dt_interrupt( + GPIO_INT_FROM_NODELABEL(int_x_ec_gpio2)); + /* EC_X_GPIO3 */ + gpio_pin_configure_dt(GPIO_DT_FROM_ALIAS(gpio_usb_c1_dp_in_hpd), + GPIO_OUTPUT_LOW); + return; + case CORSOLA_DB_NONE: + /* Set floating pins as input with PU to prevent leakage */ + gpio_pin_configure_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_x_gpio1), + GPIO_INPUT | GPIO_PULL_UP); + gpio_pin_configure_dt(GPIO_DT_FROM_NODELABEL(gpio_x_ec_gpio2), + GPIO_INPUT | GPIO_PULL_UP); + gpio_pin_configure_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_x_gpio3), + GPIO_INPUT | GPIO_PULL_UP); + return; + default: + break; + } +} + +enum corsola_db_type corsola_get_db_type(void) +{ +#if DT_NODE_EXISTS(DT_NODELABEL(db_config)) + int ret; + uint32_t val; +#endif + static enum corsola_db_type db = CORSOLA_DB_UNINIT; + + if (db != CORSOLA_DB_UNINIT) { + return db; + } + + if (!gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_hdmi_prsnt_odl))) { + db = CORSOLA_DB_HDMI; + } else { + db = CORSOLA_DB_TYPEC; + } + +/* Detect for no sub board case by FW_CONFIG */ +#if DT_NODE_EXISTS(DT_NODELABEL(db_config)) + ret = cros_cbi_get_fw_config(DB, &val); + if (ret != 0) { + CPRINTS("Error retrieving CBI FW_CONFIG field %d", DB); + } else if (val == DB_NONE) { + db = CORSOLA_DB_NONE; + } +#endif + + corsola_db_config(db); + + switch (db) { + case CORSOLA_DB_NONE: + CPRINTS("Detect %s DB", "NONE"); + break; + case CORSOLA_DB_TYPEC: + CPRINTS("Detect %s DB", "TYPEC"); + break; + case CORSOLA_DB_HDMI: + CPRINTS("Detect %s DB", "HDMI"); + break; + default: + CPRINTS("DB UNINIT"); + break; + } + + return db; +} + +static void corsola_db_init(void) +{ + corsola_get_db_type(); +} +DECLARE_HOOK(HOOK_INIT, corsola_db_init, HOOK_PRIO_PRE_I2C); diff --git a/zephyr/projects/corsola/thermistor_tentacruel.dts b/zephyr/projects/corsola/thermistor_tentacruel.dts new file mode 100644 index 0000000000..f9e5306f24 --- /dev/null +++ b/zephyr/projects/corsola/thermistor_tentacruel.dts @@ -0,0 +1,140 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + thermistor_rt9490: thermistor-rt9490 { + status = "okay"; + compatible = "cros-ec,thermistor"; + scaling-factor = <3>; + num-pairs = <21>; + steinhart-reference-mv = <4900>; + steinhart-reference-res = <10000>; + + sample-datum-0 { + milivolt = <(731 / 3)>; + temp = <0>; + sample-index = <0>; + }; + + sample-datum-1 { + milivolt = <(708 / 3)>; + temp = <5>; + sample-index = <1>; + }; + + sample-datum-2 { + milivolt = <(682 / 3)>; + temp = <10>; + sample-index = <2>; + }; + + sample-datum-3 { + milivolt = <(653 / 3)>; + temp = <15>; + sample-index = <3>; + }; + + sample-datum-4 { + milivolt = <(622 / 3)>; + temp = <20>; + sample-index = <4>; + }; + + sample-datum-5 { + milivolt = <(589 / 3)>; + temp = <25>; + sample-index = <5>; + }; + + sample-datum-6 { + milivolt = <(554 / 3)>; + temp = <30>; + sample-index = <6>; + }; + + sample-datum-7 { + milivolt = <(519 / 3)>; + temp = <35>; + sample-index = <7>; + }; + + sample-datum-8 { + milivolt = <(483 / 3)>; + temp = <40>; + sample-index = <8>; + }; + + sample-datum-9 { + milivolt = <(446 / 3)>; + temp = <45>; + sample-index = <9>; + }; + + sample-datum-10 { + milivolt = <(411 / 3)>; + temp = <50>; + sample-index = <10>; + }; + sample-datum-11 { + milivolt = <(376 / 3)>; + temp = <55>; + sample-index = <11>; + }; + + sample-datum-12 { + milivolt = <(343 / 3)>; + temp = <60>; + sample-index = <12>; + }; + + sample-datum-13 { + milivolt = <(312 / 3)>; + temp = <65>; + sample-index = <13>; + }; + + sample-datum-14 { + milivolt = <(284 / 3)>; + temp = <70>; + sample-index = <14>; + }; + + sample-datum-15 { + milivolt = <(257 / 3)>; + temp = <75>; + sample-index = <15>; + }; + + sample-datum-16 { + milivolt = <(232 / 3)>; + temp = <80>; + sample-index = <16>; + }; + + sample-datum-17 { + milivolt = <(209 / 3)>; + temp = <85>; + sample-index = <17>; + }; + + sample-datum-18 { + milivolt = <(188 / 3)>; + temp = <90>; + sample-index = <18>; + }; + + sample-datum-19 { + milivolt = <(169 / 3)>; + temp = <95>; + sample-index = <19>; + }; + + sample-datum-20 { + milivolt = <(152 / 3)>; + temp = <100>; + sample-index = <20>; + }; + }; +}; diff --git a/zephyr/projects/corsola/usba.dts b/zephyr/projects/corsola/usba.dts new file mode 100644 index 0000000000..2ecb3b7d5a --- /dev/null +++ b/zephyr/projects/corsola/usba.dts @@ -0,0 +1,11 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + usba_port_enable_list: usba-port-enable-list { + compatible = "cros-ec,usba-port-enable-pins"; + enable-pins = <&en_pp5000_usb_a0_vbus>; + }; +}; diff --git a/zephyr/projects/corsola/usba_steelix.dts b/zephyr/projects/corsola/usba_steelix.dts new file mode 100644 index 0000000000..0ddd67f664 --- /dev/null +++ b/zephyr/projects/corsola/usba_steelix.dts @@ -0,0 +1,10 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* steelix usba port enable config */ +&usba_port_enable_list { + enable-pins = <&en_pp5000_usb_a0_vbus + &en_pp5000_usb_a1_vbus>; +}; diff --git a/zephyr/projects/corsola/usbc_kingler.dts b/zephyr/projects/corsola/usbc_kingler.dts new file mode 100644 index 0000000000..18bc6ce303 --- /dev/null +++ b/zephyr/projects/corsola/usbc_kingler.dts @@ -0,0 +1,56 @@ +/* Copyright 2021 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + usbc { + #address-cells = <1>; + #size-cells = <0>; + + port0@0 { + compatible = "named-usbc-port"; + reg = <0>; + bc12 = <&bc12_port0>; + tcpc = <&tcpc_port0>; + ppc = <&ppc_port0>; + chg = <&charger>; + usb-mux-chain-0 { + compatible = "cros-ec,usb-mux-chain"; + usb-muxes = <&anx7447_mux_0 &virtual_mux_0>; + }; + }; + + port0-muxes { + anx7447_mux_0: anx7447-mux-0 { + compatible = "analogix,usbc-mux-anx7447"; + }; + virtual_mux_0: virtual-mux-0 { + compatible = "cros-ec,usbc-mux-virtual"; + }; + }; + + port1@1 { + compatible = "named-usbc-port"; + reg = <1>; + bc12 = <&bc12_port1>; + tcpc = <&tcpc_port1>; + ppc = <&ppc_port1>; + usb-mux-chain-0 { + compatible = "cros-ec,usb-mux-chain"; + usb-muxes = <&ps8743_mux_1 &virtual_mux_1>; + }; + usb_mux_chain_1_hdmi_db: usb-mux-chain-1-hdmi-db { + compatible = "cros-ec,usb-mux-chain"; + alternative-chain; + usb-muxes = <&virtual_mux_1>; + }; + }; + + port1-muxes { + virtual_mux_1: virtual-mux-1 { + compatible = "cros-ec,usbc-mux-virtual"; + }; + }; + }; +}; diff --git a/zephyr/projects/corsola/usbc_krabby.dts b/zephyr/projects/corsola/usbc_krabby.dts new file mode 100644 index 0000000000..a72864da35 --- /dev/null +++ b/zephyr/projects/corsola/usbc_krabby.dts @@ -0,0 +1,59 @@ +/* Copyright 2021 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + usbc { + #address-cells = <1>; + #size-cells = <0>; + + port0@0 { + compatible = "named-usbc-port"; + reg = <0>; + bc12 = <&bc12_ppc_port0>; + ppc = <&bc12_ppc_port0>; + tcpc = <&usbpd0>; + chg = <&charger>; + usb-mux-chain-0 { + compatible = "cros-ec,usb-mux-chain"; + usb-muxes = <&it5205_mux_0 &virtual_mux_0>; + }; + }; + port0-muxes { + virtual_mux_0: virtual-mux-0 { + compatible = "cros-ec,usbc-mux-virtual"; + }; + }; + + port1@1 { + compatible = "named-usbc-port"; + reg = <1>; + bc12 = <&bc12_port1>; + ppc = <&ppc_port1>; + tcpc = <&usbpd1>; + usb-mux-chain-1 { + compatible = "cros-ec,usb-mux-chain"; + usb-muxes = <&tusb1064_mux_1 &virtual_mux_1>; + }; + usb_mux_chain_1_hdmi_db: usb-mux-chain-1-hdmi-db { + compatible = "cros-ec,usb-mux-chain"; + alternative-chain; + usb-muxes = <&virtual_mux_1>; + }; + }; + port1-muxes { + virtual_mux_1: virtual-mux-1 { + compatible = "cros-ec,usbc-mux-virtual"; + }; + }; + }; +}; + +&usbpd0 { + status = "okay"; +}; + +&usbpd1 { + status = "okay"; +}; diff --git a/zephyr/projects/corsola/usbc_magikarp.dts b/zephyr/projects/corsola/usbc_magikarp.dts new file mode 100644 index 0000000000..c94db15b3a --- /dev/null +++ b/zephyr/projects/corsola/usbc_magikarp.dts @@ -0,0 +1,59 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + usbc { + #address-cells = <1>; + #size-cells = <0>; + + port0@0 { + compatible = "named-usbc-port"; + reg = <0>; + bc12 = <&bc12_port0>; + ppc = <&ppc_port0>; + tcpc = <&usbpd0>; + chg = <&charger>; + usb-mux-chain-0 { + compatible = "cros-ec,usb-mux-chain"; + usb-muxes = <&it5205_mux_0 &virtual_mux_0>; + }; + }; + port0-muxes { + virtual_mux_0: virtual-mux-0 { + compatible = "cros-ec,usbc-mux-virtual"; + }; + }; + + port1@1 { + compatible = "named-usbc-port"; + reg = <1>; + bc12 = <&bc12_port1>; + ppc = <&ppc_port1>; + tcpc = <&usbpd1>; + usb-mux-chain-1 { + compatible = "cros-ec,usb-mux-chain"; + usb-muxes = <&ps8743_mux_1 &virtual_mux_1>; + }; + usb_mux_chain_1_hdmi_db: usb-mux-chain-1-hdmi-db { + compatible = "cros-ec,usb-mux-chain"; + alternative-chain; + usb-muxes = <&virtual_mux_1>; + }; + }; + port1-muxes { + virtual_mux_1: virtual-mux-1 { + compatible = "cros-ec,usbc-mux-virtual"; + }; + }; + }; +}; + +&usbpd0 { + status = "okay"; +}; + +&usbpd1 { + status = "okay"; +}; diff --git a/zephyr/projects/corsola/usbc_tentacruel.dts b/zephyr/projects/corsola/usbc_tentacruel.dts new file mode 100644 index 0000000000..bb105a8e08 --- /dev/null +++ b/zephyr/projects/corsola/usbc_tentacruel.dts @@ -0,0 +1,60 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + usbc { + #address-cells = <1>; + #size-cells = <0>; + + port0@0 { + compatible = "named-usbc-port"; + reg = <0>; + bc12 = <&bc12_port0>; + ppc = <&bc12_ppc_port0>; + ppc_alt = <&ppc_port0>; + tcpc = <&usbpd0>; + chg = <&charger>; + usb-mux-chain-0 { + compatible = "cros-ec,usb-mux-chain"; + usb-muxes = <&it5205_mux_0 &virtual_mux_0>; + }; + }; + port0-muxes { + virtual_mux_0: virtual-mux-0 { + compatible = "cros-ec,usbc-mux-virtual"; + }; + }; + + port1@1 { + compatible = "named-usbc-port"; + reg = <1>; + bc12 = <&bc12_port1>; + ppc = <&ppc_port1>; + tcpc = <&usbpd1>; + usb-mux-chain-1 { + compatible = "cros-ec,usb-mux-chain"; + usb-muxes = <&ps8743_mux_1 &virtual_mux_1>; + }; + usb_mux_chain_1_hdmi_db: usb-mux-chain-1-hdmi-db { + compatible = "cros-ec,usb-mux-chain"; + alternative-chain; + usb-muxes = <&virtual_mux_1>; + }; + }; + port1-muxes { + virtual_mux_1: virtual-mux-1 { + compatible = "cros-ec,usbc-mux-virtual"; + }; + }; + }; +}; + +&usbpd0 { + status = "okay"; +}; + +&usbpd1 { + status = "okay"; +}; diff --git a/zephyr/projects/herobrine/BUILD.py b/zephyr/projects/herobrine/BUILD.py new file mode 100644 index 0000000000..d38803deb7 --- /dev/null +++ b/zephyr/projects/herobrine/BUILD.py @@ -0,0 +1,124 @@ +# Copyright 2021 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +"""Define zmake projects for herobrine.""" + + +def register_variant( + project_name, extra_dts_overlays=(), extra_kconfig_files=() +): + """Register a variant of herobrine.""" + register_npcx_project( + project_name=project_name, + zephyr_board="npcx9m3f", + dts_overlays=[ + # Common to all projects. + here / "adc.dts", + here / "common.dts", + here / "interrupts.dts", + here / "keyboard.dts", + here / "default_gpio_pinctrl.dts", + # Project-specific DTS customization. + *extra_dts_overlays, + ], + kconfig_files=[ + # Common to all projects. + here / "prj.conf", + # Project-specific KConfig customization. + *extra_kconfig_files, + ], + ) + + +register_variant( + project_name="evoker", + extra_dts_overlays=[ + here / "display.dts", + here / "battery_evoker.dts", + here / "gpio_evoker.dts", + here / "i2c_evoker.dts", + here / "led_pins_evoker.dts", + here / "led_policy_evoker.dts", + here / "motionsense_evoker.dts", + here / "switchcap.dts", + here / "usbc_evoker.dts", + ], + extra_kconfig_files=[here / "prj_evoker.conf"], +) + +register_variant( + project_name="herobrine", + extra_dts_overlays=[ + here / "display.dts", + here / "battery_herobrine.dts", + here / "gpio.dts", + here / "i2c_herobrine.dts", + here / "led_pins_herobrine.dts", + here / "led_policy_herobrine.dts", + here / "motionsense.dts", + here / "switchcap.dts", + here / "usbc_herobrine.dts", + ], + extra_kconfig_files=[here / "prj_herobrine.conf"], +) + +register_variant( + project_name="hoglin", + extra_dts_overlays=[ + here / "battery_hoglin.dts", + here / "gpio_hoglin.dts", + here / "i2c_hoglin.dts", + here / "led_pins_hoglin.dts", + here / "led_policy_hoglin.dts", + here / "motionsense_hoglin.dts", + here / "switchcap_hoglin.dts", + here / "usbc_hoglin.dts", + ], + extra_kconfig_files=[here / "prj_hoglin.conf"], +) + +register_variant( + project_name="villager", + extra_dts_overlays=[ + here / "battery_villager.dts", + here / "gpio_villager.dts", + here / "i2c_villager.dts", + here / "led_pins_villager.dts", + here / "led_policy_villager.dts", + here / "motionsense_villager.dts", + here / "switchcap.dts", + here / "usbc_villager.dts", + ], + extra_kconfig_files=[here / "prj_villager.conf"], +) + +register_variant( + project_name="zoglin", + extra_dts_overlays=[ + here / "battery_hoglin.dts", + here / "gpio_hoglin.dts", + here / "i2c_hoglin.dts", + here / "led_pins_hoglin.dts", + here / "led_policy_hoglin.dts", + here / "motionsense_hoglin.dts", + here / "switchcap_hoglin.dts", + here / "usbc_hoglin.dts", + ], + extra_kconfig_files=[here / "prj_zoglin.conf"], +) + +register_variant( + project_name="zombie", + extra_dts_overlays=[ + here / "battery_zombie.dts", + here / "gpio_zombie.dts", + here / "i2c_zombie.dts", + here / "led_pins_zombie.dts", + here / "led_policy_zombie.dts", + here / "motionsense_zombie.dts", + here / "switchcap.dts", + here / "usbc_zombie.dts", + ], + extra_kconfig_files=[here / "prj_zombie.conf"], +) diff --git a/zephyr/projects/herobrine/CMakeLists.txt b/zephyr/projects/herobrine/CMakeLists.txt new file mode 100644 index 0000000000..a7e2fc6cf6 --- /dev/null +++ b/zephyr/projects/herobrine/CMakeLists.txt @@ -0,0 +1,37 @@ +# Copyright 2021 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +cmake_minimum_required(VERSION 3.13.1) + +find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}") + +cros_ec_library_include_directories(include) + +# Common Herobrine implementation +zephyr_library_sources( + "src/board_chipset.c" +) + +# Board specific implementation +zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC + "src/usbc_config.c" + "src/usb_pd_policy.c") +zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_I2C + "src/i2c.c") + +if(DEFINED CONFIG_BOARD_EVOKER) + project(evoker) +elseif(DEFINED CONFIG_BOARD_HEROBRINE) + project(herobrine) + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC + "src/herobrine/alt_dev_replacement.c") +elseif(DEFINED CONFIG_BOARD_HOGLIN) + project(hoglin) +elseif(DEFINED CONFIG_BOARD_VILLAGER) + project(villager) +elseif(DEFINED CONFIG_BOARD_ZOGLIN) + project(zoglin) +elseif(DEFINED CONFIG_BOARD_ZOMBIE) + project(zombie) +endif() diff --git a/zephyr/projects/herobrine/Kconfig b/zephyr/projects/herobrine/Kconfig new file mode 100644 index 0000000000..d0056288d5 --- /dev/null +++ b/zephyr/projects/herobrine/Kconfig @@ -0,0 +1,41 @@ +# Copyright 2022 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +config BOARD_EVOKER + bool "Evoker Board" + help + Build the Evoker board. The board is based on the Herobrine + reference design. + +config BOARD_HEROBRINE + bool "Google Herobrine Baseboard" + help + Build Google Herobrine reference board. The board uses Nuvoton + NPCX9 chip as the EC. + +config BOARD_HOGLIN + bool "Qualcomm Hoglin Baseboard" + help + Build Qualcomm Hoglin reference board. The board uses Nuvoton + NPCX9 chip as the EC. + +config BOARD_VILLAGER + bool "Villager Board" + help + Build the Villager board. The board is based on the Herobrine + reference design. + +config BOARD_ZOGLIN + bool "Qualcomm Zoglin Baseboard" + help + Build Qualcomm Zoglin reference board. The board uses Nuvoton + NPCX9 chip as the EC. + +config BOARD_ZOMBIE + bool "Zombie Board" + help + Build the Zombie board. The board is based on the Herobrine + reference design. + +source "Kconfig.zephyr" diff --git a/zephyr/projects/herobrine/adc.dts b/zephyr/projects/herobrine/adc.dts new file mode 100644 index 0000000000..16a5434e9d --- /dev/null +++ b/zephyr/projects/herobrine/adc.dts @@ -0,0 +1,47 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <zephyr/dt-bindings/adc/adc.h> + +/ { + named-adc-channels { + compatible = "named-adc-channels"; + + vbus { + enum-name = "ADC_VBUS"; + io-channels = <&adc0 1>; + /* Measure VBUS through a 1/10 voltage divider */ + mul = <10>; + }; + amon_bmon { + enum-name = "ADC_AMON_BMON"; + io-channels = <&adc0 2>; + /* + * Adapter current output or battery charging/ + * discharging current (uV) 18x amplification on + * charger side. + */ + mul = <1000>; + div = <18>; + }; + psys { + enum-name = "ADC_PSYS"; + io-channels = <&adc0 3>; + /* + * ISL9238 PSYS output is 1.44 uA/W over 5.6K resistor, + * to read 0.8V @ 99 W, i.e. 124000 uW/mV. + */ + mul = <124000>; + }; + }; +}; + +&adc0 { + status = "okay"; + pinctrl-0 = <&adc0_chan1_gp44 + &adc0_chan2_gp43 + &adc0_chan3_gp42>; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/herobrine/battery_evoker.dts b/zephyr/projects/herobrine/battery_evoker.dts new file mode 100644 index 0000000000..0e09616c1d --- /dev/null +++ b/zephyr/projects/herobrine/battery_evoker.dts @@ -0,0 +1,15 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + batteries { + default_battery: pc_vp_bp153 { + compatible = "smp,pc-vp-bp153", "battery-smart"; + }; + ap16l5j { + compatible = "panasonic,ap16l5j", "battery-smart"; + }; + }; +}; diff --git a/zephyr/projects/herobrine/battery_herobrine.dts b/zephyr/projects/herobrine/battery_herobrine.dts new file mode 100644 index 0000000000..b347ec4c3c --- /dev/null +++ b/zephyr/projects/herobrine/battery_herobrine.dts @@ -0,0 +1,12 @@ +/* Copyright 2021 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + batteries { + default_battery: ap16l5j { + compatible = "panasonic,ap16l5j", "battery-smart"; + }; + }; +}; diff --git a/zephyr/projects/herobrine/battery_hoglin.dts b/zephyr/projects/herobrine/battery_hoglin.dts new file mode 100644 index 0000000000..11180c3988 --- /dev/null +++ b/zephyr/projects/herobrine/battery_hoglin.dts @@ -0,0 +1,12 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + batteries { + default_battery: 7c01 { + compatible = "ganfeng,7c01", "battery-smart"; + }; + }; +}; diff --git a/zephyr/projects/herobrine/battery_villager.dts b/zephyr/projects/herobrine/battery_villager.dts new file mode 100644 index 0000000000..dafd473a6e --- /dev/null +++ b/zephyr/projects/herobrine/battery_villager.dts @@ -0,0 +1,15 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + batteries { + default_battery: ap19a5k { + compatible = "panasonic,ap19a5k", "battery-smart"; + }; + ap19a8k { + compatible = "lgc,ap19a8k", "battery-smart"; + }; + }; +}; diff --git a/zephyr/projects/herobrine/battery_zombie.dts b/zephyr/projects/herobrine/battery_zombie.dts new file mode 100644 index 0000000000..dafd473a6e --- /dev/null +++ b/zephyr/projects/herobrine/battery_zombie.dts @@ -0,0 +1,15 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + batteries { + default_battery: ap19a5k { + compatible = "panasonic,ap19a5k", "battery-smart"; + }; + ap19a8k { + compatible = "lgc,ap19a8k", "battery-smart"; + }; + }; +}; diff --git a/zephyr/projects/herobrine/common.dts b/zephyr/projects/herobrine/common.dts new file mode 100644 index 0000000000..a722f1dfa2 --- /dev/null +++ b/zephyr/projects/herobrine/common.dts @@ -0,0 +1,44 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <dt-bindings/wake_mask_event_defines.h> + +/ { + chosen { + cros,rtc = &pcf85063a; + }; + + ec-console { + compatible = "ec-console"; + disabled = "hostcmd"; + }; + + ec-mkbp-host-event-wakeup-mask { + compatible = "ec-wake-mask-event"; + wakeup-mask = <( + HOST_EVENT_LID_OPEN | + HOST_EVENT_POWER_BUTTON | + HOST_EVENT_AC_CONNECTED | + HOST_EVENT_AC_DISCONNECTED | + HOST_EVENT_HANG_DETECT | + HOST_EVENT_RTC | + HOST_EVENT_MODE_CHANGE | + HOST_EVENT_DEVICE)>; + }; + + ec-mkbp-event-wakeup-mask { + compatible = "ec-wake-mask-event"; + wakeup-mask = <(MKBP_EVENT_KEY_MATRIX | \ + MKBP_EVENT_HOST_EVENT | \ + MKBP_EVENT_SENSOR_FIFO)>; + }; +}; + +&shi { + status = "okay"; + pinctrl-0 = <&shi_gp46_47_53_55>; + pinctrl-1 = <&shi_gpio_gp46_47_53_55>; + pinctrl-names = "default", "sleep"; +}; diff --git a/zephyr/projects/herobrine/default_gpio_pinctrl.dts b/zephyr/projects/herobrine/default_gpio_pinctrl.dts new file mode 100644 index 0000000000..604658a145 --- /dev/null +++ b/zephyr/projects/herobrine/default_gpio_pinctrl.dts @@ -0,0 +1,44 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Adds the &alt1_no_lpc_espi setting over the NPCX9 default setting. */ +&{/def-io-conf-list} { + pinmux = <&alt0_gpio_no_spip + &alt0_gpio_no_fpip + &alt1_no_pwrgd + &alt1_no_lpc_espi + &alta_no_peci_en + &altd_npsl_in1_sl + &altd_npsl_in2_sl + &altd_psl_in3_sl + &altd_psl_in4_sl + &alt7_no_ksi0_sl + &alt7_no_ksi1_sl + &alt7_no_ksi2_sl + &alt7_no_ksi3_sl + &alt7_no_ksi4_sl + &alt7_no_ksi5_sl + &alt7_no_ksi6_sl + &alt7_no_ksi7_sl + &alt8_no_kso00_sl + &alt8_no_kso01_sl + &alt8_no_kso02_sl + &alt8_no_kso03_sl + &alt8_no_kso04_sl + &alt8_no_kso05_sl + &alt8_no_kso06_sl + &alt8_no_kso07_sl + &alt9_no_kso08_sl + &alt9_no_kso09_sl + &alt9_no_kso10_sl + &alt9_no_kso11_sl + &alt9_no_kso12_sl + &alt9_no_kso13_sl + &alt9_no_kso14_sl + &alt9_no_kso15_sl + &alta_no_kso16_sl + &alta_no_kso17_sl + &altg_psl_gpo_sl>; +}; diff --git a/zephyr/projects/herobrine/display.dts b/zephyr/projects/herobrine/display.dts new file mode 100644 index 0000000000..65d3a2d91b --- /dev/null +++ b/zephyr/projects/herobrine/display.dts @@ -0,0 +1,18 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + displight { + compatible = "cros-ec,displight"; + pwms = <&pwm5 0 PWM_HZ(4800) PWM_POLARITY_NORMAL>; + generic-pwm-channel = <1>; + }; +}; + +&pwm5 { + status = "okay"; + pinctrl-0 = <&pwm5_gpb7>; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/herobrine/gpio.dts b/zephyr/projects/herobrine/gpio.dts new file mode 100644 index 0000000000..a355aaf099 --- /dev/null +++ b/zephyr/projects/herobrine/gpio.dts @@ -0,0 +1,329 @@ +/* Copyright 2021 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + aliases { + gpio-wp = &gpio_ec_wp_odl; + gpio-kbd-kso2 = &gpio_ec_kso_02_inv; + }; + + named-gpios { + compatible = "named-gpios"; + + gpio_usb_c0_pd_int_odl: usb_c0_pd_int_odl { + gpios = <&gpioe 0 GPIO_INPUT>; + enum-name = "GPIO_USB_C0_PD_INT_ODL"; + }; + gpio_usb_c1_pd_int_odl: usb_c1_pd_int_odl { + gpios = <&gpiof 5 GPIO_INPUT>; + enum-name = "GPIO_USB_C1_PD_INT_ODL"; + }; + gpio_usb_c0_swctl_int_odl: usb_c0_swctl_int_odl { + gpios = <&gpio0 3 GPIO_INPUT>; + enum-name = "GPIO_USB_C0_SWCTL_INT_ODL"; + }; + gpio_usb_c1_swctl_int_odl: usb_c1_swctl_int_odl { + gpios = <&gpio4 0 GPIO_INPUT>; + enum-name = "GPIO_USB_C1_SWCTL_INT_ODL"; + }; + gpio_usb_c0_bc12_int_l: usb_c0_bc12_int_l { + gpios = <&gpio6 1 GPIO_INPUT_PULL_UP>; + }; + gpio_usb_c1_bc12_int_l: usb_c1_bc12_int_l { + gpios = <&gpio8 2 GPIO_INPUT_PULL_UP>; + }; + gpio_usb_a0_oc_odl: usb_a0_oc_odl { + gpios = <&gpiof 4 GPIO_INPUT_PULL_UP>; + }; + gpio_chg_acok_od: chg_acok_od { + gpios = <&gpiod 2 GPIO_INPUT>; + enum-name = "GPIO_AC_PRESENT"; + }; + gpio_ec_pwr_btn_odl: ec_pwr_btn_odl { + gpios = <&gpio0 0 GPIO_INPUT>; + enum-name = "GPIO_POWER_BUTTON_L"; + }; + gpio_ec_voldn_btn_odl: ec_voldn_btn_odl { + gpios = <&gpio6 2 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_VOLUME_DOWN_L"; + }; + gpio_ec_volup_btn_odl: ec_volup_btn_odl { + gpios = <&gpioc 2 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_VOLUME_UP_L"; + }; + gpio_ec_wp_odl: ec_wp_odl { + gpios = <&gpiod 3 (GPIO_INPUT | GPIO_ACTIVE_LOW)>; + }; + gpio_lid_open_ec: lid_open_ec { + gpios = <&gpio0 1 GPIO_INPUT>; + enum-name = "GPIO_LID_OPEN"; + }; + gpio_ap_rst_l: ap_rst_l { + gpios = <&gpio5 1 GPIO_INPUT>; + enum-name = "GPIO_AP_RST_L"; + }; + gpio_ps_hold: ps_hold { + gpios = <&gpioa 6 GPIO_INPUT_PULL_DOWN>; + enum-name = "GPIO_PS_HOLD"; + }; + gpio_ap_suspend: ap_suspend { + gpios = <&gpio5 7 GPIO_INPUT>; + enum-name = "GPIO_AP_SUSPEND"; + }; + gpio_mb_power_good: mb_power_good { + gpios = <&gpio3 7 GPIO_INPUT_PULL_DOWN>; + enum-name = "GPIO_POWER_GOOD"; + }; + gpio_warm_reset_l: warm_reset_l { + gpios = <&gpiob 0 GPIO_INPUT>; + enum-name = "GPIO_WARM_RESET_L"; + }; + ap_ec_spi_cs_l { + gpios = <&gpio5 3 GPIO_INPUT_PULL_DOWN>; + }; + gpio_tablet_mode_l: tablet_mode_l { + gpios = <&gpioc 6 GPIO_INPUT>; + enum-name = "GPIO_TABLET_MODE_L"; + }; + gpio_accel_gyro_int_l: accel_gyro_int_l { + gpios = <&gpioa 3 GPIO_INPUT>; + }; + gpio_rtc_ec_wake_odl: rtc_ec_wake_odl { + gpios = <&gpio0 2 GPIO_INPUT>; + }; + ec_entering_rw { + gpios = <&gpio7 2 GPIO_OUTPUT_LOW>; + enum-name = "GPIO_ENTERING_RW"; + }; + ccd_mode_odl { + gpios = <&gpio6 3 GPIO_INPUT>; + enum-name = "GPIO_CCD_MODE_ODL"; + }; + ec_batt_pres_odl { + gpios = <&gpioe 5 GPIO_INPUT>; + enum-name = "GPIO_BATT_PRES_ODL"; + }; + ec_gsc_packet_mode { + gpios = <&gpio8 3 GPIO_OUTPUT_LOW>; + enum-name = "GPIO_PACKET_MODE_EN"; + }; + pmic_resin_l { + gpios = <&gpioa 0 GPIO_ODR_HIGH>; + enum-name = "GPIO_PMIC_RESIN_L"; + }; + pmic_kpd_pwr_odl { + gpios = <&gpioa 2 GPIO_ODR_HIGH>; + enum-name = "GPIO_PMIC_KPD_PWR_ODL"; + }; + ap_ec_int_l { + gpios = <&gpio5 6 GPIO_ODR_HIGH>; + enum-name = "GPIO_EC_INT_L"; + }; + gpio_switchcap_on: switchcap_on { + gpios = <&gpiod 5 GPIO_OUTPUT_LOW>; + enum-name = "GPIO_SWITCHCAP_ON"; + }; + gpio_en_pp5000_s5: en_pp5000_s5 { + gpios = <&gpio7 3 GPIO_OUTPUT_HIGH>; + enum-name = "GPIO_EN_PP5000"; + }; + ec_bl_disable_l { + /* The PMIC controls backlight enable and this pin must + * be HiZ for normal operation. But the backlight can + * be enabled by setting this pin low and configuring it + * as an output. + */ + gpios = <&gpiob 6 GPIO_INPUT>; + enum-name = "GPIO_ENABLE_BACKLIGHT"; + }; + lid_accel_int_l { + gpios = <&gpioa 1 GPIO_INPUT>; + }; + tp_int_gate { + gpios = <&gpio7 4 GPIO_OUTPUT_LOW>; + }; + gpio_usb_c0_pd_rst_l: usb_c0_pd_rst_l { + gpios = <&gpiof 1 GPIO_OUTPUT_HIGH>; + }; + gpio_usb_c1_pd_rst_l: usb_c1_pd_rst_l { + gpios = <&gpioe 4 GPIO_OUTPUT_HIGH>; + }; + gpio_dp_mux_oe_l: dp_mux_oe_l { + gpios = <&gpiob 1 GPIO_ODR_HIGH>; + }; + gpio_dp_mux_sel: dp_mux_sel { + gpios = <&gpio4 5 GPIO_OUTPUT_LOW>; + }; + gpio_dp_hot_plug_det_r: dp_hot_plug_det_r { + gpios = <&gpio9 5 GPIO_OUTPUT_LOW>; + }; + gpio_en_usb_a_5v: en_usb_a_5v { + gpios = <&gpiof 0 GPIO_OUTPUT_LOW>; + enum-name = "GPIO_EN_USB_A_5V"; + }; + usb_a_cdp_ilim_en_l { + gpios = <&gpio7 5 GPIO_OUTPUT_HIGH>; + }; + gpio_usb_c0_frs_en: usb_c0_frs_en { + gpios = <&gpioc 5 GPIO_OUTPUT_LOW>; + enum-name = "GPIO_USB_C0_FRS_EN"; + }; + gpio_usb_c1_frs_en: usb_c1_frs_en { + gpios = <&gpioc 1 GPIO_OUTPUT_LOW>; + enum-name = "GPIO_USB_C1_FRS_EN"; + }; + gpio_ec_chg_led_y_c0: ec_chg_led_y_c0 { + #led-pin-cells = <1>; + gpios = <&gpio6 0 GPIO_OUTPUT_LOW>; + }; + gpio_ec_chg_led_w_c0: ec_chg_led_w_c0 { + #led-pin-cells = <1>; + gpios = <&gpioc 0 GPIO_OUTPUT_LOW>; + }; + gpio_ec_chg_led_y_c1: ec_chg_led_y_c1 { + #led-pin-cells = <1>; + gpios = <&gpioc 3 GPIO_OUTPUT_LOW>; + }; + gpio_ec_chg_led_w_c1: ec_chg_led_w_c1 { + #led-pin-cells = <1>; + gpios = <&gpioc 4 GPIO_OUTPUT_LOW>; + }; + ap_ec_spi_mosi { + gpios = <&gpio4 6 GPIO_INPUT_PULL_DOWN>; + }; + ap_ec_spi_miso { + gpios = <&gpio4 7 GPIO_INPUT_PULL_DOWN>; + }; + ap_ec_spi_clk { + gpios = <&gpio5 5 GPIO_INPUT_PULL_DOWN>; + }; + gpio_brd_id0: brd_id0 { + gpios = <&gpio9 4 GPIO_INPUT>; + enum-name = "GPIO_BOARD_VERSION1"; + }; + gpio_brd_id1: brd_id1 { + gpios = <&gpio9 7 GPIO_INPUT>; + enum-name = "GPIO_BOARD_VERSION2"; + }; + gpio_brd_id2: brd_id2 { + gpios = <&gpioa 5 GPIO_INPUT>; + enum-name = "GPIO_BOARD_VERSION3"; + }; + gpio_sku_id0: sku_id0 { + gpios = <&gpio6 7 GPIO_INPUT>; + }; + gpio_sku_id1: sku_id1 { + gpios = <&gpio7 0 GPIO_INPUT>; + }; + gpio_sku_id2: sku_id2 { + gpios = <&gpioe 1 GPIO_INPUT>; + }; + gpio_switchcap_pg: src_vph_pwr_pg { + gpios = <&gpioe 2 GPIO_INPUT_PULL_DOWN>; + enum-name = "GPIO_SWITCHCAP_PG"; + }; + arm_x86 { + gpios = <&gpio6 6 GPIO_OUTPUT_LOW>; + }; + ec-i2c-sensor-scl { + gpios = <&gpiob 3 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; + }; + ec-i2c-sensor-sda { + gpios = <&gpiob 2 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; + }; + gpio_ec_kso_02_inv: ec_kso_02_inv { + gpios = <&gpio1 7 (GPIO_OUTPUT_LOW | GPIO_ACTIVE_LOW)>; + }; + }; + + usba-port-enable-list { + compatible = "cros-ec,usba-port-enable-pins"; + enable-pins = <&gpio_en_usb_a_5v>; + }; + + sku { + compatible = "cros-ec,gpio-id"; + + bits = < + &gpio_sku_id0 + &gpio_sku_id1 + &gpio_sku_id2 + >; + + system = "ternary"; + }; + + board { + compatible = "cros-ec,gpio-id"; + + bits = < + &gpio_brd_id0 + &gpio_brd_id1 + &gpio_brd_id2 + >; + + system = "ternary"; + }; + + unused-pins { + compatible = "unused-gpios"; + unused-gpios = + <&gpio5 2 0>, + <&gpio5 4 0>, + <&gpio7 6 0>, + <&gpiod 1 0>, + <&gpiod 0 0>, + <&gpioe 3 0>, + <&gpio0 4 0>, + <&gpiod 6 0>, + <&gpio3 2 0>, + <&gpio3 5 0>, + <&gpiod 7 0>, + <&gpio8 6 0>, + <&gpiod 4 0>, + <&gpio4 1 0>, + <&gpio3 4 0>, + <&gpioc 7 0>, + <&gpioa 4 0>, + <&gpio9 6 0>, + <&gpio9 3 0>, + <&gpioa 7 0>, + <&gpio5 0 0>, + <&gpio8 1 0>, + <&gpiob 7 0>; + }; +}; + +/* Power switch logic input pads */ +&psl_in1_gpd2 { + /* ACOK_OD */ + psl-in-mode = "edge"; + psl-in-pol = "high-rising"; +}; + +&psl_in2_gp00 { + /* EC_PWR_BTN_ODL */ + psl-in-mode = "edge"; + psl-in-pol = "low-falling"; +}; + +&psl_in3_gp01 { + /* LID_OPEN_EC */ + psl-in-mode = "edge"; + psl-in-pol = "high-rising"; +}; + +&psl_in4_gp02 { + /* RTC_EC_WAKE_ODL */ + psl-in-mode = "edge"; + psl-in-pol = "low-falling"; +}; + +/* Power domain device controlled by PSL (Power Switch Logic) IO pads */ +&power_ctrl_psl { + status = "okay"; + pinctrl-names = "sleep"; + pinctrl-0 = <&psl_in1_gpd2 &psl_in2_gp00 &psl_in3_gp01 &psl_in4_gp02>; +};
\ No newline at end of file diff --git a/zephyr/projects/herobrine/gpio_evoker.dts b/zephyr/projects/herobrine/gpio_evoker.dts new file mode 100644 index 0000000000..d60fdf93c7 --- /dev/null +++ b/zephyr/projects/herobrine/gpio_evoker.dts @@ -0,0 +1,329 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + aliases { + gpio-wp = &gpio_ec_wp_odl; + gpio-kbd-kso2 = &gpio_ec_kso_02_inv; + }; + + named-gpios { + compatible = "named-gpios"; + + gpio_usb_c0_pd_int_odl: usb_c0_pd_int_odl { + gpios = <&gpioe 0 GPIO_INPUT>; + enum-name = "GPIO_USB_C0_PD_INT_ODL"; + }; + gpio_usb_c1_pd_int_odl: usb_c1_pd_int_odl { + gpios = <&gpiof 5 GPIO_INPUT>; + enum-name = "GPIO_USB_C1_PD_INT_ODL"; + }; + gpio_usb_c0_swctl_int_odl: usb_c0_swctl_int_odl { + gpios = <&gpio0 3 GPIO_INPUT>; + enum-name = "GPIO_USB_C0_SWCTL_INT_ODL"; + }; + gpio_usb_c1_swctl_int_odl: usb_c1_swctl_int_odl { + gpios = <&gpio4 0 GPIO_INPUT>; + enum-name = "GPIO_USB_C1_SWCTL_INT_ODL"; + }; + gpio_usb_c0_bc12_int_l: usb_c0_bc12_int_l { + gpios = <&gpio6 1 GPIO_INPUT_PULL_UP>; + }; + gpio_usb_c1_bc12_int_l: usb_c1_bc12_int_l { + gpios = <&gpio8 2 GPIO_INPUT_PULL_UP>; + }; + gpio_usb_a0_oc_odl: usb_a0_oc_odl { + gpios = <&gpiof 4 GPIO_INPUT_PULL_UP>; + }; + gpio_chg_acok_od: chg_acok_od { + gpios = <&gpiod 2 GPIO_INPUT>; + enum-name = "GPIO_AC_PRESENT"; + }; + gpio_ec_pwr_btn_odl: ec_pwr_btn_odl { + gpios = <&gpio0 0 GPIO_INPUT>; + enum-name = "GPIO_POWER_BUTTON_L"; + }; + gpio_ec_voldn_btn_odl: ec_voldn_btn_odl { + gpios = <&gpio6 2 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_VOLUME_DOWN_L"; + }; + gpio_ec_volup_btn_odl: ec_volup_btn_odl { + gpios = <&gpioc 2 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_VOLUME_UP_L"; + }; + gpio_ec_wp_odl: ec_wp_odl { + gpios = <&gpiod 3 (GPIO_INPUT | GPIO_ACTIVE_LOW)>; + }; + gpio_lid_open_ec: lid_open_ec { + gpios = <&gpio0 1 GPIO_INPUT>; + enum-name = "GPIO_LID_OPEN"; + }; + gpio_ap_rst_l: ap_rst_l { + gpios = <&gpio5 1 GPIO_INPUT>; + enum-name = "GPIO_AP_RST_L"; + }; + gpio_ps_hold: ps_hold { + gpios = <&gpioa 6 GPIO_INPUT_PULL_DOWN>; + enum-name = "GPIO_PS_HOLD"; + }; + gpio_ap_suspend: ap_suspend { + gpios = <&gpio5 7 GPIO_INPUT>; + enum-name = "GPIO_AP_SUSPEND"; + }; + gpio_mb_power_good: mb_power_good { + gpios = <&gpio3 7 GPIO_INPUT_PULL_DOWN>; + enum-name = "GPIO_POWER_GOOD"; + }; + gpio_warm_reset_l: warm_reset_l { + gpios = <&gpiob 0 GPIO_INPUT>; + enum-name = "GPIO_WARM_RESET_L"; + }; + ap_ec_spi_cs_l { + gpios = <&gpio5 3 GPIO_INPUT_PULL_DOWN>; + }; + gpio_tablet_mode_l: tablet_mode_l { + gpios = <&gpioc 6 GPIO_INPUT>; + enum-name = "GPIO_TABLET_MODE_L"; + }; + gpio_accel_gyro_int_l: accel_gyro_int_l { + gpios = <&gpioa 3 GPIO_INPUT>; + }; + gpio_rtc_ec_wake_odl: rtc_ec_wake_odl { + gpios = <&gpio0 2 GPIO_INPUT>; + }; + ec_entering_rw { + gpios = <&gpio7 2 GPIO_OUTPUT_LOW>; + enum-name = "GPIO_ENTERING_RW"; + }; + ccd_mode_odl { + gpios = <&gpio6 3 GPIO_INPUT>; + enum-name = "GPIO_CCD_MODE_ODL"; + }; + ec_batt_pres_odl { + gpios = <&gpioe 5 GPIO_INPUT>; + enum-name = "GPIO_BATT_PRES_ODL"; + }; + ec_gsc_packet_mode { + gpios = <&gpio8 3 GPIO_OUTPUT_LOW>; + enum-name = "GPIO_PACKET_MODE_EN"; + }; + pmic_resin_l { + gpios = <&gpioa 0 GPIO_ODR_HIGH>; + enum-name = "GPIO_PMIC_RESIN_L"; + }; + pmic_kpd_pwr_odl { + gpios = <&gpioa 2 GPIO_ODR_HIGH>; + enum-name = "GPIO_PMIC_KPD_PWR_ODL"; + }; + ap_ec_int_l { + gpios = <&gpio5 6 GPIO_ODR_HIGH>; + enum-name = "GPIO_EC_INT_L"; + }; + gpio_switchcap_on: switchcap_on { + gpios = <&gpiod 5 GPIO_OUTPUT_LOW>; + enum-name = "GPIO_SWITCHCAP_ON"; + }; + gpio_en_pp5000_s5: en_pp5000_s5 { + gpios = <&gpio7 3 GPIO_OUTPUT_HIGH>; + enum-name = "GPIO_EN_PP5000"; + }; + ec_bl_disable_l { + /* The PMIC controls backlight enable and this pin must + * be HiZ for normal operation. But the backlight can + * be enabled by setting this pin low and configuring it + * as an output. + */ + gpios = <&gpiob 6 GPIO_INPUT>; + enum-name = "GPIO_ENABLE_BACKLIGHT"; + }; + lid_accel_int_l { + gpios = <&gpioa 1 GPIO_INPUT>; + }; + tp_int_gate { + gpios = <&gpio7 4 GPIO_OUTPUT_LOW>; + }; + gpio_usb_c0_pd_rst_l: usb_c0_pd_rst_l { + gpios = <&gpiof 1 GPIO_OUTPUT_HIGH>; + }; + gpio_usb_c1_pd_rst_l: usb_c1_pd_rst_l { + gpios = <&gpioe 4 GPIO_OUTPUT_HIGH>; + }; + gpio_dp_mux_oe_l: dp_mux_oe_l { + gpios = <&gpiob 1 GPIO_ODR_HIGH>; + }; + gpio_dp_mux_sel: dp_mux_sel { + gpios = <&gpio4 5 GPIO_OUTPUT_LOW>; + }; + gpio_dp_hot_plug_det_r: dp_hot_plug_det_r { + gpios = <&gpio9 5 GPIO_OUTPUT_LOW>; + }; + gpio_en_usb_a_5v: en_usb_a_5v { + gpios = <&gpiof 0 GPIO_OUTPUT_LOW>; + enum-name = "GPIO_EN_USB_A_5V"; + }; + usb_a_cdp_ilim_en_l { + gpios = <&gpio7 5 GPIO_OUTPUT_HIGH>; + }; + gpio_usb_c0_frs_en: usb_c0_frs_en { + gpios = <&gpioc 5 GPIO_OUTPUT_LOW>; + enum-name = "GPIO_USB_C0_FRS_EN"; + }; + gpio_usb_c1_frs_en: usb_c1_frs_en { + gpios = <&gpioc 1 GPIO_OUTPUT_LOW>; + enum-name = "GPIO_USB_C1_FRS_EN"; + }; + gpio_ec_chg_led_y_c0: ec_chg_led_y_c0 { + #led-pin-cells = <1>; + gpios = <&gpio6 0 GPIO_OUTPUT_LOW>; + }; + gpio_ec_chg_led_w_c0: ec_chg_led_w_c0 { + #led-pin-cells = <1>; + gpios = <&gpioc 0 GPIO_OUTPUT_LOW>; + }; + gpio_ec_chg_led_w_c1: ec_chg_led_w_c1 { + #led-pin-cells = <1>; + gpios = <&gpioc 3 GPIO_OUTPUT_LOW>; + }; + gpio_ec_chg_led_r_c0: ec_chg_led_r_c0 { + #led-pin-cells = <1>; + gpios = <&gpioc 4 GPIO_OUTPUT_LOW>; + }; + ap_ec_spi_mosi { + gpios = <&gpio4 6 GPIO_INPUT_PULL_DOWN>; + }; + ap_ec_spi_miso { + gpios = <&gpio4 7 GPIO_INPUT_PULL_DOWN>; + }; + ap_ec_spi_clk { + gpios = <&gpio5 5 GPIO_INPUT_PULL_DOWN>; + }; + gpio_brd_id0: brd_id0 { + gpios = <&gpio9 4 GPIO_INPUT>; + enum-name = "GPIO_BOARD_VERSION1"; + }; + gpio_brd_id1: brd_id1 { + gpios = <&gpio9 7 GPIO_INPUT>; + enum-name = "GPIO_BOARD_VERSION2"; + }; + gpio_brd_id2: brd_id2 { + gpios = <&gpioa 5 GPIO_INPUT>; + enum-name = "GPIO_BOARD_VERSION3"; + }; + gpio_sku_id0: sku_id0 { + gpios = <&gpio6 7 GPIO_INPUT>; + }; + gpio_sku_id1: sku_id1 { + gpios = <&gpio7 0 GPIO_INPUT>; + }; + gpio_sku_id2: sku_id2 { + gpios = <&gpioe 1 GPIO_INPUT>; + }; + gpio_switchcap_pg: src_vph_pwr_pg { + gpios = <&gpioe 2 GPIO_INPUT_PULL_DOWN>; + enum-name = "GPIO_SWITCHCAP_PG"; + }; + arm_x86 { + gpios = <&gpio6 6 GPIO_OUTPUT_LOW>; + }; + ec-i2c-sensor-scl { + gpios = <&gpiob 3 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; + }; + ec-i2c-sensor-sda { + gpios = <&gpiob 2 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; + }; + gpio_ec_kso_02_inv: ec_kso_02_inv { + gpios = <&gpio1 7 (GPIO_OUTPUT_LOW | GPIO_ACTIVE_LOW)>; + }; + }; + + usba-port-enable-list { + compatible = "cros-ec,usba-port-enable-pins"; + enable-pins = <&gpio_en_usb_a_5v>; + }; + + sku { + compatible = "cros-ec,gpio-id"; + + bits = < + &gpio_sku_id0 + &gpio_sku_id1 + &gpio_sku_id2 + >; + + system = "ternary"; + }; + + board { + compatible = "cros-ec,gpio-id"; + + bits = < + &gpio_brd_id0 + &gpio_brd_id1 + &gpio_brd_id2 + >; + + system = "ternary"; + }; + + unused-pins { + compatible = "unused-gpios"; + unused-gpios = + <&gpio5 2 0>, + <&gpio5 4 0>, + <&gpio7 6 0>, + <&gpiod 1 0>, + <&gpiod 0 0>, + <&gpioe 3 0>, + <&gpio0 4 0>, + <&gpiod 6 0>, + <&gpio3 2 0>, + <&gpio3 5 0>, + <&gpiod 7 0>, + <&gpio8 6 0>, + <&gpiod 4 0>, + <&gpio4 1 0>, + <&gpio3 4 0>, + <&gpioc 7 0>, + <&gpioa 4 0>, + <&gpio9 6 0>, + <&gpio9 3 0>, + <&gpioa 7 0>, + <&gpio5 0 0>, + <&gpio8 1 0>, + <&gpiob 7 0>; + }; +}; + +/* Power switch logic input pads */ +&psl_in1_gpd2 { + /* ACOK_OD */ + psl-in-mode = "edge"; + psl-in-pol = "high-rising"; +}; + +&psl_in2_gp00 { + /* EC_PWR_BTN_ODL */ + psl-in-mode = "edge"; + psl-in-pol = "low-falling"; +}; + +&psl_in3_gp01 { + /* LID_OPEN_EC */ + psl-in-mode = "edge"; + psl-in-pol = "high-rising"; +}; + +&psl_in4_gp02 { + /* RTC_EC_WAKE_ODL */ + psl-in-mode = "edge"; + psl-in-pol = "low-falling"; +}; + +/* Power domain device controlled by PSL (Power Switch Logic) IO pads */ +&power_ctrl_psl { + status = "okay"; + pinctrl-names = "sleep"; + pinctrl-0 = <&psl_in1_gpd2 &psl_in2_gp00 &psl_in3_gp01 &psl_in4_gp02>; +}; diff --git a/zephyr/projects/herobrine/gpio_hoglin.dts b/zephyr/projects/herobrine/gpio_hoglin.dts new file mode 100644 index 0000000000..cb7babc9cf --- /dev/null +++ b/zephyr/projects/herobrine/gpio_hoglin.dts @@ -0,0 +1,327 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + aliases { + gpio-wp = &gpio_ec_wp_odl; + gpio-kbd-kso2 = &gpio_ec_kso_02_inv; + }; + + named-gpios { + compatible = "named-gpios"; + + gpio_usb_c0_pd_int_odl: usb_c0_pd_int_odl { + gpios = <&gpioe 0 GPIO_INPUT>; + enum-name = "GPIO_USB_C0_PD_INT_ODL"; + }; + gpio_usb_c1_pd_int_odl: usb_c1_pd_int_odl { + gpios = <&gpiof 5 GPIO_INPUT>; + enum-name = "GPIO_USB_C1_PD_INT_ODL"; + }; + gpio_usb_c0_swctl_int_odl: usb_c0_swctl_int_odl { + gpios = <&gpio0 3 GPIO_INPUT>; + enum-name = "GPIO_USB_C0_SWCTL_INT_ODL"; + }; + gpio_usb_c1_swctl_int_odl: usb_c1_swctl_int_odl { + gpios = <&gpio4 0 GPIO_INPUT>; + enum-name = "GPIO_USB_C1_SWCTL_INT_ODL"; + }; + gpio_usb_c0_bc12_int_l: usb_c0_bc12_int_l { + gpios = <&gpio6 1 GPIO_INPUT_PULL_UP>; + }; + gpio_usb_c1_bc12_int_l: usb_c1_bc12_int_l { + gpios = <&gpio8 2 GPIO_INPUT_PULL_UP>; + }; + gpio_usb_a0_oc_odl: usb_a0_oc_odl { + gpios = <&gpiof 4 GPIO_INPUT_PULL_UP>; + }; + gpio_chg_acok_od: chg_acok_od { + gpios = <&gpiod 2 GPIO_INPUT>; + enum-name = "GPIO_AC_PRESENT"; + }; + gpio_ec_pwr_btn_odl: ec_pwr_btn_odl { + gpios = <&gpio0 0 GPIO_INPUT>; + enum-name = "GPIO_POWER_BUTTON_L"; + }; + gpio_ec_voldn_btn_odl: ec_voldn_btn_odl { + gpios = <&gpio6 2 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_VOLUME_DOWN_L"; + }; + gpio_ec_volup_btn_odl: ec_volup_btn_odl { + gpios = <&gpioc 2 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_VOLUME_UP_L"; + }; + gpio_ec_wp_odl: ec_wp_odl { + gpios = <&gpiod 3 (GPIO_INPUT | GPIO_ACTIVE_LOW)>; + }; + gpio_lid_open_ec: lid_open_ec { + gpios = <&gpio0 1 GPIO_INPUT>; + enum-name = "GPIO_LID_OPEN"; + }; + gpio_ap_rst_l: ap_rst_l { + gpios = <&gpio5 1 GPIO_INPUT>; + enum-name = "GPIO_AP_RST_L"; + }; + gpio_ps_hold: ps_hold { + gpios = <&gpioa 6 GPIO_INPUT_PULL_DOWN>; + enum-name = "GPIO_PS_HOLD"; + }; + gpio_ap_suspend: ap_suspend { + gpios = <&gpio5 7 GPIO_INPUT>; + enum-name = "GPIO_AP_SUSPEND"; + }; + gpio_mb_power_good: mb_power_good { + gpios = <&gpio3 7 GPIO_INPUT_PULL_DOWN>; + enum-name = "GPIO_POWER_GOOD"; + }; + gpio_warm_reset_l: warm_reset_l { + gpios = <&gpiob 0 GPIO_INPUT>; + enum-name = "GPIO_WARM_RESET_L"; + }; + ap_ec_spi_cs_l { + gpios = <&gpio5 3 GPIO_INPUT_PULL_DOWN>; + }; + gpio_tablet_mode_l: tablet_mode_l { + gpios = <&gpioc 6 GPIO_INPUT>; + enum-name = "GPIO_TABLET_MODE_L"; + }; + gpio_accel_gyro_int_l: accel_gyro_int_l { + gpios = <&gpioa 3 GPIO_INPUT>; + }; + gpio_rtc_ec_wake_odl: rtc_ec_wake_odl { + gpios = <&gpio0 2 GPIO_INPUT>; + }; + ec_entering_rw { + gpios = <&gpio7 2 GPIO_OUTPUT_LOW>; + enum-name = "GPIO_ENTERING_RW"; + }; + ccd_mode_odl { + gpios = <&gpio6 3 GPIO_INPUT>; + enum-name = "GPIO_CCD_MODE_ODL"; + }; + ec_batt_pres_odl { + gpios = <&gpioe 5 GPIO_INPUT>; + enum-name = "GPIO_BATT_PRES_ODL"; + }; + ec_gsc_packet_mode { + gpios = <&gpio8 3 GPIO_OUTPUT_LOW>; + enum-name = "GPIO_PACKET_MODE_EN"; + }; + pmic_resin_l { + gpios = <&gpioa 0 GPIO_ODR_HIGH>; + enum-name = "GPIO_PMIC_RESIN_L"; + }; + pmic_kpd_pwr_odl { + gpios = <&gpioa 2 GPIO_ODR_HIGH>; + enum-name = "GPIO_PMIC_KPD_PWR_ODL"; + }; + ap_ec_int_l { + gpios = <&gpio5 6 GPIO_ODR_HIGH>; + enum-name = "GPIO_EC_INT_L"; + }; + gpio_switchcap_on: switchcap_on { + gpios = <&gpio5 0 GPIO_OUTPUT_LOW>; + enum-name = "GPIO_SWITCHCAP_ON"; + }; + gpio_en_pp5000_s5: en_pp5000_s5 { + gpios = <&gpio7 3 GPIO_OUTPUT_HIGH>; + enum-name = "GPIO_EN_PP5000"; + }; + ec_bl_disable_l { + /* The PMIC controls backlight enable and this pin must + * be HiZ for normal operation. But the backlight can + * be enabled by setting this pin low and configuring it + * as an output. + */ + gpios = <&gpiob 6 GPIO_INPUT>; + enum-name = "GPIO_ENABLE_BACKLIGHT"; + }; + lid_accel_int_l { + gpios = <&gpioa 1 GPIO_INPUT>; + }; + tp_int_gate { + gpios = <&gpio7 4 GPIO_OUTPUT_LOW>; + }; + gpio_usb_c0_pd_rst_l: usb_c0_pd_rst_l { + gpios = <&gpiof 1 GPIO_OUTPUT_HIGH>; + }; + gpio_usb_c1_pd_rst_l: usb_c1_pd_rst_l { + gpios = <&gpioe 4 GPIO_OUTPUT_HIGH>; + }; + gpio_dp_mux_oe_l: dp_mux_oe_l { + gpios = <&gpiob 1 GPIO_ODR_HIGH>; + }; + gpio_dp_mux_sel: dp_mux_sel { + gpios = <&gpio4 5 GPIO_OUTPUT_LOW>; + }; + gpio_dp_hot_plug_det_r: dp_hot_plug_det_r { + gpios = <&gpio9 5 GPIO_OUTPUT_LOW>; + }; + gpio_en_usb_a_5v: en_usb_a_5v { + gpios = <&gpiof 0 GPIO_OUTPUT_LOW>; + enum-name = "GPIO_EN_USB_A_5V"; + }; + usb_a_cdp_ilim_en_l { + gpios = <&gpio7 5 GPIO_OUTPUT_HIGH>; + }; + gpio_usb_c0_frs_en: usb_c0_frs_en { + gpios = <&gpioc 5 GPIO_OUTPUT_LOW>; + enum-name = "GPIO_USB_C0_FRS_EN"; + }; + gpio_usb_c1_frs_en: usb_c1_frs_en { + gpios = <&gpioc 1 GPIO_OUTPUT_LOW>; + enum-name = "GPIO_USB_C1_FRS_EN"; + }; + gpio_ec_chg_led_b_c0: ec_chg_led_b_c0 { + #led-pin-cells = <1>; + gpios = <&gpio6 0 GPIO_OUTPUT_LOW>; + }; + gpio_ec_chg_led_r_c0: ec_chg_led_r_c0 { + #led-pin-cells = <1>; + gpios = <&gpioc 0 GPIO_OUTPUT_LOW>; + }; + gpio_ec_chg_led_y_c1: ec_chg_led_b_c1 { + gpios = <&gpioc 3 GPIO_OUTPUT_LOW>; + }; + gpio_ec_chg_led_w_c1: ec_chg_led_r_c1 { + gpios = <&gpioc 4 GPIO_OUTPUT_LOW>; + }; + ap_ec_spi_mosi { + gpios = <&gpio4 6 GPIO_INPUT_PULL_DOWN>; + }; + ap_ec_spi_miso { + gpios = <&gpio4 7 GPIO_INPUT_PULL_DOWN>; + }; + ap_ec_spi_clk { + gpios = <&gpio5 5 GPIO_INPUT_PULL_DOWN>; + }; + gpio_brd_id0: brd_id0 { + gpios = <&gpio9 4 GPIO_INPUT>; + enum-name = "GPIO_BOARD_VERSION1"; + }; + gpio_brd_id1: brd_id1 { + gpios = <&gpio9 7 GPIO_INPUT>; + enum-name = "GPIO_BOARD_VERSION2"; + }; + gpio_brd_id2: brd_id2 { + gpios = <&gpioa 5 GPIO_INPUT>; + enum-name = "GPIO_BOARD_VERSION3"; + }; + gpio_sku_id0: sku_id0 { + gpios = <&gpio6 7 GPIO_INPUT>; + }; + gpio_sku_id1: sku_id1 { + gpios = <&gpio7 0 GPIO_INPUT>; + }; + gpio_sku_id2: sku_id2 { + gpios = <&gpioe 1 GPIO_INPUT>; + }; + gpio_switchcap_pg: src_vph_pwr_pg { + gpios = <&gpioe 2 GPIO_INPUT_PULL_DOWN>; + enum-name = "GPIO_SWITCHCAP_PG"; + }; + arm_x86 { + gpios = <&gpio6 6 GPIO_OUTPUT_LOW>; + }; + ec-i2c-sensor-scl { + gpios = <&gpiob 3 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; + }; + ec-i2c-sensor-sda { + gpios = <&gpiob 2 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; + }; + gpio_ec_kso_02_inv: ec_kso_02_inv { + gpios = <&gpio1 7 (GPIO_OUTPUT_LOW | GPIO_ACTIVE_LOW)>; + }; + }; + + usba-port-enable-list { + compatible = "cros-ec,usba-port-enable-pins"; + enable-pins = <&gpio_en_usb_a_5v>; + }; + + sku { + compatible = "cros-ec,gpio-id"; + + bits = < + &gpio_sku_id0 + &gpio_sku_id1 + &gpio_sku_id2 + >; + + system = "ternary"; + }; + + board { + compatible = "cros-ec,gpio-id"; + + bits = < + &gpio_brd_id0 + &gpio_brd_id1 + &gpio_brd_id2 + >; + + system = "ternary"; + }; + + unused-pins { + compatible = "unused-gpios"; + unused-gpios = + <&gpio5 2 0>, + <&gpio5 4 0>, + <&gpio7 6 0>, + <&gpiod 1 0>, + <&gpiod 0 0>, + <&gpioe 3 0>, + <&gpio0 4 0>, + <&gpiod 6 0>, + <&gpio3 2 0>, + <&gpio3 5 0>, + <&gpiod 7 0>, + <&gpio8 6 0>, + <&gpiod 4 0>, + <&gpio4 1 0>, + <&gpio3 4 0>, + <&gpioc 7 0>, + <&gpioa 4 0>, + <&gpio9 6 0>, + <&gpio9 3 0>, + <&gpioa 7 0>, + <&gpiod 5 0>, + <&gpio8 1 0>, + <&gpiob 7 0>; + }; +}; + +/* Power switch logic input pads */ +&psl_in1_gpd2 { + /* ACOK_OD */ + psl-in-mode = "edge"; + psl-in-pol = "high-rising"; +}; + +&psl_in2_gp00 { + /* EC_PWR_BTN_ODL */ + psl-in-mode = "edge"; + psl-in-pol = "low-falling"; +}; + +&psl_in3_gp01 { + /* LID_OPEN_EC */ + psl-in-mode = "edge"; + psl-in-pol = "high-rising"; +}; + +&psl_in4_gp02 { + /* RTC_EC_WAKE_ODL */ + psl-in-mode = "edge"; + psl-in-pol = "low-falling"; +}; + +/* Power domain device controlled by PSL (Power Switch Logic) IO pads */ +&power_ctrl_psl { + status = "okay"; + pinctrl-names = "sleep"; + pinctrl-0 = <&psl_in1_gpd2 &psl_in2_gp00 &psl_in3_gp01 &psl_in4_gp02>; +}; diff --git a/zephyr/projects/herobrine/gpio_villager.dts b/zephyr/projects/herobrine/gpio_villager.dts new file mode 100644 index 0000000000..1e7625ff6a --- /dev/null +++ b/zephyr/projects/herobrine/gpio_villager.dts @@ -0,0 +1,323 @@ +/* Copyright 2021 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + aliases { + gpio-wp = &gpio_ec_wp_odl; + gpio-kbd-kso2 = &gpio_ec_kso_02_inv; + }; + + named-gpios { + compatible = "named-gpios"; + + gpio_usb_c0_pd_int_odl: usb_c0_pd_int_odl { + gpios = <&gpioe 0 GPIO_INPUT>; + enum-name = "GPIO_USB_C0_PD_INT_ODL"; + }; + gpio_usb_c1_pd_int_odl: usb_c1_pd_int_odl { + gpios = <&gpiof 5 GPIO_INPUT>; + enum-name = "GPIO_USB_C1_PD_INT_ODL"; + }; + gpio_usb_c0_swctl_int_odl: usb_c0_swctl_int_odl { + gpios = <&gpio0 3 GPIO_INPUT>; + enum-name = "GPIO_USB_C0_SWCTL_INT_ODL"; + }; + gpio_usb_c1_swctl_int_odl: usb_c1_swctl_int_odl { + gpios = <&gpio4 0 GPIO_INPUT>; + enum-name = "GPIO_USB_C1_SWCTL_INT_ODL"; + }; + gpio_usb_c0_bc12_int_l: usb_c0_bc12_int_l { + gpios = <&gpio6 1 GPIO_INPUT_PULL_UP>; + }; + gpio_usb_c1_bc12_int_l: usb_c1_bc12_int_l { + gpios = <&gpio8 2 GPIO_INPUT_PULL_UP>; + }; + gpio_usb_a0_oc_odl: usb_a0_oc_odl { + gpios = <&gpiof 4 GPIO_INPUT_PULL_UP>; + }; + gpio_chg_acok_od: chg_acok_od { + gpios = <&gpiod 2 GPIO_INPUT>; + enum-name = "GPIO_AC_PRESENT"; + }; + gpio_ec_pwr_btn_odl: ec_pwr_btn_odl { + gpios = <&gpio0 0 GPIO_INPUT>; + enum-name = "GPIO_POWER_BUTTON_L"; + }; + gpio_ec_voldn_btn_odl: ec_voldn_btn_odl { + gpios = <&gpio6 2 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_VOLUME_DOWN_L"; + }; + gpio_ec_volup_btn_odl: ec_volup_btn_odl { + gpios = <&gpioc 2 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_VOLUME_UP_L"; + }; + gpio_ec_wp_odl: ec_wp_odl { + gpios = <&gpiod 3 (GPIO_INPUT | GPIO_ACTIVE_LOW)>; + }; + gpio_lid_open_ec: lid_open_ec { + gpios = <&gpio0 1 GPIO_INPUT>; + enum-name = "GPIO_LID_OPEN"; + }; + gpio_ap_rst_l: ap_rst_l { + gpios = <&gpio5 1 GPIO_INPUT>; + enum-name = "GPIO_AP_RST_L"; + }; + gpio_ps_hold: ps_hold { + gpios = <&gpioa 6 GPIO_INPUT_PULL_DOWN>; + enum-name = "GPIO_PS_HOLD"; + }; + gpio_ap_suspend: ap_suspend { + gpios = <&gpio5 7 GPIO_INPUT>; + enum-name = "GPIO_AP_SUSPEND"; + }; + gpio_mb_power_good: mb_power_good { + gpios = <&gpio3 7 GPIO_INPUT_PULL_DOWN>; + enum-name = "GPIO_POWER_GOOD"; + }; + gpio_warm_reset_l: warm_reset_l { + gpios = <&gpiob 0 GPIO_INPUT>; + enum-name = "GPIO_WARM_RESET_L"; + }; + ap_ec_spi_cs_l { + gpios = <&gpio5 3 GPIO_INPUT_PULL_DOWN>; + }; + gpio_tablet_mode_l: tablet_mode_l { + gpios = <&gpioc 6 GPIO_INPUT>; + enum-name = "GPIO_TABLET_MODE_L"; + }; + gpio_accel_gyro_int_l: accel_gyro_int_l { + gpios = <&gpioa 3 GPIO_INPUT>; + }; + gpio_rtc_ec_wake_odl: rtc_ec_wake_odl { + gpios = <&gpio0 2 GPIO_INPUT>; + }; + ec_entering_rw { + gpios = <&gpio7 2 GPIO_OUTPUT_LOW>; + enum-name = "GPIO_ENTERING_RW"; + }; + ccd_mode_odl { + gpios = <&gpio6 3 GPIO_INPUT>; + enum-name = "GPIO_CCD_MODE_ODL"; + }; + ec_batt_pres_odl { + gpios = <&gpioe 5 GPIO_INPUT>; + enum-name = "GPIO_BATT_PRES_ODL"; + }; + ec_gsc_packet_mode { + gpios = <&gpio8 3 GPIO_OUTPUT_LOW>; + enum-name = "GPIO_PACKET_MODE_EN"; + }; + pmic_resin_l { + gpios = <&gpioa 0 GPIO_ODR_HIGH>; + enum-name = "GPIO_PMIC_RESIN_L"; + }; + pmic_kpd_pwr_odl { + gpios = <&gpioa 2 GPIO_ODR_HIGH>; + enum-name = "GPIO_PMIC_KPD_PWR_ODL"; + }; + ap_ec_int_l { + gpios = <&gpio5 6 GPIO_ODR_HIGH>; + enum-name = "GPIO_EC_INT_L"; + }; + gpio_switchcap_on: switchcap_on { + gpios = <&gpiod 5 GPIO_OUTPUT_LOW>; + enum-name = "GPIO_SWITCHCAP_ON"; + }; + gpio_en_pp5000_s5: en_pp5000_s5 { + gpios = <&gpio7 3 GPIO_OUTPUT_HIGH>; + enum-name = "GPIO_EN_PP5000"; + }; + ec_bl_disable_l { + /* The PMIC controls backlight enable and this pin must + * be HiZ for normal operation. But the backlight can + * be enabled by setting this pin low and configuring it + * as an output. + */ + gpios = <&gpiob 6 GPIO_INPUT>; + enum-name = "GPIO_ENABLE_BACKLIGHT"; + }; + lid_accel_int_l { + gpios = <&gpioa 1 GPIO_INPUT>; + }; + tp_int_gate { + gpios = <&gpio7 4 GPIO_OUTPUT_LOW>; + }; + gpio_usb_c0_pd_rst_l: usb_c0_pd_rst_l { + gpios = <&gpiof 1 GPIO_OUTPUT_HIGH>; + }; + gpio_usb_c1_pd_rst_l: usb_c1_pd_rst_l { + gpios = <&gpioe 4 GPIO_OUTPUT_HIGH>; + }; + gpio_dp_mux_oe_l: dp_mux_oe_l { + gpios = <&gpiob 1 GPIO_ODR_HIGH>; + }; + gpio_dp_mux_sel: dp_mux_sel { + gpios = <&gpio4 5 GPIO_OUTPUT_LOW>; + }; + gpio_dp_hot_plug_det_r: dp_hot_plug_det_r { + gpios = <&gpio9 5 GPIO_OUTPUT_LOW>; + }; + gpio_en_usb_a_5v: en_usb_a_5v { + gpios = <&gpiof 0 GPIO_OUTPUT_LOW>; + enum-name = "GPIO_EN_USB_A_5V"; + }; + usb_a_cdp_ilim_en_l { + gpios = <&gpio7 5 GPIO_OUTPUT_HIGH>; + }; + gpio_usb_c0_frs_en: usb_c0_frs_en { + gpios = <&gpioc 5 GPIO_OUTPUT_LOW>; + enum-name = "GPIO_USB_C0_FRS_EN"; + }; + gpio_usb_c1_frs_en: usb_c1_frs_en { + gpios = <&gpioc 1 GPIO_OUTPUT_LOW>; + enum-name = "GPIO_USB_C1_FRS_EN"; + }; + gpio_ec_chg_led_y_c0: ec_chg_led_y_c0 { + #led-pin-cells = <1>; + gpios = <&gpio6 0 GPIO_OUTPUT_LOW>; + }; + gpio_ec_chg_led_b_c0: ec_chg_led_b_c0 { + #led-pin-cells = <1>; + gpios = <&gpioc 0 GPIO_OUTPUT_LOW>; + }; + ap_ec_spi_mosi { + gpios = <&gpio4 6 GPIO_INPUT_PULL_DOWN>; + }; + ap_ec_spi_miso { + gpios = <&gpio4 7 GPIO_INPUT_PULL_DOWN>; + }; + ap_ec_spi_clk { + gpios = <&gpio5 5 GPIO_INPUT_PULL_DOWN>; + }; + gpio_brd_id0: brd_id0 { + gpios = <&gpio9 4 GPIO_INPUT>; + enum-name = "GPIO_BOARD_VERSION1"; + }; + gpio_brd_id1: brd_id1 { + gpios = <&gpio9 7 GPIO_INPUT>; + enum-name = "GPIO_BOARD_VERSION2"; + }; + gpio_brd_id2: brd_id2 { + gpios = <&gpioa 5 GPIO_INPUT>; + enum-name = "GPIO_BOARD_VERSION3"; + }; + gpio_sku_id0: sku_id0 { + gpios = <&gpio6 7 GPIO_INPUT>; + }; + gpio_sku_id1: sku_id1 { + gpios = <&gpio7 0 GPIO_INPUT>; + }; + gpio_sku_id2: sku_id2 { + gpios = <&gpioe 1 GPIO_INPUT>; + }; + gpio_switchcap_pg: src_vph_pwr_pg { + gpios = <&gpioe 2 GPIO_INPUT_PULL_DOWN>; + enum-name = "GPIO_SWITCHCAP_PG"; + }; + arm_x86 { + gpios = <&gpio6 6 GPIO_OUTPUT_LOW>; + }; + ec-i2c-sensor-scl { + gpios = <&gpiob 3 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; + }; + ec-i2c-sensor-sda { + gpios = <&gpiob 2 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; + }; + gpio_ec_kso_02_inv: ec_kso_02_inv { + gpios = <&gpio1 7 (GPIO_OUTPUT_LOW | GPIO_ACTIVE_LOW)>; + }; + }; + + usba-port-enable-list { + compatible = "cros-ec,usba-port-enable-pins"; + enable-pins = <&gpio_en_usb_a_5v>; + }; + + sku { + compatible = "cros-ec,gpio-id"; + + bits = < + &gpio_sku_id0 + &gpio_sku_id1 + &gpio_sku_id2 + >; + + system = "ternary"; + }; + + board { + compatible = "cros-ec,gpio-id"; + + bits = < + &gpio_brd_id0 + &gpio_brd_id1 + &gpio_brd_id2 + >; + + system = "ternary"; + }; + + unused-pins { + compatible = "unused-gpios"; + unused-gpios = + <&gpio5 2 0>, + <&gpio5 4 0>, + <&gpio7 6 0>, + <&gpiod 1 0>, + <&gpiod 0 0>, + <&gpioe 3 0>, + <&gpio0 4 0>, + <&gpiod 6 0>, + <&gpio3 2 0>, + <&gpio3 5 0>, + <&gpiod 7 0>, + <&gpio8 6 0>, + <&gpiod 4 0>, + <&gpio4 1 0>, + <&gpio3 4 0>, + <&gpioc 3 0>, + <&gpioc 4 0>, + <&gpioc 7 0>, + <&gpioa 4 0>, + <&gpio9 6 0>, + <&gpio9 3 0>, + <&gpioa 7 0>, + <&gpio5 0 0>, + <&gpio8 1 0>, + <&gpiob 7 0>; + }; +}; + +/* Power switch logic input pads */ +&psl_in1_gpd2 { + /* ACOK_OD */ + psl-in-mode = "edge"; + psl-in-pol = "high-rising"; +}; + +&psl_in2_gp00 { + /* EC_PWR_BTN_ODL */ + psl-in-mode = "edge"; + psl-in-pol = "low-falling"; +}; + +&psl_in3_gp01 { + /* LID_OPEN_EC */ + psl-in-mode = "edge"; + psl-in-pol = "high-rising"; +}; + +&psl_in4_gp02 { + /* RTC_EC_WAKE_ODL */ + psl-in-mode = "edge"; + psl-in-pol = "low-falling"; +}; + +/* Power domain device controlled by PSL (Power Switch Logic) IO pads */ +&power_ctrl_psl { + status = "okay"; + pinctrl-names = "sleep"; + pinctrl-0 = <&psl_in1_gpd2 &psl_in2_gp00 &psl_in3_gp01 &psl_in4_gp02>; +}; diff --git a/zephyr/projects/herobrine/gpio_zombie.dts b/zephyr/projects/herobrine/gpio_zombie.dts new file mode 100644 index 0000000000..14ed1f54d6 --- /dev/null +++ b/zephyr/projects/herobrine/gpio_zombie.dts @@ -0,0 +1,323 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + aliases { + gpio-wp = &gpio_ec_wp_odl; + gpio-kbd-kso2 = &gpio_ec_kso_02_inv; + }; + + named-gpios { + compatible = "named-gpios"; + + gpio_usb_c0_pd_int_odl: usb_c0_pd_int_odl { + gpios = <&gpioe 0 GPIO_INPUT>; + enum-name = "GPIO_USB_C0_PD_INT_ODL"; + }; + gpio_usb_c1_pd_int_odl: usb_c1_pd_int_odl { + gpios = <&gpiof 5 GPIO_INPUT>; + enum-name = "GPIO_USB_C1_PD_INT_ODL"; + }; + gpio_usb_c0_swctl_int_odl: usb_c0_swctl_int_odl { + gpios = <&gpio0 3 GPIO_INPUT>; + enum-name = "GPIO_USB_C0_SWCTL_INT_ODL"; + }; + gpio_usb_c1_swctl_int_odl: usb_c1_swctl_int_odl { + gpios = <&gpio4 0 GPIO_INPUT>; + enum-name = "GPIO_USB_C1_SWCTL_INT_ODL"; + }; + gpio_usb_c0_bc12_int_l: usb_c0_bc12_int_l { + gpios = <&gpio6 1 GPIO_INPUT_PULL_UP>; + }; + gpio_usb_c1_bc12_int_l: usb_c1_bc12_int_l { + gpios = <&gpio8 2 GPIO_INPUT_PULL_UP>; + }; + gpio_usb_a0_oc_odl: usb_a0_oc_odl { + gpios = <&gpiof 4 GPIO_INPUT_PULL_UP>; + }; + gpio_chg_acok_od: chg_acok_od { + gpios = <&gpiod 2 GPIO_INPUT>; + enum-name = "GPIO_AC_PRESENT"; + }; + gpio_ec_pwr_btn_odl: ec_pwr_btn_odl { + gpios = <&gpio0 0 GPIO_INPUT>; + enum-name = "GPIO_POWER_BUTTON_L"; + }; + gpio_ec_voldn_btn_odl: ec_voldn_btn_odl { + gpios = <&gpio6 2 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_VOLUME_DOWN_L"; + }; + gpio_ec_volup_btn_odl: ec_volup_btn_odl { + gpios = <&gpioc 2 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_VOLUME_UP_L"; + }; + gpio_ec_wp_odl: ec_wp_odl { + gpios = <&gpiod 3 (GPIO_INPUT | GPIO_ACTIVE_LOW)>; + }; + gpio_lid_open_ec: lid_open_ec { + gpios = <&gpio0 1 GPIO_INPUT>; + enum-name = "GPIO_LID_OPEN"; + }; + gpio_ap_rst_l: ap_rst_l { + gpios = <&gpio5 1 GPIO_INPUT>; + enum-name = "GPIO_AP_RST_L"; + }; + gpio_ps_hold: ps_hold { + gpios = <&gpioa 6 GPIO_INPUT_PULL_DOWN>; + enum-name = "GPIO_PS_HOLD"; + }; + gpio_ap_suspend: ap_suspend { + gpios = <&gpio5 7 GPIO_INPUT>; + enum-name = "GPIO_AP_SUSPEND"; + }; + gpio_mb_power_good: mb_power_good { + gpios = <&gpio3 7 GPIO_INPUT_PULL_DOWN>; + enum-name = "GPIO_POWER_GOOD"; + }; + gpio_warm_reset_l: warm_reset_l { + gpios = <&gpiob 0 GPIO_INPUT>; + enum-name = "GPIO_WARM_RESET_L"; + }; + ap_ec_spi_cs_l { + gpios = <&gpio5 3 GPIO_INPUT_PULL_DOWN>; + }; + gpio_tablet_mode_l: tablet_mode_l { + gpios = <&gpioc 6 GPIO_INPUT>; + enum-name = "GPIO_TABLET_MODE_L"; + }; + gpio_accel_gyro_int_l: accel_gyro_int_l { + gpios = <&gpioa 3 GPIO_INPUT>; + }; + gpio_rtc_ec_wake_odl: rtc_ec_wake_odl { + gpios = <&gpio0 2 GPIO_INPUT>; + }; + ec_entering_rw { + gpios = <&gpio7 2 GPIO_OUTPUT_LOW>; + enum-name = "GPIO_ENTERING_RW"; + }; + ccd_mode_odl { + gpios = <&gpio6 3 GPIO_INPUT>; + enum-name = "GPIO_CCD_MODE_ODL"; + }; + ec_batt_pres_odl { + gpios = <&gpioe 5 GPIO_INPUT>; + enum-name = "GPIO_BATT_PRES_ODL"; + }; + ec_gsc_packet_mode { + gpios = <&gpio8 3 GPIO_OUTPUT_LOW>; + enum-name = "GPIO_PACKET_MODE_EN"; + }; + pmic_resin_l { + gpios = <&gpioa 0 GPIO_ODR_HIGH>; + enum-name = "GPIO_PMIC_RESIN_L"; + }; + pmic_kpd_pwr_odl { + gpios = <&gpioa 2 GPIO_ODR_HIGH>; + enum-name = "GPIO_PMIC_KPD_PWR_ODL"; + }; + ap_ec_int_l { + gpios = <&gpio5 6 GPIO_ODR_HIGH>; + enum-name = "GPIO_EC_INT_L"; + }; + gpio_switchcap_on: switchcap_on { + gpios = <&gpiod 5 GPIO_OUTPUT_LOW>; + enum-name = "GPIO_SWITCHCAP_ON"; + }; + gpio_en_pp5000_s5: en_pp5000_s5 { + gpios = <&gpio7 3 GPIO_OUTPUT_HIGH>; + enum-name = "GPIO_EN_PP5000"; + }; + ec_bl_disable_l { + /* The PMIC controls backlight enable and this pin must + * be HiZ for normal operation. But the backlight can + * be enabled by setting this pin low and configuring it + * as an output. + */ + gpios = <&gpiob 6 GPIO_INPUT>; + enum-name = "GPIO_ENABLE_BACKLIGHT"; + }; + lid_accel_int_l { + gpios = <&gpioa 1 GPIO_INPUT>; + }; + tp_int_gate { + gpios = <&gpio7 4 GPIO_OUTPUT_LOW>; + }; + gpio_usb_c0_pd_rst_l: usb_c0_pd_rst_l { + gpios = <&gpiof 1 GPIO_OUTPUT_HIGH>; + }; + gpio_usb_c1_pd_rst_l: usb_c1_pd_rst_l { + gpios = <&gpioe 4 GPIO_OUTPUT_HIGH>; + }; + gpio_dp_mux_oe_l: dp_mux_oe_l { + gpios = <&gpiob 1 GPIO_ODR_HIGH>; + }; + gpio_dp_mux_sel: dp_mux_sel { + gpios = <&gpio4 5 GPIO_OUTPUT_LOW>; + }; + gpio_dp_hot_plug_det_r: dp_hot_plug_det_r { + gpios = <&gpio9 5 GPIO_OUTPUT_LOW>; + }; + gpio_en_usb_a_5v: en_usb_a_5v { + gpios = <&gpiof 0 GPIO_OUTPUT_LOW>; + enum-name = "GPIO_EN_USB_A_5V"; + }; + usb_a_cdp_ilim_en_l { + gpios = <&gpio7 5 GPIO_OUTPUT_HIGH>; + }; + gpio_usb_c0_frs_en: usb_c0_frs_en { + gpios = <&gpioc 5 GPIO_OUTPUT_LOW>; + enum-name = "GPIO_USB_C0_FRS_EN"; + }; + gpio_usb_c1_frs_en: usb_c1_frs_en { + gpios = <&gpioc 1 GPIO_OUTPUT_LOW>; + enum-name = "GPIO_USB_C1_FRS_EN"; + }; + gpio_ec_chg_led_y_c0: ec_chg_led_y_c0 { + #led-pin-cells = <1>; + gpios = <&gpio6 0 GPIO_OUTPUT_LOW>; + }; + gpio_ec_chg_led_b_c0: ec_chg_led_b_c0 { + #led-pin-cells = <1>; + gpios = <&gpioc 0 GPIO_OUTPUT_LOW>; + }; + ap_ec_spi_mosi { + gpios = <&gpio4 6 GPIO_INPUT_PULL_DOWN>; + }; + ap_ec_spi_miso { + gpios = <&gpio4 7 GPIO_INPUT_PULL_DOWN>; + }; + ap_ec_spi_clk { + gpios = <&gpio5 5 GPIO_INPUT_PULL_DOWN>; + }; + gpio_brd_id0: brd_id0 { + gpios = <&gpio9 4 GPIO_INPUT>; + enum-name = "GPIO_BOARD_VERSION1"; + }; + gpio_brd_id1: brd_id1 { + gpios = <&gpio9 7 GPIO_INPUT>; + enum-name = "GPIO_BOARD_VERSION2"; + }; + gpio_brd_id2: brd_id2 { + gpios = <&gpioa 5 GPIO_INPUT>; + enum-name = "GPIO_BOARD_VERSION3"; + }; + gpio_sku_id0: sku_id0 { + gpios = <&gpio6 7 GPIO_INPUT>; + }; + gpio_sku_id1: sku_id1 { + gpios = <&gpio7 0 GPIO_INPUT>; + }; + gpio_sku_id2: sku_id2 { + gpios = <&gpioe 1 GPIO_INPUT>; + }; + gpio_switchcap_pg: src_vph_pwr_pg { + gpios = <&gpioe 2 GPIO_INPUT_PULL_DOWN>; + enum-name = "GPIO_SWITCHCAP_PG"; + }; + arm_x86 { + gpios = <&gpio6 6 GPIO_OUTPUT_LOW>; + }; + ec-i2c-sensor-scl { + gpios = <&gpiob 3 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; + }; + ec-i2c-sensor-sda { + gpios = <&gpiob 2 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; + }; + gpio_ec_kso_02_inv: ec_kso_02_inv { + gpios = <&gpio1 7 (GPIO_OUTPUT_LOW | GPIO_ACTIVE_LOW)>; + }; + }; + + usba-port-enable-list { + compatible = "cros-ec,usba-port-enable-pins"; + enable-pins = <&gpio_en_usb_a_5v>; + }; + + sku { + compatible = "cros-ec,gpio-id"; + + bits = < + &gpio_sku_id0 + &gpio_sku_id1 + &gpio_sku_id2 + >; + + system = "ternary"; + }; + + board { + compatible = "cros-ec,gpio-id"; + + bits = < + &gpio_brd_id0 + &gpio_brd_id1 + &gpio_brd_id2 + >; + + system = "ternary"; + }; + + unused-pins { + compatible = "unused-gpios"; + unused-gpios = + <&gpio5 2 0>, + <&gpio5 4 0>, + <&gpio7 6 0>, + <&gpiod 1 0>, + <&gpiod 0 0>, + <&gpioe 3 0>, + <&gpio0 4 0>, + <&gpiod 6 0>, + <&gpio3 2 0>, + <&gpio3 5 0>, + <&gpiod 7 0>, + <&gpio8 6 0>, + <&gpiod 4 0>, + <&gpio4 1 0>, + <&gpio3 4 0>, + <&gpioc 3 0>, + <&gpioc 4 0>, + <&gpioc 7 0>, + <&gpioa 4 0>, + <&gpio9 6 0>, + <&gpio9 3 0>, + <&gpioa 7 0>, + <&gpio5 0 0>, + <&gpio8 1 0>, + <&gpiob 7 0>; + }; +}; + +/* Power switch logic input pads */ +&psl_in1_gpd2 { + /* ACOK_OD */ + psl-in-mode = "edge"; + psl-in-pol = "high-rising"; +}; + +&psl_in2_gp00 { + /* EC_PWR_BTN_ODL */ + psl-in-mode = "edge"; + psl-in-pol = "low-falling"; +}; + +&psl_in3_gp01 { + /* LID_OPEN_EC */ + psl-in-mode = "edge"; + psl-in-pol = "high-rising"; +}; + +&psl_in4_gp02 { + /* RTC_EC_WAKE_ODL */ + psl-in-mode = "edge"; + psl-in-pol = "low-falling"; +}; + +/* Power domain device controlled by PSL (Power Switch Logic) IO pads */ +&power_ctrl_psl { + status = "okay"; + pinctrl-names = "sleep"; + pinctrl-0 = <&psl_in1_gpd2 &psl_in2_gp00 &psl_in3_gp01 &psl_in4_gp02>; +}; diff --git a/zephyr/projects/herobrine/i2c_common.dtsi b/zephyr/projects/herobrine/i2c_common.dtsi new file mode 100644 index 0000000000..b1ed0242c0 --- /dev/null +++ b/zephyr/projects/herobrine/i2c_common.dtsi @@ -0,0 +1,157 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + aliases { + i2c-0 = &i2c0_0; + i2c-1 = &i2c1_0; + i2c-2 = &i2c2_0; + i2c-3 = &i2c3_0; + i2c-4 = &i2c4_1; + i2c-5 = &i2c5_0; + i2c-7 = &i2c7_0; + }; + + named-i2c-ports { + compatible = "named-i2c-ports"; + + i2c_power: power { + i2c-port = <&i2c0_0>; + remote-port = <0>; + enum-names = "I2C_PORT_POWER", + "I2C_PORT_BATTERY", + "I2C_PORT_VIRTUAL_BATTERY", + "I2C_PORT_CHARGER"; + }; + i2c_tcpc0: tcpc0 { + i2c-port = <&i2c1_0>; + dynamic-speed; + enum-names = "I2C_PORT_TCPC0"; + }; + i2c_tcpc1: tcpc1 { + i2c-port = <&i2c2_0>; + dynamic-speed; + enum-names = "I2C_PORT_TCPC1"; + }; + rtc { + i2c-port = <&i2c4_1>; + enum-names = "I2C_PORT_RTC"; + }; + i2c_eeprom: eeprom { + i2c-port = <&i2c5_0>; + enum-names = "I2C_PORT_EEPROM"; + }; + i2c_sensor: sensor { + i2c-port = <&i2c7_0>; + enum-names = "I2C_PORT_SENSOR", + "I2C_PORT_ACCEL"; + }; + }; + + +}; + +&i2c0_0 { + label = "I2C_POWER"; + status = "okay"; + clock-frequency = <I2C_BITRATE_STANDARD>; + pinctrl-0 = <&i2c0_0_sda_scl_gpb4_b5>; + pinctrl-names = "default"; + + bc12_port0: pi3usb9201@5f { + compatible = "pericom,pi3usb9201"; + status = "okay"; + reg = <0x5f>; + irq = <&int_usb_c0_bc12>; + }; + + charger: isl923x@9 { + compatible = "intersil,isl923x"; + status = "okay"; + reg = <0x9>; + }; +}; + +&i2c_ctrl0 { + status = "okay"; +}; + +&i2c1_0 { + label = "I2C_USB_C0_PD"; + status = "okay"; + clock-frequency = <I2C_BITRATE_FAST_PLUS>; + pinctrl-0 = <&i2c1_0_sda_scl_gp87_90>; + pinctrl-names = "default"; +}; + +&i2c_ctrl1 { + status = "okay"; +}; + +&i2c2_0 { + label = "I2C_USB_C1_PD"; + status = "okay"; + clock-frequency = <I2C_BITRATE_FAST_PLUS>; + pinctrl-0 = <&i2c2_0_sda_scl_gp91_92>; + pinctrl-names = "default"; +}; + +&i2c_ctrl2 { + status = "okay"; +}; + +&i2c3_0 { + /* Not used as no WLC connected */ + clock-frequency = <I2C_BITRATE_FAST>; +}; + +&i2c4_1 { + label = "I2C_RTC"; + status = "okay"; + clock-frequency = <I2C_BITRATE_FAST>; + pinctrl-0 = <&i2c4_1_sda_scl_gpf2_f3>; + pinctrl-names = "default"; + + pcf85063a: pcf85063a@51 { + compatible = "nxp,rtc-pcf85063a"; + reg = <0x51>; + int-pin = <&gpio_rtc_ec_wake_odl>; + }; +}; + +&i2c_ctrl4 { + status = "okay"; +}; + +&i2c5_0 { + label = "I2C_EEPROM"; + status = "okay"; + clock-frequency = <I2C_BITRATE_FAST>; + pinctrl-0 = <&i2c5_0_sda_scl_gp33_36>; + pinctrl-names = "default"; + + bc12_port1: pi3usb9201@5f { + compatible = "pericom,pi3usb9201"; + status = "okay"; + reg = <0x5f>; + irq = <&int_usb_c1_bc12>; + }; +}; + +&i2c_ctrl5 { + status = "okay"; +}; + +&i2c7_0 { + label = "I2C_SENSOR"; + status = "okay"; + clock-frequency = <I2C_BITRATE_FAST>; + pinctrl-0 = <&i2c7_0_sda_scl_gpb2_b3>; + pinctrl-names = "default"; +}; + +&i2c_ctrl7 { + status = "okay"; +}; diff --git a/zephyr/projects/herobrine/i2c_evoker.dts b/zephyr/projects/herobrine/i2c_evoker.dts new file mode 100644 index 0000000000..7023d08c8d --- /dev/null +++ b/zephyr/projects/herobrine/i2c_evoker.dts @@ -0,0 +1,46 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "i2c_common.dtsi" + +&i2c1_0 { + ppc_port0: syv682x@41 { + compatible = "silergy,syv682x"; + status = "okay"; + reg = <0x41>; + frs_en_gpio = <&gpio_usb_c0_frs_en>; + }; + + ppc_port0_alt: sn5s330@40 { + compatible = "ti,sn5s330"; + status = "okay"; + reg = <0x40>; + }; + + tcpc_port0: ps8xxx@b { + compatible = "parade,ps8xxx"; + reg = <0xb>; + }; +}; + +&i2c2_0 { + ppc_port1: syv682x@41 { + compatible = "silergy,syv682x"; + status = "okay"; + reg = <0x41>; + frs_en_gpio = <&gpio_usb_c1_frs_en>; + }; + + ppc_port1_alt: sn5s330@40 { + compatible = "ti,sn5s330"; + status = "okay"; + reg = <0x40>; + }; + + tcpc_port1: ps8xxx@b { + compatible = "parade,ps8xxx"; + reg = <0xb>; + }; +}; diff --git a/zephyr/projects/herobrine/i2c_herobrine.dts b/zephyr/projects/herobrine/i2c_herobrine.dts new file mode 100644 index 0000000000..92c68f4215 --- /dev/null +++ b/zephyr/projects/herobrine/i2c_herobrine.dts @@ -0,0 +1,39 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "i2c_common.dtsi" + +&i2c1_0 { + ppc_port0: sn5s330@40 { + compatible = "ti,sn5s330"; + status = "okay"; + reg = <0x40>; + }; + + ppc_port0_alt: syv682x@41 { + compatible = "silergy,syv682x"; + status = "okay"; + reg = <0x41>; + frs_en_gpio = <&gpio_usb_c0_frs_en>; + }; + + tcpc_port0: ps8xxx@b { + compatible = "parade,ps8xxx"; + reg = <0xb>; + }; +}; + +&i2c2_0 { + ppc_port1: sn5s330@40 { + compatible = "ti,sn5s330"; + status = "okay"; + reg = <0x40>; + }; + + tcpc_port1: ps8xxx@b { + compatible = "parade,ps8xxx"; + reg = <0xb>; + }; +}; diff --git a/zephyr/projects/herobrine/i2c_hoglin.dts b/zephyr/projects/herobrine/i2c_hoglin.dts new file mode 100644 index 0000000000..504dbb9248 --- /dev/null +++ b/zephyr/projects/herobrine/i2c_hoglin.dts @@ -0,0 +1,34 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "i2c_common.dtsi" + +&i2c1_0 { + ppc_port0: syv682x@41 { + compatible = "silergy,syv682x"; + status = "okay"; + reg = <0x41>; + frs_en_gpio = <&gpio_usb_c0_frs_en>; + }; + + tcpc_port0: ps8xxx@1b { + compatible = "parade,ps8xxx"; + reg = <0x1b>; + }; +}; + +&i2c2_0 { + ppc_port1: syv682x@41 { + compatible = "silergy,syv682x"; + status = "okay"; + reg = <0x41>; + frs_en_gpio = <&gpio_usb_c1_frs_en>; + }; + + tcpc_port1: ps8xxx@1b { + compatible = "parade,ps8xxx"; + reg = <0x1b>; + }; +}; diff --git a/zephyr/projects/herobrine/i2c_villager.dts b/zephyr/projects/herobrine/i2c_villager.dts new file mode 100644 index 0000000000..efdf88ac38 --- /dev/null +++ b/zephyr/projects/herobrine/i2c_villager.dts @@ -0,0 +1,34 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "i2c_common.dtsi" + +&i2c1_0 { + ppc_port0: syv682x@41 { + compatible = "silergy,syv682x"; + status = "okay"; + reg = <0x41>; + frs_en_gpio = <&gpio_usb_c0_frs_en>; + }; + + tcpc_port0: ps8xxx@b { + compatible = "parade,ps8xxx"; + reg = <0xb>; + }; +}; + +&i2c2_0 { + ppc_port1: syv682x@41 { + compatible = "silergy,syv682x"; + status = "okay"; + reg = <0x41>; + frs_en_gpio = <&gpio_usb_c1_frs_en>; + }; + + tcpc_port1: ps8xxx@b { + compatible = "parade,ps8xxx"; + reg = <0xb>; + }; +}; diff --git a/zephyr/projects/herobrine/i2c_zombie.dts b/zephyr/projects/herobrine/i2c_zombie.dts new file mode 100644 index 0000000000..efdf88ac38 --- /dev/null +++ b/zephyr/projects/herobrine/i2c_zombie.dts @@ -0,0 +1,34 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "i2c_common.dtsi" + +&i2c1_0 { + ppc_port0: syv682x@41 { + compatible = "silergy,syv682x"; + status = "okay"; + reg = <0x41>; + frs_en_gpio = <&gpio_usb_c0_frs_en>; + }; + + tcpc_port0: ps8xxx@b { + compatible = "parade,ps8xxx"; + reg = <0xb>; + }; +}; + +&i2c2_0 { + ppc_port1: syv682x@41 { + compatible = "silergy,syv682x"; + status = "okay"; + reg = <0x41>; + frs_en_gpio = <&gpio_usb_c1_frs_en>; + }; + + tcpc_port1: ps8xxx@b { + compatible = "parade,ps8xxx"; + reg = <0xb>; + }; +}; diff --git a/zephyr/projects/herobrine/include/board_chipset.h b/zephyr/projects/herobrine/include/board_chipset.h new file mode 100644 index 0000000000..81c0dd1a40 --- /dev/null +++ b/zephyr/projects/herobrine/include/board_chipset.h @@ -0,0 +1,11 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#ifndef __CROS_EC_HEROBRINE_BOARD_CHIPSET_H +#define __CROS_EC_HEROBRINE_BOARD_CHIPSET_H + +__test_only void reset_pp5000_inited(void); + +#endif /* __CROS_EC_HEROBRINE_BOARD_CHIPSET_H */ diff --git a/zephyr/projects/herobrine/interrupts.dts b/zephyr/projects/herobrine/interrupts.dts new file mode 100644 index 0000000000..82650bfc51 --- /dev/null +++ b/zephyr/projects/herobrine/interrupts.dts @@ -0,0 +1,115 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + aliases { + int-wp = &int_wp_l; + }; + + gpio-interrupts { + compatible = "cros-ec,gpio-interrupts"; + + int_ac_present: ac_present { + irq-pin = <&gpio_chg_acok_od>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "extpower_interrupt"; + }; + int_lid_open: lid_open { + irq-pin = <&gpio_lid_open_ec>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "lid_interrupt"; + }; + int_wp_l: wp_l { + irq-pin = <&gpio_ec_wp_odl>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "switch_interrupt"; + }; + int_power_button: power_button { + irq-pin = <&gpio_ec_pwr_btn_odl>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "power_button_interrupt"; + }; + int_volume_up: volume_up { + irq-pin = <&gpio_ec_volup_btn_odl>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "button_interrupt"; + }; + int_volume_down: volume_down { + irq-pin = <&gpio_ec_voldn_btn_odl>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "button_interrupt"; + }; + int_ap_rst: ap_rst { + irq-pin = <&gpio_ap_rst_l>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "chipset_ap_rst_interrupt"; + }; + int_ap_suspend: ap_suspend { + irq-pin = <&gpio_ap_suspend>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "power_signal_interrupt"; + }; + int_power_good: power_good { + irq-pin = <&gpio_mb_power_good>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "power_signal_interrupt"; + }; + int_ps_hold: ps_hold { + irq-pin = <&gpio_ps_hold>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "power_signal_interrupt"; + }; + int_warm_reset: warm_reset { + irq-pin = <&gpio_warm_reset_l>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "power_signal_interrupt"; + }; + int_usb_c0_pd: usb_c0_pd { + irq-pin = <&gpio_usb_c0_pd_int_odl>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "tcpc_alert_event"; + }; + int_usb_c1_pd: usb_c1_pd { + irq-pin = <&gpio_usb_c1_pd_int_odl>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "tcpc_alert_event"; + }; + int_usb_c0_swctl: usb_c0_swctl { + irq-pin = <&gpio_usb_c0_swctl_int_odl>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "ppc_interrupt"; + }; + int_usb_c1_swctl: usb_c1_swctl { + irq-pin = <&gpio_usb_c1_swctl_int_odl>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "ppc_interrupt"; + }; + int_usb_c0_bc12: usb_c0_bc12 { + irq-pin = <&gpio_usb_c0_bc12_int_l>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "usb0_evt"; + }; + int_usb_c1_bc12: usb_c1_bc12 { + irq-pin = <&gpio_usb_c1_bc12_int_l>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "usb1_evt"; + }; + int_usb_a0_oc: usb_a0_oc { + irq-pin = <&gpio_usb_a0_oc_odl>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "usba_oc_interrupt"; + }; + int_accel_gyro: accel_gyro { + irq-pin = <&gpio_accel_gyro_int_l>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "bmi260_interrupt"; + }; + int_tablet_mode: tablet_mode { + irq-pin = <&gpio_tablet_mode_l>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "gmr_tablet_switch_isr"; + }; + }; +}; diff --git a/zephyr/projects/herobrine/keyboard.dts b/zephyr/projects/herobrine/keyboard.dts new file mode 100644 index 0000000000..3b7e830f2f --- /dev/null +++ b/zephyr/projects/herobrine/keyboard.dts @@ -0,0 +1,46 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + kblight { + compatible = "cros-ec,kblight-pwm"; + pwms = <&pwm3 0 PWM_KHZ(10) PWM_POLARITY_NORMAL>; + generic-pwm-channel = <0>; + }; +}; + +&pwm3 { + status = "okay"; + pinctrl-0 = <&pwm3_gp80>; + pinctrl-names = "default"; +}; + +&cros_kb_raw { + status = "okay"; + /* No KSO2 (it's inverted and implemented by GPIO) */ + pinctrl-0 = < + &ksi0_gp31 + &ksi1_gp30 + &ksi2_gp27 + &ksi3_gp26 + &ksi4_gp25 + &ksi5_gp24 + &ksi6_gp23 + &ksi7_gp22 + &kso00_gp21 + &kso01_gp20 + &kso03_gp16 + &kso04_gp15 + &kso05_gp14 + &kso06_gp13 + &kso07_gp12 + &kso08_gp11 + &kso09_gp10 + &kso10_gp07 + &kso11_gp06 + &kso12_gp05 + >; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/herobrine/led_pins_evoker.dts b/zephyr/projects/herobrine/led_pins_evoker.dts new file mode 100644 index 0000000000..ff2dc0e36c --- /dev/null +++ b/zephyr/projects/herobrine/led_pins_evoker.dts @@ -0,0 +1,54 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + gpio-led-pins { + compatible = "cros-ec,gpio-led-pins"; + + color_power_off: color-power-off { + led-color = "LED_OFF"; + led-id = "EC_LED_ID_POWER_LED"; + led-pins = <&gpio_ec_chg_led_w_c1 0>; + }; + + color_power_white: color-power-white { + led-color = "LED_WHITE"; + led-id = "EC_LED_ID_POWER_LED"; + led-pins = <&gpio_ec_chg_led_w_c1 1>; + }; + + color_battery_off: color-battery-off { + led-color = "LED_OFF"; + led-id = "EC_LED_ID_BATTERY_LED"; + led-pins = <&gpio_ec_chg_led_y_c0 0>, + <&gpio_ec_chg_led_w_c0 0>, + <&gpio_ec_chg_led_r_c0 0>; + }; + + color_battery_amber: color-battery-amber { + led-color = "LED_AMBER"; + led-id = "EC_LED_ID_BATTERY_LED"; + led-pins = <&gpio_ec_chg_led_y_c0 1>, + <&gpio_ec_chg_led_w_c0 0>, + <&gpio_ec_chg_led_r_c0 0>; + }; + + color_battery_white: color-battery-white { + led-color = "LED_WHITE"; + led-id = "EC_LED_ID_BATTERY_LED"; + led-pins = <&gpio_ec_chg_led_y_c0 0>, + <&gpio_ec_chg_led_w_c0 1>, + <&gpio_ec_chg_led_r_c0 0>; + }; + + color_battery_red: color-battery-red { + led-color = "LED_RED"; + led-id = "EC_LED_ID_BATTERY_LED"; + led-pins = <&gpio_ec_chg_led_y_c0 0>, + <&gpio_ec_chg_led_w_c0 0>, + <&gpio_ec_chg_led_r_c0 1>; + }; + }; +}; diff --git a/zephyr/projects/herobrine/led_pins_herobrine.dts b/zephyr/projects/herobrine/led_pins_herobrine.dts new file mode 100644 index 0000000000..c509ab1a64 --- /dev/null +++ b/zephyr/projects/herobrine/led_pins_herobrine.dts @@ -0,0 +1,56 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + gpio-led-pins { + compatible = "cros-ec,gpio-led-pins"; + + color_off_left: color-off-left { + led-color = "LED_OFF"; + led-id = "EC_LED_ID_LEFT_LED"; + led-pins = <&gpio_ec_chg_led_y_c1 0>, + <&gpio_ec_chg_led_w_c1 0>; + }; + + color_off_right: color-off-right { + led-color = "LED_OFF"; + led-id = "EC_LED_ID_RIGHT_LED"; + led-pins = <&gpio_ec_chg_led_y_c0 0>, + <&gpio_ec_chg_led_w_c0 0>; + }; + + color_amber_left: color-amber-left { + led-color = "LED_AMBER"; + led-id = "EC_LED_ID_LEFT_LED"; + br-color = "EC_LED_COLOR_AMBER"; + led-pins = <&gpio_ec_chg_led_y_c1 1>, + <&gpio_ec_chg_led_w_c1 0>; + }; + + color_amber_right: color-amber-right { + led-color = "LED_AMBER"; + led-id = "EC_LED_ID_RIGHT_LED"; + br-color = "EC_LED_COLOR_AMBER"; + led-pins = <&gpio_ec_chg_led_y_c0 1>, + <&gpio_ec_chg_led_w_c0 0>; + }; + + color_white_left: color-white-left { + led-color = "LED_WHITE"; + led-id = "EC_LED_ID_LEFT_LED"; + br-color = "EC_LED_COLOR_WHITE"; + led-pins = <&gpio_ec_chg_led_y_c1 0>, + <&gpio_ec_chg_led_w_c1 1>; + }; + + color_white_right: color-white-right { + led-color = "LED_WHITE"; + led-id = "EC_LED_ID_RIGHT_LED"; + br-color = "EC_LED_COLOR_WHITE"; + led-pins = <&gpio_ec_chg_led_y_c0 0>, + <&gpio_ec_chg_led_w_c0 1>; + }; + }; +}; diff --git a/zephyr/projects/herobrine/led_pins_hoglin.dts b/zephyr/projects/herobrine/led_pins_hoglin.dts new file mode 100644 index 0000000000..7b125c5cac --- /dev/null +++ b/zephyr/projects/herobrine/led_pins_hoglin.dts @@ -0,0 +1,33 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + gpio-led-pins { + compatible = "cros-ec,gpio-led-pins"; + + color_off: color-off { + led-color = "LED_OFF"; + led-id = "EC_LED_ID_BATTERY_LED"; + led-pins = <&gpio_ec_chg_led_b_c0 0>, + <&gpio_ec_chg_led_r_c0 0>; + }; + + color_blue: color-blue { + led-color = "LED_BLUE"; + led-id = "EC_LED_ID_BATTERY_LED"; + br-color = "EC_LED_COLOR_BLUE"; + led-pins = <&gpio_ec_chg_led_b_c0 1>, + <&gpio_ec_chg_led_r_c0 0>; + }; + + color_red: color-red { + led-color = "LED_RED"; + led-id = "EC_LED_ID_BATTERY_LED"; + br-color = "EC_LED_COLOR_RED"; + led-pins = <&gpio_ec_chg_led_b_c0 0>, + <&gpio_ec_chg_led_r_c0 1>; + }; + }; +}; diff --git a/zephyr/projects/herobrine/led_pins_villager.dts b/zephyr/projects/herobrine/led_pins_villager.dts new file mode 100644 index 0000000000..b0913cdbce --- /dev/null +++ b/zephyr/projects/herobrine/led_pins_villager.dts @@ -0,0 +1,33 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + gpio-led-pins { + compatible = "cros-ec,gpio-led-pins"; + + color_off: color-off { + led-color = "LED_OFF"; + led-id = "EC_LED_ID_BATTERY_LED"; + led-pins = <&gpio_ec_chg_led_y_c0 0>, + <&gpio_ec_chg_led_b_c0 0>; + }; + + color_amber: color-amber { + led-color = "LED_AMBER"; + led-id = "EC_LED_ID_BATTERY_LED"; + br-color = "EC_LED_COLOR_AMBER"; + led-pins = <&gpio_ec_chg_led_y_c0 1>, + <&gpio_ec_chg_led_b_c0 0>; + }; + + color_blue: color-blue { + led-color = "LED_BLUE"; + led-id = "EC_LED_ID_BATTERY_LED"; + br-color = "EC_LED_COLOR_BLUE"; + led-pins = <&gpio_ec_chg_led_y_c0 0>, + <&gpio_ec_chg_led_b_c0 1>; + }; + }; +}; diff --git a/zephyr/projects/herobrine/led_pins_zombie.dts b/zephyr/projects/herobrine/led_pins_zombie.dts new file mode 100644 index 0000000000..b0913cdbce --- /dev/null +++ b/zephyr/projects/herobrine/led_pins_zombie.dts @@ -0,0 +1,33 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + gpio-led-pins { + compatible = "cros-ec,gpio-led-pins"; + + color_off: color-off { + led-color = "LED_OFF"; + led-id = "EC_LED_ID_BATTERY_LED"; + led-pins = <&gpio_ec_chg_led_y_c0 0>, + <&gpio_ec_chg_led_b_c0 0>; + }; + + color_amber: color-amber { + led-color = "LED_AMBER"; + led-id = "EC_LED_ID_BATTERY_LED"; + br-color = "EC_LED_COLOR_AMBER"; + led-pins = <&gpio_ec_chg_led_y_c0 1>, + <&gpio_ec_chg_led_b_c0 0>; + }; + + color_blue: color-blue { + led-color = "LED_BLUE"; + led-id = "EC_LED_ID_BATTERY_LED"; + br-color = "EC_LED_COLOR_BLUE"; + led-pins = <&gpio_ec_chg_led_y_c0 0>, + <&gpio_ec_chg_led_b_c0 1>; + }; + }; +}; diff --git a/zephyr/projects/herobrine/led_policy_evoker.dts b/zephyr/projects/herobrine/led_policy_evoker.dts new file mode 100644 index 0000000000..fc17755ede --- /dev/null +++ b/zephyr/projects/herobrine/led_policy_evoker.dts @@ -0,0 +1,86 @@ +#include <dt-bindings/battery.h> + +/ { + led-colors { + compatible = "cros-ec,led-policy"; + + battery-state-charge { + charge-state = "PWR_STATE_CHARGE"; + + color-0 { + led-color = <&color_battery_amber>; + }; + }; + + battery-state-near-full { + charge-state = "PWR_STATE_CHARGE_NEAR_FULL"; + + color-0 { + led-color = <&color_battery_white>; + }; + }; + + battery-state-discharge { + charge-state = "PWR_STATE_DISCHARGE"; + + color-0 { + led-color = <&color_battery_off>; + }; + }; + + battery-state-error { + charge-state = "PWR_STATE_ERROR"; + + color-0 { + led-color = <&color_battery_red>; + }; + }; + + /* force idle mode */ + battery-state-forced-idle { + charge-state = "PWR_STATE_FORCED_IDLE"; + + /* Red 1 sec, White 1 sec */ + color-0 { + led-color = <&color_battery_red>; + period-ms = <1000>; + }; + + color-1 { + led-color = <&color_battery_white>; + period-ms = <1000>; + }; + }; + + pwr-power-state-s0 { + chipset-state = "POWER_S0"; + + color-0 { + led-color = <&color_power_white>; + }; + }; + + power-state-s3 { + chipset-state = "POWER_S3"; + + /* white LED - on 1 sec, off 1 sec */ + color-0 { + led-color = <&color_power_white>; + period-ms = <1000>; + }; + + color-1 { + led-color = <&color_power_off>; + period-ms = <1000>; + }; + }; + + power-state-s5 { + chipset-state = "POWER_S5"; + + color-0 { + led-color = <&color_power_off>; + }; + }; + }; +}; diff --git a/zephyr/projects/herobrine/led_policy_herobrine.dts b/zephyr/projects/herobrine/led_policy_herobrine.dts new file mode 100644 index 0000000000..13e5306deb --- /dev/null +++ b/zephyr/projects/herobrine/led_policy_herobrine.dts @@ -0,0 +1,202 @@ +#include <dt-bindings/battery.h> + +/ { + led-colors { + compatible = "cros-ec,led-policy"; + + power-state-charge-left { + charge-state = "PWR_STATE_CHARGE"; + charge-port = <1>; /* Left port */ + + /* Turn off the right LED */ + color-0 { + led-color = <&color_off_right>; + }; + /* Left LED to Amber */ + color-1 { + led-color = <&color_amber_left>; + }; + }; + + power-state-charge-right { + charge-state = "PWR_STATE_CHARGE"; + charge-port = <0>; /* Right port */ + + /* Turn off the left LED */ + color-0 { + led-color = <&color_off_left>; + }; + /* Right LED to Amber */ + color-1 { + led-color = <&color_amber_right>; + }; + }; + + power-state-discharge-right-low { + charge-state = "PWR_STATE_DISCHARGE"; + /* Battery percent range (>= Empty, <= Low) */ + batt-lvl = <BATTERY_LEVEL_EMPTY BATTERY_LEVEL_LOW>; + + /* Turn off the left LED */ + color-0 { + led-color = <&color_off_left>; + }; + /* Right LED - White 1 sec, off 3 sec */ + color-1 { + led-color = <&color_white_right>; + period-ms = <1000>; + }; + color-2 { + led-color = <&color_off_right>; + period-ms = <3000>; + }; + }; + + power-state-discharge-right { + charge-state = "PWR_STATE_DISCHARGE"; + /* Battery percent range (> Low, <= Full) */ + batt-lvl = <(BATTERY_LEVEL_LOW + 1) BATTERY_LEVEL_FULL>; + + /* Turn off the left LED */ + color-0 { + led-color = <&color_off_left>; + }; + /* Turn off the right LED */ + color-1 { + led-color = <&color_off_right>; + }; + }; + + power-state-error-left { + charge-state = "PWR_STATE_ERROR"; + charge-port = <1>; /* Left port */ + + /* Turn off the right LED */ + color-0 { + led-color = <&color_off_right>; + }; + /* Left LED - White 2 sec, off 2 sec */ + color-1 { + led-color = <&color_white_left>; + period-ms = <2000>; + }; + color-2 { + led-color = <&color_off_right>; + period-ms = <2000>; + }; + }; + + power-state-error-right { + charge-state = "PWR_STATE_ERROR"; + charge-port = <0>; /* Right port */ + + /* Turn off the left LED */ + color-0 { + led-color = <&color_off_left>; + }; + /* Right LED - White 2 sec, off 2 sec */ + color-1 { + led-color = <&color_white_right>; + period-ms = <2000>; + }; + color-2 { + led-color = <&color_off_right>; + period-ms = <2000>; + }; + }; + + power-state-near-full-left { + charge-state = "PWR_STATE_CHARGE_NEAR_FULL"; + charge-port = <1>; /* Left port */ + + /* Turn off the right LED */ + color-0 { + led-color = <&color_off_right>; + }; + /* Left LED to White */ + color-1 { + led-color = <&color_white_left>; + }; + }; + + power-state-near-full-right { + charge-state = "PWR_STATE_CHARGE_NEAR_FULL"; + charge-port = <0>; /* Right port */ + + /* Turn off the left LED */ + color-0 { + led-color = <&color_off_left>; + }; + /* Right LED to White */ + color-1 { + led-color = <&color_white_right>; + }; + }; + + power-state-forced-idle-left { + charge-state = "PWR_STATE_FORCED_IDLE"; + charge-port = <1>; /* Left port */ + + /* Turn off the right LED */ + color-0 { + led-color = <&color_off_right>; + }; + /* Left LED - Amber 3 sec, Off 1 sec */ + color-1 { + led-color = <&color_amber_left>; + period-ms = <3000>; + }; + color-2 { + led-color = <&color_off_left>; + period-ms = <1000>; + }; + }; + + power-state-forced-idle-right { + charge-state = "PWR_STATE_FORCED_IDLE"; + charge-port = <0>; /* Right port */ + + /* Turn off the left LED */ + color-0 { + led-color = <&color_off_left>; + }; + /* Right LED - Amber 3 sec, Off 1 sec */ + color-1 { + led-color = <&color_amber_right>; + period-ms = <3000>; + }; + color-2 { + led-color = <&color_off_right>; + period-ms = <1000>; + }; + }; + + power-state-idle-left { + charge-state = "PWR_STATE_IDLE"; + charge-port = <1>; /* Left port */ + + /* Turn off the right LED */ + color-0 { + led-color = <&color_off_right>; + }; + /* Left LED to White */ + color-1 { + led-color = <&color_white_left>; + }; + }; + + power-state-idle-right { + charge-state = "PWR_STATE_IDLE"; + charge-port = <0>; /* Right port */ + + /* Turn off the left LED */ + color-0 { + led-color = <&color_off_left>; + }; + /* Right LED to White */ + color-1 { + led-color = <&color_white_right>; + }; + }; + }; +}; diff --git a/zephyr/projects/herobrine/led_policy_hoglin.dts b/zephyr/projects/herobrine/led_policy_hoglin.dts new file mode 100644 index 0000000000..043dfbcaa5 --- /dev/null +++ b/zephyr/projects/herobrine/led_policy_hoglin.dts @@ -0,0 +1,95 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + led-colors { + compatible = "cros-ec,led-policy"; + + power-state-charge { + charge-state = "PWR_STATE_CHARGE"; + + color-0 { + led-color = <&color_blue>; + }; + }; + + power-state-discharge-s0 { + charge-state = "PWR_STATE_DISCHARGE"; + chipset-state = "POWER_S0"; + + color-0 { + led-color = <&color_off>; + }; + }; + + power-state-discharge-s3 { + charge-state = "PWR_STATE_DISCHARGE"; + chipset-state = "POWER_S3"; + + /* Blue 1 sec, off 3 sec */ + color-0 { + led-color = <&color_blue>; + period-ms = <1000>; + }; + color-1 { + led-color = <&color_off>; + period-ms = <3000>; + }; + }; + + power-state-discharge-s5 { + charge-state = "PWR_STATE_DISCHARGE"; + chipset-state = "POWER_S5"; + + color-0 { + led-color = <&color_off>; + }; + }; + + power-state-error { + charge-state = "PWR_STATE_ERROR"; + + /* Red 1 sec, off 1 sec */ + color-0 { + led-color = <&color_red>; + period-ms = <1000>; + }; + color-1 { + led-color = <&color_off>; + period-ms = <1000>; + }; + }; + + power-state-near-full { + charge-state = "PWR_STATE_CHARGE_NEAR_FULL"; + + color-0 { + led-color = <&color_red>; + }; + }; + + power-state-forced-idle { + charge-state = "PWR_STATE_FORCED_IDLE"; + + /* Red 2 sec, Blue 2 sec */ + color-0 { + led-color = <&color_red>; + period-ms = <2000>; + }; + color-1 { + led-color = <&color_blue>; + period-ms = <2000>; + }; + }; + + power-state-idle-default { + charge-state = "PWR_STATE_IDLE"; + + color-0 { + led-color = <&color_red>; + }; + }; + }; +}; diff --git a/zephyr/projects/herobrine/led_policy_villager.dts b/zephyr/projects/herobrine/led_policy_villager.dts new file mode 100644 index 0000000000..f8996a3f4b --- /dev/null +++ b/zephyr/projects/herobrine/led_policy_villager.dts @@ -0,0 +1,95 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + led-colors { + compatible = "cros-ec,led-policy"; + + power-state-charge { + charge-state = "PWR_STATE_CHARGE"; + + color-0 { + led-color = <&color_amber>; + }; + }; + + power-state-discharge-s0 { + charge-state = "PWR_STATE_DISCHARGE"; + chipset-state = "POWER_S0"; + + color-0 { + led-color = <&color_blue>; + }; + }; + + power-state-discharge-s3 { + charge-state = "PWR_STATE_DISCHARGE"; + chipset-state = "POWER_S3"; + + /* Amber 1 sec, off 3 sec */ + color-0 { + led-color = <&color_amber>; + period-ms = <1000>; + }; + color-1 { + led-color = <&color_off>; + period-ms = <3000>; + }; + }; + + power-state-discharge-s5 { + charge-state = "PWR_STATE_DISCHARGE"; + chipset-state = "POWER_S5"; + + color-0 { + led-color = <&color_off>; + }; + }; + + power-state-error { + charge-state = "PWR_STATE_ERROR"; + + /* Amber 1 sec, off 1 sec */ + color-0 { + led-color = <&color_amber>; + period-ms = <1000>; + }; + color-1 { + led-color = <&color_off>; + period-ms = <1000>; + }; + }; + + power-state-near-full { + charge-state = "PWR_STATE_CHARGE_NEAR_FULL"; + + color-0 { + led-color = <&color_blue>; + }; + }; + + power-state-forced-idle { + charge-state = "PWR_STATE_FORCED_IDLE"; + + /* Blue 2 sec, Amber 2 sec */ + color-0 { + led-color = <&color_blue>; + period-ms = <2000>; + }; + color-1 { + led-color = <&color_amber>; + period-ms = <2000>; + }; + }; + + power-state-idle { + charge-state = "PWR_STATE_IDLE"; + + color-0 { + led-color = <&color_blue>; + }; + }; + }; +}; diff --git a/zephyr/projects/herobrine/led_policy_zombie.dts b/zephyr/projects/herobrine/led_policy_zombie.dts new file mode 100644 index 0000000000..f8996a3f4b --- /dev/null +++ b/zephyr/projects/herobrine/led_policy_zombie.dts @@ -0,0 +1,95 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + led-colors { + compatible = "cros-ec,led-policy"; + + power-state-charge { + charge-state = "PWR_STATE_CHARGE"; + + color-0 { + led-color = <&color_amber>; + }; + }; + + power-state-discharge-s0 { + charge-state = "PWR_STATE_DISCHARGE"; + chipset-state = "POWER_S0"; + + color-0 { + led-color = <&color_blue>; + }; + }; + + power-state-discharge-s3 { + charge-state = "PWR_STATE_DISCHARGE"; + chipset-state = "POWER_S3"; + + /* Amber 1 sec, off 3 sec */ + color-0 { + led-color = <&color_amber>; + period-ms = <1000>; + }; + color-1 { + led-color = <&color_off>; + period-ms = <3000>; + }; + }; + + power-state-discharge-s5 { + charge-state = "PWR_STATE_DISCHARGE"; + chipset-state = "POWER_S5"; + + color-0 { + led-color = <&color_off>; + }; + }; + + power-state-error { + charge-state = "PWR_STATE_ERROR"; + + /* Amber 1 sec, off 1 sec */ + color-0 { + led-color = <&color_amber>; + period-ms = <1000>; + }; + color-1 { + led-color = <&color_off>; + period-ms = <1000>; + }; + }; + + power-state-near-full { + charge-state = "PWR_STATE_CHARGE_NEAR_FULL"; + + color-0 { + led-color = <&color_blue>; + }; + }; + + power-state-forced-idle { + charge-state = "PWR_STATE_FORCED_IDLE"; + + /* Blue 2 sec, Amber 2 sec */ + color-0 { + led-color = <&color_blue>; + period-ms = <2000>; + }; + color-1 { + led-color = <&color_amber>; + period-ms = <2000>; + }; + }; + + power-state-idle { + charge-state = "PWR_STATE_IDLE"; + + color-0 { + led-color = <&color_blue>; + }; + }; + }; +}; diff --git a/zephyr/projects/herobrine/motionsense.dts b/zephyr/projects/herobrine/motionsense.dts new file mode 100644 index 0000000000..1955f43284 --- /dev/null +++ b/zephyr/projects/herobrine/motionsense.dts @@ -0,0 +1,241 @@ +/* Copyright 2021 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <dt-bindings/motionsense/utils.h> + + +/ { + aliases { + /* + * motion sense's <>_INT_EVENT is handled + * by alias. Using the alias, each driver creates + * its own <>_INT_EVENT. + */ + bmi260-int = &base_accel; + tcs3400-int = &als_clear; + }; + + /* + * Declare mutexes used by sensor drivers. + * A mutex node is used to create an instance of mutex_t. + * A mutex node is referenced by a sensor node if the + * corresponding sensor driver needs to use the + * instance of the mutex. + */ + motionsense-mutex { + compatible = "cros-ec,motionsense-mutex"; + lid_mutex: lid-mutex { + }; + + mutex_bmi260: bmi260-mutex { + }; + }; + + /* Rotation matrix used by drivers. */ + motionsense-rotation-ref { + compatible = "cros-ec,motionsense-rotation-ref"; + lid_rot_ref: lid-rotation-ref { + mat33 = <0 1 0 + 1 0 0 + 0 0 (-1)>; + }; + + base_rot_ref: base-rotation-ref { + mat33 = <1 0 0 + 0 (-1) 0 + 0 0 (-1)>; + }; + }; + + /* + * Driver specific data. A driver-specific data can be shared with + * different motion sensors while they are using the same driver. + * + * If a node's compatible starts with "cros-ec,accelgyro-", it is for + * a common structure defined in accelgyro.h. + * e.g) compatible = "cros-ec,accelgyro-als-drv-data" is for + * "struct als_drv_data_t" in accelgyro.h + */ + motionsense-sensor-data { + bma255_data: bma255-drv-data { + compatible = "cros-ec,drvdata-bma255"; + status = "okay"; + }; + + bmi260_data: bmi260-drv-data { + compatible = "cros-ec,drvdata-bmi260"; + status = "okay"; + }; + + tcs_clear_data: tcs3400-clear-drv-data { + compatible = "cros-ec,drvdata-tcs3400-clear"; + status = "okay"; + + als-drv-data { + compatible = "cros-ec,accelgyro-als-drv-data"; + als-cal { + scale = <1>; + uscale = <0>; + offset = <0>; + als-channel-scale { + compatible = "cros-ec,accelgyro-als-channel-scale"; + k-channel-scale = <1>; + cover-scale = <1>; + }; + }; + }; + }; + + tcs_rgb_data: tcs3400-rgb-drv-data { + compatible = "cros-ec,drvdata-tcs3400-rgb"; + status = "okay"; + + /* node for rgb_calibration_t defined in accelgyro.h */ + rgb_calibration { + compatible = + "cros-ec,accelgyro-rgb-calibration"; + + irt = <1>; + + rgb-cal-x { + offset = <0>; + coeff = <0 0 0 1>; + als-channel-scale { + compatible = "cros-ec,accelgyro-als-channel-scale"; + k-channel-scale = <1>; + cover-scale = <1>; + }; + }; + rgb-cal-y { + offset = <0>; + coeff = <0 0 0 1>; + als-channel-scale { + compatible = "cros-ec,accelgyro-als-channel-scale"; + k-channel-scale = <1>; + cover-scale = <1>; + }; + }; + rgb-cal-z { + offset = <0>; + coeff = <0 0 0 1>; + als-channel-scale { + compatible = "cros-ec,accelgyro-als-channel-scale"; + k-channel-scale = <1>; + cover-scale = <1>; + }; + }; + }; + }; + }; + + /* + * List of motion sensors that creates motion_sensors array. + * The nodelabel "lid_accel" and "base_accel" are used to indicate + * motion sensor IDs for lid angle calculation. + */ + motionsense-sensor { + lid_accel: lid-accel { + compatible = "cros-ec,bma255"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_LID"; + mutex = <&lid_mutex>; + port = <&i2c_sensor>; + rot-standard-ref = <&lid_rot_ref>; + default-range = <2>; + drv-data = <&bma255_data>; + i2c-spi-addr-flags = "BMA2x2_I2C_ADDR1_FLAGS"; + configs { + compatible = + "cros-ec,motionsense-sensor-config"; + ec-s0 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + ec-s3 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + }; + }; + + base_accel: base-accel { + compatible = "cros-ec,bmi260-accel"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_BASE"; + mutex = <&mutex_bmi260>; + port = <&i2c_sensor>; + rot-standard-ref = <&base_rot_ref>; + drv-data = <&bmi260_data>; + configs { + compatible = + "cros-ec,motionsense-sensor-config"; + ec-s0 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + ec-s3 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + }; + }; + + base-gyro { + compatible = "cros-ec,bmi260-gyro"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_BASE"; + mutex = <&mutex_bmi260>; + port = <&i2c_sensor>; + rot-standard-ref = <&base_rot_ref>; + drv-data = <&bmi260_data>; + }; + + als_clear: base-als-clear { + compatible = "cros-ec,tcs3400-clear"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_CAMERA"; + port = <&i2c_sensor>; + default-range = <0x10000>; + drv-data = <&tcs_clear_data>; + i2c-spi-addr-flags = "TCS3400_I2C_ADDR_FLAGS"; + configs { + compatible = + "cros-ec,motionsense-sensor-config"; + ec-s0 { + /* Run ALS sensor in S0 */ + odr = <1000>; + }; + }; + }; + + base-als-rgb { + compatible = "cros-ec,tcs3400-rgb"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_CAMERA"; + default-range = <0x10000>; /* scale = 1x, uscale = 0 */ + drv-data = <&tcs_rgb_data>; + }; + }; + + motionsense-sensor-info { + compatible = "cros-ec,motionsense-sensor-info"; + + /* list of entries for motion_als_sensors */ + als-sensors = <&als_clear>; + /* + * list of GPIO interrupts that have to + * be enabled at initial stage + */ + sensor-irqs = <&int_accel_gyro>; + /* list of sensors in force mode */ + accel-force-mode-sensors = <&lid_accel &als_clear>; + }; +}; diff --git a/zephyr/projects/herobrine/motionsense_evoker.dts b/zephyr/projects/herobrine/motionsense_evoker.dts new file mode 100644 index 0000000000..aa7646e0b3 --- /dev/null +++ b/zephyr/projects/herobrine/motionsense_evoker.dts @@ -0,0 +1,148 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <dt-bindings/motionsense/utils.h> + + +/ { + aliases { + /* + * motion sense's <>_INT_EVENT is handled + * by alias. Using the alias, each driver creates + * its own <>_INT_EVENT. + */ + bmi260-int = &base_accel; + }; + + /* + * Declare mutexes used by sensor drivers. + * A mutex node is used to create an instance of mutex_t. + * A mutex node is referenced by a sensor node if the + * corresponding sensor driver needs to use the + * instance of the mutex. + */ + motionsense-mutex { + compatible = "cros-ec,motionsense-mutex"; + lid_mutex: lid-mutex { + }; + + mutex_bmi260: bmi260-mutex { + }; + }; + + /* Rotation matrix used by drivers. */ + motionsense-rotation-ref { + compatible = "cros-ec,motionsense-rotation-ref"; + lid_rot_ref: lid-rotation-ref { + mat33 = <(-1) 0 0 + 0 (-1) 0 + 0 0 1>; + }; + + base_rot_ref: base-rotation-ref { + mat33 = <0 1 0 + (-1) 0 0 + 0 0 1>; + }; + }; + + /* + * Driver specific data. A driver-specific data can be shared with + * different motion sensors while they are using the same driver. + * + * If a node's compatible starts with "cros-ec,accelgyro-", it is for + * a common structure defined in accelgyro.h. + * e.g) compatible = "cros-ec,accelgyro-als-drv-data" is for + * "struct als_drv_data_t" in accelgyro.h + */ + motionsense-sensor-data { + bma4xx_data: bma4xx-drv-data { + compatible = "cros-ec,drvdata-bma4xx"; + status = "okay"; + }; + + bmi260_data: bmi260-drv-data { + compatible = "cros-ec,drvdata-bmi260"; + status = "okay"; + }; + }; + + /* + * List of motion sensors that creates motion_sensors array. + * The nodelabel "lid_accel" and "base_accel" are used to indicate + * motion sensor IDs for lid angle calculation. + */ + motionsense-sensor { + lid_accel: lid-accel { + compatible = "cros-ec,bma4xx"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_LID"; + mutex = <&lid_mutex>; + port = <&i2c_sensor>; + rot-standard-ref = <&lid_rot_ref>; + default-range = <2>; + drv-data = <&bma4xx_data>; + i2c-spi-addr-flags = "BMA4_I2C_ADDR_PRIMARY"; + configs { + compatible = + "cros-ec,motionsense-sensor-config"; + ec-s0 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + ec-s3 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + }; + }; + + base_accel: base-accel { + compatible = "cros-ec,bmi260-accel"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_BASE"; + mutex = <&mutex_bmi260>; + port = <&i2c_sensor>; + rot-standard-ref = <&base_rot_ref>; + drv-data = <&bmi260_data>; + configs { + compatible = + "cros-ec,motionsense-sensor-config"; + ec-s0 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + ec-s3 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + }; + }; + + base-gyro { + compatible = "cros-ec,bmi260-gyro"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_BASE"; + mutex = <&mutex_bmi260>; + port = <&i2c_sensor>; + rot-standard-ref = <&base_rot_ref>; + drv-data = <&bmi260_data>; + }; + }; + + motionsense-sensor-info { + compatible = "cros-ec,motionsense-sensor-info"; + + /* + * list of GPIO interrupts that have to + * be enabled at initial stage + */ + sensor-irqs = <&int_accel_gyro>; + /* list of sensors in force mode */ + accel-force-mode-sensors = <&lid_accel>; + }; +}; diff --git a/zephyr/projects/herobrine/motionsense_hoglin.dts b/zephyr/projects/herobrine/motionsense_hoglin.dts new file mode 100644 index 0000000000..c3935178ff --- /dev/null +++ b/zephyr/projects/herobrine/motionsense_hoglin.dts @@ -0,0 +1,241 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <dt-bindings/motionsense/utils.h> + + +/ { + aliases { + /* + * motion sense's <>_INT_EVENT is handled + * by alias. Using the alias, each driver creates + * its own <>_INT_EVENT. + */ + bmi260-int = &base_accel; + tcs3400-int = &als_clear; + }; + + /* + * Declare mutexes used by sensor drivers. + * A mutex node is used to create an instance of mutex_t. + * A mutex node is referenced by a sensor node if the + * corresponding sensor driver needs to use the + * instance of the mutex. + */ + motionsense-mutex { + compatible = "cros-ec,motionsense-mutex"; + lid_mutex: lid-mutex { + }; + + mutex_bmi260: bmi260-mutex { + }; + }; + + /* Rotation matrix used by drivers. */ + motionsense-rotation-ref { + compatible = "cros-ec,motionsense-rotation-ref"; + lid_rot_ref: lid-rotation-ref { + mat33 = <(-1) 0 0 + 0 (-1) 0 + 0 0 1>; + }; + + base_rot_ref: base-rotation-ref { + mat33 = <1 0 0 + 0 (-1) 0 + 0 0 (-1)>; + }; + }; + + /* + * Driver specific data. A driver-specific data can be shared with + * different motion sensors while they are using the same driver. + * + * If a node's compatible starts with "cros-ec,accelgyro-", it is for + * a common structure defined in accelgyro.h. + * e.g) compatible = "cros-ec,accelgyro-als-drv-data" is for + * "struct als_drv_data_t" in accelgyro.h + */ + motionsense-sensor-data { + bma4xx_data: bma4xx-drv-data { + compatible = "cros-ec,drvdata-bma4xx"; + status = "okay"; + }; + + bmi260_data: bmi260-drv-data { + compatible = "cros-ec,drvdata-bmi260"; + status = "okay"; + }; + + tcs_clear_data: tcs3400-clear-drv-data { + compatible = "cros-ec,drvdata-tcs3400-clear"; + status = "okay"; + + als-drv-data { + compatible = "cros-ec,accelgyro-als-drv-data"; + als-cal { + scale = <1>; + uscale = <0>; + offset = <0>; + als-channel-scale { + compatible = "cros-ec,accelgyro-als-channel-scale"; + k-channel-scale = <1>; + cover-scale = <1>; + }; + }; + }; + }; + + tcs_rgb_data: tcs3400-rgb-drv-data { + compatible = "cros-ec,drvdata-tcs3400-rgb"; + status = "okay"; + + /* node for rgb_calibration_t defined in accelgyro.h */ + rgb_calibration { + compatible = + "cros-ec,accelgyro-rgb-calibration"; + + irt = <1>; + + rgb-cal-x { + offset = <0>; + coeff = <0 0 0 1>; + als-channel-scale { + compatible = "cros-ec,accelgyro-als-channel-scale"; + k-channel-scale = <1>; + cover-scale = <1>; + }; + }; + rgb-cal-y { + offset = <0>; + coeff = <0 0 0 1>; + als-channel-scale { + compatible = "cros-ec,accelgyro-als-channel-scale"; + k-channel-scale = <1>; + cover-scale = <1>; + }; + }; + rgb-cal-z { + offset = <0>; + coeff = <0 0 0 1>; + als-channel-scale { + compatible = "cros-ec,accelgyro-als-channel-scale"; + k-channel-scale = <1>; + cover-scale = <1>; + }; + }; + }; + }; + }; + + /* + * List of motion sensors that creates motion_sensors array. + * The nodelabel "lid_accel" and "base_accel" are used to indicate + * motion sensor IDs for lid angle calculation. + */ + motionsense-sensor { + lid_accel: lid-accel { + compatible = "cros-ec,bma4xx"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_LID"; + mutex = <&lid_mutex>; + port = <&i2c_sensor>; + rot-standard-ref = <&lid_rot_ref>; + default-range = <2>; + drv-data = <&bma4xx_data>; + i2c-spi-addr-flags = "BMA4_I2C_ADDR_PRIMARY"; + configs { + compatible = + "cros-ec,motionsense-sensor-config"; + ec-s0 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + ec-s3 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + }; + }; + + base_accel: base-accel { + compatible = "cros-ec,bmi260-accel"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_BASE"; + mutex = <&mutex_bmi260>; + port = <&i2c_sensor>; + rot-standard-ref = <&base_rot_ref>; + drv-data = <&bmi260_data>; + configs { + compatible = + "cros-ec,motionsense-sensor-config"; + ec-s0 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + ec-s3 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + }; + }; + + base-gyro { + compatible = "cros-ec,bmi260-gyro"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_BASE"; + mutex = <&mutex_bmi260>; + port = <&i2c_sensor>; + rot-standard-ref = <&base_rot_ref>; + drv-data = <&bmi260_data>; + }; + + als_clear: base-als-clear { + compatible = "cros-ec,tcs3400-clear"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_CAMERA"; + port = <&i2c_sensor>; + default-range = <0x10000>; + drv-data = <&tcs_clear_data>; + i2c-spi-addr-flags = "TCS3400_I2C_ADDR_FLAGS"; + configs { + compatible = + "cros-ec,motionsense-sensor-config"; + ec-s0 { + /* Run ALS sensor in S0 */ + odr = <1000>; + }; + }; + }; + + base-als-rgb { + compatible = "cros-ec,tcs3400-rgb"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_CAMERA"; + default-range = <0x10000>; /* scale = 1x, uscale = 0 */ + drv-data = <&tcs_rgb_data>; + }; + }; + + motionsense-sensor-info { + compatible = "cros-ec,motionsense-sensor-info"; + + /* list of entries for motion_als_sensors */ + als-sensors = <&als_clear>; + /* + * list of GPIO interrupts that have to + * be enabled at initial stage + */ + sensor-irqs = <&int_accel_gyro>; + /* list of sensors in force mode */ + accel-force-mode-sensors = <&lid_accel &als_clear>; + }; +}; diff --git a/zephyr/projects/herobrine/motionsense_villager.dts b/zephyr/projects/herobrine/motionsense_villager.dts new file mode 100644 index 0000000000..31d00e04a5 --- /dev/null +++ b/zephyr/projects/herobrine/motionsense_villager.dts @@ -0,0 +1,148 @@ +/* Copyright 2021 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <dt-bindings/motionsense/utils.h> + + +/ { + aliases { + /* + * motion sense's <>_INT_EVENT is handled + * by alias. Using the alias, each driver creates + * its own <>_INT_EVENT. + */ + bmi260-int = &base_accel; + }; + + /* + * Declare mutexes used by sensor drivers. + * A mutex node is used to create an instance of mutex_t. + * A mutex node is referenced by a sensor node if the + * corresponding sensor driver needs to use the + * instance of the mutex. + */ + motionsense-mutex { + compatible = "cros-ec,motionsense-mutex"; + lid_mutex: lid-mutex { + }; + + mutex_bmi260: bmi260-mutex { + }; + }; + + /* Rotation matrix used by drivers. */ + motionsense-rotation-ref { + compatible = "cros-ec,motionsense-rotation-ref"; + lid_rot_ref: lid-rotation-ref { + mat33 = <0 1 0 + (-1) 0 0 + 0 0 1>; + }; + + base_rot_ref: base-rotation-ref { + mat33 = <1 0 0 + 0 (-1) 0 + 0 0 (-1)>; + }; + }; + + /* + * Driver specific data. A driver-specific data can be shared with + * different motion sensors while they are using the same driver. + * + * If a node's compatible starts with "cros-ec,accelgyro-", it is for + * a common structure defined in accelgyro.h. + * e.g) compatible = "cros-ec,accelgyro-als-drv-data" is for + * "struct als_drv_data_t" in accelgyro.h + */ + motionsense-sensor-data { + kx022_data: kx022-drv-data { + compatible = "cros-ec,drvdata-kionix"; + status = "okay"; + }; + + bmi260_data: bmi260-drv-data { + compatible = "cros-ec,drvdata-bmi260"; + status = "okay"; + }; + }; + + /* + * List of motion sensors that creates motion_sensors array. + * The nodelabel "lid_accel" and "base_accel" are used to indicate + * motion sensor IDs for lid angle calculation. + */ + motionsense-sensor { + lid_accel: lid-accel { + compatible = "cros-ec,kx022"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_LID"; + mutex = <&lid_mutex>; + port = <&i2c_sensor>; + rot-standard-ref = <&lid_rot_ref>; + default-range = <2>; + drv-data = <&kx022_data>; + i2c-spi-addr-flags = "KX022_ADDR0_FLAGS"; + configs { + compatible = + "cros-ec,motionsense-sensor-config"; + ec-s0 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + ec-s3 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + }; + }; + + base_accel: base-accel { + compatible = "cros-ec,bmi260-accel"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_BASE"; + mutex = <&mutex_bmi260>; + port = <&i2c_sensor>; + rot-standard-ref = <&base_rot_ref>; + drv-data = <&bmi260_data>; + configs { + compatible = + "cros-ec,motionsense-sensor-config"; + ec-s0 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + ec-s3 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + }; + }; + + base-gyro { + compatible = "cros-ec,bmi260-gyro"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_BASE"; + mutex = <&mutex_bmi260>; + port = <&i2c_sensor>; + rot-standard-ref = <&base_rot_ref>; + drv-data = <&bmi260_data>; + }; + }; + + motionsense-sensor-info { + compatible = "cros-ec,motionsense-sensor-info"; + + /* + * list of GPIO interrupts that have to + * be enabled at initial stage + */ + sensor-irqs = <&int_accel_gyro>; + /* list of sensors in force mode */ + accel-force-mode-sensors = <&lid_accel>; + }; +}; diff --git a/zephyr/projects/herobrine/motionsense_zombie.dts b/zephyr/projects/herobrine/motionsense_zombie.dts new file mode 100644 index 0000000000..e069564b35 --- /dev/null +++ b/zephyr/projects/herobrine/motionsense_zombie.dts @@ -0,0 +1,148 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <dt-bindings/motionsense/utils.h> + + +/ { + aliases { + /* + * motion sense's <>_INT_EVENT is handled + * by alias. Using the alias, each driver creates + * its own <>_INT_EVENT. + */ + bmi260-int = &base_accel; + }; + + /* + * Declare mutexes used by sensor drivers. + * A mutex node is used to create an instance of mutex_t. + * A mutex node is referenced by a sensor node if the + * corresponding sensor driver needs to use the + * instance of the mutex. + */ + motionsense-mutex { + compatible = "cros-ec,motionsense-mutex"; + lid_mutex: lid-mutex { + }; + + mutex_bmi260: bmi260-mutex { + }; + }; + + /* Rotation matrix used by drivers. */ + motionsense-rotation-ref { + compatible = "cros-ec,motionsense-rotation-ref"; + lid_rot_ref: lid-rotation-ref { + mat33 = <0 1 0 + (-1) 0 0 + 0 0 1>; + }; + + base_rot_ref: base-rotation-ref { + mat33 = <1 0 0 + 0 (-1) 0 + 0 0 (-1)>; + }; + }; + + /* + * Driver specific data. A driver-specific data can be shared with + * different motion sensors while they are using the same driver. + * + * If a node's compatible starts with "cros-ec,accelgyro-", it is for + * a common structure defined in accelgyro.h. + * e.g) compatible = "cros-ec,accelgyro-als-drv-data" is for + * "struct als_drv_data_t" in accelgyro.h + */ + motionsense-sensor-data { + kx022_data: kx022-drv-data { + compatible = "cros-ec,drvdata-kionix"; + status = "okay"; + }; + + bmi260_data: bmi260-drv-data { + compatible = "cros-ec,drvdata-bmi260"; + status = "okay"; + }; + }; + + /* + * List of motion sensors that creates motion_sensors array. + * The nodelabel "lid_accel" and "base_accel" are used to indicate + * motion sensor IDs for lid angle calculation. + */ + motionsense-sensor { + lid_accel: lid-accel { + compatible = "cros-ec,kx022"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_LID"; + mutex = <&lid_mutex>; + port = <&i2c_sensor>; + rot-standard-ref = <&lid_rot_ref>; + default-range = <2>; + drv-data = <&kx022_data>; + i2c-spi-addr-flags = "KX022_ADDR0_FLAGS"; + configs { + compatible = + "cros-ec,motionsense-sensor-config"; + ec-s0 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + ec-s3 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + }; + }; + + base_accel: base-accel { + compatible = "cros-ec,bmi260-accel"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_BASE"; + mutex = <&mutex_bmi260>; + port = <&i2c_sensor>; + rot-standard-ref = <&base_rot_ref>; + drv-data = <&bmi260_data>; + configs { + compatible = + "cros-ec,motionsense-sensor-config"; + ec-s0 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + ec-s3 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + }; + }; + + base-gyro { + compatible = "cros-ec,bmi260-gyro"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_BASE"; + mutex = <&mutex_bmi260>; + port = <&i2c_sensor>; + rot-standard-ref = <&base_rot_ref>; + drv-data = <&bmi260_data>; + }; + }; + + motionsense-sensor-info { + compatible = "cros-ec,motionsense-sensor-info"; + + /* + * list of GPIO interrupts that have to + * be enabled at initial stage + */ + sensor-irqs = <&int_accel_gyro>; + /* list of sensors in force mode */ + accel-force-mode-sensors = <&lid_accel>; + }; +}; diff --git a/zephyr/projects/herobrine/prj.conf b/zephyr/projects/herobrine/prj.conf new file mode 100644 index 0000000000..3391e60dce --- /dev/null +++ b/zephyr/projects/herobrine/prj.conf @@ -0,0 +1,160 @@ +# Copyright 2021 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +CONFIG_CROS_EC=y +CONFIG_SHIMMED_TASKS=y +CONFIG_PLATFORM_EC=y +CONFIG_PLATFORM_EC_BRINGUP=y +CONFIG_PLATFORM_EC_EXTPOWER_GPIO=y +CONFIG_PLATFORM_EC_SWITCH=y +CONFIG_PLATFORM_EC_LID_SWITCH=y +CONFIG_PLATFORM_EC_BACKLIGHT_LID=y +CONFIG_PLATFORM_EC_POWER_BUTTON=y +CONFIG_PLATFORM_EC_CBI_GPIO=y +CONFIG_KERNEL_SHELL=y +CONFIG_PLATFORM_EC_BOARD_RESET_AFTER_POWER_ON=y + +# I2C options +CONFIG_I2C=y +CONFIG_PLATFORM_EC_CONSOLE_CMD_I2C_SPEED=y +CONFIG_PLATFORM_EC_HOSTCMD_I2C_CONTROL=y + +# Shell history and tab autocompletion (for convenience) +CONFIG_SHELL_HELP=y +CONFIG_SHELL_HISTORY=y +CONFIG_SHELL_TAB=y +CONFIG_SHELL_TAB_AUTOCOMPLETION=y + +# LED +CONFIG_PLATFORM_EC_LED_COMMON=n +CONFIG_PLATFORM_EC_LED_DT=y + +# PWM +CONFIG_PWM=y +CONFIG_PWM_SHELL=n + +# Application Processor is Qualcomm SC7280 +CONFIG_AP_ARM_QUALCOMM_SC7280=y + +# GPIO Switchcap +CONFIG_PLATFORM_EC_SWITCHCAP_GPIO=y + +# Board version is selected over GPIO board ID pins. +CONFIG_PLATFORM_EC_BOARD_VERSION_GPIO=y + +# Power Sequencing +CONFIG_PLATFORM_EC_POWERSEQ=y +CONFIG_PLATFORM_EC_POWERSEQ_HOST_SLEEP=y +CONFIG_PLATFORM_EC_POWERSEQ_PP5000_CONTROL=n +CONFIG_PLATFORM_EC_POWER_SLEEP_FAILURE_DETECTION=y +CONFIG_PLATFORM_EC_CHIPSET_RESET_HOOK=y +CONFIG_PLATFORM_EC_CHIPSET_RESUME_INIT_HOOK=y + +# MKBP event +CONFIG_PLATFORM_EC_MKBP_EVENT=y +CONFIG_PLATFORM_EC_MKBP_USE_GPIO=y + +# Keyboard +CONFIG_PLATFORM_EC_KEYBOARD=y +CONFIG_PLATFORM_EC_KEYBOARD_PROTOCOL_MKBP=y +CONFIG_PLATFORM_EC_MKBP_INPUT_DEVICES=y +CONFIG_PLATFORM_EC_KEYBOARD_COL2_INVERTED=y +CONFIG_PLATFORM_EC_KEYBOARD_REFRESH_ROW3=y +CONFIG_PLATFORM_EC_VOLUME_BUTTONS=y +CONFIG_PLATFORM_EC_CMD_BUTTON=y +CONFIG_CROS_KB_RAW_NPCX=y + +# ADC +CONFIG_ADC=y +CONFIG_ADC_SHELL=n + +# Battery +CONFIG_PLATFORM_EC_BATTERY=y +CONFIG_PLATFORM_EC_BATTERY_SMART=y +CONFIG_PLATFORM_EC_I2C_VIRTUAL_BATTERY=y +CONFIG_PLATFORM_EC_I2C_PASSTHRU_RESTRICTED=y +CONFIG_PLATFORM_EC_BATTERY_FUEL_GAUGE=y +CONFIG_PLATFORM_EC_BATTERY_CUT_OFF=y +CONFIG_PLATFORM_EC_BATTERY_PRESENT_GPIO=y +CONFIG_PLATFORM_EC_CHARGER_ISL9238C=y +CONFIG_PLATFORM_EC_CHARGE_RAMP_HW=y +CONFIG_PLATFORM_EC_USE_BATTERY_DEVICE_CHEMISTRY=y +CONFIG_PLATFORM_EC_BATTERY_DEVICE_CHEMISTRY="LION" +CONFIG_PLATFORM_EC_BATTERY_REVIVE_DISCONNECT=y +CONFIG_PLATFORM_EC_CHARGER_DISCHARGE_ON_AC=y +CONFIG_PLATFORM_EC_CHARGER_DISCHARGE_ON_AC_CHARGER=y +CONFIG_PLATFORM_EC_CHARGER_MIN_BAT_PCT_FOR_POWER_ON=2 +CONFIG_PLATFORM_EC_CHARGER_MIN_POWER_MW_FOR_POWER_ON=12500 +CONFIG_PLATFORM_EC_CHARGER_PROFILE_OVERRIDE=y +CONFIG_PLATFORM_EC_CHARGER_PSYS=y +CONFIG_PLATFORM_EC_CHARGER_PSYS_READ=y +CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR=10 +CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR_AC=20 +CONFIG_PLATFORM_EC_CONSOLE_CMD_CHARGER_ADC_AMON_BMON=y + +# USB-A +CONFIG_PLATFORM_EC_USBA=y + +# USB-C +CONFIG_PLATFORM_EC_USB_PD_FRS=y +CONFIG_PLATFORM_EC_BC12_DETECT_PI3USB9201=y +CONFIG_PLATFORM_EC_USB_PD_USB32_DRD=n +CONFIG_PLATFORM_EC_USBC_PPC_SN5S330=y +CONFIG_PLATFORM_EC_USBC_PPC_SYV682C=y +CONFIG_PLATFORM_EC_USBC_PPC_SYV682X=y +CONFIG_PLATFORM_EC_USB_PD_FRS_PPC=y +CONFIG_PLATFORM_EC_USBC_RETIMER_FW_UPDATE=n +CONFIG_PLATFORM_EC_USBC_SS_MUX_DFP_ONLY=y +CONFIG_PLATFORM_EC_USB_DRP_ACC_TRYSRC=y +CONFIG_PLATFORM_EC_USB_PD_5V_EN_CUSTOM=y +CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_TCPC=y +CONFIG_PLATFORM_EC_USB_PD_DISCHARGE_PPC=y +CONFIG_PLATFORM_EC_USB_PD_DPS=y +CONFIG_PLATFORM_EC_USB_PD_REV30=y +CONFIG_PLATFORM_EC_USB_PD_TBT_COMPAT_MODE=n +CONFIG_PLATFORM_EC_USB_PD_USB4=n +CONFIG_PLATFORM_EC_USB_PD_TCPC_LOW_POWER=y +CONFIG_PLATFORM_EC_USB_PD_TCPM_PS8805=y +CONFIG_PLATFORM_EC_USB_PD_TCPC_RUNTIME_CONFIG=n +CONFIG_PLATFORM_EC_USB_MUX_RUNTIME_CONFIG=n +CONFIG_PLATFORM_EC_USB_PD_LOGGING=y +CONFIG_PLATFORM_EC_CONFIG_USB_PD_3A_PORTS=2 + +# USB ID +# This is allocated specifically for Herobrine +# http://google3/hardware/standards/usb/ +# TODO(b/183608112): Move to device tree +CONFIG_PLATFORM_EC_USB_PID=0x5055 + +# RTC +CONFIG_PLATFORM_EC_RTC=y +CONFIG_CROS_RTC_NXP_PCF85063A=y +CONFIG_PLATFORM_EC_HOSTCMD_RTC=y +CONFIG_PLATFORM_EC_CONSOLE_CMD_RTC=y +CONFIG_PLATFORM_EC_CONSOLE_CMD_RTC_ALARM=y + +# EC software sync +CONFIG_PLATFORM_EC_VBOOT_HASH=y + +# Sensors +CONFIG_PLATFORM_EC_MOTIONSENSE=y +CONFIG_PLATFORM_EC_ACCEL_FIFO=y +CONFIG_PLATFORM_EC_ACCEL_SPOOF_MODE=y +CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCELS=y +CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCEL_INFO=y +CONFIG_PLATFORM_EC_GMR_TABLET_MODE=y +CONFIG_PLATFORM_EC_LID_ANGLE=y +CONFIG_PLATFORM_EC_LID_ANGLE_UPDATE=y +CONFIG_PLATFORM_EC_SENSOR_TIGHT_TIMESTAMPS=y +CONFIG_PLATFORM_EC_TABLET_MODE=y +CONFIG_PLATFORM_EC_TABLET_MODE_SWITCH=y +CONFIG_PLATFORM_EC_MAX_SENSOR_FREQ_MILLIHZ=100000 + +# Sensor Drivers +CONFIG_PLATFORM_EC_ACCEL_BMA255=y +CONFIG_PLATFORM_EC_ACCELGYRO_BMI260=y +CONFIG_PLATFORM_EC_ACCELGYRO_BMI_COMM_I2C=y + +CONFIG_SYSCON=y +CONFIG_PLATFORM_EC_EMULATED_SYSRQ=y diff --git a/zephyr/projects/herobrine/prj_evoker.conf b/zephyr/projects/herobrine/prj_evoker.conf new file mode 100644 index 0000000000..b4a5fce160 --- /dev/null +++ b/zephyr/projects/herobrine/prj_evoker.conf @@ -0,0 +1,16 @@ +# Copyright 2022 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +# Evoker board-specific Kconfig settings. +CONFIG_BOARD_EVOKER=y + +# Disable type-c port sourcing 3A +CONFIG_PLATFORM_EC_CONFIG_USB_PD_3A_PORTS=0 + +CONFIG_PLATFORM_EC_ACCEL_BMA255=n +CONFIG_PLATFORM_EC_ACCEL_BMA4XX=y + +# ISL9238C disable the CMOUT latch function. +CONFIG_PLATFORM_EC_ISL9238C_DISABLE_CMOUT_LATCH=y +CONFIG_PLATFORM_EC_CONSOLE_CMD_CHARGER_DUMP=y
\ No newline at end of file diff --git a/zephyr/projects/herobrine/prj_herobrine.conf b/zephyr/projects/herobrine/prj_herobrine.conf new file mode 100644 index 0000000000..bf39f65692 --- /dev/null +++ b/zephyr/projects/herobrine/prj_herobrine.conf @@ -0,0 +1,13 @@ +# Copyright 2022 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +# Herobrine-NPCX9 reference-board-specific Kconfig settings. +CONFIG_BOARD_HEROBRINE=y + +# Sensors +CONFIG_PLATFORM_EC_ALS=y + +# Sensor Drivers +CONFIG_PLATFORM_EC_ALS_TCS3400=y +CONFIG_PLATFORM_EC_ALS_TCS3400_EMULATED_IRQ_EVENT=y diff --git a/zephyr/projects/herobrine/prj_hoglin.conf b/zephyr/projects/herobrine/prj_hoglin.conf new file mode 100644 index 0000000000..c6e20937c0 --- /dev/null +++ b/zephyr/projects/herobrine/prj_hoglin.conf @@ -0,0 +1,15 @@ +# Copyright 2022 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +# Hoglin reference-board-specific Kconfig settings. +CONFIG_BOARD_HOGLIN=y +CONFIG_PLATFORM_EC_ACCEL_BMA255=n +CONFIG_PLATFORM_EC_ACCEL_BMA4XX=y + +# Sensors +CONFIG_PLATFORM_EC_ALS=y + +# Sensor Drivers +CONFIG_PLATFORM_EC_ALS_TCS3400=y +CONFIG_PLATFORM_EC_ALS_TCS3400_EMULATED_IRQ_EVENT=y diff --git a/zephyr/projects/herobrine/prj_villager.conf b/zephyr/projects/herobrine/prj_villager.conf new file mode 100644 index 0000000000..35eebe6d99 --- /dev/null +++ b/zephyr/projects/herobrine/prj_villager.conf @@ -0,0 +1,8 @@ +# Copyright 2022 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +# Villager board-specific Kconfig settings. +CONFIG_BOARD_VILLAGER=y + +CONFIG_PLATFORM_EC_ACCEL_KX022=y diff --git a/zephyr/projects/herobrine/prj_zoglin.conf b/zephyr/projects/herobrine/prj_zoglin.conf new file mode 100644 index 0000000000..7f96cf6c79 --- /dev/null +++ b/zephyr/projects/herobrine/prj_zoglin.conf @@ -0,0 +1,15 @@ +# Copyright 2022 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +# Zoglin reference-board-specific Kconfig settings. +CONFIG_BOARD_ZOGLIN=y +CONFIG_PLATFORM_EC_ACCEL_BMA255=n +CONFIG_PLATFORM_EC_ACCEL_BMA4XX=y + +# Sensors +CONFIG_PLATFORM_EC_ALS=y + +# Sensor Drivers +CONFIG_PLATFORM_EC_ALS_TCS3400=y +CONFIG_PLATFORM_EC_ALS_TCS3400_EMULATED_IRQ_EVENT=y diff --git a/zephyr/projects/herobrine/prj_zombie.conf b/zephyr/projects/herobrine/prj_zombie.conf new file mode 100644 index 0000000000..037ab5cc05 --- /dev/null +++ b/zephyr/projects/herobrine/prj_zombie.conf @@ -0,0 +1,8 @@ +# Copyright 2022 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +# Zombie board-specific Kconfig settings. +CONFIG_BOARD_ZOMBIE=y + +CONFIG_PLATFORM_EC_ACCEL_KX022=y diff --git a/zephyr/projects/herobrine/src/board_chipset.c b/zephyr/projects/herobrine/src/board_chipset.c new file mode 100644 index 0000000000..2312bdb1c4 --- /dev/null +++ b/zephyr/projects/herobrine/src/board_chipset.c @@ -0,0 +1,83 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Herobrine chipset-specific configuration */ + +#include "charger.h" +#include "common.h" +#include "console.h" +#include "battery.h" +#include "gpio.h" +#include "hooks.h" +#include "timer.h" +#include "usb_pd.h" + +#include "board_chipset.h" + +#define CPRINTS(format, args...) cprints(CC_HOOK, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_HOOK, format, ##args) + +/* + * A window of PD negotiation. It starts from the Type-C state reaching + * Attached.SNK, and ends when the PD contract is created. The VBUS may be + * raised anytime in this window. + * + * The current implementation is the worst case scenario: every message the PD + * negotiation is received at the last moment before timeout. More extra time + * is added to compensate the delay internally, like the decision of the DPM. + * + * TODO(waihong): Cancel this timer when the PD contract is negotiated. + */ +#define PD_READY_TIMEOUT \ + (PD_T_SINK_WAIT_CAP + PD_T_SENDER_RESPONSE + PD_T_SINK_TRANSITION + \ + 20 * MSEC) + +#define PD_READY_POLL_DELAY (10 * MSEC) + +static timestamp_t pd_ready_timeout; + +static bool pp5000_inited; + +__test_only void reset_pp5000_inited(void) +{ + pp5000_inited = false; +} + +/* Called on USB PD connected */ +static void board_usb_pd_connect(void) +{ + int soc = -1; + + /* First boot, battery unattached or low SOC */ + if (!pp5000_inited && + ((battery_state_of_charge_abs(&soc) != EC_SUCCESS || + soc < charger_get_min_bat_pct_for_power_on()))) { + pd_ready_timeout = get_time(); + pd_ready_timeout.val += PD_READY_TIMEOUT; + } +} +DECLARE_HOOK(HOOK_USB_PD_CONNECT, board_usb_pd_connect, HOOK_PRIO_DEFAULT); + +static void wait_pd_ready(void) +{ + CPRINTS("Wait PD negotiated VBUS transition %u", + pd_ready_timeout.le.lo); + while (pd_ready_timeout.val && get_time().val < pd_ready_timeout.val) + usleep(PD_READY_POLL_DELAY); +} + +/* Called on AP S5 -> S3 transition */ +static void board_chipset_pre_init(void) +{ + if (!pp5000_inited) { + if (pd_ready_timeout.val) { + wait_pd_ready(); + } + CPRINTS("Enable 5V rail"); + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_en_pp5000_s5), 1); + pp5000_inited = true; + } +} +DECLARE_HOOK(HOOK_CHIPSET_PRE_INIT, board_chipset_pre_init, HOOK_PRIO_DEFAULT); diff --git a/zephyr/projects/herobrine/src/herobrine/alt_dev_replacement.c b/zephyr/projects/herobrine/src/herobrine/alt_dev_replacement.c new file mode 100644 index 0000000000..00acd509f4 --- /dev/null +++ b/zephyr/projects/herobrine/src/herobrine/alt_dev_replacement.c @@ -0,0 +1,36 @@ +/* Copyright 2021 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ +#include <zephyr/logging/log.h> +#include "usbc/ppc.h" +#include "hooks.h" +#include "cros_board_info.h" + +LOG_MODULE_REGISTER(alt_dev_replacement); + +#define BOARD_VERSION_UNKNOWN 0xffffffff + +/* Check board version to decide which ppc is used. */ +static bool board_has_alt_ppc(void) +{ + static uint32_t board_version = BOARD_VERSION_UNKNOWN; + + if (board_version == BOARD_VERSION_UNKNOWN) { + if (cbi_get_board_version(&board_version) != EC_SUCCESS) { + LOG_ERR("Failed to get board version."); + board_version = 0; + } + } + + return (board_version >= 1); +} + +static void check_alternate_devices(void) +{ + /* Configure the PPC driver */ + if (board_has_alt_ppc()) + /* Arg is the USB port number */ + PPC_ENABLE_ALTERNATE(0); +} +DECLARE_HOOK(HOOK_INIT, check_alternate_devices, HOOK_PRIO_DEFAULT); diff --git a/zephyr/projects/herobrine/src/i2c.c b/zephyr/projects/herobrine/src/i2c.c new file mode 100644 index 0000000000..88b722c42d --- /dev/null +++ b/zephyr/projects/herobrine/src/i2c.c @@ -0,0 +1,17 @@ +/* Copyright 2021 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "i2c/i2c.h" +#include "i2c.h" + +/* Herobrine-NPCX9 board specific i2c implementation */ + +#ifdef CONFIG_PLATFORM_EC_I2C_PASSTHRU_RESTRICTED +int board_allow_i2c_passthru(const struct i2c_cmd_desc_t *cmd_desc) +{ + return (i2c_get_device_for_port(cmd_desc->port) == + i2c_get_device_for_port(I2C_PORT_VIRTUAL_BATTERY)); +} +#endif diff --git a/zephyr/projects/herobrine/src/usb_pd_policy.c b/zephyr/projects/herobrine/src/usb_pd_policy.c new file mode 100644 index 0000000000..adc517d3cb --- /dev/null +++ b/zephyr/projects/herobrine/src/usb_pd_policy.c @@ -0,0 +1,254 @@ +/* Copyright 2021 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <zephyr/drivers/gpio.h> + +#include "charge_manager.h" +#include "chipset.h" +#include "console.h" +#include "system.h" +#include "usb_mux.h" +#include "usbc_ppc.h" +#include "util.h" + +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) + +int pd_check_vconn_swap(int port) +{ + /* In G3, do not allow vconn swap since PP5000 rail is off */ + return gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_en_pp5000_s5)); +} + +static uint8_t vbus_en[CONFIG_USB_PD_PORT_MAX_COUNT]; + +static void board_vbus_update_source_current(int port) +{ + ppc_vbus_source_enable(port, vbus_en[port]); +} + +void pd_power_supply_reset(int port) +{ + int prev_en; + + prev_en = vbus_en[port]; + + /* Disable VBUS */ + vbus_en[port] = 0; + board_vbus_update_source_current(port); + + /* Enable discharge if we were previously sourcing 5V */ + if (prev_en) + pd_set_vbus_discharge(port, 1); + + /* notify host of power info change */ + pd_send_host_event(PD_EVENT_POWER_CHANGE); +} + +int pd_set_power_supply_ready(int port) +{ + /* Disable charging */ + board_vbus_sink_enable(port, 0); + + pd_set_vbus_discharge(port, 0); + + /* Provide VBUS */ + vbus_en[port] = 1; + board_vbus_update_source_current(port); + + /* notify host of power info change */ + pd_send_host_event(PD_EVENT_POWER_CHANGE); + + return EC_SUCCESS; /* we are ready */ +} + +int board_vbus_source_enabled(int port) +{ + return vbus_en[port]; +} + +int pd_snk_is_vbus_provided(int port) +{ + return tcpm_check_vbus_level(port, VBUS_PRESENT); +} + +/* ----------------- Vendor Defined Messages ------------------ */ +#ifdef CONFIG_USB_PD_ALT_MODE_DFP +__override int svdm_dp_config(int port, uint32_t *payload) +{ + int opos = pd_alt_mode(port, TCPCI_MSG_SOP, USB_SID_DISPLAYPORT); + uint8_t pin_mode = get_dp_pin_mode(port); + + if (!pin_mode) + return 0; + + /* + * Defer setting the usb_mux until HPD goes high, svdm_dp_attention(). + * The AP only supports one DP phy. An external DP mux switches between + * the two ports. Should switch those muxes when it is really used, + * i.e. HPD high; otherwise, the real use case is preempted, like: + * (1) plug a dongle without monitor connected to port-0, + * (2) plug a dongle without monitor connected to port-1, + * (3) plug a monitor to the port-1 dongle. + */ + + payload[0] = + VDO(USB_SID_DISPLAYPORT, 1, CMD_DP_CONFIG | VDO_OPOS(opos)); + payload[1] = VDO_DP_CFG(pin_mode, /* pin mode */ + 1, /* DPv1.3 signaling */ + 2); /* UFP connected */ + return 2; +}; + +__override void svdm_dp_post_config(int port) +{ + dp_flags[port] |= DP_FLAGS_DP_ON; +} + +/** + * Is the port fine to be muxed its DisplayPort lines? + * + * Only one port can be muxed to DisplayPort at a time. + * + * @param port Port number of TCPC. + * @return 1 is fine; 0 is bad as other port is already muxed; + */ +static int is_dp_muxable(int port) +{ + int i; + + for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) + if (i != port) { + if (usb_mux_get(i) & USB_PD_MUX_DP_ENABLED) + return 0; + } + + return 1; +} + +__override int svdm_dp_attention(int port, uint32_t *payload) +{ + const struct gpio_dt_spec *hpd = + GPIO_DT_FROM_NODELABEL(gpio_dp_hot_plug_det_r); + int lvl = PD_VDO_DPSTS_HPD_LVL(payload[1]); + int irq = PD_VDO_DPSTS_HPD_IRQ(payload[1]); + int cur_lvl = gpio_pin_get_dt(hpd); + mux_state_t mux_state; + + dp_status[port] = payload[1]; + + if (!is_dp_muxable(port)) { + /* TODO(waihong): Info user? */ + CPRINTS("p%d: The other port is already muxed.", port); + return 0; + } + + /* + * Initial implementation to handle HPD. Only the first-plugged port + * works, i.e. sending HPD signal to AP. The second-plugged port + * will be ignored. + * + * TODO(waihong): Continue the above case, if the first-plugged port + * is then unplugged, switch to the second-plugged port and signal AP? + */ + if (lvl) { + /* + * Enable and switch the DP port selection mux to the + * correct port. + * + * TODO(waihong): Better to move switching DP mux to + * the usb_mux abstraction. + */ + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_dp_mux_sel), + port == 1); + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_dp_mux_oe_l), 0); + + /* Connect the SBU lines in PPC chip. */ + if (IS_ENABLED(CONFIG_USBC_PPC_SBU)) + ppc_set_sbu(port, 1); + + /* + * Connect the USB SS/DP lines in TCPC chip. + * + * When mf_pref not true, still use the dock muxing + * because of the board USB-C topology (limited to 2 + * lanes DP). + */ + usb_mux_set(port, USB_PD_MUX_DOCK, USB_SWITCH_CONNECT, + polarity_rm_dts(pd_get_polarity(port))); + } else { + /* Disconnect the DP port selection mux. */ + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_dp_mux_oe_l), 1); + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_dp_mux_sel), 0); + + /* Disconnect the SBU lines in PPC chip. */ + if (IS_ENABLED(CONFIG_USBC_PPC_SBU)) + ppc_set_sbu(port, 0); + + /* Disconnect the DP but keep the USB SS lines in TCPC chip. */ + usb_mux_set(port, USB_PD_MUX_USB_ENABLED, USB_SWITCH_CONNECT, + polarity_rm_dts(pd_get_polarity(port))); + } + + if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) && (irq || lvl)) + /* + * Wake up the AP. IRQ or level high indicates a DP sink is now + * present. + */ + pd_notify_dp_alt_mode_entry(port); + + /* Configure TCPC for the HPD event, for proper muxing */ + mux_state = (lvl ? USB_PD_MUX_HPD_LVL : USB_PD_MUX_HPD_LVL_DEASSERTED) | + (irq ? USB_PD_MUX_HPD_IRQ : USB_PD_MUX_HPD_IRQ_DEASSERTED); + usb_mux_hpd_update(port, mux_state); + + /* Signal AP for the HPD event, through GPIO to AP */ + if (irq & cur_lvl) { + uint64_t now = get_time().val; + /* Wait for the minimum spacing between IRQ_HPD if needed */ + if (now < svdm_hpd_deadline[port]) + usleep(svdm_hpd_deadline[port] - now); + + /* Generate IRQ_HPD pulse */ + CPRINTS("C%d: Recv IRQ. HPD->0", port); + gpio_pin_set_dt(hpd, 0); + usleep(HPD_DSTREAM_DEBOUNCE_IRQ); + gpio_pin_set_dt(hpd, 1); + CPRINTS("C%d: Recv IRQ. HPD->1", port); + + /* Set the minimum time delay (2ms) for the next HPD IRQ */ + svdm_hpd_deadline[port] = + get_time().val + HPD_USTREAM_DEBOUNCE_LVL; + } else if (irq & !lvl) { + CPRINTF("ERR:HPD:IRQ&LOW\n"); + return 0; + } else { + CPRINTS("C%d: Recv lvl. HPD->%d", port, lvl); + gpio_pin_set_dt(hpd, lvl); + /* Set the minimum time delay (2ms) for the next HPD IRQ */ + svdm_hpd_deadline[port] = + get_time().val + HPD_USTREAM_DEBOUNCE_LVL; + } + + return 1; +} + +__override void svdm_exit_dp_mode(int port) +{ + CPRINTS("%s(%d)", __func__, port); + if (is_dp_muxable(port)) { + /* Disconnect the DP port selection mux. */ + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_dp_mux_oe_l), 1); + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_dp_mux_sel), 0); + + /* Signal AP for the HPD low event */ + usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED | + USB_PD_MUX_HPD_IRQ_DEASSERTED); + CPRINTS("C%d: DP exit. HPD->0", port); + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_dp_hot_plug_det_r), + 0); + } +} +#endif /* CONFIG_USB_PD_ALT_MODE_DFP */ diff --git a/zephyr/projects/herobrine/src/usbc_config.c b/zephyr/projects/herobrine/src/usbc_config.c new file mode 100644 index 0000000000..f040ab12cb --- /dev/null +++ b/zephyr/projects/herobrine/src/usbc_config.c @@ -0,0 +1,278 @@ +/* Copyright 2021 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Herobrine board-specific USB-C configuration */ + +#include <zephyr/drivers/gpio.h> + +#include "charger.h" +#include "charger/isl923x_public.h" +#include "charge_manager.h" +#include "charge_state.h" +#include "common.h" +#include "config.h" +#include "cros_board_info.h" +#include "gpio/gpio_int.h" +#include "hooks.h" +#include "ppc/sn5s330_public.h" +#include "ppc/syv682x_public.h" +#include "system.h" +#include "tcpm/ps8xxx_public.h" +#include "tcpm/tcpci.h" +#include "timer.h" +#include "usb_pd.h" +#include "usb_mux.h" +#include "usbc_ocp.h" +#include "usbc_ppc.h" +#include "usbc/ppc.h" + +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) + +/* GPIO Interrupt Handlers */ +void tcpc_alert_event(enum gpio_signal signal) +{ + int port = -1; + + switch (signal) { + case GPIO_USB_C0_PD_INT_ODL: + port = 0; + break; + case GPIO_USB_C1_PD_INT_ODL: + port = 1; + break; + default: + return; + } + + schedule_deferred_pd_interrupt(port); +} + +static void usba_oc_deferred(void) +{ + /* Use next number after all USB-C ports to indicate the USB-A port */ + board_overcurrent_event( + CONFIG_USB_PD_PORT_MAX_COUNT, + !gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_a0_oc_odl))); +} +DECLARE_DEFERRED(usba_oc_deferred); + +void usba_oc_interrupt(enum gpio_signal signal) +{ + hook_call_deferred(&usba_oc_deferred_data, 0); +} + +void ppc_interrupt(enum gpio_signal signal) +{ + switch (signal) { + case GPIO_USB_C0_SWCTL_INT_ODL: + ppc_chips[0].drv->interrupt(0); + break; + + case GPIO_USB_C1_SWCTL_INT_ODL: + ppc_chips[1].drv->interrupt(1); + break; + + default: + break; + } +} + +int charger_profile_override(struct charge_state_data *curr) +{ + int usb_mv; + int port; + + if (curr->state != ST_CHARGE) + return 0; + + /* Lower the max requested voltage to 5V when battery is full. */ + if (chipset_in_state(CHIPSET_STATE_ANY_OFF) && + !(curr->batt.flags & BATT_FLAG_BAD_STATUS) && + !(curr->batt.flags & BATT_FLAG_WANT_CHARGE) && + (curr->batt.status & STATUS_FULLY_CHARGED)) + usb_mv = 5000; + else + usb_mv = PD_MAX_VOLTAGE_MV; + + if (pd_get_max_voltage() != usb_mv) { + CPRINTS("VBUS limited to %dmV", usb_mv); + for (port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; port++) + pd_set_external_voltage_limit(port, usb_mv); + } + + return 0; +} + +enum ec_status charger_profile_override_get_param(uint32_t param, + uint32_t *value) +{ + return EC_RES_INVALID_PARAM; +} + +enum ec_status charger_profile_override_set_param(uint32_t param, + uint32_t value) +{ + return EC_RES_INVALID_PARAM; +} + +/* Initialize board USC-C things */ +static void board_init_usbc(void) +{ + /* Enable USB-A overcurrent interrupt */ + gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_a0_oc)); +} +DECLARE_HOOK(HOOK_INIT, board_init_usbc, HOOK_PRIO_DEFAULT); + +void board_tcpc_init(void) +{ + /* Only reset TCPC if not sysjump */ + if (!system_jumped_late()) { + /* TODO(crosbug.com/p/61098): How long do we need to wait? */ + board_reset_pd_mcu(); + } + + /* Enable PPC interrupts */ + gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0_swctl)); + + /* Enable TCPC interrupts */ + gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0_pd)); + gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c1_pd)); + + /* + * Initialize HPD to low; after sysjump SOC needs to see + * HPD pulse to enable video path + */ + for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port) + usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED | + USB_PD_MUX_HPD_IRQ_DEASSERTED); +} +DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_POST_I2C); + +void board_reset_pd_mcu(void) +{ + cprints(CC_USB, "Resetting TCPCs..."); + cflush(); + + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_c0_pd_rst_l), 0); + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_c1_pd_rst_l), 0); + msleep(PS8XXX_RESET_DELAY_MS); + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_c0_pd_rst_l), 1); + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_c1_pd_rst_l), 1); + msleep(PS8805_FW_INIT_DELAY_MS); +} + +void board_set_tcpc_power_mode(int port, int mode) +{ + /* Ignore the "mode" to turn the chip on. We can only do a reset. */ + if (mode) + return; + + board_reset_pd_mcu(); +} + +int board_vbus_sink_enable(int port, int enable) +{ + /* Both ports are controlled by PPC SN5S330 */ + return ppc_vbus_sink_enable(port, enable); +} + +int board_is_sourcing_vbus(int port) +{ + /* Both ports are controlled by PPC SN5S330 */ + return ppc_is_sourcing_vbus(port); +} + +void board_overcurrent_event(int port, int is_overcurrented) +{ + /* TODO(b/120231371): Notify AP */ + CPRINTS("p%d: overcurrent!", port); +} + +int board_set_active_charge_port(int port) +{ + int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT); + int i; + + if (!is_real_port && port != CHARGE_PORT_NONE) + return EC_ERROR_INVAL; + + if (port == CHARGE_PORT_NONE) { + CPRINTS("Disabling all charging port"); + + /* Disable all ports. */ + for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) { + /* + * Do not return early if one fails otherwise we can + * get into a boot loop assertion failure. + */ + if (board_vbus_sink_enable(i, 0)) + CPRINTS("Disabling p%d sink path failed.", i); + } + + return EC_SUCCESS; + } + + /* Check if the port is sourcing VBUS. */ + if (board_is_sourcing_vbus(port)) { + CPRINTS("Skip enable p%d", port); + return EC_ERROR_INVAL; + } + + CPRINTS("New charge port: p%d", port); + + /* + * Turn off the other ports' sink path FETs, before enabling the + * requested charge port. + */ + for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) { + if (i == port) + continue; + + if (board_vbus_sink_enable(i, 0)) + CPRINTS("p%d: sink path disable failed.", i); + } + + /* Enable requested charge port. */ + if (board_vbus_sink_enable(port, 1)) { + CPRINTS("p%d: sink path enable failed.", port); + return EC_ERROR_UNKNOWN; + } + + return EC_SUCCESS; +} + +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) +{ + /* + * Ignore lower charge ceiling on PD transition if our battery is + * critical, as we may brownout. + */ + if (supplier == CHARGE_SUPPLIER_PD && charge_ma < 1500 && + charge_get_percent() < CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON) { + CPRINTS("Using max ilim %d", max_ma); + charge_ma = max_ma; + } + + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); +} + +uint16_t tcpc_get_alert_status(void) +{ + uint16_t status = 0; + + if (!gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_c0_pd_int_odl))) + if (gpio_pin_get_dt( + GPIO_DT_FROM_NODELABEL(gpio_usb_c0_pd_rst_l))) + status |= PD_STATUS_TCPC_ALERT_0; + if (!gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_c1_pd_int_odl))) + if (gpio_pin_get_dt( + GPIO_DT_FROM_NODELABEL(gpio_usb_c1_pd_rst_l))) + status |= PD_STATUS_TCPC_ALERT_1; + + return status; +} diff --git a/zephyr/projects/herobrine/switchcap.dts b/zephyr/projects/herobrine/switchcap.dts new file mode 100644 index 0000000000..ed200a0c6f --- /dev/null +++ b/zephyr/projects/herobrine/switchcap.dts @@ -0,0 +1,12 @@ +/* Copyright 2021 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + switchcap { + compatible = "switchcap-gpio"; + enable-pin = <&gpio_switchcap_on>; + power-good-pin = <&gpio_switchcap_pg>; + }; +}; diff --git a/zephyr/projects/herobrine/switchcap_hoglin.dts b/zephyr/projects/herobrine/switchcap_hoglin.dts new file mode 100644 index 0000000000..7c083667a1 --- /dev/null +++ b/zephyr/projects/herobrine/switchcap_hoglin.dts @@ -0,0 +1,12 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + switchcap { + compatible = "switchcap-gpio"; + enable-pin = <&gpio_switchcap_on>; + poff-delay-ms = <550>; + }; +}; diff --git a/zephyr/projects/herobrine/usbc_evoker.dts b/zephyr/projects/herobrine/usbc_evoker.dts new file mode 100644 index 0000000000..20bd48382f --- /dev/null +++ b/zephyr/projects/herobrine/usbc_evoker.dts @@ -0,0 +1,42 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + usbc { + #address-cells = <1>; + #size-cells = <0>; + + port0@0 { + compatible = "named-usbc-port"; + reg = <0>; + bc12 = <&bc12_port0>; + ppc = <&ppc_port0>; + tcpc = <&tcpc_port0>; + chg = <&charger>; + usb-mux-chain-0 { + compatible = "cros-ec,usb-mux-chain"; + usb-muxes = <&usb_mux_0>; + }; + }; + usb_mux_0: usb-mux-0 { + compatible = "parade,usbc-mux-ps8xxx"; + }; + + port1@1 { + compatible = "named-usbc-port"; + reg = <1>; + bc12 = <&bc12_port1>; + ppc = <&ppc_port1>; + tcpc = <&tcpc_port1>; + usb-mux-chain-1 { + compatible = "cros-ec,usb-mux-chain"; + usb-muxes = <&usb_mux_1>; + }; + }; + usb_mux_1: usb-mux-1 { + compatible = "parade,usbc-mux-ps8xxx"; + }; + }; +}; diff --git a/zephyr/projects/herobrine/usbc_herobrine.dts b/zephyr/projects/herobrine/usbc_herobrine.dts new file mode 100644 index 0000000000..675286ecd7 --- /dev/null +++ b/zephyr/projects/herobrine/usbc_herobrine.dts @@ -0,0 +1,43 @@ +/* Copyright 2021 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + usbc { + #address-cells = <1>; + #size-cells = <0>; + + port0@0 { + compatible = "named-usbc-port"; + reg = <0>; + bc12 = <&bc12_port0>; + ppc = <&ppc_port0>; + ppc_alt = <&ppc_port0_alt>; + tcpc = <&tcpc_port0>; + chg = <&charger>; + usb-mux-chain-0 { + compatible = "cros-ec,usb-mux-chain"; + usb-muxes = <&usb_mux_0>; + }; + }; + usb_mux_0: usb-mux-0 { + compatible = "parade,usbc-mux-ps8xxx"; + }; + + port1@1 { + compatible = "named-usbc-port"; + reg = <1>; + bc12 = <&bc12_port1>; + ppc = <&ppc_port1>; + tcpc = <&tcpc_port1>; + usb-mux-chain-1 { + compatible = "cros-ec,usb-mux-chain"; + usb-muxes = <&usb_mux_1>; + }; + }; + usb_mux_1: usb-mux-1 { + compatible = "parade,usbc-mux-ps8xxx"; + }; + }; +}; diff --git a/zephyr/projects/herobrine/usbc_hoglin.dts b/zephyr/projects/herobrine/usbc_hoglin.dts new file mode 100644 index 0000000000..20bd48382f --- /dev/null +++ b/zephyr/projects/herobrine/usbc_hoglin.dts @@ -0,0 +1,42 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + usbc { + #address-cells = <1>; + #size-cells = <0>; + + port0@0 { + compatible = "named-usbc-port"; + reg = <0>; + bc12 = <&bc12_port0>; + ppc = <&ppc_port0>; + tcpc = <&tcpc_port0>; + chg = <&charger>; + usb-mux-chain-0 { + compatible = "cros-ec,usb-mux-chain"; + usb-muxes = <&usb_mux_0>; + }; + }; + usb_mux_0: usb-mux-0 { + compatible = "parade,usbc-mux-ps8xxx"; + }; + + port1@1 { + compatible = "named-usbc-port"; + reg = <1>; + bc12 = <&bc12_port1>; + ppc = <&ppc_port1>; + tcpc = <&tcpc_port1>; + usb-mux-chain-1 { + compatible = "cros-ec,usb-mux-chain"; + usb-muxes = <&usb_mux_1>; + }; + }; + usb_mux_1: usb-mux-1 { + compatible = "parade,usbc-mux-ps8xxx"; + }; + }; +}; diff --git a/zephyr/projects/herobrine/usbc_villager.dts b/zephyr/projects/herobrine/usbc_villager.dts new file mode 100644 index 0000000000..20bd48382f --- /dev/null +++ b/zephyr/projects/herobrine/usbc_villager.dts @@ -0,0 +1,42 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + usbc { + #address-cells = <1>; + #size-cells = <0>; + + port0@0 { + compatible = "named-usbc-port"; + reg = <0>; + bc12 = <&bc12_port0>; + ppc = <&ppc_port0>; + tcpc = <&tcpc_port0>; + chg = <&charger>; + usb-mux-chain-0 { + compatible = "cros-ec,usb-mux-chain"; + usb-muxes = <&usb_mux_0>; + }; + }; + usb_mux_0: usb-mux-0 { + compatible = "parade,usbc-mux-ps8xxx"; + }; + + port1@1 { + compatible = "named-usbc-port"; + reg = <1>; + bc12 = <&bc12_port1>; + ppc = <&ppc_port1>; + tcpc = <&tcpc_port1>; + usb-mux-chain-1 { + compatible = "cros-ec,usb-mux-chain"; + usb-muxes = <&usb_mux_1>; + }; + }; + usb_mux_1: usb-mux-1 { + compatible = "parade,usbc-mux-ps8xxx"; + }; + }; +}; diff --git a/zephyr/projects/herobrine/usbc_zombie.dts b/zephyr/projects/herobrine/usbc_zombie.dts new file mode 100644 index 0000000000..20bd48382f --- /dev/null +++ b/zephyr/projects/herobrine/usbc_zombie.dts @@ -0,0 +1,42 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + usbc { + #address-cells = <1>; + #size-cells = <0>; + + port0@0 { + compatible = "named-usbc-port"; + reg = <0>; + bc12 = <&bc12_port0>; + ppc = <&ppc_port0>; + tcpc = <&tcpc_port0>; + chg = <&charger>; + usb-mux-chain-0 { + compatible = "cros-ec,usb-mux-chain"; + usb-muxes = <&usb_mux_0>; + }; + }; + usb_mux_0: usb-mux-0 { + compatible = "parade,usbc-mux-ps8xxx"; + }; + + port1@1 { + compatible = "named-usbc-port"; + reg = <1>; + bc12 = <&bc12_port1>; + ppc = <&ppc_port1>; + tcpc = <&tcpc_port1>; + usb-mux-chain-1 { + compatible = "cros-ec,usb-mux-chain"; + usb-muxes = <&usb_mux_1>; + }; + }; + usb_mux_1: usb-mux-1 { + compatible = "parade,usbc-mux-ps8xxx"; + }; + }; +}; diff --git a/zephyr/projects/intelrvp/BUILD.py b/zephyr/projects/intelrvp/BUILD.py new file mode 100644 index 0000000000..f129b3d2d2 --- /dev/null +++ b/zephyr/projects/intelrvp/BUILD.py @@ -0,0 +1,98 @@ +# Copyright 2022 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +"""Define zmake projects for intelrvp.""" + +# intelrvp has adlrvp_npcx, adlrvpp_ite, adlrvpp_mchp etc + + +def register_intelrvp_project( + project_name, + chip="npcx9m3f", + extra_dts_overlays=(), + extra_kconfig_files=(), +): + """Register a variant of intelrvp.""" + register_func = register_binman_project + if chip.startswith("mec1727"): + register_func = register_mchp_project + elif chip.startswith("npcx"): + register_func = register_npcx_project + + kconfig_files = [here / "prj.conf"] + dts_overlays = [] + if project_name.startswith("adlrvp"): + kconfig_files.append(here / "adlrvp/prj.conf") + dts_overlays.append(here / "adlrvp/battery.dts") + dts_overlays.append(here / "adlrvp/ioex.dts") + if project_name.startswith("mtlrvp"): + kconfig_files.append(here / "mtlrvp/prj.conf") + dts_overlays.append(here / "adlrvp/battery.dts") + kconfig_files.extend(extra_kconfig_files) + dts_overlays.extend(extra_dts_overlays) + + register_func( + project_name=project_name, + zephyr_board=chip, + dts_overlays=dts_overlays, + kconfig_files=kconfig_files, + ) + + +register_intelrvp_project( + project_name="adlrvp_mchp", + chip="mec1727", + extra_dts_overlays=[ + here / "adlrvp/adlrvp_mchp/adlrvp_mchp.dts", + here / "adlrvp/adlrvp_mchp/gpio.dts", + here / "adlrvp/adlrvp_mchp/interrupts.dts", + here / "adlrvp/adlrvp_mchp/keyboard.dts", + here / "adlrvp/adlrvp_mchp/usbc.dts", + ], + extra_kconfig_files=[ + here / "legacy_ec_pwrseq.conf", + here / "adlrvp/adlrvp_mchp/prj.conf", + ], +) + + +register_intelrvp_project( + project_name="adlrvp_npcx", + chip="npcx9m7f", + extra_dts_overlays=[ + here / "adlrvp/adlrvp_npcx/adlrvp_npcx.dts", + here / "adlrvp/adlrvp_npcx/fan.dts", + here / "adlrvp/adlrvp_npcx/gpio.dts", + here / "adlrvp/adlrvp_npcx/interrupts.dts", + here / "adlrvp/adlrvp_npcx/keyboard.dts", + here / "adlrvp/adlrvp_npcx/temp_sensor.dts", + here / "adlrvp/adlrvp_npcx/usbc.dts", + here / "adlrvp/adlrvp_npcx/pwm_leds.dts", + ], + extra_kconfig_files=[ + here / "legacy_ec_pwrseq.conf", + here / "adlrvp/adlrvp_npcx/prj.conf", + ], +) + + +register_intelrvp_project( + project_name="mtlrvpp_npcx", + chip="npcx9m3f", + extra_dts_overlays=[ + here / "mtlrvp/mtlrvpp_npcx/fan.dts", + here / "mtlrvp/mtlrvpp_npcx/gpio.dts", + here / "mtlrvp/mtlrvpp_npcx/keyboard.dts", + here / "mtlrvp/mtlrvpp_npcx/interrupts.dts", + here / "mtlrvp/ioex.dts", + here / "mtlrvp/mtlrvpp_npcx/mtlrvp_npcx.dts", + here / "mtlrvp/mtlrvpp_npcx/mtlrvp_npcx_power_signals.dts", + here / "adlrvp/adlrvp_npcx/temp_sensor.dts", + here / "mtlrvp/usbc.dts", + ], + extra_kconfig_files=[ + here / "zephyr_ap_pwrseq.conf", + here / "mtlrvp/mtlrvpp_npcx/prj.conf", + ], +) diff --git a/zephyr/projects/intelrvp/CMakeLists.txt b/zephyr/projects/intelrvp/CMakeLists.txt new file mode 100644 index 0000000000..039627dec6 --- /dev/null +++ b/zephyr/projects/intelrvp/CMakeLists.txt @@ -0,0 +1,32 @@ +# Copyright 2022 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +cmake_minimum_required(VERSION 3.13.1) + +find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}") +project(intelrvp) + +cros_ec_library_include_directories(include) +cros_ec_library_include_directories("${PLATFORM_EC}/driver/charger") +cros_ec_library_include_directories("${PLATFORM_EC}/driver/ppc") +cros_ec_library_include_directories("${PLATFORM_EC}/driver/tcpm") +cros_ec_library_include_directories("${PLATFORM_EC}/driver/usb_mux") +zephyr_library_sources("src/intel_rvp_board_id.c") + +if((DEFINED CONFIG_BOARD_ADLRVP_MCHP) OR (DEFINED CONFIG_BOARD_ADLRVP_NPCX)) + add_subdirectory(adlrvp) + zephyr_library_sources("src/intelrvp.c") + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "${PLATFORM_EC}/baseboard/intelrvp/usb_pd_policy_mecc_1_0.c") + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "${PLATFORM_EC}/baseboard/intelrvp/chg_usb_pd_mecc_1_0.c") + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "${PLATFORM_EC}/baseboard/intelrvp/chg_usb_pd.c") + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_LED_PWM "src/intel_rvp_led.c") +endif() + +if(DEFINED CONFIG_BOARD_MTLRVP_NPCX) + add_subdirectory(mtlrvp) + zephyr_library_sources("src/intelrvp.c") + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "src/usb_pd_policy_mecc_1_1.c") + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "src/chg_usb_pd_mecc_1_1.c") + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "src/chg_usb_pd.c") +endif() diff --git a/zephyr/projects/intelrvp/Kconfig b/zephyr/projects/intelrvp/Kconfig new file mode 100644 index 0000000000..605f57c054 --- /dev/null +++ b/zephyr/projects/intelrvp/Kconfig @@ -0,0 +1,26 @@ +# Copyright 2022 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +config BOARD_ADLRVP_MCHP + bool "Intel ADLRVP_MCHP board" + depends on SOC_MEC172X_NSZ + help + Build Intel ADLRVP_MCHP reference board. This board has Intel ADL RVP + SoC with MEC1727 EC. + +config BOARD_ADLRVP_NPCX + bool "Intel ADLRVP_NPCX board" + depends on SOC_NPCX9M7F + help + Build Intel ADLRVP_NPCX reference board. This board has Intel ADL RVP + SoC with NPCX9M37F EC. + +config BOARD_MTLRVP_NPCX + bool "Intel MTLRVP_NPCX board" + depends on SOC_NPCX9M3F + help + Build Intel MTLRVP_NPCX reference board. This board is Intel MTL RVP + SOC with NPCX_NPCX9M3F + +source "Kconfig.zephyr" diff --git a/zephyr/projects/intelrvp/adlrvp/CMakeLists.txt b/zephyr/projects/intelrvp/adlrvp/CMakeLists.txt new file mode 100644 index 0000000000..71dee29552 --- /dev/null +++ b/zephyr/projects/intelrvp/adlrvp/CMakeLists.txt @@ -0,0 +1,6 @@ +# Copyright 2022 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +cros_ec_library_include_directories("include") +zephyr_library_sources("src/adlrvp.c") diff --git a/zephyr/projects/intelrvp/adlrvp/adlrvp_mchp/adlrvp_mchp.dts b/zephyr/projects/intelrvp/adlrvp/adlrvp_mchp/adlrvp_mchp.dts new file mode 100644 index 0000000000..527a62e776 --- /dev/null +++ b/zephyr/projects/intelrvp/adlrvp/adlrvp_mchp/adlrvp_mchp.dts @@ -0,0 +1,201 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + hibernate-wake-pins { + compatible = "cros-ec,hibernate-wake-pins"; + wakeup-irqs = < + &int_ac_present + &int_lid_open + &int_power_button + >; + }; + + named-i2c-ports { + compatible = "named-i2c-ports"; + + i2c_charger: charger { + i2c-port = <&i2c_smb_0>; + enum-names = "I2C_PORT_BATTERY", + "I2C_PORT_CHARGER", + "I2C_PORT_EEPROM", + "I2C_PORT_PORT80"; + }; + typec_0: typec-0 { + i2c-port = <&i2c_smb_1>; + enum-names = "I2C_PORT_TYPEC_0"; + }; + typec_1: typec-1 { + i2c-port = <&i2c_smb_2>; + enum-names = "I2C_PORT_TYPEC_1"; + }; + typec_2: typec-2 { + i2c-port = <&i2c_smb_3>; + enum-names = "I2C_PORT_TYPEC_2"; + }; + typec_3: typec-3 { + i2c-port = <&i2c_smb_4>; + enum-names = "I2C_PORT_TYPEC_3"; + }; + }; +}; + +/* charger */ +&i2c_smb_0 { + status = "okay"; + clock-frequency = <I2C_BITRATE_STANDARD>; + port_sel = <0>; + pinctrl-0 = <&i2c00_scl_gpio004 &i2c00_sda_gpio003>; + pinctrl-names = "default"; + + pca95xx: pca95xx@22 { + compatible = "nxp,pca95xx"; + label = "PCA95XX"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + }; + + rvp_board_id: rvp-board-id { + compatible = "intel,rvp-board-id"; + + /* + * BOM ID [2] : IOEX[0] + * BOM ID [1:0] : IOEX[15:14] + */ + bom-gpios = <&pca95xx 0 0>, <&pca95xx 15 0>, <&pca95xx 14 0>; + + /* + * FAB ID [1:0] : IOEX[2:1] + */ + fab-gpios = <&pca95xx 2 0>, <&pca95xx 1 0>; + + /* + * BOARD ID[5:0] : IOEX[13:8] + */ + board-gpios = <&pca95xx 13 0>, <&pca95xx 12 0>, <&pca95xx 11 0>, + <&pca95xx 10 0>, <&pca95xx 9 0>, <&pca95xx 8 0>; + }; + + seven_seg_display: max695x-seven-seg-display@38 { + compatible = "maxim,seven-seg-display"; + reg = <0x38>; + label = "MAX695X_SEVEN_SEG_DISPLAY"; + }; + + charger: isl9241@9 { + compatible = "intersil,isl9241"; + status = "okay"; + reg = <0x9>; + }; + + cbi_eeprom: eeprom@50 { + compatible = "atmel,at24"; + reg = <0x50>; + size = <2048>; + pagesize = <16>; + address-width = <8>; + timeout = <5>; + }; +}; + +/* typec_0 */ +&i2c_smb_1 { + status = "okay"; + clock-frequency = <I2C_BITRATE_FAST>; + port_sel = <6>; + pinctrl-0 = <&i2c06_scl_gpio140 &i2c06_sda_gpio132>; + pinctrl-names = "default"; + + tcpc_port0: fusb302@22 { + compatible = "fairchild,fusb302"; + reg = <0x22>; + }; + + usb_c0_soc_side_bb_retimer: jhl8040r-c0-soc-side@54 { + compatible = "intel,jhl8040r"; + reg = <0x54>; + reset-pin = <&usb_c0_bb_retimer_rst>; + ls-en-pin = <&usb_c0_bb_retimer_ls_en>; + }; + + usb_c0_bb_retimer: jhl8040r-c0@56 { + compatible = "intel,jhl8040r"; + reg = <0x56>; + reset-pin = <&usb_c0_bb_retimer_rst>; + ls-en-pin = <&usb_c0_bb_retimer_ls_en>; + }; +}; + +/* typec_1 */ +&i2c_smb_2 { + status = "okay"; + clock-frequency = <I2C_BITRATE_FAST>; + port_sel = <3>; + pinctrl-0 = <&i2c03_scl_gpio010 &i2c03_sda_gpio007>; + pinctrl-names = "default"; + + tcpc_port1: fusb302@22 { + compatible = "fairchild,fusb302"; + reg = <0x22>; + }; + + usb_c1_soc_side_bb_retimer: jhl8040r-c1-soc-side@55 { + compatible = "intel,jhl8040r"; + reg = <0x55>; + reset-pin = <&usb_c1_bb_retimer_rst>; + ls-en-pin = <&usb_c1_bb_retimer_ls_en>; + }; + + usb_c1_bb_retimer: jhl8040r-c1@57 { + compatible = "intel,jhl8040r"; + reg = <0x57>; + reset-pin = <&usb_c1_bb_retimer_rst>; + ls-en-pin = <&usb_c1_bb_retimer_ls_en>; + }; +}; + +/* typec_2 */ +&i2c_smb_3 { + status = "okay"; + clock-frequency = <I2C_BITRATE_FAST>; + port_sel = <7>; + pinctrl-0 = <&i2c07_scl_gpio013 &i2c07_sda_gpio012>; + pinctrl-names = "default"; + + tcpc_port2: fusb302@22 { + compatible = "fairchild,fusb302"; + reg = <0x22>; + }; + + usb_c2_bb_retimer: jhl8040r-c2@58 { + compatible = "intel,jhl8040r"; + reg = <0x58>; + reset-pin = <&usb_c2_bb_retimer_rst>; + ls-en-pin = <&usb_c2_bb_retimer_ls_en>; + }; +}; + +/* typec_3 */ +&i2c_smb_4 { + status = "okay"; + clock-frequency = <I2C_BITRATE_FAST>; + port_sel = <2>; + pinctrl-0 = <&i2c02_scl_gpio155 &i2c02_sda_gpio154>; + pinctrl-names = "default"; + + tcpc_port3: fusb302@22 { + compatible = "fairchild,fusb302"; + reg = <0x22>; + }; + + usb_c3_bb_retimer: jhl8040r-c3@59 { + compatible = "intel,jhl8040r"; + reg = <0x59>; + reset-pin = <&usb_c3_bb_retimer_rst>; + ls-en-pin = <&usb_c3_bb_retimer_ls_en>; + }; +}; diff --git a/zephyr/projects/intelrvp/adlrvp/adlrvp_mchp/bb_retimer.dts b/zephyr/projects/intelrvp/adlrvp/adlrvp_mchp/bb_retimer.dts new file mode 100644 index 0000000000..1c760120f1 --- /dev/null +++ b/zephyr/projects/intelrvp/adlrvp/adlrvp_mchp/bb_retimer.dts @@ -0,0 +1,28 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +&i2c_smb_1 { + status = "okay"; + clock-frequency = <I2C_BITRATE_FAST>; + + usb_c0_bb_retimer: jhl8040r@56 { + compatible = "intel,jhl8040r"; + reg = <0x56>; + label = "USB_C0_BB_RETIMER"; + reset-pin = <&usb_c0_bb_retimer_rst>; + }; +}; + +&i2c_smb_2 { + status = "okay"; + clock-frequency = <I2C_BITRATE_FAST>; + + usb_c1_bb_retimer: jhl8040r@57 { + compatible = "intel,jhl8040r"; + reg = <0x57>; + label = "USB_C1_BB_RETIMER"; + reset-pin = <&usb_c1_bb_retimer_rst>; + }; +}; diff --git a/zephyr/projects/intelrvp/adlrvp/adlrvp_mchp/gpio.dts b/zephyr/projects/intelrvp/adlrvp/adlrvp_mchp/gpio.dts new file mode 100644 index 0000000000..d526fdcb3b --- /dev/null +++ b/zephyr/projects/intelrvp/adlrvp/adlrvp_mchp/gpio.dts @@ -0,0 +1,299 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + aliases { + gpio-wp = &gpio_wp; + gpio-kbd-kso2 = &gpio_ec_kso_02_inv; + }; + + named-gpios { + compatible = "named-gpios"; + + all_sys_pwrgd: all-sys-pwrgd { + gpios = <&gpio_040_076 15 GPIO_INPUT>; + enum-name = "GPIO_PG_EC_ALL_SYS_PWRGD"; + }; /* GPIO057 */ + rsmrst_pwrgd: rsmrst-pwrgd { + gpios = <&gpio_200_236 17 GPIO_INPUT>; + enum-name = "GPIO_PG_EC_RSMRST_ODL"; + }; /* GPIO221 */ + pch_slp_s0_n: pch-slp-s0-n { + gpios = <&gpio_240_276 3 GPIO_INPUT>; + enum-name = "GPIO_PCH_SLP_S0_L"; + }; /* GPIO243 */ + vccpdsw_3p3: vccpdsw-3p3 { + gpios = <&gpio_200_236 1 GPIO_INPUT>; + enum-name = "GPIO_PG_EC_DSW_PWROK"; + }; /* GPIO201 */ + pm_slp_sus_ec_n: pm-slp-sus-ec-n { + gpios = <&gpio_200_236 23 GPIO_INPUT>; + enum-name = "GPIO_SLP_SUS_L"; + }; /* GPIO227 */ + pm_slp_s3_n: pm-slp-s3-n { + gpios = <&gpio_140_176 17 GPIO_INPUT>; + enum-name = "GPIO_PCH_SLP_S3_L"; + }; /* GPIO161 */ + pm_slp_s4_n: pm-slp-s4-n { + gpios = <&gpio_140_176 18 GPIO_INPUT>; + }; /* GPIO162 */ + volume_up { + gpios = <&gpio_000_036 30 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_VOLUME_UP_L"; + }; /* GPIO036 */ + vol_dn_ec { + gpios = <&gpio_240_276 12 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_VOLUME_DOWN_L"; + }; /* GPIO254 */ + smc_lid: smc-lid { + gpios = <&gpio_200_236 22 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_LID_OPEN"; + }; /* GPIO226 */ + mech_pwr_btn_odl: mech-pwr-btn-odl { + gpios = <&gpio_100_136 13 GPIO_INPUT>; + enum-name = "GPIO_POWER_BUTTON_L"; + }; /* GPIO115 */ + std_adp_prsnt: std-adp-prsnt { + gpios = <&gpio_040_076 3 GPIO_INPUT>; + enum-name= "GPIO_DC_JACK_PRESENT"; + }; /* GPIO043 */ + bc_acok: bc-acok { + gpios = <&gpio_140_176 14 GPIO_INPUT>; + enum-name = "GPIO_AC_PRESENT"; + }; /* GPIO156 */ + usbc_tcpc_alrt_p0: usbc-tcpc-alrt-p0 { + gpios = <&gpio_140_176 3 GPIO_INPUT>; + }; /* GPIO143 */ + usbc_tcpc_alrt_p1: usbc-tcpc-alrt-p1 { + gpios = <&gpio_240_276 1 GPIO_INPUT>; + }; /* GPIO241 */ + usbc_tcpc_alrt_p2: usbc-tcpc-alrt-p2 { + gpios = <&gpio_100_136 24 GPIO_INPUT>; + }; /* GPIO130 */ + usbc_tcpc_alrt_p3: usbc-tcpc-alrt-p3 { + gpios = <&gpio_240_276 2 GPIO_INPUT>; + }; /* GPIO242 */ + usbc_tcpc_ppc_alrt_p0: usbc-tcpc-ppc-alrt-p0 { + gpios = <&gpio_240_276 0 GPIO_INPUT>; + }; /* GPIO240 */ + usbc_tcpc_ppc_alrt_p1: usbc-tcpc-ppc-alrt-p1 { + gpios = <&gpio_100_136 1 GPIO_INPUT>; + }; /* GPIO101 */ + usbc_tcpc_ppc_alrt_p2: usbc-tcpc-ppc-alrt-p2 { + gpios = <&gpio_140_176 4 GPIO_INPUT>; + }; /* GPIO144 */ + usbc_tcpc_ppc_alrt_p3: usbc-tcpc-ppc-alrt-p3 { + gpios = <&gpio_140_176 2 GPIO_INPUT>; + }; /* GPIO142 */ + gpio_ec_pch_wake_odl: smc-wake-sci-n-mecc { + gpios = <&gpio_040_076 9 GPIO_ODR_HIGH>; + }; /* GPIO051 */ + ec_pch_mkbp_int_odl { + gpios = <&gpio_100_136 23 GPIO_ODR_HIGH>; + }; /* GPIO127 */ + lpc_espi_rst_n { + gpios = <&gpio_040_076 17 GPIO_INPUT>; + }; /* GPIO061 NANA */ + plt_rst_l { + gpios = <&gpio_040_076 10 GPIO_INPUT>; + }; /* GPIO052 NANA */ + slate_mode_indication { + gpios = <&gpio_200_236 18 GPIO_INPUT>; + }; /* GPIO222 */ + prochot_ec_n { + gpios = <&gpio_000_036 2 GPIO_INPUT>; + enum-name = "GPIO_CPU_PROCHOT"; + }; /* GPIO002 ???? */ + sys_rst_odl { + gpios = <&gpio_040_076 16 GPIO_ODR_HIGH>; + enum-name = "GPIO_SYS_RESET_L"; + }; /* GPIO060 */ + pm_rsmrst_n { + gpios = <&gpio_040_076 12 GPIO_OUTPUT_LOW>; + enum-name = "GPIO_PCH_RSMRST_L"; + }; /* GPIO054 */ + pm_pwrbtn_n { + gpios = <&gpio_000_036 14 GPIO_ODR_HIGH>; + enum-name = "GPIO_PCH_PWRBTN_L"; + }; /* GPIO016 */ + ec_spi_oe_mecc: ec-spi-oe-mecc { + gpios = <&gpio_040_076 2 GPIO_OUTPUT_LOW>; + }; /* GPIO042 */ + ec_ds3 { + gpios = <&gpio_000_036 21 GPIO_OUTPUT_LOW>; + enum-name = "GPIO_EN_PP3300_A"; + }; /* GPIO025 */ + pch_pwrok_ec { + gpios = <&gpio_100_136 6 GPIO_INPUT>; + enum-name = "GPIO_PCH_PWROK"; + }; /* GPIO106 */ + sys_pwrok { + gpios = <&gpio_200_236 2 GPIO_OUTPUT_LOW>; + enum-name = "GPIO_PCH_SYS_PWROK"; + }; /* GPIO202 */ + ec_dsw_pwrok { + gpios = <&gpio_000_036 28 GPIO_OUTPUT_LOW>; + enum-name = "GPIO_PCH_DSW_PWROK"; + }; /* GPIO034 */ + gpio_wp: ec-flash-wp-odl { + gpios = <&gpio_000_036 12 GPIO_INPUT>; + }; /* GPIO014 */ + ec_h1_packet_mode { + gpios = <&gpio_000_036 29 GPIO_OUTPUT_LOW>; + enum-name = "GPIO_PACKET_MODE_EN"; + }; /* GPIO035 */ + ec_entering_rw { + gpios = <&gpio_100_136 2 GPIO_OUTPUT_LOW>; + enum-name = "GPIO_ENTERING_RW"; + }; /* GPIO102 */ + ccd_mode_odl: ccd-mode-odl { + gpios = <&gpio_140_176 29 GPIO_INPUT>; + enum-name = "GPIO_CCD_MODE_ODL"; + }; /* GPIO175 */ + bat_det { + gpios = <&gpio_200_236 6 GPIO_INPUT>; + enum-name = "GPIO_BATT_PRES_ODL"; + }; /* GPIO206 */ + edp_bklt_en_mecc { + gpios = <&gpio_000_036 18 GPIO_OUTPUT_HIGH>; + }; /* GPIO022 */ + led_1_l { + gpios = <&gpio_140_176 15 GPIO_OUTPUT_HIGH>; + }; /* GPIO157 */ + led_2_l { + gpios = <&gpio_140_176 11 GPIO_OUTPUT_HIGH>; + }; /* GPIO153 */ + therm_sen_mecc { + gpios = <&gpio_140_176 1 GPIO_OUTPUT_LOW>; + }; /* GPIO141 */ + smb_bs_clk { + gpios = <&gpio_000_036 4 GPIO_INPUT>; + }; /* GPIO004 */ + smb_bs_data { + gpios = <&gpio_000_036 3 GPIO_INPUT>; + }; /* GPIO003 */ + usbc_tcpc_i2c_clk_p0 { + gpios = <&gpio_140_176 0 GPIO_INPUT>; + }; /* GPIO140 */ + usbc_tcpc_i2c_data_p0 { + gpios = <&gpio_100_136 26 GPIO_INPUT>; + }; /* GPIO132 */ + usbc_tcpc_i2c_clk_p2 { + gpios = <&gpio_000_036 8 GPIO_INPUT>; + }; /* GPIO010 */ + usbc_tcpc_i2c_data_p2 { + gpios = <&gpio_000_036 7 GPIO_INPUT>; + }; /* GPIO007 */ + usbc_tcpc_i2c_clk_p1 { + gpios = <&gpio_000_036 11 GPIO_INPUT>; + }; /* GPIO013 */ + usbc_tcpc_i2c_data_p1 { + gpios = <&gpio_000_036 10 GPIO_INPUT>; + }; /* GPIO012 */ + usbc_tcpc_i2c_clk_p3 { + gpios = <&gpio_140_176 13 GPIO_INPUT>; + }; /* GPIO155 */ + usbc_tcpc_i2c_data_p3 { + gpios = <&gpio_140_176 12 GPIO_INPUT>; + }; /* GPIO154 */ + sml1_clk_mecc { + gpios = <&gpio_100_136 25 GPIO_INPUT>; + }; /* GPIO131 */ + cpu_cat_err_mecc { + gpios = <&gpio_000_036 0 GPIO_INPUT>; + }; /* GPIO000 */ + espi_alert0_n { + gpios = <&gpio_040_076 19 GPIO_INPUT>; + }; /* GPIO063 NANA */ + batt_disable_ec { + gpios = <&gpio_040_076 23 GPIO_INPUT>; + }; /* GPIO067 */ + cpu_c10_gate_mecc { + gpios = <&gpio_000_036 19 GPIO_INPUT>; + }; /* GPIO023 */ + smc_sdown_mecc { + gpios = <&gpio_240_276 13 GPIO_INPUT>; + }; /* GPIO255 */ + std_adpt_cntrl_gpio { + gpios = <&gpio_240_276 4 GPIO_INPUT>; + }; /* GPIO244 */ + smc_onoff_n { + gpios = <&gpio_100_136 12 GPIO_INPUT>; + }; /* GPIO114 */ + suswarn { + gpios = <&gpio_000_036 20 GPIO_INPUT>; + }; /* GPIO024 */ + me_g3_to_m3_ec { + gpios = <&gpio_000_036 27 GPIO_INPUT>; + }; /* GPIO033 */ + gpio_ec_kso_02_inv: ec-kso-02-inv { + gpios = <&gpio_040_076 6 (GPIO_OUTPUT_LOW + | GPIO_ACTIVE_LOW)>; + }; /* GPIO046 */ + + usb_c0_bb_retimer_rst: usb-c0-bb-retimer-rst { + gpios = <&ioex_c0_port 0 GPIO_OUTPUT_LOW>; + enum-name = "IOEX_USB_C0_BB_RETIMER_RST"; + }; + usb_c0_bb_retimer_ls_en: usb-c0-bb-retimer-ls-en { + gpios = <&ioex_c0_port 1 GPIO_OUTPUT_LOW>; + enum-name = "IOEX_USB_C0_BB_RETIMER_LS_EN"; + }; + usb-c0-usb-mux-cntrl-1 { + gpios = <&ioex_c0_port 4 GPIO_OUTPUT_LOW>; + enum-name = "IOEX_USB_C0_USB_MUX_CNTRL_1"; + }; + usb-c0-usb-mux-cntrl-0 { + gpios = <&ioex_c0_port 5 GPIO_OUTPUT_LOW>; + enum-name = "IOEX_USB_C0_USB_MUX_CNTRL_0"; + }; + usb_c1_bb_retimer_rst: usb-c1-bb-retimer-rst { + gpios = <&ioex_c1_port 0 GPIO_OUTPUT_LOW>; + enum-name = "IOEX_USB_C1_BB_RETIMER_RST"; + }; + usb_c1_bb_retimer_ls_en: usb-c1-bb-retimer-ls-en { + gpios = <&ioex_c1_port 1 GPIO_OUTPUT_LOW>; + enum-name = "IOEX_USB_C1_BB_RETIMER_LS_EN"; + }; + usb-c1-hpd { + gpios = <&ioex_c1_port 2 GPIO_OUTPUT_LOW>; + enum-name = "IOEX_USB_C1_HPD"; + }; + usb-c0-c1-oc { + gpios = <&ioex_c1_port 8 GPIO_OUTPUT_HIGH>; + enum-name = "IOEX_USB_C0_C1_OC"; + }; + usb_c2_bb_retimer_rst: usb-c2-bb-retimer-rst { + gpios = <&ioex_c2_port 0 GPIO_OUTPUT_LOW>; + enum-name = "IOEX_USB_C2_BB_RETIMER_RST"; + }; + usb_c2_bb_retimer_ls_en: usb-c2-bb-retimer-ls-en { + gpios = <&ioex_c2_port 1 GPIO_OUTPUT_LOW>; + enum-name = "IOEX_USB_C2_BB_RETIMER_LS_EN"; + }; + usb-c2-usb-mux-cntrl-1 { + gpios = <&ioex_c2_port 4 GPIO_OUTPUT_LOW>; + }; + usb-c2-usb-mux-cntrl-0 { + gpios = <&ioex_c2_port 5 GPIO_OUTPUT_LOW>; + }; + usb_c3_bb_retimer_rst: usb-c3-bb-retimer-rst { + gpios = <&ioex_c3_port 0 GPIO_OUTPUT_LOW>; + enum-name = "IOEX_USB_C3_BB_RETIMER_RST"; + }; + usb_c3_bb_retimer_ls_en: usb-c3-bb-retimer-ls-en { + gpios = <&ioex_c3_port 1 GPIO_OUTPUT_LOW>; + enum-name = "IOEX_USB_C3_BB_RETIMER_LS_EN"; + }; + usb-c2-c3-oc { + gpios = <&ioex_c3_port 8 GPIO_OUTPUT_HIGH>; + enum-name = "IOEX_USB_C2_C3_OC"; + }; + /* unimplemented GPIOs */ + en-pp5000 { + enum-name = "GPIO_EN_PP5000"; + }; + }; +}; diff --git a/zephyr/projects/intelrvp/adlrvp/adlrvp_mchp/interrupts.dts b/zephyr/projects/intelrvp/adlrvp/adlrvp_mchp/interrupts.dts new file mode 100644 index 0000000000..17986fe2c7 --- /dev/null +++ b/zephyr/projects/intelrvp/adlrvp/adlrvp_mchp/interrupts.dts @@ -0,0 +1,80 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ +/ { + gpio-interrupts { + compatible = "cros-ec,gpio-interrupts"; + + int_lid_open: lid-open { + irq-pin = <&smc_lid>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "lid_interrupt"; + }; + int_power_button: power-button { + irq-pin = <&mech_pwr_btn_odl>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "power_button_interrupt"; + }; + int_ac_present: ac-present { + irq-pin = <&bc_acok>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "extpower_interrupt"; + }; + int_slp_s0: slp-s0 { + irq-pin = <&pch_slp_s0_n>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "power_signal_interrupt"; + }; + int_slp_sus: slp-sus { + irq-pin = <&pm_slp_sus_ec_n>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "power_signal_interrupt"; + }; + int_pg_dsw_pwrok: pg-dsw-pwrok { + irq-pin = <&vccpdsw_3p3>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "power_signal_interrupt"; + }; + int_rsmrst_pwrgd: rsmrst-pwrgd { + irq-pin = <&rsmrst_pwrgd>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "power_signal_interrupt"; + }; + int_all_sys_pwrgd: all-sys-pwrgd { + irq-pin = <&all_sys_pwrgd>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "power_signal_interrupt"; + }; + int_usbc_tcpc_alrt_p0: usbc-tcpc-alrt-p0 { + irq-pin = <&usbc_tcpc_alrt_p0>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "tcpc_alert_event"; + }; + int_usbc_tcpc_alrt_p1: usbc-tcpc-alrt-p1 { + irq-pin = <&usbc_tcpc_alrt_p1>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "tcpc_alert_event"; + }; + int_usbc_tcpc_ppc_alrt_p0: usbc-tcpc-ppc-alrt-p0 { + irq-pin = <&usbc_tcpc_ppc_alrt_p0>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "ppc_interrupt"; + }; + int_usbc_tcpc_ppc_alrt_p1: usbc-tcpc-ppc-alrt-p1 { + irq-pin = <&usbc_tcpc_ppc_alrt_p1>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "ppc_interrupt"; + }; + int_std_adp_prsnt: std-adp-prsnt { + irq-pin = <&std_adp_prsnt>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "board_dc_jack_interrupt"; + }; + int_ccd_mode_odl: ccd-mode-odl { + irq-pin = <&ccd_mode_odl>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "board_connect_c0_sbu"; + }; + }; +}; diff --git a/zephyr/projects/intelrvp/adlrvp/adlrvp_mchp/keyboard.dts b/zephyr/projects/intelrvp/adlrvp/adlrvp_mchp/keyboard.dts new file mode 100644 index 0000000000..b3577e6afd --- /dev/null +++ b/zephyr/projects/intelrvp/adlrvp/adlrvp_mchp/keyboard.dts @@ -0,0 +1,31 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + cros-keyscan { + compatible = "cros-keyscan"; + + output-settle = <80>; + debounce-down = <9000>; + debounce-up = <30000>; + poll-timeout = <100000>; + + actual-key-mask = < + 0x14 /* C0 */ + 0xff /* C1 */ + 0xff /* C2 */ + 0xff /* C3 */ + 0xff /* C4 */ + 0xf5 /* C5 */ + 0xff /* C6 */ + 0xa4 /* C7 */ + 0xff /* C8 */ + 0xfe /* C9 */ + 0x55 /* C10 */ + 0xfa /* C11 */ + 0xca /* C12 */ + >; + }; +}; diff --git a/zephyr/projects/intelrvp/adlrvp/adlrvp_mchp/prj.conf b/zephyr/projects/intelrvp/adlrvp/adlrvp_mchp/prj.conf new file mode 100644 index 0000000000..083530c858 --- /dev/null +++ b/zephyr/projects/intelrvp/adlrvp/adlrvp_mchp/prj.conf @@ -0,0 +1,84 @@ +# Copyright 2022 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +CONFIG_BOARD_ADLRVP_MCHP=y +CONFIG_CROS_FLASH_XEC=y +CONFIG_CROS_SYSTEM_XEC=y +CONFIG_CROS_KB_RAW_XEC=y + +# For MCHP ESPI Drivers +CONFIG_ESPI_PERIPHERAL_EC_HOST_CMD=y +CONFIG_ESPI_PERIPHERAL_ACPI_SHM_REGION=y +CONFIG_ESPI_PERIPHERAL_CUSTOM_OPCODE=y +CONFIG_ESPI_PERIPHERAL_XEC_EMI0=y +CONFIG_ESPI_PERIPHERAL_ACPI_EC_IBF_EVT_DATA=y +CONFIG_ESPI_PERIPHERAL_KBC_OBE_CBK=y +CONFIG_ESPI_PERIPHERAL_KBC_IBF_EVT_DATA=y + +# Invoke SoC Python script to create zephyr.mchp.bin which +# is zephyr.bin processed for Boot-ROM loading. +CONFIG_MCHP_MEC_UNSIGNED_HEADER=y +CONFIG_MCHP_MEC_HEADER_FLASH_SIZE_256K=y + +# Support Zephyr SPI NOR driver to work with MCHP SPI driver +CONFIG_SPI_NOR=y +CONFIG_SPI_XEC_QMSPI_FULL_DUPLEX=y + +# Sensors - MCHP TACH driver under sensor +CONFIG_SENSOR=n +CONFIG_SENSOR_SHELL=n + +# Debug option +# Enable flash console commands +CONFIG_PLATFORM_EC_CONSOLE_CMD_FLASH=y + + +## TODO - support following features next +# Fan +CONFIG_PLATFORM_EC_FAN=n + +# RTC +CONFIG_PLATFORM_EC_RTC=n + +# PWM +CONFIG_PWM=n +CONFIG_PWM_SHELL=n + +## INTEL RVP +# Host command +CONFIG_PLATFORM_EC_HOSTCMD_AP_RESET=n + +# Power Sequencing +CONFIG_PLATFORM_EC_THROTTLE_AP=n + +## ADL RVP +# CBI +CONFIG_EEPROM=n +CONFIG_EEPROM_AT24=n +CONFIG_EEPROM_SHELL=n +CONFIG_PLATFORM_EC_CBI_EEPROM=n + +# LED +CONFIG_PLATFORM_EC_LED_COMMON=n +CONFIG_PLATFORM_EC_LED_PWM=n +CONFIG_PLATFORM_EC_LED_PWM_TASK_DISABLED=n + +# Temperature sensors +CONFIG_PLATFORM_EC_TEMP_SENSOR=n +CONFIG_PLATFORM_EC_THERMISTOR=n +CONFIG_PLATFORM_EC_TEMP_SENSOR_POWER=n + +# Charger +CONFIG_PLATFORM_EC_DEDICATED_CHARGE_PORT=y + +# H1 issues second reset +CONFIG_PLATFORM_EC_BOARD_RESET_AFTER_POWER_ON=n + +# 7-Segment Display +CONFIG_PLATFORM_EC_MAX695X_SEVEN_SEGMENT_DISPLAY=n + +# Debug options +# Enable flash console commands +CONFIG_PLATFORM_EC_CONSOLE_CMD_FLASH=y +CONFIG_WDT_DISABLE_AT_BOOT=y diff --git a/zephyr/projects/intelrvp/adlrvp/adlrvp_mchp/usbc.dts b/zephyr/projects/intelrvp/adlrvp/adlrvp_mchp/usbc.dts new file mode 100644 index 0000000000..471a1f52e9 --- /dev/null +++ b/zephyr/projects/intelrvp/adlrvp/adlrvp_mchp/usbc.dts @@ -0,0 +1,89 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + usbc { + #address-cells = <1>; + #size-cells = <0>; + usbc_port0: port0@0 { + compatible = "named-usbc-port"; + reg = <0>; + tcpc = <&tcpc_port0>; + chg = <&charger>; + usb_mux_chain_0: usb-mux-chain-0 { + compatible = "cros-ec,usb-mux-chain"; + usb-muxes = <&usb_c0_bb_retimer + &virtual_mux_c0>; + }; + usb_mux_alt_chain_0: usb-mux-alt-chain-0 { + compatible = "cros-ec,usb-mux-chain"; + alternative-chain; + usb-muxes = <&usb_c0_bb_retimer + &usb_c0_soc_side_bb_retimer + &virtual_mux_c0>; + }; + }; + port0-muxes { + virtual_mux_c0: virtual-mux-c0 { + compatible = "cros-ec,usbc-mux-virtual"; + }; + }; + + usbc_port1: port1@1 { + compatible = "named-usbc-port"; + reg = <1>; + tcpc = <&tcpc_port1>; + usb_mux_chain_1: usb-mux-chain-1 { + compatible = "cros-ec,usb-mux-chain"; + usb-muxes = <&usb_c1_bb_retimer + &virtual_mux_c1>; + }; + usb_mux_alt_chain_1: usb-mux-alt-chain-1 { + compatible = "cros-ec,usb-mux-chain"; + alternative-chain; + usb-muxes = <&usb_c1_bb_retimer + &usb_c1_soc_side_bb_retimer + &virtual_mux_c1>; + }; + }; + port1-muxes { + virtual_mux_c1: virtual-mux-c1 { + compatible = "cros-ec,usbc-mux-virtual"; + }; + }; + + port2@2 { + compatible = "named-usbc-port"; + reg = <2>; + tcpc = <&tcpc_port2>; + usb_mux_chain_2: usb-mux-chain-2 { + compatible = "cros-ec,usb-mux-chain"; + usb-muxes = <&usb_c2_bb_retimer + &virtual_mux_c2>; + }; + }; + port2-muxes { + virtual_mux_c2: virtual-mux-c2 { + compatible = "cros-ec,usbc-mux-virtual"; + }; + }; + + port3@3 { + compatible = "named-usbc-port"; + reg = <3>; + tcpc = <&tcpc_port3>; + usb_mux_chain_3: usb-mux-chain-3 { + compatible = "cros-ec,usb-mux-chain"; + usb-muxes = <&usb_c3_bb_retimer + &virtual_mux_c3>; + }; + }; + port3-muxes { + virtual_mux_c3: virtual-mux-c3 { + compatible = "cros-ec,usbc-mux-virtual"; + }; + }; + }; +}; diff --git a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/adlrvp_npcx.dts b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/adlrvp_npcx.dts new file mode 100644 index 0000000000..79723beabd --- /dev/null +++ b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/adlrvp_npcx.dts @@ -0,0 +1,258 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + chosen { + cros,rtc = &mtc; + }; + + hibernate-wake-pins { + compatible = "cros-ec,hibernate-wake-pins"; + wakeup-irqs = < + &int_ac_present + &int_lid_open + &int_power_button + >; + }; + + named-i2c-ports { + compatible = "named-i2c-ports"; + + i2c_charger: charger { + i2c-port = <&i2c7_0>; + enum-names = "I2C_PORT_BATTERY", + "I2C_PORT_CHARGER", + "I2C_PORT_EEPROM", + "I2C_PORT_PORT80"; + }; + typec_0: typec-0 { + i2c-port = <&i2c0_0>; + enum-names = "I2C_PORT_TYPEC_0"; + }; + typec_1: typec-1 { + i2c-port = <&i2c2_0>; + enum-names = "I2C_PORT_TYPEC_1"; + }; + typec_2: typec-2 { + i2c-port = <&i2c1_0>; + enum-names = "I2C_PORT_TYPEC_2"; + }; + typec_3: typec-3 { + i2c-port = <&i2c3_0>; + enum-names = "I2C_PORT_TYPEC_3"; + }; + }; + + named-adc-channels { + compatible = "named-adc-channels"; + + adc_ambient: ambient { + enum-name = "ADC_TEMP_SENSOR_1"; + io-channels = <&adc0 3>; + }; + adc_ddr: ddr { + enum-name = "ADC_TEMP_SENSOR_2"; + io-channels = <&adc0 4>; + }; + adc_skin: skin { + enum-name = "ADC_TEMP_SENSOR_3"; + io-channels = <&adc0 2>; + }; + adc_vr: vr { + enum-name = "ADC_TEMP_SENSOR_4"; + io-channels = <&adc0 1>; + }; + }; + +}; + +/* host interface */ +&espi0 { + status = "okay"; + pinctrl-0 = <&espi_lpc_gp46_47_51_52_53_54_55_57>; + pinctrl-names = "default"; +}; + +/* charger */ +&i2c7_0 { + status = "okay"; + clock-frequency = <I2C_BITRATE_STANDARD>; + pinctrl-0 = <&i2c7_0_sda_scl_gpb2_b3>; + pinctrl-names = "default"; + + pca95xx: pca95xx@22 { + compatible = "nxp,pca95xx"; + label = "PCA95XX"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + }; + + rvp_board_id: rvp-board-id { + compatible = "intel,rvp-board-id"; + + /* + * BOM ID [2] : IOEX[0] + * BOM ID [1:0] : IOEX[15:14] + */ + bom-gpios = <&pca95xx 0 0>, <&pca95xx 15 0>, <&pca95xx 14 0>; + + /* + * FAB ID [1:0] : IOEX[2:1] + */ + fab-gpios = <&pca95xx 2 0>, <&pca95xx 1 0>; + + /* + * BOARD ID[5:0] : IOEX[13:8] + */ + board-gpios = <&pca95xx 13 0>, <&pca95xx 12 0>, <&pca95xx 11 0>, + <&pca95xx 10 0>, <&pca95xx 9 0>, <&pca95xx 8 0>; + }; + + seven_seg_display: max695x-seven-seg-display@38 { + compatible = "maxim,seven-seg-display"; + reg = <0x38>; + label = "MAX695X_SEVEN_SEG_DISPLAY"; + }; + + charger: isl9241@9 { + compatible = "intersil,isl9241"; + status = "okay"; + reg = <0x9>; + }; + + cbi_eeprom: eeprom@50 { + compatible = "atmel,at24"; + reg = <0x50>; + size = <2048>; + pagesize = <16>; + address-width = <8>; + timeout = <5>; + }; +}; + +&i2c_ctrl7 { + status = "okay"; +}; + +/* typec_0 */ +&i2c0_0 { + status = "okay"; + clock-frequency = <I2C_BITRATE_FAST>; + pinctrl-0 = <&i2c0_0_sda_scl_gpb4_b5>; + pinctrl-names = "default"; + + tcpc_port0: fusb302@22 { + compatible = "fairchild,fusb302"; + reg = <0x22>; + }; + + usb_c0_soc_side_bb_retimer: jhl8040r-c0-soc-side@54 { + compatible = "intel,jhl8040r"; + reg = <0x54>; + reset-pin = <&usb_c0_bb_retimer_rst>; + ls-en-pin = <&usb_c0_bb_retimer_ls_en>; + }; + + usb_c0_bb_retimer: jhl8040r-c0@56 { + compatible = "intel,jhl8040r"; + reg = <0x56>; + reset-pin = <&usb_c0_bb_retimer_rst>; + ls-en-pin = <&usb_c0_bb_retimer_ls_en>; + }; +}; + +&i2c_ctrl0 { + status = "okay"; +}; + +/* typec_1 */ +&i2c2_0 { + status = "okay"; + clock-frequency = <I2C_BITRATE_FAST>; + pinctrl-0 = <&i2c2_0_sda_scl_gp91_92>; + pinctrl-names = "default"; + + tcpc_port1: fusb302@22 { + compatible = "fairchild,fusb302"; + reg = <0x22>; + }; + + usb_c1_soc_side_bb_retimer: jhl8040r-c1-soc-side@55 { + compatible = "intel,jhl8040r"; + reg = <0x55>; + reset-pin = <&usb_c1_bb_retimer_rst>; + ls-en-pin = <&usb_c1_bb_retimer_ls_en>; + }; + + usb_c1_bb_retimer: jhl8040r-c1@57 { + compatible = "intel,jhl8040r"; + reg = <0x57>; + reset-pin = <&usb_c1_bb_retimer_rst>; + ls-en-pin = <&usb_c1_bb_retimer_ls_en>; + }; +}; + +&i2c_ctrl2 { + status = "okay"; +}; + +/* typec_2 */ +&i2c1_0 { + status = "okay"; + clock-frequency = <I2C_BITRATE_FAST>; + pinctrl-0 = <&i2c1_0_sda_scl_gp87_90>; + pinctrl-names = "default"; + + tcpc_port2: fusb302@22 { + compatible = "fairchild,fusb302"; + reg = <0x22>; + }; + + usb_c2_bb_retimer: jhl8040r-c2@58 { + compatible = "intel,jhl8040r"; + reg = <0x58>; + reset-pin = <&usb_c2_bb_retimer_rst>; + ls-en-pin = <&usb_c2_bb_retimer_ls_en>; + }; +}; + +&i2c_ctrl1 { + status = "okay"; +}; + +/* typec_3 */ +&i2c3_0 { + status = "okay"; + clock-frequency = <I2C_BITRATE_FAST>; + pinctrl-0 = <&i2c3_0_sda_scl_gpd0_d1>; + pinctrl-names = "default"; + + tcpc_port3: fusb302@22 { + compatible = "fairchild,fusb302"; + reg = <0x22>; + }; + + usb_c3_bb_retimer: jhl8040r-c3@59 { + compatible = "intel,jhl8040r"; + reg = <0x59>; + reset-pin = <&usb_c3_bb_retimer_rst>; + ls-en-pin = <&usb_c3_bb_retimer_ls_en>; + }; +}; + +&i2c_ctrl3 { + status = "okay"; +}; + +&adc0 { + status = "okay"; + pinctrl-0 = <&adc0_chan1_gp44 + &adc0_chan2_gp43 + &adc0_chan3_gp42 + &adc0_chan4_gp41>; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/fan.dts b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/fan.dts new file mode 100644 index 0000000000..8babe53903 --- /dev/null +++ b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/fan.dts @@ -0,0 +1,36 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + fans { + compatible = "cros-ec,fans"; + + fan_0 { + pwms = <&pwm3 0 PWM_KHZ(30) PWM_POLARITY_NORMAL>; + rpm_min = <3000>; + rpm_start = <3000>; + rpm_max = <10000>; + tach = <&tach2>; + pgood_gpio = <&all_sys_pwrgd>; + enable_gpio = <&gpio_fan_control>; + }; + }; +}; + +/* Tachemeter for fan speed measurement */ +&tach2 { + status = "okay"; + pinctrl-0 = <&ta2_2_in_gpa6>; + pinctrl-names = "default"; + port = <NPCX_TACH_PORT_A>; /* port-A is selected */ + sample-clk = <NPCX_TACH_FREQ_LFCLK>; /* Use LFCLK as sampling clock */ + pulses-per-round = <2>; /* number of pulses per round of encoder */ +}; + +&pwm3 { + status = "okay"; + pinctrl-0 = <&pwm3_gp80>; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/gpio.dts b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/gpio.dts new file mode 100644 index 0000000000..1d38fc877c --- /dev/null +++ b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/gpio.dts @@ -0,0 +1,344 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + aliases { + gpio-wp = &gpio_wp; + gpio-kbd-kso2 = &gpio_ec_kso_02_inv; + }; + + named-gpios { + compatible = "named-gpios"; + + all_sys_pwrgd: all-sys-pwrgd { + gpios = <&gpio7 0 GPIO_INPUT>; + enum-name = "GPIO_PG_EC_ALL_SYS_PWRGD"; + }; + rsmrst_pwrgd: rsmrst-pwrgd { + gpios = <&gpio3 7 GPIO_INPUT>; + enum-name = "GPIO_PG_EC_RSMRST_ODL"; + }; + pch_slp_s0_n: pch-slp-s0-n { + gpios = <&gpioa 1 GPIO_INPUT>; + enum-name = "GPIO_PCH_SLP_S0_L"; + }; + vccpdsw_3p3: vccpdsw-3p3 { + gpios = <&gpio4 5 GPIO_INPUT>; + enum-name = "GPIO_PG_EC_DSW_PWROK"; + }; + pm_slp_sus_ec_n: pm-slp-sus-ec-n { + gpios = <&gpio8 6 GPIO_INPUT>; + enum-name = "GPIO_SLP_SUS_L"; + }; + pm-slp-s3-n { + gpios = <&gpiob 0 GPIO_INPUT>; + enum-name = "GPIO_PCH_SLP_S3_L"; + }; + pm-slp-s4-n { + gpios = <&gpioa 5 GPIO_INPUT>; + }; + volume-up { + gpios = <&gpio6 1 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_VOLUME_UP_L"; + }; + vol-dn-ec { + gpios = <&gpio0 3 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_VOLUME_DOWN_L"; + }; + smc_lid: smc-lid { + gpios = <&gpio0 1 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_LID_OPEN"; + }; + mech_pwr_btn_odl: mech-pwr-btn-odl { + gpios = <&gpio0 0 GPIO_INPUT>; + enum-name = "GPIO_POWER_BUTTON_L"; + }; + std_adp_prsnt: std-adp-prsnt { + gpios = <&gpio0 2 GPIO_INPUT>; + enum-name= "GPIO_DC_JACK_PRESENT"; + }; + bc_acok: bc-acok { + gpios = <&gpioc 6 GPIO_INPUT>; + enum-name = "GPIO_AC_PRESENT"; + }; + usbc_tcpc_alrt_p0: usbc-tcpc-alrt-p0 { + gpios = <&gpio4 0 GPIO_INPUT>; + }; + usbc_tcpc_alrt_p1: usbc-tcpc-alrt-p1 { + gpios = <&gpio6 2 GPIO_INPUT>; + }; + usbc_tcpc_alrt_p2: usbc-tcpc-alrt-p2 { + gpios = <&gpio6 3 GPIO_INPUT>; + }; + usbc_tcpc_alrt_p3: usbc-tcpc-alrt-p3 { + gpios = <&gpio6 7 GPIO_INPUT>; + }; + usbc_tcpc_ppc_alrt_p0: usbc-tcpc-ppc-alrt-p0 { + gpios = <&gpiof 0 GPIO_INPUT>; + }; + usbc_tcpc_ppc_alrt_p1: usbc-tcpc-ppc-alrt-p1 { + gpios = <&gpiof 1 GPIO_INPUT>; + }; + usbc_tcpc_ppc_alrt_p2: usbc-tcpc-ppc-alrt-p2 { + gpios = <&gpiof 2 GPIO_INPUT>; + }; + usbc_tcpc_ppc_alrt_p3: usbc-tcpc-ppc-alrt-p3 { + gpios = <&gpiof 3 GPIO_INPUT>; + }; + gpio_ec_pch_wake_odl: smc-wake-sci-n-mecc { + gpios = <&gpioa 4 GPIO_ODR_HIGH>; + }; + ec-pch-mkbp-int-odl { + gpios = <&gpiof 5 GPIO_ODR_HIGH>; + }; + lpc-espi-rst-n { + gpios = <&gpio5 4 GPIO_INPUT>; + }; + plt-rst-l { + gpios = <&gpioa 2 GPIO_INPUT>; + }; + slate-mode-indication { + gpios = <&gpioe 5 GPIO_INPUT>; + }; + prochot-ec-n { + gpios = <&gpioa 7 GPIO_INPUT>; + enum-name = "GPIO_CPU_PROCHOT"; + }; + sys-rst-odl { + gpios = <&gpioc 5 GPIO_ODR_HIGH>; + enum-name = "GPIO_SYS_RESET_L"; + }; + pm-rsmrst-n { + gpios = <&gpiod 3 GPIO_OUTPUT_LOW>; + enum-name = "GPIO_PCH_RSMRST_L"; + }; + pm-pwrbtn-n { + gpios = <&gpio9 7 GPIO_ODR_HIGH>; + enum-name = "GPIO_PCH_PWRBTN_L"; + }; + ec_spi_oe_mecc: ec-spi-oe-mecc { + gpios = <&gpio6 0 GPIO_OUTPUT_LOW>; + }; + ec-ds3 { + gpios = <&gpioc 4 GPIO_OUTPUT_LOW>; + enum-name = "GPIO_EN_PP3300_A"; + alias = "GPIO_TEMP_SENSOR_POWER"; + }; + pch-pwrok-ec { + gpios = <&gpioa 0 GPIO_INPUT>; + enum-name = "GPIO_PCH_PWROK"; + }; + sys-pwrok { + gpios = <&gpio9 3 GPIO_OUTPUT_LOW>; + enum-name = "GPIO_PCH_SYS_PWROK"; + }; + ec-dsw-pwrok { + gpios = <&gpio9 5 GPIO_OUTPUT_LOW>; + enum-name = "GPIO_PCH_DSW_PWROK"; + }; + gpio_wp: ec-flash-wp-odl { + gpios = <&gpio9 4 (GPIO_INPUT | GPIO_ACTIVE_LOW)>; + }; + ec-h1-packet-mode { + gpios = <&gpioe 2 GPIO_OUTPUT_LOW>; + enum-name = "GPIO_PACKET_MODE_EN"; + }; + ec-entering-rw { + gpios = <&gpiod 4 GPIO_OUTPUT_LOW>; + enum-name = "GPIO_ENTERING_RW"; + }; + ccd_mode_odl: ccd-mode-odl { + gpios = <&gpiof 4 GPIO_INPUT>; + enum-name = "GPIO_CCD_MODE_ODL"; + }; + bat-det { + gpios = <&gpio7 6 GPIO_INPUT>; + enum-name = "GPIO_BATT_PRES_ODL"; + }; + edp-bklt-en-mecc { + gpios = <&gpioe 1 GPIO_OUTPUT_HIGH>; + }; + led_red_l: led-1-l { + gpios = <&gpiob 6 GPIO_OUTPUT_HIGH>; + }; + led_white_l: led-2-l { + gpios = <&gpiob 7 GPIO_OUTPUT_HIGH>; + }; + gpio_fan_control: therm-sen-mecc { + gpios = <&gpioc 0 GPIO_OUTPUT_LOW>; + }; + smb-bs-clk { + gpios = <&gpiob 3 GPIO_INPUT>; + }; + smb-bs-data { + gpios = <&gpiob 2 GPIO_INPUT>; + }; + usbc-tcpc-i2c-clk-p0 { + gpios = <&gpiob 5 GPIO_INPUT>; + }; + usbc-tcpc-i2c-data-p0 { + gpios = <&gpiob 4 GPIO_INPUT>; + }; + usbc-tcpc-i2c-clk-p2 { + gpios = <&gpio9 2 GPIO_INPUT>; + }; + usbc-tcpc-i2c-data-p2 { + gpios = <&gpio9 1 GPIO_INPUT>; + }; + usbc-tcpc-i2c-clk-p1 { + gpios = <&gpio9 0 GPIO_INPUT>; + }; + usbc-tcpc-i2c-data-p1 { + gpios = <&gpio8 7 GPIO_INPUT>; + }; + usbc-tcpc-i2c-clk-p3 { + gpios = <&gpiod 1 GPIO_INPUT>; + }; + usbc-tcpc-i2c-data-p3 { + gpios = <&gpiod 0 GPIO_INPUT>; + }; + sml1-clk-mecc { + gpios = <&gpio3 3 GPIO_INPUT>; + }; + sml1-data-mecc { + gpios = <&gpio3 6 GPIO_INPUT>; + }; + smb-pch-clk { + gpios = <&gpioc 2 GPIO_INPUT>; + }; + smb-pch-data { + gpios = <&gpioc 1 GPIO_INPUT>; + }; + i3c-0-scl { + gpios = <&gpioe 4 GPIO_INPUT>; + }; + i3c-0-sda { + gpios = <&gpioe 3 GPIO_INPUT>; + }; + cpu-cat-err-mecc { + gpios = <&gpio3 4 GPIO_INPUT>; + }; + tp29 { + gpios = <&gpio5 0 GPIO_INPUT>; + }; + tp28 { + gpios = <&gpio5 6 GPIO_INPUT>; + }; + espi-alert0-n { + gpios = <&gpio5 7 GPIO_INPUT>; + }; + batt-disable-ec { + gpios = <&gpio6 6 GPIO_INPUT>; + }; + tp33 { + gpios = <&gpio7 2 GPIO_INPUT>; + }; + tp26 { + gpios = <&gpio7 3 GPIO_INPUT>; + }; + slp-s0-cs-n { + gpios = <&gpio7 4 GPIO_INPUT>; + }; + ec-peci { + gpios = <&gpio8 1 GPIO_INPUT>; + }; + cpu-c10-gate-mecc { + gpios = <&gpio9 6 GPIO_INPUT>; + }; + smb-pch-alrt { + gpios = <&gpioa 3 GPIO_INPUT>; + }; + smc-sdown-mecc { + gpios = <&gpiob 1 GPIO_INPUT>; + }; + std-adpt-cntrl-gpio { + gpios = <&gpioc 3 GPIO_INPUT>; + }; + sml1-alert { + gpios = <&gpioc 7 GPIO_INPUT>; + }; + smc-onoff-n { + gpios = <&gpiod 2 GPIO_INPUT>; + }; + suswarn { + gpios = <&gpiod 5 GPIO_INPUT>; + }; + tp-gpiod6-ec { + gpios = <&gpiod 6 GPIO_INPUT>; + }; + tp-gpiod7-ec { + gpios = <&gpiod 7 GPIO_INPUT>; + }; + me-g3-to-m3-ec { + gpios = <&gpioe 0 GPIO_INPUT>; + }; + gpio_ec_kso_02_inv: ec-kso-02-inv { + gpios = <&gpio1 7 (GPIO_OUTPUT_LOW | GPIO_ACTIVE_LOW)>; + }; + + usb_c0_bb_retimer_rst: usb-c0-bb-retimer-rst { + gpios = <&ioex_c0_port 0 GPIO_OUTPUT_LOW>; + enum-name = "IOEX_USB_C0_BB_RETIMER_RST"; + }; + usb_c0_bb_retimer_ls_en: usb-c0-bb-retimer-ls-en { + gpios = <&ioex_c0_port 1 GPIO_OUTPUT_LOW>; + enum-name = "IOEX_USB_C0_BB_RETIMER_LS_EN"; + }; + usb-c0-usb-mux-cntrl-1 { + gpios = <&ioex_c0_port 4 GPIO_OUTPUT_LOW>; + enum-name = "IOEX_USB_C0_USB_MUX_CNTRL_1"; + }; + usb-c0-usb-mux-cntrl-0 { + gpios = <&ioex_c0_port 5 GPIO_OUTPUT_LOW>; + enum-name = "IOEX_USB_C0_USB_MUX_CNTRL_0"; + }; + usb_c1_bb_retimer_rst: usb-c1-bb-retimer-rst { + gpios = <&ioex_c1_port 0 GPIO_OUTPUT_LOW>; + enum-name = "IOEX_USB_C1_BB_RETIMER_RST"; + }; + usb_c1_bb_retimer_ls_en: usb-c1-bb-retimer-ls-en { + gpios = <&ioex_c1_port 1 GPIO_OUTPUT_LOW>; + enum-name = "IOEX_USB_C1_BB_RETIMER_LS_EN"; + }; + usb-c1-hpd { + gpios = <&ioex_c1_port 2 GPIO_OUTPUT_LOW>; + enum-name = "IOEX_USB_C1_HPD"; + }; + usb-c0-c1-oc { + gpios = <&ioex_c1_port 8 GPIO_OUTPUT_HIGH>; + enum-name = "IOEX_USB_C0_C1_OC"; + }; + usb_c2_bb_retimer_rst: usb-c2-bb-retimer-rst { + gpios = <&ioex_c2_port 0 GPIO_OUTPUT_LOW>; + enum-name = "IOEX_USB_C2_BB_RETIMER_RST"; + }; + usb_c2_bb_retimer_ls_en: usb-c2-bb-retimer-ls-en { + gpios = <&ioex_c2_port 1 GPIO_OUTPUT_LOW>; + enum-name = "IOEX_USB_C2_BB_RETIMER_LS_EN"; + }; + usb-c2-usb-mux-cntrl-1 { + gpios = <&ioex_c2_port 4 GPIO_OUTPUT_LOW>; + }; + usb-c2-usb-mux-cntrl-0 { + gpios = <&ioex_c2_port 5 GPIO_OUTPUT_LOW>; + }; + usb_c3_bb_retimer_rst: usb-c3-bb-retimer-rst { + gpios = <&ioex_c3_port 0 GPIO_OUTPUT_LOW>; + enum-name = "IOEX_USB_C3_BB_RETIMER_RST"; + }; + usb_c3_bb_retimer_ls_en: usb-c3-bb-retimer-ls-en { + gpios = <&ioex_c3_port 1 GPIO_OUTPUT_LOW>; + enum-name = "IOEX_USB_C3_BB_RETIMER_LS_EN"; + }; + usb-c2-c3-oc { + gpios = <&ioex_c3_port 8 GPIO_OUTPUT_HIGH>; + enum-name = "IOEX_USB_C2_C3_OC"; + }; + /* unimplemented GPIOs */ + en-pp5000 { + enum-name = "GPIO_EN_PP5000"; + }; + }; +}; diff --git a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/interrupts.dts b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/interrupts.dts new file mode 100644 index 0000000000..d7bb40fad2 --- /dev/null +++ b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/interrupts.dts @@ -0,0 +1,100 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ +/ { + gpio-interrupts { + compatible = "cros-ec,gpio-interrupts"; + + int_lid_open: lid-open { + irq-pin = <&smc_lid>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "lid_interrupt"; + }; + int_power_button: power-button { + irq-pin = <&mech_pwr_btn_odl>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "power_button_interrupt"; + }; + int_ac_present: ac-present { + irq-pin = <&bc_acok>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "extpower_interrupt"; + }; + int_slp_s0: slp-s0 { + irq-pin = <&pch_slp_s0_n>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "power_signal_interrupt"; + }; + int_slp_sus: slp-sus { + irq-pin = <&pm_slp_sus_ec_n>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "power_signal_interrupt"; + }; + int_pg_dsw_pwrok: pg-dsw-pwrok { + irq-pin = <&vccpdsw_3p3>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "power_signal_interrupt"; + }; + int_rsmrst_pwrgd: rsmrst-pwrgd { + irq-pin = <&rsmrst_pwrgd>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "power_signal_interrupt"; + }; + int_all_sys_pwrgd: all-sys-pwrgd { + irq-pin = <&all_sys_pwrgd>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "power_signal_interrupt"; + }; + int_usbc_tcpc_alrt_p0: usbc-tcpc-alrt-p0 { + irq-pin = <&usbc_tcpc_alrt_p0>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "tcpc_alert_event"; + }; + int_usbc_tcpc_alrt_p1: usbc-tcpc-alrt-p1 { + irq-pin = <&usbc_tcpc_alrt_p1>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "tcpc_alert_event"; + }; + int_usbc_tcpc_alrt_p2: usbc-tcpc-alrt-p2 { + irq-pin = <&usbc_tcpc_alrt_p2>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "tcpc_alert_event"; + }; + int_usbc_tcpc_alrt_p3: usbc-tcpc-alrt-p3 { + irq-pin = <&usbc_tcpc_alrt_p3>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "tcpc_alert_event"; + }; + int_usbc_tcpc_ppc_alrt_p0: usbc-tcpc-ppc-alrt-p0 { + irq-pin = <&usbc_tcpc_ppc_alrt_p0>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "ppc_interrupt"; + }; + int_usbc_tcpc_ppc_alrt_p1: usbc-tcpc-ppc-alrt-p1 { + irq-pin = <&usbc_tcpc_ppc_alrt_p1>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "ppc_interrupt"; + }; + int_usbc_tcpc_ppc_alrt_p2: usbc-tcpc-ppc-alrt-p2 { + irq-pin = <&usbc_tcpc_ppc_alrt_p2>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "ppc_interrupt"; + }; + int_usbc_tcpc_ppc_alrt_p3: usbc-tcpc-ppc-alrt-p3 { + irq-pin = <&usbc_tcpc_ppc_alrt_p3>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "ppc_interrupt"; + }; + int_std_adp_prsnt: std-adp-prsnt { + irq-pin = <&std_adp_prsnt>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "board_dc_jack_interrupt"; + }; + int_ccd_mode_odl: ccd-mode-odl { + irq-pin = <&ccd_mode_odl>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "board_connect_c0_sbu"; + }; + }; +}; diff --git a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/keyboard.dts b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/keyboard.dts new file mode 100644 index 0000000000..81d6e82f48 --- /dev/null +++ b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/keyboard.dts @@ -0,0 +1,59 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + cros-keyscan { + compatible = "cros-keyscan"; + + output-settle = <35>; + debounce-down = <5000>; + debounce-up = <40000>; + poll-timeout = <100000>; + + actual-key-mask = < + 0x14 /* C0 */ + 0xff /* C1 */ + 0xff /* C2 */ + 0xff /* C3 */ + 0xff /* C4 */ + 0xf5 /* C5 */ + 0xff /* C6 */ + 0xa4 /* C7 */ + 0xff /* C8 */ + 0xfe /* C9 */ + 0x55 /* C10 */ + 0xfa /* C11 */ + 0xca /* C12 */ + >; + }; +}; + +&cros_kb_raw { + status = "okay"; + /* No KSO2 (it's inverted and implemented by GPIO) */ + pinctrl-0 = < + &ksi0_gp31 + &ksi1_gp30 + &ksi2_gp27 + &ksi3_gp26 + &ksi4_gp25 + &ksi5_gp24 + &ksi6_gp23 + &ksi7_gp22 + &kso00_gp21 + &kso01_gp20 + &kso03_gp16 + &kso04_gp15 + &kso05_gp14 + &kso06_gp13 + &kso07_gp12 + &kso08_gp11 + &kso09_gp10 + &kso10_gp07 + &kso11_gp06 + &kso12_gp05 + >; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/prj.conf b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/prj.conf new file mode 100644 index 0000000000..2c98fd9330 --- /dev/null +++ b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/prj.conf @@ -0,0 +1,24 @@ +# Copyright 2022 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +CONFIG_BOARD_ADLRVP_NPCX=y +CONFIG_CROS_FLASH_NPCX=y +CONFIG_CROS_SYSTEM_NPCX=y +CONFIG_SYSCON=y + +# Charger +CONFIG_PLATFORM_EC_DEDICATED_CHARGE_PORT=y + +# FAN +CONFIG_TACH_NPCX=y + +# Keyboard +CONFIG_CROS_KB_RAW_NPCX=y + +# PWM +CONFIG_PWM=y +CONFIG_PWM_SHELL=n + +# RTC +CONFIG_PLATFORM_EC_RTC=y diff --git a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/pwm_leds.dts b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/pwm_leds.dts new file mode 100644 index 0000000000..eb1576dbff --- /dev/null +++ b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/pwm_leds.dts @@ -0,0 +1,57 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + pwmleds { + compatible = "pwm-leds"; + pwm_led0: pwm_led_0 { + pwms = <&pwm4 0 PWM_HZ(4800) PWM_POLARITY_INVERTED>; + }; + pwm_led1: pwm_led_1 { + pwms = <&pwm5 0 PWM_HZ(4800) PWM_POLARITY_INVERTED>; + }; + }; + + cros-pwmleds { + compatible = "cros-ec,pwm-leds"; + + leds = <&pwm_led0 &pwm_led1>; + + color-map-green = <100>; + + /* brightness-range = <red green blue yellow white amber> */ + brightness-range = <0 100 0 0 0 0>; + + + #address-cells = <1>; + #size-cells = <0>; + + pwm_led_0@0 { + reg = <0>; + ec-led-name = "EC_LED_ID_BATTERY_LED"; + }; + + pwm_led_1@1 { + reg = <1>; + ec-led-name = "EC_LED_ID_POWER_LED"; + }; + }; +}; + +/* LED1 */ +&pwm4 { + status = "okay"; + clock-bus = "NPCX_CLOCK_BUS_LFCLK"; + pinctrl-0 = <&pwm4_gpb6>; + pinctrl-names = "default"; +}; + +/* LED2 */ +&pwm5 { + status = "okay"; + clock-bus = "NPCX_CLOCK_BUS_LFCLK"; + pinctrl-0 = <&pwm5_gpb7>; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/temp_sensor.dts b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/temp_sensor.dts new file mode 100644 index 0000000000..93ecaa02f6 --- /dev/null +++ b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/temp_sensor.dts @@ -0,0 +1,89 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <cros/thermistor/thermistor.dtsi> + +/ { + temp_ambient: ambient { + compatible = "cros-ec,temp-sensor-thermistor"; + thermistor = <&thermistor_3V0_22K6_47K_4050B>; + adc = <&adc_ambient>; + }; + temp_ddr: ddr { + compatible = "cros-ec,temp-sensor-thermistor"; + thermistor = <&thermistor_3V0_22K6_47K_4050B>; + adc = <&adc_ddr>; + }; + temp_skin: skin { + compatible = "cros-ec,temp-sensor-thermistor"; + thermistor = <&thermistor_3V0_22K6_47K_4050B>; + adc = <&adc_skin>; + }; + temp_vr: vr { + compatible = "cros-ec,temp-sensor-thermistor"; + thermistor = <&thermistor_3V0_22K6_47K_4050B>; + adc = <&adc_vr>; + }; + + named-temp-sensors { + compatible = "cros-ec,temp-sensors"; + ambient { + temp_fan_off = <15>; + temp_fan_max = <50>; + temp_host_high = <75>; + temp_host_halt = <80>; + temp_host_release_high = <65>; + sensor = <&temp_ambient>; + }; + + /* + * TDB: battery temp read api is not using thermistor and + * zephyr shim layer doesn't support to configure custom read + * function. + * + * battery { + * compatible = "cros-ec,temp-sensor-thermistor", + * "cros-ec,temp-sensor"; + * thermistor = < >; + * enum-name = ""; + * temp_fan_off = <15>; + * temp_fan_max = <50>; + * temp_host_high = <75>; + * temp_host_halt = <80>; + * temp_host_release_high = <65>; + * adc = <&adc_battery>; + * }; + */ + + ddr { + temp_fan_off = <15>; + temp_fan_max = <50>; + temp_host_high = <75>; + temp_host_halt = <80>; + temp_host_release_high = <65>; + sensor = <&temp_ddr>; + }; + skin { + temp_fan_off = <15>; + temp_fan_max = <50>; + temp_host_high = <75>; + temp_host_halt = <80>; + temp_host_release_high = <65>; + sensor = <&temp_skin>; + }; + vr { + temp_fan_off = <15>; + temp_fan_max = <50>; + temp_host_high = <75>; + temp_host_halt = <80>; + temp_host_release_high = <65>; + sensor = <&temp_vr>; + }; + }; +}; + +&thermistor_3V0_22K6_47K_4050B { + status = "okay"; +}; diff --git a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/usbc.dts b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/usbc.dts new file mode 100644 index 0000000000..471a1f52e9 --- /dev/null +++ b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/usbc.dts @@ -0,0 +1,89 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + usbc { + #address-cells = <1>; + #size-cells = <0>; + usbc_port0: port0@0 { + compatible = "named-usbc-port"; + reg = <0>; + tcpc = <&tcpc_port0>; + chg = <&charger>; + usb_mux_chain_0: usb-mux-chain-0 { + compatible = "cros-ec,usb-mux-chain"; + usb-muxes = <&usb_c0_bb_retimer + &virtual_mux_c0>; + }; + usb_mux_alt_chain_0: usb-mux-alt-chain-0 { + compatible = "cros-ec,usb-mux-chain"; + alternative-chain; + usb-muxes = <&usb_c0_bb_retimer + &usb_c0_soc_side_bb_retimer + &virtual_mux_c0>; + }; + }; + port0-muxes { + virtual_mux_c0: virtual-mux-c0 { + compatible = "cros-ec,usbc-mux-virtual"; + }; + }; + + usbc_port1: port1@1 { + compatible = "named-usbc-port"; + reg = <1>; + tcpc = <&tcpc_port1>; + usb_mux_chain_1: usb-mux-chain-1 { + compatible = "cros-ec,usb-mux-chain"; + usb-muxes = <&usb_c1_bb_retimer + &virtual_mux_c1>; + }; + usb_mux_alt_chain_1: usb-mux-alt-chain-1 { + compatible = "cros-ec,usb-mux-chain"; + alternative-chain; + usb-muxes = <&usb_c1_bb_retimer + &usb_c1_soc_side_bb_retimer + &virtual_mux_c1>; + }; + }; + port1-muxes { + virtual_mux_c1: virtual-mux-c1 { + compatible = "cros-ec,usbc-mux-virtual"; + }; + }; + + port2@2 { + compatible = "named-usbc-port"; + reg = <2>; + tcpc = <&tcpc_port2>; + usb_mux_chain_2: usb-mux-chain-2 { + compatible = "cros-ec,usb-mux-chain"; + usb-muxes = <&usb_c2_bb_retimer + &virtual_mux_c2>; + }; + }; + port2-muxes { + virtual_mux_c2: virtual-mux-c2 { + compatible = "cros-ec,usbc-mux-virtual"; + }; + }; + + port3@3 { + compatible = "named-usbc-port"; + reg = <3>; + tcpc = <&tcpc_port3>; + usb_mux_chain_3: usb-mux-chain-3 { + compatible = "cros-ec,usb-mux-chain"; + usb-muxes = <&usb_c3_bb_retimer + &virtual_mux_c3>; + }; + }; + port3-muxes { + virtual_mux_c3: virtual-mux-c3 { + compatible = "cros-ec,usbc-mux-virtual"; + }; + }; + }; +}; diff --git a/zephyr/projects/intelrvp/adlrvp/battery.dts b/zephyr/projects/intelrvp/adlrvp/battery.dts new file mode 100644 index 0000000000..1de4111791 --- /dev/null +++ b/zephyr/projects/intelrvp/adlrvp/battery.dts @@ -0,0 +1,20 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + aliases { + getac-3s = &default_battery; + getac-2s = &getac_smp_hhp_408_2s; + }; + + batteries { + default_battery: getac-smp-hhp-408-3s { + compatible = "getac,bq40z50-R3-S3", "battery-smart"; + }; + getac_smp_hhp_408_2s: getac-smp-hhp-408-2s { + compatible = "getac,bq40z50-R3-S2", "battery-smart"; + }; + }; +}; diff --git a/zephyr/projects/intelrvp/adlrvp/include/adlrvp_zephyr.h b/zephyr/projects/intelrvp/adlrvp/include/adlrvp_zephyr.h new file mode 100644 index 0000000000..135fd4ef4f --- /dev/null +++ b/zephyr/projects/intelrvp/adlrvp/include/adlrvp_zephyr.h @@ -0,0 +1,58 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Intel ADL-RVP specific configuration */ + +#ifndef __ADLRVP_BOARD_H +#define __ADLRVP_BOARD_H + +#include "config.h" + +#define I2C_ADDR_FUSB302_TCPC_AIC 0x22 +#define I2C_ADDR_SN5S330_TCPC_AIC_PPC 0x40 + +#define I2C_ADDR_PCA9675_TCPC_AIC_IOEX 0x21 + +/* SOC side BB retimers (dual retimer config) */ +#define I2C_PORT0_BB_RETIMER_SOC_ADDR 0x54 +#if defined(HAS_TASK_PD_C1) +#define I2C_PORT1_BB_RETIMER_SOC_ADDR 0x55 +#endif + +#define ADLM_LP4_RVP1_SKU_BOARD_ID 0x01 +#define ADLM_LP5_RVP2_SKU_BOARD_ID 0x02 +#define ADLM_LP5_RVP3_SKU_BOARD_ID 0x03 +#define ADLN_LP5_ERB_SKU_BOARD_ID 0x06 +#define ADLN_LP5_RVP_SKU_BOARD_ID 0x07 +#define ADLP_DDR5_RVP_SKU_BOARD_ID 0x12 +#define ADLP_LP5_T4_RVP_SKU_BOARD_ID 0x13 +#define ADL_RVP_BOARD_ID(id) ((id)&0x3F) + +#define CONFIG_BATTERY_TYPE_NO_AUTO_DETECT + +enum adlrvp_charge_ports { + TYPE_C_PORT_0, +#if defined(HAS_TASK_PD_C1) + TYPE_C_PORT_1, +#endif +#if defined(HAS_TASK_PD_C2) + TYPE_C_PORT_2, +#endif +#if defined(HAS_TASK_PD_C3) + TYPE_C_PORT_3, +#endif +}; + +enum ioex_port { + IOEX_C0_PCA9675, + IOEX_C1_PCA9675, +#if defined(HAS_TASK_PD_C2) + IOEX_C2_PCA9675, + IOEX_C3_PCA9675, +#endif + IOEX_PORT_COUNT +}; + +#endif /* __ADLRVP_BOARD_H */ diff --git a/zephyr/projects/intelrvp/adlrvp/ioex.dts b/zephyr/projects/intelrvp/adlrvp/ioex.dts new file mode 100644 index 0000000000..3e2227dacb --- /dev/null +++ b/zephyr/projects/intelrvp/adlrvp/ioex.dts @@ -0,0 +1,78 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + /* IOEX_C0_PCA9675 */ + ioex-c0 { + compatible = "cros,ioex-chip"; + i2c-port = <&typec_0>; + i2c-addr = <0x21>; + drv = "pca9675_ioexpander_drv"; + flags = <0x00>; + #address-cells = <1>; + #size-cells = <0>; + ioex_c0_port: ioex-c0-port@0 { + compatible = "cros,ioex-port"; + reg = <0>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + }; + }; + + /* IOEX_C1_PCA9675 */ + ioex-c1 { + compatible = "cros,ioex-chip"; + i2c-port = <&typec_1>; + i2c-addr = <0x21>; + drv = "pca9675_ioexpander_drv"; + flags = <0x00>; + #address-cells = <1>; + #size-cells = <0>; + ioex_c1_port: ioex-c1-port@0 { + compatible = "cros,ioex-port"; + reg = <0>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + }; + }; + + /* IOEX_C2_PCA9675 */ + ioex-c2 { + compatible = "cros,ioex-chip"; + i2c-port = <&typec_2>; + i2c-addr = <0x21>; + drv = "pca9675_ioexpander_drv"; + flags = <0x00>; + #address-cells = <1>; + #size-cells = <0>; + ioex_c2_port: ioex-c2-port@0 { + compatible = "cros,ioex-port"; + reg = <0>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + }; + }; + + /* IOEX_C3_PCA9675 */ + ioex-c3 { + compatible = "cros,ioex-chip"; + i2c-port = <&typec_3>; + i2c-addr = <0x21>; + drv = "pca9675_ioexpander_drv"; + flags = <0x00>; + #address-cells = <1>; + #size-cells = <0>; + ioex_c3_port: ioex-c3-port@0 { + compatible = "cros,ioex-port"; + reg = <0>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + }; + }; +}; diff --git a/zephyr/projects/intelrvp/adlrvp/prj.conf b/zephyr/projects/intelrvp/adlrvp/prj.conf new file mode 100644 index 0000000000..4bcee4a953 --- /dev/null +++ b/zephyr/projects/intelrvp/adlrvp/prj.conf @@ -0,0 +1,76 @@ +# Copyright 2022 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +# Power Sequencing +CONFIG_AP_X86_INTEL_TGL=y +CONFIG_PLATFORM_EC_POWERSEQ_SLP_S3_L_OVERRIDE=n +CONFIG_PLATFORM_EC_POWERSEQ_PP5000_CONTROL=n +CONFIG_PLATFORM_EC_POWERSEQ_ICELAKE=y + +# Battery +CONFIG_PLATFORM_EC_BATTERY_TYPE_NO_AUTO_DETECT=y +CONFIG_PLATFORM_EC_BATTERY_V2=y + +# BC1.2 +CONFIG_PLATFORM_EC_USB_CHARGER=n + +# CBI +CONFIG_EEPROM=y +CONFIG_EEPROM_AT24=y +CONFIG_EEPROM_SHELL=n +CONFIG_PLATFORM_EC_CBI_EEPROM=y + +# Charger +CONFIG_PLATFORM_EC_CHARGER=y +CONFIG_PLATFORM_EC_CHARGER_DISCHARGE_ON_AC=y +CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR=5 +CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR_AC=10 +CONFIG_PLATFORM_EC_CHARGE_RAMP_HW=n +CONFIG_PLATFORM_EC_CHARGER_BQ25720=y +CONFIG_PLATFORM_EC_CHARGER_BQ25720_VSYS_TH2_CUSTOM=y +CONFIG_PLATFORM_EC_CHARGER_BQ25720_VSYS_TH2_DV=70 +CONFIG_PLATFORM_EC_CHARGER_ISL9241=y +CONFIG_PLATFORM_EC_CHARGER_RUNTIME_CONFIG=y + +# LED +CONFIG_PLATFORM_EC_LED_COMMON=y +CONFIG_PLATFORM_EC_LED_PWM=y +CONFIG_PLATFORM_EC_LED_PWM_TASK_DISABLED=y + +# Temperature sensors +CONFIG_PLATFORM_EC_TEMP_SENSOR=y +CONFIG_PLATFORM_EC_THERMISTOR=y +CONFIG_PLATFORM_EC_TEMP_SENSOR_POWER=y + +# USB-C and PD +CONFIG_PLATFORM_EC_USB_DRP_ACC_TRYSRC=y +CONFIG_PLATFORM_EC_USB_PD_DUAL_ROLE_AUTO_TOGGLE=n +CONFIG_PLATFORM_EC_USB_PD_VBUS_MEASURE_CHARGER=y +CONFIG_PLATFORM_EC_USB_PD_VBUS_MEASURE_TCPC=y +CONFIG_PLATFORM_EC_USB_PD_TCPC_RUNTIME_CONFIG=n +CONFIG_PLATFORM_EC_USBC_RETIMER_INTEL_BB_RUNTIME_CONFIG=n +CONFIG_PLATFORM_EC_USB_MUX_TUSB1044=y +CONFIG_PLATFORM_EC_USB_MUX_VIRTUAL=y +CONFIG_PLATFORM_EC_USB_PD_DISCHARGE_PPC=y +CONFIG_PLATFORM_EC_USB_PD_REV30=y +CONFIG_PLATFORM_EC_USB_PD_USB32_DRD=y +CONFIG_PLATFORM_EC_USB_PD_TBT_COMPAT_MODE=y +CONFIG_PLATFORM_EC_USB_PD_USB4=y +CONFIG_PLATFORM_EC_USB_PD_TCPM_FUSB302=y +CONFIG_PLATFORM_EC_USB_PD_TCPM_MUX=y +CONFIG_PLATFORM_EC_USB_PD_TCPM_TCPCI=y +CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_PPC=y +CONFIG_PLATFORM_EC_USBC_PPC_SN5S330=y +CONFIG_PLATFORM_EC_USBC_RETIMER_INTEL_BB=y + +# IOEX +CONFIG_PLATFORM_EC_IOEX_CROS_DRV=y +CONFIG_PLATFORM_EC_IOEX_PCA9675=y +CONFIG_GPIO_PCA95XX=y + +# 7-Segment Display +CONFIG_PLATFORM_EC_MAX695X_SEVEN_SEGMENT_DISPLAY=y + +# eSPI +CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_DEFAULT_VW_WIDTH_US=150 diff --git a/zephyr/projects/intelrvp/adlrvp/src/adlrvp.c b/zephyr/projects/intelrvp/adlrvp/src/adlrvp.c new file mode 100644 index 0000000000..ce5196c60d --- /dev/null +++ b/zephyr/projects/intelrvp/adlrvp/src/adlrvp.c @@ -0,0 +1,430 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* TODO: b/218904113: Convert to using Zephyr GPIOs */ +#include "gpio_signal.h" +#include "adlrvp_zephyr.h" +#include "common.h" +#include "console.h" +#include "intelrvp.h" +#include "intel_rvp_board_id.h" +#include "battery_fuel_gauge.h" +#include "charger.h" +#include "battery.h" +#include "bq25710.h" +#include "driver/retimer/bb_retimer_public.h" +#include "extpower.h" +#include "hooks.h" +#include "ioexpander.h" +#include "isl9241.h" +#include "power/icelake.h" +#include "sn5s330.h" +#include "system.h" +#include "task.h" +#include "tusb1064.h" +#include "usb_mux.h" +#include "usbc/usb_muxes.h" +#include "usbc_ppc.h" +#include "util.h" + +#define CPRINTF(format, args...) cprintf(CC_COMMAND, format, ##args) +#define CPRINTS(format, args...) cprints(CC_COMMAND, format, ##args) + +/* TCPC AIC GPIO Configuration */ +const struct tcpc_aic_gpio_config_t tcpc_aic_gpios[] = { + [TYPE_C_PORT_0] = { + .tcpc_alert = GPIO_SIGNAL(DT_NODELABEL(usbc_tcpc_alrt_p0)), + .ppc_alert = GPIO_SIGNAL(DT_NODELABEL(usbc_tcpc_ppc_alrt_p0)), + .ppc_intr_handler = sn5s330_interrupt, + }, +#if defined(HAS_TASK_PD_C1) + [TYPE_C_PORT_1] = { + .tcpc_alert = GPIO_SIGNAL(DT_NODELABEL(usbc_tcpc_alrt_p1)), + .ppc_alert = GPIO_SIGNAL(DT_NODELABEL(usbc_tcpc_ppc_alrt_p1)), + .ppc_intr_handler = sn5s330_interrupt, + }, +#endif +#if defined(HAS_TASK_PD_C2) + [TYPE_C_PORT_2] = { + .tcpc_alert = GPIO_SIGNAL(DT_NODELABEL(usbc_tcpc_alrt_p2)), + .ppc_alert = GPIO_SIGNAL(DT_NODELABEL(usbc_tcpc_ppc_alrt_p2)), + .ppc_intr_handler = sn5s330_interrupt, + }, +#endif +#if defined(HAS_TASK_PD_C3) + [TYPE_C_PORT_3] = { + .tcpc_alert = GPIO_SIGNAL(DT_NODELABEL(usbc_tcpc_alrt_p3)), + .ppc_alert = GPIO_SIGNAL(DT_NODELABEL(usbc_tcpc_ppc_alrt_p3)), + .ppc_intr_handler = sn5s330_interrupt, + }, +#endif +}; +BUILD_ASSERT(ARRAY_SIZE(tcpc_aic_gpios) == CONFIG_USB_PD_PORT_MAX_COUNT); + +/* USB-C PPC configuration */ +struct ppc_config_t ppc_chips[] = { + [TYPE_C_PORT_0] = { + .i2c_port = I2C_PORT_TYPEC_0, + .i2c_addr_flags = I2C_ADDR_SN5S330_TCPC_AIC_PPC, + .drv = &sn5s330_drv, + }, +#if defined(HAS_TASK_PD_C1) + [TYPE_C_PORT_1] = { + .i2c_port = I2C_PORT_TYPEC_1, + .i2c_addr_flags = I2C_ADDR_SN5S330_TCPC_AIC_PPC, + .drv = &sn5s330_drv + }, +#endif +#if defined(HAS_TASK_PD_C2) + [TYPE_C_PORT_2] = { + .i2c_port = I2C_PORT_TYPEC_2, + .i2c_addr_flags = I2C_ADDR_SN5S330_TCPC_AIC_PPC, + .drv = &sn5s330_drv, + }, +#endif +#if defined(HAS_TASK_PD_C3) + [TYPE_C_PORT_3] = { + .i2c_port = I2C_PORT_TYPEC_3, + .i2c_addr_flags = I2C_ADDR_SN5S330_TCPC_AIC_PPC, + .drv = &sn5s330_drv, + }, +#endif +}; +BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == CONFIG_USB_PD_PORT_MAX_COUNT); +unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips); + +/* Cache BB retimer power state */ +static bool cache_bb_enable[CONFIG_USB_PD_PORT_MAX_COUNT]; + +void board_overcurrent_event(int port, int is_overcurrented) +{ + /* Port 0 & 1 and 2 & 3 share same line for over current indication */ +#if defined(HAS_TASK_PD_C2) + enum ioex_signal oc_signal = port < TYPE_C_PORT_2 ? IOEX_USB_C0_C1_OC : + IOEX_USB_C2_C3_OC; +#else + enum ioex_signal oc_signal = IOEX_USB_C0_C1_OC; +#endif + + /* Overcurrent indication is active low signal */ + ioex_set_level(oc_signal, is_overcurrented ? 0 : 1); +} + +__override int bb_retimer_power_enable(const struct usb_mux *me, bool enable) +{ + /* + * ADL-P-DDR5 RVP SKU has cascaded retimer topology. + * Ports with cascaded retimers share common load switch and reset pin + * hence no need to set the power state again if the 1st retimer's power + * status has already changed. + */ + if (cache_bb_enable[me->usb_port] == enable) + return EC_SUCCESS; + + cache_bb_enable[me->usb_port] = enable; + + /* Handle retimer's power domain.*/ + if (enable) { + ioex_set_level(bb_controls[me->usb_port].usb_ls_en_gpio, 1); + + /* + * minimum time from VCC to RESET_N de-assertion is 100us + * For boards that don't provide a load switch control, the + * retimer_init() function ensures power is up before calling + * this function. + */ + msleep(1); + ioex_set_level(bb_controls[me->usb_port].retimer_rst_gpio, 1); + + /* + * Allow 1ms time for the retimer to power up lc_domain + * which powers I2C controller within retimer + */ + msleep(1); + + } else { + ioex_set_level(bb_controls[me->usb_port].retimer_rst_gpio, 0); + msleep(1); + ioex_set_level(bb_controls[me->usb_port].usb_ls_en_gpio, 0); + } + return EC_SUCCESS; +} + +static void board_connect_c0_sbu_deferred(void) +{ + int ccd_intr_level = gpio_get_level(GPIO_CCD_MODE_ODL); + + if (ccd_intr_level) { + /* Default set the SBU lines to AUX mode on TCPC-AIC */ + ioex_set_level(IOEX_USB_C0_USB_MUX_CNTRL_1, 0); + ioex_set_level(IOEX_USB_C0_USB_MUX_CNTRL_0, 0); + } else { + /* Set the SBU lines to CCD mode on TCPC-AIC */ + ioex_set_level(IOEX_USB_C0_USB_MUX_CNTRL_1, 1); + ioex_set_level(IOEX_USB_C0_USB_MUX_CNTRL_0, 0); + } +} +DECLARE_DEFERRED(board_connect_c0_sbu_deferred); + +void board_connect_c0_sbu(enum gpio_signal s) +{ + hook_call_deferred(&board_connect_c0_sbu_deferred_data, 0); +} + +static void enable_h1_irq(void) +{ + gpio_enable_interrupt(GPIO_CCD_MODE_ODL); +} +DECLARE_HOOK(HOOK_INIT, enable_h1_irq, HOOK_PRIO_LAST); + +void set_charger_system_voltage(void) +{ + switch (ADL_RVP_BOARD_ID(board_get_version())) { + case ADLN_LP5_ERB_SKU_BOARD_ID: + case ADLN_LP5_RVP_SKU_BOARD_ID: + /* + * As per b:196184163 configure the PPVAR_SYS depend + * on AC or AC+battery + */ + if (extpower_is_present() && battery_is_present()) { + bq25710_set_min_system_voltage( + CHARGER_SOLO, battery_get_info()->voltage_min); + } else { + bq25710_set_min_system_voltage( + CHARGER_SOLO, battery_get_info()->voltage_max); + } + break; + + /* Add additional board SKUs */ + default: + break; + } +} +DECLARE_HOOK(HOOK_AC_CHANGE, set_charger_system_voltage, HOOK_PRIO_DEFAULT); + +static void configure_charger(void) +{ + switch (ADL_RVP_BOARD_ID(board_get_version())) { + case ADLN_LP5_ERB_SKU_BOARD_ID: + case ADLN_LP5_RVP_SKU_BOARD_ID: + /* charger chip BQ25720 support */ + chg_chips[0].i2c_addr_flags = BQ25710_SMBUS_ADDR1_FLAGS; + chg_chips[0].drv = &bq25710_drv; + set_charger_system_voltage(); + break; + + /* Add additional board SKUs */ + default: + break; + } +} + +static void configure_retimer_usbmux(void) +{ + struct usb_mux *mux; + + switch (ADL_RVP_BOARD_ID(board_get_version())) { + case ADLN_LP5_ERB_SKU_BOARD_ID: + case ADLN_LP5_RVP_SKU_BOARD_ID: + /* enable TUSB1044RNQR redriver on Port0 */ + mux = USB_MUX_POINTER(DT_NODELABEL(usb_mux_chain_0), 0); + mux->i2c_addr_flags = TUSB1064_I2C_ADDR14_FLAGS; + mux->driver = &tusb1064_usb_mux_driver; + mux->hpd_update = tusb1044_hpd_update; + +#if defined(HAS_TASK_PD_C1) + mux = USB_MUX_POINTER(DT_NODELABEL(usb_mux_chain_1), 0); + mux->driver = NULL; + mux->hpd_update = NULL; +#endif + break; + + case ADLP_LP5_T4_RVP_SKU_BOARD_ID: + /* No retimer on Port-2 */ +#if defined(HAS_TASK_PD_C2) + mux = USB_MUX_POINTER(DT_NODELABEL(usb_mux_chain_2), 0); + mux->driver = NULL; +#endif + break; + + case ADLP_DDR5_RVP_SKU_BOARD_ID: + /* + * ADL-P-DDR5 RVP has dual BB-retimers for port0 & port1. + * Change the default usb mux config on runtime to support + * dual retimer topology. + */ + USB_MUX_ENABLE_ALTERNATIVE(usb_mux_alt_chain_0); +#if defined(HAS_TASK_PD_C1) + USB_MUX_ENABLE_ALTERNATIVE(usb_mux_alt_chain_1); +#endif + break; + + /* Add additional board SKUs */ + + default: + break; + } +} + +static void configure_battery_type(void) +{ + int bat_cell_type; + + switch (ADL_RVP_BOARD_ID(board_get_version())) { + case ADLM_LP4_RVP1_SKU_BOARD_ID: + case ADLM_LP5_RVP2_SKU_BOARD_ID: + case ADLM_LP5_RVP3_SKU_BOARD_ID: + case ADLN_LP5_ERB_SKU_BOARD_ID: + case ADLN_LP5_RVP_SKU_BOARD_ID: + /* configure Battery to 2S based */ + bat_cell_type = BATTERY_TYPE(DT_ALIAS(getac_2s)); + break; + default: + /* configure Battery to 3S based */ + bat_cell_type = BATTERY_TYPE(DT_ALIAS(getac_3s)); + break; + } + + /* Set the fixed battery type */ + battery_set_fixed_battery_type(bat_cell_type); +} +/******************************************************************************/ +/* PWROK signal configuration */ +/* + * On ADLRVP, SYS_PWROK_EC is an output controlled by EC and uses ALL_SYS_PWRGD + * as input. + */ +const struct intel_x86_pwrok_signal pwrok_signal_assert_list[] = { + { + .gpio = GPIO_PCH_SYS_PWROK, + .delay_ms = 3, + }, +}; +const int pwrok_signal_assert_count = ARRAY_SIZE(pwrok_signal_assert_list); + +const struct intel_x86_pwrok_signal pwrok_signal_deassert_list[] = { + { + .gpio = GPIO_PCH_SYS_PWROK, + }, +}; +const int pwrok_signal_deassert_count = ARRAY_SIZE(pwrok_signal_deassert_list); + +/* + * Returns board information (board id[7:0] and Fab id[15:8]) on success + * -1 on error. + */ +__override int board_get_version(void) +{ + /* Cache the board ID */ + static int adlrvp_board_id; + + int i; + int rv = EC_ERROR_UNKNOWN; + + int fab_id, board_id, bom_id; + + /* Board ID is already read */ + if (adlrvp_board_id) + return adlrvp_board_id; + + /* + * IOExpander that has Board ID information is on DSW-VAL rail on + * ADL RVP. On cold boot cycles, DSW-VAL rail is taking time to settle. + * This loop retries to ensure rail is settled and read is successful + */ + for (i = 0; i < RVP_VERSION_READ_RETRY_CNT; i++) { + rv = gpio_pin_get_dt(&bom_id_config[0]); + + if (rv >= 0) + break; + + k_msleep(1); + } + + /* retrun -1 if failed to read board id */ + if (rv < 0) + return -1; + + /* + * BOM ID [2] : IOEX[0] + * BOM ID [1:0] : IOEX[15:14] + */ + bom_id = gpio_pin_get_dt(&bom_id_config[0]) << 2; + bom_id |= gpio_pin_get_dt(&bom_id_config[1]) << 1; + bom_id |= gpio_pin_get_dt(&bom_id_config[2]); + + /* + * FAB ID [1:0] : IOEX[2:1] + 1 + */ + fab_id = gpio_pin_get_dt(&fab_id_config[0]) << 1; + fab_id |= gpio_pin_get_dt(&fab_id_config[1]); + fab_id += 1; + + /* + * BOARD ID[5:0] : IOEX[13:8] + */ + board_id = gpio_pin_get_dt(&board_id_config[0]) << 5; + board_id |= gpio_pin_get_dt(&board_id_config[1]) << 4; + board_id |= gpio_pin_get_dt(&board_id_config[2]) << 3; + board_id |= gpio_pin_get_dt(&board_id_config[3]) << 2; + board_id |= gpio_pin_get_dt(&board_id_config[4]) << 1; + board_id |= gpio_pin_get_dt(&board_id_config[5]); + + CPRINTF("BID:0x%x, FID:0x%x, BOM:0x%x", board_id, fab_id, bom_id); + + adlrvp_board_id = board_id | (fab_id << 8); + return adlrvp_board_id; +} + +__override bool board_is_tbt_usb4_port(int port) +{ + bool tbt_usb4 = true; + + switch (ADL_RVP_BOARD_ID(board_get_version())) { + case ADLN_LP5_ERB_SKU_BOARD_ID: + case ADLN_LP5_RVP_SKU_BOARD_ID: + /* No retimer on both ports */ + tbt_usb4 = false; + break; + + case ADLP_LP5_T4_RVP_SKU_BOARD_ID: + /* No retimer on Port-2 hence no platform level AUX & LSx mux */ +#if defined(HAS_TASK_PD_C2) + if (port == TYPE_C_PORT_2) + tbt_usb4 = false; +#endif + break; + + /* Add additional board SKUs */ + default: + break; + } + + return tbt_usb4; +} + +static int board_pre_task_peripheral_init(const struct device *unused) +{ + ARG_UNUSED(unused); + + /* Initialized IOEX-0 to access IOEX-GPIOs needed pre-task */ + ioex_init(IOEX_C0_PCA9675); + + /* Make sure SBU are routed to CCD or AUX based on CCD status at init */ + board_connect_c0_sbu_deferred(); + + /* Configure battery type */ + configure_battery_type(); + + /* Reconfigure board specific charger drivers */ + configure_charger(); + + /* Configure board specific retimer & mux */ + configure_retimer_usbmux(); + + return 0; +} +SYS_INIT(board_pre_task_peripheral_init, APPLICATION, + CONFIG_APPLICATION_INIT_PRIORITY); diff --git a/zephyr/projects/intelrvp/include/intel_rvp_board_id.h b/zephyr/projects/intelrvp/include/intel_rvp_board_id.h new file mode 100644 index 0000000000..7825b272e3 --- /dev/null +++ b/zephyr/projects/intelrvp/include/intel_rvp_board_id.h @@ -0,0 +1,17 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#ifndef __INTEL_RVP_BOARD_ID_H +#define __INTEL_RVP_BOARD_ID_H + +#include <zephyr/drivers/gpio.h> + +extern const struct gpio_dt_spec bom_id_config[]; + +extern const struct gpio_dt_spec fab_id_config[]; + +extern const struct gpio_dt_spec board_id_config[]; + +#endif /* __INTEL_RVP_BOARD_ID_H */ diff --git a/zephyr/projects/intelrvp/include/intelrvp.h b/zephyr/projects/intelrvp/include/intelrvp.h new file mode 100644 index 0000000000..9b6dc98485 --- /dev/null +++ b/zephyr/projects/intelrvp/include/intelrvp.h @@ -0,0 +1,35 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ +#ifndef __INTELRVP_BOARD_H +#define __INTELRVP_BOARD_H + +#include "compiler.h" +#include "gpio_signal.h" +#include "stdbool.h" + +/* RVP ID read retry count */ +#define RVP_VERSION_READ_RETRY_CNT 2 + +#define DC_JACK_MAX_VOLTAGE_MV 19000 + +FORWARD_DECLARE_ENUM(tcpc_rp_value); + +struct tcpc_aic_gpio_config_t { + /* TCPC interrupt */ + enum gpio_signal tcpc_alert; + /* PPC interrupt */ + enum gpio_signal ppc_alert; + /* PPC interrupt handler */ + void (*ppc_intr_handler)(int port); +}; +extern const struct tcpc_aic_gpio_config_t tcpc_aic_gpios[]; + +void board_charging_enable(int port, int enable); +void board_vbus_enable(int port, int enable); +void board_set_vbus_source_current_limit(int port, enum tcpc_rp_value rp); +void board_dc_jack_interrupt(enum gpio_signal signal); +void tcpc_alert_event(enum gpio_signal signal); +bool is_typec_port(int port); +#endif /* __INTELRVP_BOARD_H */ diff --git a/zephyr/projects/intelrvp/led.md b/zephyr/projects/intelrvp/led.md new file mode 100644 index 0000000000..c36bc6b36c --- /dev/null +++ b/zephyr/projects/intelrvp/led.md @@ -0,0 +1,44 @@ +## LED behavior on Intel RVP + +There are two LEDs on RVP, they represent battery and charger status +respectively. + +LED | Description +------------|------------------------ +CHARGER_LED | Represent charger state +BATTERY_LED | Represent battery state + +LEDs on RVP emit a single color (green). Rather than just using the on and off +state of the LED, PWM is used to blink the LED to represent multiple states and +the below table represents the multiple LED states. + +LED State | Description +---------------|------------------------------ +LED_ON | Switch On using gpio/pwmduty +LED_OFF | Switch Off using gpio/pwmduty +LED_FLASH_SLOW | Flashing with 2 sec period +LED_FLASH_FAST | Flashing with 250ms period + +### LED Behavior : Charger + +CHARGER_LED is dedicated to represent Charger status and the below table +represents the LED states for the Charger. + +Charger Status | LED States +---------------------|--------------- +Charging | LED_ON +Discharging | LED_FLASH_SLOW +Charging error | LED_FLASH_FAST +No Charger Connected | LED_OFF + +### LED Behavior : Battery + +BATTERY_LED is dedicated to represent Battery status and the below table +represents the LED states for the Battery. + +Battery Status | LED States +----------------------------|--------------- +Battery Low (<10%) | LED_FLASH_FAST +Battery Normal (10% to 90%) | LED_FLASH_SLOW +Battery Full (>90%) | LED_ON +Battery Not Present | LED_OFF diff --git a/zephyr/projects/intelrvp/legacy_ec_pwrseq.conf b/zephyr/projects/intelrvp/legacy_ec_pwrseq.conf new file mode 100644 index 0000000000..331afb637d --- /dev/null +++ b/zephyr/projects/intelrvp/legacy_ec_pwrseq.conf @@ -0,0 +1,12 @@ +# Copyright 2022 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +# Legacy EC Power Sequencing Common Config +CONFIG_PLATFORM_EC_POWERSEQ=y +CONFIG_PLATFORM_EC_POWERSEQ_HOST_SLEEP=y +CONFIG_PLATFORM_EC_POWERSEQ_INTEL=y +CONFIG_PLATFORM_EC_POWERSEQ_RSMRST_DELAY=y +CONFIG_PLATFORM_EC_POWERSEQ_S0IX=y +CONFIG_PLATFORM_EC_POWERSEQ_S4=y +CONFIG_PLATFORM_EC_THROTTLE_AP=y diff --git a/zephyr/projects/intelrvp/mtlrvp/CMakeLists.txt b/zephyr/projects/intelrvp/mtlrvp/CMakeLists.txt new file mode 100644 index 0000000000..c6729af776 --- /dev/null +++ b/zephyr/projects/intelrvp/mtlrvp/CMakeLists.txt @@ -0,0 +1,6 @@ +# Copyright 2022 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +zephyr_library_sources("src/mtlrvp.c") +zephyr_library_sources("src/board_power.c") diff --git a/zephyr/projects/intelrvp/mtlrvp/ioex.dts b/zephyr/projects/intelrvp/mtlrvp/ioex.dts new file mode 100644 index 0000000000..7d2f4b5820 --- /dev/null +++ b/zephyr/projects/intelrvp/mtlrvp/ioex.dts @@ -0,0 +1,71 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + /* IOEX_KBD_GPIO IT8801 */ + ioex-kbd-gpio { + compatible = "cros,ioex-chip"; + i2c-port = <&i2c_charger>; + i2c-addr = <0x39>; + drv = "it8801_ioexpander_drv"; + flags = <0x00>; + #address-cells = <1>; + #size-cells = <0>; + + ioex_it8801_port0: it8801_port@0 { + compatible = "cros,ioex-port"; + reg = <0>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + }; + + ioex_it8801_port1: it8801_port@1 { + compatible = "cros,ioex-port"; + reg = <1>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + }; + }; + /* IOEX_C2_CCGXXF */ + ioex-c2 { + compatible = "cros,ioex-chip"; + i2c-port = <&typec_aic2>; + i2c-addr = <0x0B>; + drv = "ccgxxf_ioexpander_drv"; + flags = <0x00>; + #address-cells = <1>; + #size-cells = <0>; + ioex_c2_port0: ioex-c2-port@0 { + compatible = "cros,ioex-port"; + reg = <0>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + }; + ioex_c2_port1: ioex-c2-port@1 { + compatible = "cros,ioex-port"; + reg = <1>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + }; + ioex_c2_port2: ioex-c2-port@2 { + compatible = "cros,ioex-port"; + reg = <2>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + }; + ioex_c2_port3: ioex-c2-port@3 { + compatible = "cros,ioex-port"; + reg = <3>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + }; + }; +}; diff --git a/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/fan.dts b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/fan.dts new file mode 100644 index 0000000000..cf85dd3413 --- /dev/null +++ b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/fan.dts @@ -0,0 +1,36 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + fans { + compatible = "cros-ec,fans"; + + fan_0 { + pwms = <&pwm3 0 PWM_KHZ(30) PWM_POLARITY_NORMAL>; + rpm_min = <3200>; + rpm_start = <2200>; + rpm_max = <6600>; + tach = <&tach2>; + pgood_gpio = <&all_sys_pwrgd>; + enable_gpio = <&gpio_fan_control>; + }; + }; +}; + +/* Tachemeter for fan speed measurement */ +&tach2 { + status = "okay"; + pinctrl-0 = <&ta2_1_in_gp73>; /* TA2 input on GPIO73 */ + pinctrl-names = "default"; + port = <NPCX_TACH_PORT_A>; /* port-A is selected */ + sample-clk = <NPCX_TACH_FREQ_LFCLK>; /* Use LFCLK as sampling clock */ + pulses-per-round = <2>; /* number of pulses per round of encoder */ +}; + +&pwm3 { + status = "okay"; + pinctrl-0 = <&pwm3_gp80>; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/gpio.dts b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/gpio.dts new file mode 100644 index 0000000000..77b4cf0573 --- /dev/null +++ b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/gpio.dts @@ -0,0 +1,366 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + aliases { + gpio-wp = &gpio_wp; + }; + + named-gpios { + compatible = "named-gpios"; + + ioex_kbd_intr_n: ioex-kbd-intr-n { + gpios = <&gpio0 0 GPIO_INPUT>; + enum-name = "GPIO_KB_DISCRETE_INT"; + }; + all_sys_pwrgd: all-sys-pwrgd { + gpios = <&gpio7 0 GPIO_INPUT>; + enum-name = "GPIO_PG_EC_ALL_SYS_PWRGD"; + }; + rsmrst_pwrgd: rsmrst-pwrgd { + gpios = <&gpio6 6 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; + enum-name = "GPIO_PG_EC_RSMRST_ODL"; + }; + pch_slp_s0_n: pch-slp-s0-n-ec { + gpios = <&gpioa 1 GPIO_INPUT>; + enum-name = "GPIO_PCH_SLP_S0_L"; /* 1.8V */ + }; + pm-slp-s3-n-ec { + gpios = <&gpiob 0 GPIO_INPUT>; /* 1.8V */ + enum-name = "GPIO_PCH_SLP_S3_L"; + }; + pm-slp-s4-n-ec { + gpios = <&gpioa 5 GPIO_INPUT>; /* 1.8V */ + }; + volume-up { + gpios = <&gpio6 1 (GPIO_INPUT | GPIO_PULL_UP)>; + enum-name = "GPIO_VOLUME_UP_L"; + }; + vol-dn-ec-r { + gpios = <&gpio0 3 (GPIO_INPUT | GPIO_PULL_UP)>; + enum-name = "GPIO_VOLUME_DOWN_L"; + }; + smc_lid: smc-lid { + gpios = <&gpio0 1 (GPIO_INPUT | GPIO_PULL_UP)>; + enum-name = "GPIO_LID_OPEN"; + }; + smc_onoff_n: smc-onoff-n { + gpios = <&gpiod 2 GPIO_INPUT>; + enum-name = "GPIO_POWER_BUTTON_L"; + }; + gpio_wp: wp-l { + gpios = <&gpiod 5 GPIO_INPUT>; + }; + std_adp_prsnt: std-adp-prsnt { + gpios = <&gpioc 6 GPIO_INPUT>; + enum-name = "GPIO_DC_JACK_PRESENT"; + }; + bc_acok: bc-acok-ec { + gpios = <&gpio0 2 GPIO_INPUT>; + enum-name = "GPIO_AC_PRESENT"; + }; + usbc_tcpc_alrt_p0: usbc-tcpc-alrt-p0 { + gpios = <&gpio4 0 GPIO_INPUT>; + }; + /* NOTE: Netname is USBC_TCPC_PPC_ALRT_P0 */ + usb_c0_c1_tcpc_rst_odl: usb-c0-c1-tcpc-rst-odl { + gpios = <&gpiod 0 GPIO_ODR_HIGH>; + }; + /* NOTE: Netname is USBC_TCPC_ALRT_P1 */ + usbc_tcpc_ppc_alrt_p0: usbc-tcpc-ppc-alrt-p0 { + gpios = <&gpiod 1 GPIO_INPUT>; + }; + usbc_tcpc_ppc_alrt_p1: usbc-tcpc-ppc-alrt-p1 { + gpios = <&gpioe 4 GPIO_INPUT>; + }; + usbc_tcpc_alrt_p2: usbc-tcpc-alrt-p2 { + gpios = <&gpio9 1 GPIO_INPUT>; + }; + /* NOTE: Netname is USBC_TCPC_PPC_ALRT_P3 */ + usbc_tcpc_alrt_p3: usbc-tcpc-alrt-p3 { + gpios = <&gpiof 3 GPIO_INPUT>; + }; + gpio_ec_pch_wake_odl: pch-wake-n { + gpios = <&gpio7 4 GPIO_ODR_HIGH>; + }; + espi-rst-n { + gpios = <&gpio5 4 GPIO_INPUT>; /* 1.8V */ + }; + plt-rst-l { + gpios = <&gpioa 2 GPIO_INPUT>; /* 1.8V */ + }; + slate-mode-indication { + gpios = <&gpio9 4 GPIO_INPUT>; /* 1.8V */ + }; + prochot-ec { + gpios = <&gpio6 0 GPIO_INPUT>; + enum-name = "GPIO_CPU_PROCHOT"; + }; + sys_rst_odl: sys-rst-odl-ec { + gpios = <&gpioc 5 GPIO_ODR_HIGH>; + enum-name = "GPIO_SYS_RESET_L"; + }; + ec_pch_rsmrst_l: pm-rsmrst-r-n { + gpios = <&gpioa 4 GPIO_OUTPUT_LOW>; /* 1.8V */ + enum-name = "GPIO_PCH_RSMRST_L"; + }; + pm-pwrbtn-n-ec { + gpios = <&gpiod 4 GPIO_ODR_HIGH>; + enum-name = "GPIO_PCH_PWRBTN_L"; + }; + ec_spi_oe_mecc: ec-spi-oe-mecc-r { + gpios = <&gpioa 7 GPIO_OUTPUT_LOW>; /* 1.8V */ + }; + en_pp3300_a: ec-ds3-r { + gpios = <&gpioc 4 GPIO_OUTPUT_LOW>; + enum-name = "GPIO_EN_PP3300_A"; + alias = "GPIO_TEMP_SENSOR_POWER"; + }; + ec_pch_pwrok_od: pch-pwrok-ec-r { + gpios = <&gpiod 3 GPIO_ODR_LOW>; + enum-name = "GPIO_PCH_PWROK"; + }; + sys_pwrok_ec: sys-pwrok-ec { + gpios = <&gpiof 5 GPIO_ODR_LOW>; + enum-name = "GPIO_PCH_SYS_PWROK"; + }; + bat-det-ec { + gpios = <&gpio7 6 GPIO_INPUT>; + enum-name = "GPIO_BATT_PRES_ODL"; + }; + edp-bklt-en { + gpios = <&gpioe 1 GPIO_OUTPUT_HIGH>; + }; + /* TODO: move both LEDs to PWM */ + led-1-l-ec { + gpios = <&gpiob 6 GPIO_OUTPUT_HIGH>; + }; + led-2-l-ec { + gpios = <&gpiob 7 GPIO_OUTPUT_HIGH>; + }; + gpio_fan_control: therm-sen-mecc-r { + gpios = <&gpioc 0 GPIO_OUTPUT_LOW>; + }; + /* NOTE: Netname is USBC_TCPC_ALRT_P3 */ + ccd_mode_odl: ccd-mode-odl { + gpios = <&gpio9 2 GPIO_INPUT>; + enum-name = "GPIO_CCD_MODE_ODL"; + }; + smb-bs-clk { + gpios = <&gpiob 3 GPIO_INPUT>; + }; + smb-bs-data { + gpios = <&gpiob 2 GPIO_INPUT>; + }; + usbc-tcpc-i2c-clk-aic1 { + gpios = <&gpiob 5 GPIO_INPUT>; + }; + usbc-tcpc-i2c-data-aic1 { + gpios = <&gpiob 4 GPIO_INPUT>; + }; + usbc-tcpc-i2c-clk-aic2 { + gpios = <&gpio9 0 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; + }; + usbc-tcpc-i2c-data-aic2 { + gpios = <&gpio8 7 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; + }; + /* Unused 1.8V pins */ + i3c-1-sda-r { + gpios = <&gpio5 0 GPIO_INPUT>; + }; + i3c-1-scl-r { + gpios = <&gpio5 6 GPIO_INPUT>; + }; + espi-alert0-n-r { + gpios = <&gpio5 7 GPIO_INPUT>; + }; + tp-gpio95 { + gpios = <&gpio9 5 GPIO_INPUT>; + }; + cpu-c10-gate { + gpios = <&gpio9 6 GPIO_INPUT>; + }; + slp-s0-cs-n-ec { + gpios = <&gpio9 7 GPIO_INPUT>; + }; + rtc-rst-n-r { + gpios = <&gpioa 0 GPIO_INPUT>; + }; + tp-gpioa6 { + gpios = <&gpioa 6 GPIO_INPUT>; + }; + sml1-clk-mecc { + gpios = <&gpio3 3 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; + }; + sml1-data-mecc { + gpios = <&gpio3 6 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; + }; + sml1-alert { + gpios = <&gpioc 7 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; + }; + smb-pch-alrt { + gpios = <&gpioa 3 GPIO_INPUT>; + }; + smb-pch-data { + gpios = <&gpioc 1 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; + }; + smb-pch-clk { + gpios = <&gpioc 2 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; + }; + /* Unused 3.3V pins */ + cpu-cat-err-mecc { + gpios = <&gpio3 4 GPIO_INPUT>; + }; + tp-gpio37 { + gpios = <&gpio3 7 GPIO_INPUT>; + }; + tp-vccpdsw-3p3-ec { + gpios = <&gpio4 5 GPIO_INPUT>; + }; + mech-pwr-btn-in-odl { + gpios = <&gpio6 2 GPIO_INPUT>; + }; + tp-gpio63 { + gpios = <&gpio6 3 GPIO_INPUT>; + }; + tp-gpio67 { + gpios = <&gpio6 7 GPIO_INPUT>; + }; + tp-gpio72 { + gpios = <&gpio7 2 GPIO_INPUT>; + }; + tp-gpio75 { + gpios = <&gpio7 5 GPIO_INPUT>; + }; + ec-peci-ec { + gpios = <&gpio8 1 GPIO_INPUT>; + }; + tp-gpiob1 { + gpios = <&gpiob 1 GPIO_INPUT>; + }; + std-adpt-cntrl-GPIO_r { + gpios = <&gpioc 3 GPIO_INPUT>; + }; + ec-packet-mode-ec { + gpios = <&gpioe 2 GPIO_INPUT>; + }; + tp-gpioe3 { + gpios = <&gpioe 3 GPIO_INPUT>; + }; + boot-stall-r { + gpios = <&gpioe 5 GPIO_INPUT>; + }; + tp-gpiof0 { + gpios = <&gpiof 0 GPIO_INPUT>; + }; + tp-gpiof1 { + gpios = <&gpiof 1 GPIO_INPUT>; + }; + usbc_tcpc_ppc_alrt_p2: usbc-tcpc-ppc-alrt-p2 { + gpios = <&gpiof 2 GPIO_INPUT>; + }; + tp-gpiof4 { + gpios = <&gpiof 4 GPIO_INPUT>; + }; + + /* KBD IOEX configuration */ + srtc-rst { + gpios = <&ioex_it8801_port0 3 GPIO_OUTPUT_LOW>; + }; + ec-h1-packet-mode { + gpios = <&ioex_it8801_port0 4 GPIO_OUTPUT_LOW>; + enum-name = "GPIO_PACKET_MODE_EN"; + }; + rtc-rst { + gpios = <&ioex_it8801_port0 6 GPIO_OUTPUT_LOW>; + }; + ec-entering-rw { + gpios = <&ioex_it8801_port0 7 GPIO_OUTPUT_LOW>; + enum-name = "GPIO_ENTERING_RW"; + }; + ioex-sys-rst-odl-ec { + gpios = <&ioex_it8801_port1 0 GPIO_INPUT>; + }; + ioex-slate-mode-indication { + gpios = <&ioex_it8801_port1 2 GPIO_INPUT>; + }; + + /* USB C IOEX configuration */ + usb_c0_hb_retimer_ls_en: usb-c0-hbr-ls-en { + gpios = <&ioex_c0 2 GPIO_OUTPUT_LOW>; + enum-name = "IOEX_USB_C0_HBR_LS_EN"; + no-auto-init; + }; + usb_c0_hb_retimer_rst: usb-c0-hbr-rst { + gpios = <&ioex_c0 3 GPIO_OUTPUT_LOW>; + enum-name = "IOEX_USB_C0_HBR_RST"; + no-auto-init; + }; + usb_c1_hb_retimer_ls_en: usb-c1-hbr-ls-en { + gpios = <&ioex_c1 2 GPIO_OUTPUT_LOW>; + enum-name = "IOEX_USB_C1_HBR_LS_EN"; + no-auto-init; + }; + usb_c1_hb_retimer_rst: usb-c1-hbr-rst { + gpios = <&ioex_c1 3 GPIO_OUTPUT_LOW>; + enum-name = "IOEX_USB_C1_HBR_RST"; + no-auto-init; + }; + usb-c0-mux-oe-n { + gpios = <&ioex_c0 4 GPIO_OUTPUT_LOW>; + no-auto-init; + }; + usb-c0-mux-sbu-sel-0 { + gpios = <&ioex_c0 6 GPIO_OUTPUT_HIGH>; + enum-name = "IOEX_USB_C0_MUX_SBU_SEL_0"; + no-auto-init; + }; + usb-c0-mux-sbu-sel-1 { + gpios = <&ioex_c1 4 GPIO_OUTPUT_LOW>; + enum-name = "IOEX_USB_C0_MUX_SBU_SEL_1"; + no-auto-init; + }; + usb-c0-c1-prochot-n { + gpios = <&ioex_c1 6 GPIO_INPUT>; + no-auto-init; + }; + dg-bssb-sbu-sel { + gpios = <&ioex_c2_port1 4 GPIO_INPUT>; + no-auto-init; + }; + usb_c2_hb_retimer_rst: usb-c2-hbr-rst { + gpios = <&ioex_c2_port1 1 (GPIO_ODR_LOW | \ + GPIO_VOLTAGE_1P8)>; + enum-name = "IOEX_USB_C2_HBR_RST"; + no-auto-init; + }; + usb_c2_hb_retimer_ls_en: usb-c2-hbr-ls-en { + gpios = <&ioex_c2_port2 0 (GPIO_ODR_LOW | \ + GPIO_VOLTAGE_1P8)>; + enum-name = "IOEX_USB_C2_HBR_LS_EN"; + no-auto-init; + }; + usb_c3_hb_retimer_rst: usb-c3-hbr-rst { + gpios = <&ioex_c2_port1 3 (GPIO_ODR_LOW | \ + GPIO_VOLTAGE_1P8)>; + enum-name = "IOEX_USB_C3_HBR_RST"; + no-auto-init; + }; + usb_c3_hb_retimer_ls_en: usb-c3-hbr-ls-en { + gpios = <&ioex_c2_port3 3 (GPIO_ODR_LOW | \ + GPIO_VOLTAGE_1P8)>; + enum-name = "IOEX_USB_C3_HBR_LS_EN"; + no-auto-init; + }; + usb-c2-c3-prochot-n { + gpios = <&ioex_c2_port0 0 GPIO_INPUT>; + no-auto-init; + }; + /* unimplemented GPIOs */ + en-pp5000 { + enum-name = "GPIO_EN_PP5000"; + }; + }; +}; diff --git a/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/interrupts.dts b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/interrupts.dts new file mode 100644 index 0000000000..b120f6c05e --- /dev/null +++ b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/interrupts.dts @@ -0,0 +1,60 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ +/ { + gpio-interrupts { + compatible = "cros-ec,gpio-interrupts"; + + int_lid_open: lid_open { + irq-pin = <&smc_lid>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "lid_interrupt"; + }; + int_power_button: power_button { + irq-pin = <&smc_onoff_n>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "power_button_interrupt"; + }; + int_ac_present: ac_present { + irq-pin = <&bc_acok>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "extpower_interrupt"; + }; + int_ioex_kbd_intr_n: ioex_kbd_intr_n { + irq-pin = <&ioex_kbd_intr_n>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "io_expander_it8801_interrupt"; + }; + int_usb_c0_c1_tcpc: usb_c0_tcpc { + irq-pin = <&usbc_tcpc_alrt_p0>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "tcpc_alert_event"; + }; + int_usb_c0_ppc: usb_c0_ppc { + irq-pin = <&usbc_tcpc_ppc_alrt_p0>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "ppc_interrupt"; + }; + int_usb_c1_ppc: usb_c1_ppc { + irq-pin = <&usbc_tcpc_ppc_alrt_p1>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "ppc_interrupt"; + }; + int_usb_c2_tcpc: usb_c2_tcpc { + irq-pin = <&usbc_tcpc_alrt_p2>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "tcpc_alert_event"; + }; + int_usb_c3_tcpc: usb_c3_tcpc { + irq-pin = <&usbc_tcpc_alrt_p3>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "tcpc_alert_event"; + }; + int_ccd_mode: ccd_mode { + irq-pin = <&ccd_mode_odl>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "board_connect_c0_sbu"; + }; + }; +}; diff --git a/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/keyboard.dts b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/keyboard.dts new file mode 100644 index 0000000000..81d6e82f48 --- /dev/null +++ b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/keyboard.dts @@ -0,0 +1,59 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + cros-keyscan { + compatible = "cros-keyscan"; + + output-settle = <35>; + debounce-down = <5000>; + debounce-up = <40000>; + poll-timeout = <100000>; + + actual-key-mask = < + 0x14 /* C0 */ + 0xff /* C1 */ + 0xff /* C2 */ + 0xff /* C3 */ + 0xff /* C4 */ + 0xf5 /* C5 */ + 0xff /* C6 */ + 0xa4 /* C7 */ + 0xff /* C8 */ + 0xfe /* C9 */ + 0x55 /* C10 */ + 0xfa /* C11 */ + 0xca /* C12 */ + >; + }; +}; + +&cros_kb_raw { + status = "okay"; + /* No KSO2 (it's inverted and implemented by GPIO) */ + pinctrl-0 = < + &ksi0_gp31 + &ksi1_gp30 + &ksi2_gp27 + &ksi3_gp26 + &ksi4_gp25 + &ksi5_gp24 + &ksi6_gp23 + &ksi7_gp22 + &kso00_gp21 + &kso01_gp20 + &kso03_gp16 + &kso04_gp15 + &kso05_gp14 + &kso06_gp13 + &kso07_gp12 + &kso08_gp11 + &kso09_gp10 + &kso10_gp07 + &kso11_gp06 + &kso12_gp05 + >; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/mtlrvp_npcx.dts b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/mtlrvp_npcx.dts new file mode 100644 index 0000000000..86a46e3e7a --- /dev/null +++ b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/mtlrvp_npcx.dts @@ -0,0 +1,273 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + + #include <dt-bindings/usb_pd_tcpm.h> + +/ { + chosen { + cros,rtc = &mtc; + }; + + hibernate-wake-pins { + compatible = "cros-ec,hibernate-wake-pins"; + wakeup-irqs = < + &int_ac_present + &int_lid_open + &int_power_button + >; + }; + + named-i2c-ports { + compatible = "named-i2c-ports"; + + i2c_charger: charger { + i2c-port = <&i2c7_0>; + enum-names = "I2C_PORT_CHARGER", + "I2C_PORT_BATTERY", + "I2C_PORT_EEPROM", + "I2C_PORT_KB_DISCRETE", + "I2C_PORT_PORT80"; + }; + typec_aic1: typec-aic1{ + i2c-port = <&i2c0_0>; + enum-names = "I2C_PORT_TYPEC_AIC_1"; + }; + typec_aic2: typec-aic2{ + i2c-port = <&i2c1_0>; + enum-names = "I2C_PORT_TYPEC_AIC_2"; + }; + }; + + named-adc-channels { + compatible = "named-adc-channels"; + + adc_ambient: ambient { + enum-name = "ADC_TEMP_SENSOR_1"; + io-channels = <&adc0 3>; + }; + adc_ddr: ddr { + enum-name = "ADC_TEMP_SENSOR_2"; + io-channels = <&adc0 4>; + }; + adc_skin: skin { + enum-name = "ADC_TEMP_SENSOR_3"; + io-channels = <&adc0 2>; + }; + adc_vr: vr { + enum-name = "ADC_TEMP_SENSOR_4"; + io-channels = <&adc0 1>; + }; + }; +}; + +/* charger */ +&i2c7_0 { + label = "I2C_CHARGER"; + status = "okay"; + clock-frequency = <I2C_BITRATE_STANDARD>; + pinctrl-0 = <&i2c7_0_sda_scl_gpb2_b3>; + pinctrl-names = "default"; + + pca95xx: pca95xx@22 { + compatible = "nxp,pca95xx"; + label = "PCA95XX"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + }; + + rvp_board_id: rvp-board-id { + compatible = "intel,rvp-board-id"; + + /* + * BOM ID [2] : IOEX[0] + * BOM ID [1:0] : IOEX[15:14] + */ + bom-gpios = <&pca95xx 0 0>, <&pca95xx 15 0>, <&pca95xx 14 0>; + + /* + * FAB ID [1:0] : IOEX[2:1] + */ + fab-gpios = <&pca95xx 2 0>, <&pca95xx 1 0>; + + /* + * BOARD ID[5:0] : IOEX[13:8] + */ + board-gpios = <&pca95xx 13 0>, <&pca95xx 12 0>, <&pca95xx 11 0>, + <&pca95xx 10 0>, <&pca95xx 9 0>, <&pca95xx 8 0>; + }; + + kb_discrete: ite-it8801@39 { + compatible = "ite,it8801"; + reg = <0x39>; + }; + + seven_seg_display: max695x-seven-seg-display@38 { + compatible = "maxim,seven-seg-display"; + reg = <0x38>; + label = "MAX695X_SEVEN_SEG_DISPLAY"; + }; + + charger: isl9241@9 { + compatible = "intersil,isl9241"; + status = "okay"; + reg = <0x9>; + }; + + cbi_eeprom: eeprom@50 { + compatible = "atmel,at24"; + reg = <0x50>; + size = <2048>; + pagesize = <16>; + address-width = <8>; + timeout = <5>; + }; +}; + +/* host interface */ +&espi0 { + status = "okay"; + pinctrl-0 = <&espi_lpc_gp46_47_51_52_53_54_55_57>; + pinctrl-names = "default"; +}; + +&i2c_ctrl7 { + status = "okay"; +}; + +/* typec_aic1 */ +&i2c0_0 { + label = "I2C_USB_C0_C1_TCPC"; + status = "okay"; + clock-frequency = <I2C_BITRATE_FAST>; + pinctrl-0 = <&i2c0_0_sda_scl_gpb4_b5>; + pinctrl-names = "default"; + + tcpc_port0: nct38xx@73 { + compatible = "nuvoton,nct38xx"; + reg = <0x73>; + gpio-dev = <&nct38xx_c0>; + tcpc-flags = <( + TCPC_FLAGS_TCPCI_REV2_0 | + TCPC_FLAGS_NO_DEBUG_ACC_CONTROL)>; + }; + + nct38xx_c0: nct38xx_c0@73 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nuvoton,nct38xx-gpio"; + reg = <0x73>; + label = "NCT38XX_C0"; + + ioex_c0:gpio@0 { + compatible = "nuvoton,nct38xx-gpio-port"; + reg = <0x0>; + label = "NCT38XX_C0_GPIO0"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + pin_mask = <0xdc>; + pinmux_mask = <0xff>; + }; + }; + + tcpc_port1: nct38xx@77 { + compatible = "nuvoton,nct38xx"; + reg = <0x77>; + gpio-dev = <&nct38xx_c1>; + tcpc-flags = <(TCPC_FLAGS_TCPCI_REV2_0)>; + }; + + nct38xx_c1: nct38xx_c1@77 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nuvoton,nct38xx-gpio"; + reg = <0x77>; + label = "NCT38XX_C1"; + + ioex_c1:gpio@0 { + compatible = "nuvoton,nct38xx-gpio-port"; + reg = <0x0>; + label = "NCT38XX_C1_GPIO0"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + pin_mask = <0xdc>; + pinmux_mask = <0xff>; + }; + }; + + nct38xx_alert_0 { + compatible = "nuvoton,nct38xx-gpio-alert"; + irq-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>; + nct38xx-dev = <&nct38xx_c0 &nct38xx_c1>; + label = "NCT38XX_ALERT_1"; + }; + + usb_c0_hb_retimer: jhl8040r-c0@56 { + compatible = "intel,jhl8040r"; + reg = <0x56>; + reset-pin = <&usb_c0_hb_retimer_rst>; + ls-en-pin = <&usb_c0_hb_retimer_ls_en>; + }; + + usb_c1_hb_retimer: jhl8040r-c1@57 { + compatible = "intel,jhl8040r"; + reg = <0x57>; + reset-pin = <&usb_c1_hb_retimer_rst>; + ls-en-pin = <&usb_c1_hb_retimer_ls_en>; + }; +}; + +&i2c_ctrl0 { + status = "okay"; +}; + +/* typec_aic2 */ +&i2c1_0 { + label = "I2C_USB_C2_C3_TCPC"; + status = "okay"; + clock-frequency = <I2C_BITRATE_FAST>; + pinctrl-0 = <&i2c1_0_sda_scl_gp87_90>; + pinctrl-names = "default"; + + tcpc_port2: ccgxxf@b { + compatible = "cypress,ccgxxf"; + reg = <0xb>; + }; + + tcpc_port3: ccgxxf@1b { + compatible = "cypress,ccgxxf"; + reg = <0x1b>; + }; + + usb_c2_hb_retimer: jhl8040r-c2@58 { + compatible = "intel,jhl8040r"; + reg = <0x58>; + reset-pin = <&usb_c2_hb_retimer_rst>; + ls-en-pin = <&usb_c2_hb_retimer_ls_en>; + }; + + usb_c3_hb_retimer: jhl8040r-c3@59 { + compatible = "intel,jhl8040r"; + reg = <0x59>; + reset-pin = <&usb_c3_hb_retimer_rst>; + ls-en-pin = <&usb_c3_hb_retimer_ls_en>; + }; +}; + +&i2c_ctrl1 { + status = "okay"; +}; + +&adc0 { + status = "okay"; + pinctrl-0 = <&adc0_chan1_gp44 + &adc0_chan2_gp43 + &adc0_chan3_gp42 + &adc0_chan4_gp41>; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/mtlrvp_npcx_power_signals.dts b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/mtlrvp_npcx_power_signals.dts new file mode 100644 index 0000000000..3c270d296f --- /dev/null +++ b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/mtlrvp_npcx_power_signals.dts @@ -0,0 +1,125 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + chosen { + intel-ap-pwrseq,espi = &espi0; + }; + + common-pwrseq { + compatible = "intel,ap-pwrseq"; + + sys-pwrok-delay = <3>; + all-sys-pwrgd-timeout = <20>; + sys-reset-delay = <60>; + }; + + pwr-en-pp3300-s5 { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "PP3300_S5 enable output to LS"; + enum-name = "PWR_EN_PP3300_A"; + gpios = <&gpioc 4 0>; + output; + }; + pwr-pg-ec-rsmrst-od { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "RSMRST power good from regulator"; + enum-name = "PWR_RSMRST"; + gpios = <&gpio6 6 0>; + interrupt-flags = <GPIO_INT_EDGE_BOTH>; + }; + pwr-ec-pch-rsmrst-odl { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "RSMRST output to PCH"; + enum-name = "PWR_EC_PCH_RSMRST"; + gpios = <&gpioa 4 0>; + output; + }; + pwr-slp-s0-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SLP_S0_L input from PCH"; + enum-name = "PWR_SLP_S0"; + gpios = <&gpioa 1 GPIO_ACTIVE_LOW>; + interrupt-flags = <GPIO_INT_EDGE_BOTH>; + }; + pwr-pch-pwrok { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "PCH_PWROK output to PCH"; + enum-name = "PWR_PCH_PWROK"; + gpios = <&gpiod 3 GPIO_OPEN_DRAIN>; + output; + }; + pwr-ec-pch-sys-pwrok { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SYS_PWROK output to PCH"; + enum-name = "PWR_EC_PCH_SYS_PWROK"; + gpios = <&gpiof 5 GPIO_OPEN_DRAIN>; + output; + }; + pwr-sys-rst-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SYS_RESET# output to PCH"; + enum-name = "PWR_SYS_RST"; + gpios = <&gpioc 5 (GPIO_ACTIVE_LOW|GPIO_OPEN_DRAIN)>; + output; + }; + pwr-slp-s3 { + compatible = "intel,ap-pwrseq-vw"; + dbg-label = "SLP_S3 virtual wire input from PCH"; + enum-name = "PWR_SLP_S3"; + virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S3"; + vw-invert; + }; + pwr-slp-s4 { + compatible = "intel,ap-pwrseq-vw"; + dbg-label = "SLP_S4 virtual wire input from PCH"; + enum-name = "PWR_SLP_S4"; + virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S4"; + vw-invert; + }; + pwr-slp-s5 { + compatible = "intel,ap-pwrseq-vw"; + dbg-label = "SLP_S5 virtual wire input from PCH"; + enum-name = "PWR_SLP_S5"; + virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S5"; + vw-invert; + }; + pwr-all-sys-pwrgd { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "all power good"; + enum-name = "PWR_ALL_SYS_PWRGD"; + gpios = <&gpio7 0 0>; + interrupt-flags = <GPIO_INT_EDGE_BOTH>; + }; +}; + +/* + * Because the power signals directly reference the GPIOs, + * the correspinding named-gpios need to have no-auto-init set. + */ +&en_pp3300_a { + no-auto-init; +}; +&rsmrst_pwrgd { + no-auto-init; +}; +&ec_pch_rsmrst_l { + no-auto-init; +}; +&pch_slp_s0_n { + no-auto-init; +}; +&ec_pch_pwrok_od { + no-auto-init; +}; +&sys_pwrok_ec { + no-auto-init; +}; +&sys_rst_odl { + no-auto-init; +}; +&all_sys_pwrgd { + no-auto-init; +}; diff --git a/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/prj.conf b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/prj.conf new file mode 100644 index 0000000000..45b101a7ac --- /dev/null +++ b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/prj.conf @@ -0,0 +1,18 @@ +# Copyright 2022 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +CONFIG_BOARD_MTLRVP_NPCX=y +CONFIG_CROS_FLASH_NPCX=y +CONFIG_CROS_SYSTEM_NPCX=y +CONFIG_SYSCON=y + +# PWM +CONFIG_PWM=y +CONFIG_PWM_SHELL=n + +# Fan +CONFIG_TACH_NPCX=y + +#RTC +CONFIG_PLATFORM_EC_RTC=y diff --git a/zephyr/projects/intelrvp/mtlrvp/prj.conf b/zephyr/projects/intelrvp/mtlrvp/prj.conf new file mode 100644 index 0000000000..1a521d4c89 --- /dev/null +++ b/zephyr/projects/intelrvp/mtlrvp/prj.conf @@ -0,0 +1,80 @@ +# Copyright 2022 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +# Power Sequencing +CONFIG_AP_X86_INTEL_MTL=y +CONFIG_X86_NON_DSX_PWRSEQ_MTL=y +CONFIG_PLATFORM_EC_POWERSEQ_SLP_S3_L_OVERRIDE=n +CONFIG_PLATFORM_EC_POWERSEQ_PP5000_CONTROL=n + +# Battery +CONFIG_PLATFORM_EC_BATTERY_TYPE_NO_AUTO_DETECT=y +CONFIG_PLATFORM_EC_BATTERY_V2=y + +# CBI +CONFIG_EEPROM=y +CONFIG_EEPROM_AT24=y +CONFIG_EEPROM_SHELL=n +CONFIG_PLATFORM_EC_CBI_EEPROM=y +CONFIG_PLATFORM_EC_BYPASS_CBI_EEPROM_WP_CHECK=y +CONFIG_PLATFORM_EC_SYSTEM_UNLOCKED=y + +# Disable BC1.2 +CONFIG_PLATFORM_EC_USB_CHARGER=n + +# Charger +CONFIG_PLATFORM_EC_CHARGER=y +CONFIG_PLATFORM_EC_CHARGER_DISCHARGE_ON_AC=y +CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR=5 +CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR_AC=10 +CONFIG_PLATFORM_EC_CHARGE_RAMP_HW=n +CONFIG_PLATFORM_EC_CHARGER_ISL9241=y +CONFIG_PLATFORM_EC_DEDICATED_CHARGE_PORT=y + +# IOEX +CONFIG_PLATFORM_EC_IOEX_CROS_DRV=y +CONFIG_PLATFORM_EC_IOEX_CCGXXF=y +CONFIG_GPIO_PCA95XX=y +CONFIG_GPIO_NCT38XX=y +CONFIG_PLATFORM_EC_IOEX_IT8801=y + +#Keyboard from I/O expander +CONFIG_PLATFORM_EC_KEYBOARD_DISCRETE=y +CONFIG_CROS_KB_RAW_NPCX=n + +# Temperature sensors +CONFIG_PLATFORM_EC_TEMP_SENSOR=y +CONFIG_PLATFORM_EC_THERMISTOR=y +CONFIG_PLATFORM_EC_TEMP_SENSOR_POWER=y + +# USB CONFIG +CONFIG_PLATFORM_EC_USB_DRP_ACC_TRYSRC=y +CONFIG_PLATFORM_EC_USB_MUX_VIRTUAL=y +CONFIG_PLATFORM_EC_USB_MUX_TASK=y +CONFIG_PLATFORM_EC_USBC_PPC_SN5S330=y +CONFIG_PLATFORM_EC_USBC_PPC=y +CONFIG_PLATFORM_EC_USB_PD_PPC=y +CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_PPC=y +CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_TCPC=y +CONFIG_PLATFORM_EC_USB_PD_DISCHARGE_PPC=y +CONFIG_PLATFORM_EC_USB_PD_DISCHARGE_TCPC=y +CONFIG_PLATFORM_EC_USB_PD_TCPC_LOW_POWER=y +CONFIG_PLATFORM_EC_USB_PD_TCPM_TCPCI=y +CONFIG_PLATFORM_EC_USB_PD_TCPM_CCGXXF=y +CONFIG_PLATFORM_EC_USB_PD_TCPM_NCT38XX=y +CONFIG_PLATFORM_EC_USB_PD_TCPM_MUX=y +CONFIG_PLATFORM_EC_USB_PD_TRY_SRC=y +CONFIG_PLATFORM_EC_USB_PD_TCPM_SBU=y +CONFIG_PLATFORM_EC_USB_PD_DUAL_ROLE_AUTO_TOGGLE=y +CONFIG_PLATFORM_EC_USBC_RETIMER_INTEL_HB=y +CONFIG_PLATFORM_EC_USBC_VCONN=y +CONFIG_PLATFORM_EC_USB_PD_TBT_COMPAT_MODE=y +CONFIG_PLATFORM_EC_USB_PD_USB32_DRD=y +CONFIG_PLATFORM_EC_USB_PD_USB4=y +CONFIG_PLATFORM_EC_USB_PD_INT_SHARED=y +CONFIG_PLATFORM_EC_USB_PD_PORT_0_SHARED=y +CONFIG_PLATFORM_EC_USB_PD_PORT_1_SHARED=y + +# 7-Segment Display +CONFIG_PLATFORM_EC_MAX695X_SEVEN_SEGMENT_DISPLAY=y diff --git a/zephyr/projects/intelrvp/mtlrvp/src/board_power.c b/zephyr/projects/intelrvp/mtlrvp/src/board_power.c new file mode 100644 index 0000000000..301402bf0f --- /dev/null +++ b/zephyr/projects/intelrvp/mtlrvp/src/board_power.c @@ -0,0 +1,61 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <zephyr/sys/atomic.h> +#include <zephyr/logging/log.h> +#include <zephyr/drivers/gpio.h> + +#include <ap_power/ap_power.h> +#include <ap_power/ap_power_events.h> +#include <ap_power/ap_power_interface.h> +#include <ap_power_override_functions.h> +#include <power_signals.h> +#include <x86_power_signals.h> + +#include "gpio_signal.h" +#include "gpio/gpio.h" + +LOG_MODULE_DECLARE(ap_pwrseq, LOG_LEVEL_INF); + +#if CONFIG_X86_NON_DSX_PWRSEQ_MTL +#define X86_NON_DSX_MTL_FORCE_SHUTDOWN_TO_MS 50 + +void board_ap_power_force_shutdown(void) +{ + int timeout_ms = X86_NON_DSX_MTL_FORCE_SHUTDOWN_TO_MS; + + /* Turn off PCH_RMSRST to meet tPCH12 */ + power_signal_set(PWR_EC_PCH_RSMRST, 0); + + /* Turn off PRIM load switch. */ + power_signal_set(PWR_EN_PP3300_A, 0); + + /* Wait RSMRST to be off. */ + while (power_signal_get(PWR_RSMRST) && (timeout_ms > 0)) { + k_msleep(1); + timeout_ms--; + }; + + if (power_signal_get(PWR_RSMRST)) + LOG_WRN("RSMRST_ODL didn't go low! Assuming G3."); +} + +void board_ap_power_action_g3_s5(void) +{ + /* Turn on the PP3300_PRIM rail. */ + power_signal_set(PWR_EN_PP3300_A, 1); + + if (!power_wait_signals_timeout( + IN_PGOOD_ALL_CORE, + AP_PWRSEQ_DT_VALUE(wait_signal_timeout))) { + ap_power_ev_send_callbacks(AP_POWER_PRE_INIT); + } +} + +bool board_ap_power_check_power_rails_enabled(void) +{ + return power_signal_get(PWR_EN_PP3300_A); +} +#endif /* CONFIG_X86_NON_DSX_PWRSEQ_MTL */ diff --git a/zephyr/projects/intelrvp/mtlrvp/src/mtlrvp.c b/zephyr/projects/intelrvp/mtlrvp/src/mtlrvp.c new file mode 100644 index 0000000000..9d96a08712 --- /dev/null +++ b/zephyr/projects/intelrvp/mtlrvp/src/mtlrvp.c @@ -0,0 +1,331 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "battery.h" +#include "battery_fuel_gauge.h" +#include "charger.h" +#include "common.h" +#include "console.h" +#include "driver/retimer/bb_retimer_public.h" +#include "driver/tcpm/ccgxxf.h" +#include "driver/tcpm/nct38xx.h" +#include "driver/tcpm/tcpci.h" +#include "extpower.h" +#include "gpio.h" +#include "gpio/gpio_int.h" +#include "hooks.h" +#include "i2c.h" +#include "intelrvp.h" +#include "intel_rvp_board_id.h" +#include "ioexpander.h" +#include "isl9241.h" +#include "keyboard_raw.h" +#include "power/meteorlake.h" +#include "sn5s330.h" +#include "system.h" +#include "task.h" +#include "tusb1064.h" +#include "usb_mux.h" +#include "usbc_ppc.h" +#include "util.h" + +#define CPRINTF(format, args...) cprintf(CC_COMMAND, format, ##args) +#define CPRINTS(format, args...) cprints(CC_COMMAND, format, ##args) + +/*******************************************************************/ +/* USB-C Configuration Start */ + +/* PPC */ +#define I2C_ADDR_SN5S330_P0 0x40 +#define I2C_ADDR_SN5S330_P1 0x41 + +/* IOEX ports */ +enum ioex_port { + IOEX_KBD = 0, +#if defined(HAS_TASK_PD_C2) + IOEX_C2_CCGXXF, +#endif + IOEX_COUNT +}; + +/* USB-C ports */ +enum usbc_port { + USBC_PORT_C0 = 0, + USBC_PORT_C1, +#if defined(HAS_TASK_PD_C2) + USBC_PORT_C2, + USBC_PORT_C3, +#endif + USBC_PORT_COUNT +}; +BUILD_ASSERT(USBC_PORT_COUNT == CONFIG_USB_PD_PORT_MAX_COUNT); + +/* USB-C PPC configuration */ +struct ppc_config_t ppc_chips[] = { + [USBC_PORT_C0] = { + .i2c_port = I2C_PORT_TYPEC_AIC_1, + .i2c_addr_flags = I2C_ADDR_SN5S330_P0, + .drv = &sn5s330_drv, + }, + [USBC_PORT_C1] = { + .i2c_port = I2C_PORT_TYPEC_AIC_1, + .i2c_addr_flags = I2C_ADDR_SN5S330_P1, + .drv = &sn5s330_drv, + }, +}; +unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips); + +/* TCPC AIC GPIO Configuration */ +const struct tcpc_aic_gpio_config_t tcpc_aic_gpios[] = { + [USBC_PORT_C0] = { + .tcpc_alert = GPIO_SIGNAL(DT_NODELABEL(usbc_tcpc_alrt_p0)), + .ppc_alert = GPIO_SIGNAL(DT_NODELABEL(usbc_tcpc_ppc_alrt_p0)), + .ppc_intr_handler = sn5s330_interrupt, + }, + [USBC_PORT_C1] = { + .tcpc_alert = GPIO_SIGNAL(DT_NODELABEL(usbc_tcpc_alrt_p0)), + .ppc_alert = GPIO_SIGNAL(DT_NODELABEL(usbc_tcpc_ppc_alrt_p1)), + .ppc_intr_handler = sn5s330_interrupt, + }, +#if defined(HAS_TASK_PD_C2) + [USBC_PORT_C2] = { + .tcpc_alert = GPIO_SIGNAL(DT_NODELABEL(usbc_tcpc_alrt_p2)), + /* No PPC alert for CCGXXF */ + }, + [USBC_PORT_C3] = { + .tcpc_alert = GPIO_SIGNAL(DT_NODELABEL(usbc_tcpc_alrt_p3)), + /* No PPC alert for CCGXXF */ + }, +#endif +}; +BUILD_ASSERT(ARRAY_SIZE(tcpc_aic_gpios) == CONFIG_USB_PD_PORT_MAX_COUNT); + +static void board_connect_c0_sbu_deferred(void) +{ + enum pd_power_role prole; + + if (gpio_get_level(GPIO_CCD_MODE_ODL)) { + CPRINTS("Default AUX line connected"); + /* Default set the SBU lines to AUX mode */ + ioex_set_level(IOEX_USB_C0_MUX_SBU_SEL_1, 0); + ioex_set_level(IOEX_USB_C0_MUX_SBU_SEL_0, 1); + } else { + prole = pd_get_power_role(USBC_PORT_C0); + CPRINTS("%s debug device is attached", + prole == PD_ROLE_SINK ? "Servo V4C/SuzyQ" : "Intel"); + + if (prole == PD_ROLE_SINK) { + /* Set the SBU lines to Google CCD mode */ + ioex_set_level(IOEX_USB_C0_MUX_SBU_SEL_1, 1); + ioex_set_level(IOEX_USB_C0_MUX_SBU_SEL_0, 1); + } else { + /* Set the SBU lines to Intel CCD mode */ + ioex_set_level(IOEX_USB_C0_MUX_SBU_SEL_1, 0); + ioex_set_level(IOEX_USB_C0_MUX_SBU_SEL_0, 0); + } + } +} +DECLARE_DEFERRED(board_connect_c0_sbu_deferred); + +void board_overcurrent_event(int port, int is_overcurrented) +{ + /* + * TODO: Meteorlake PCH does not use Physical GPIO for over current + * error, hence Send 'Over Current Virtual Wire' eSPI signal. + */ +} + +void board_reset_pd_mcu(void) +{ + /* Reset NCT38XX TCPC */ + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(usb_c0_c1_tcpc_rst_odl), 0); + msleep(NCT38XX_RESET_HOLD_DELAY_MS); + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(usb_c0_c1_tcpc_rst_odl), 1); + nct38xx_reset_notify(0); + nct38xx_reset_notify(1); + + if (NCT3807_RESET_POST_DELAY_MS != 0) { + msleep(NCT3807_RESET_POST_DELAY_MS); + } + + /* NCT38XX chip uses gpio ioex */ + gpio_reset_port(DEVICE_DT_GET(DT_NODELABEL(ioex_c0))); + gpio_reset_port(DEVICE_DT_GET(DT_NODELABEL(ioex_c1))); + +#if defined(HAS_TASK_PD_C2) + /* Reset the ccgxxf ports only resetting 1 is required */ + ccgxxf_reset(USBC_PORT_C2); + + /* CCGXXF has ioex on port 2 */ + ioex_init(IOEX_C2_CCGXXF); +#endif +} + +void board_connect_c0_sbu(enum gpio_signal signal) +{ + hook_call_deferred(&board_connect_c0_sbu_deferred_data, 0); +} + +/******************************************************************************/ +/* KSO mapping for discrete keyboard */ +__override const uint8_t it8801_kso_mapping[] = { + 0, 1, 20, 3, 4, 5, 6, 11, 12, 13, 14, 15, 16, +}; +BUILD_ASSERT(ARRAY_SIZE(it8801_kso_mapping) == KEYBOARD_COLS_MAX); + +/* PWROK signal configuration */ +/* + * On MTLRVP, SYS_PWROK_EC is an output controlled by EC and uses ALL_SYS_PWRGD + * as input. + */ +const struct intel_x86_pwrok_signal pwrok_signal_assert_list[] = { + { + .gpio = GPIO_PCH_SYS_PWROK, + .delay_ms = 3, + }, +}; +const int pwrok_signal_assert_count = ARRAY_SIZE(pwrok_signal_assert_list); + +const struct intel_x86_pwrok_signal pwrok_signal_deassert_list[] = { + { + .gpio = GPIO_PCH_SYS_PWROK, + }, +}; +const int pwrok_signal_deassert_count = ARRAY_SIZE(pwrok_signal_deassert_list); + +/* + * Returns board information (board id[7:0] and Fab id[15:8]) on success + * -1 on error. + */ +__override int board_get_version(void) +{ + /* Cache the MTLRVP board ID */ + static int mtlrvp_board_id; + + int i; + int rv = EC_ERROR_UNKNOWN; + int fab_id, board_id, bom_id; + + /* Board ID is already read */ + if (mtlrvp_board_id) + return mtlrvp_board_id; + + /* + * IOExpander that has Board ID information is on DSW-VAL rail on + * ADL RVP. On cold boot cycles, DSW-VAL rail is taking time to settle. + * This loop retries to ensure rail is settled and read is successful + */ + for (i = 0; i < RVP_VERSION_READ_RETRY_CNT; i++) { + rv = gpio_pin_get_dt(&bom_id_config[0]); + + if (rv >= 0) + break; + + k_msleep(1); + } + + /* return -1 if failed to read board id */ + if (rv) + return -1; + + /* + * BOM ID [2] : IOEX[0] + * BOM ID [1:0] : IOEX[15:14] + */ + bom_id = gpio_pin_get_dt(&bom_id_config[0]) << 2; + bom_id |= gpio_pin_get_dt(&bom_id_config[1]) << 1; + bom_id |= gpio_pin_get_dt(&bom_id_config[2]); + /* + * FAB ID [1:0] : IOEX[2:1] + 1 + */ + fab_id = gpio_pin_get_dt(&fab_id_config[0]) << 1; + fab_id |= gpio_pin_get_dt(&fab_id_config[1]); + fab_id += 1; + + /* + * BOARD ID[5:0] : IOEX[13:8] + */ + board_id = gpio_pin_get_dt(&board_id_config[0]) << 5; + board_id |= gpio_pin_get_dt(&board_id_config[1]) << 4; + board_id |= gpio_pin_get_dt(&board_id_config[2]) << 3; + board_id |= gpio_pin_get_dt(&board_id_config[3]) << 2; + board_id |= gpio_pin_get_dt(&board_id_config[4]) << 1; + board_id |= gpio_pin_get_dt(&board_id_config[5]); + + CPRINTF("BID:0x%x, FID:0x%x, BOM:0x%x", board_id, fab_id, bom_id); + + mtlrvp_board_id = board_id | (fab_id << 8); + return mtlrvp_board_id; +} + +static void board_int_init(void) +{ + /* Enable PPC interrupts. */ + gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0_ppc)); + gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c1_ppc)); + + /* Enable TCPC interrupts. */ + gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0_c1_tcpc)); +#if defined(HAS_TASK_PD_C2) + gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c2_tcpc)); + gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c3_tcpc)); +#endif + + /* Enable CCD Mode interrupt */ + gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_ccd_mode)); +} + +static int board_pre_task_peripheral_init(const struct device *unused) +{ + ARG_UNUSED(unused); + + /* Only reset tcpc/pd if not sysjump */ + if (!system_jumped_late()) { + /* Initialize tcpc and all ioex */ + board_reset_pd_mcu(); + } + + /* Initialize all interrupts */ + board_int_init(); + + /* Make sure SBU are routed to CCD or AUX based on CCD status at init */ + board_connect_c0_sbu_deferred(); + + return 0; +} +SYS_INIT(board_pre_task_peripheral_init, APPLICATION, + CONFIG_APPLICATION_INIT_PRIORITY); + +/* + * Since MTLRVP has both PPC and TCPC ports override to check if the port + * is a PPC or non PPC port + */ +__override bool pd_check_vbus_level(int port, enum vbus_level level) +{ + if (!board_port_has_ppc(port)) { + return tcpm_check_vbus_level(port, level); + } else if (level == VBUS_PRESENT) { + return pd_snk_is_vbus_provided(port); + } else { + return !pd_snk_is_vbus_provided(port); + } +} + +__override bool board_port_has_ppc(int port) +{ + bool ppc_port; + + switch (port) { + case USBC_PORT_C0: + case USBC_PORT_C1: + ppc_port = true; + break; + default: + ppc_port = false; + break; + } + + return ppc_port; +} diff --git a/zephyr/projects/intelrvp/mtlrvp/usbc.dts b/zephyr/projects/intelrvp/mtlrvp/usbc.dts new file mode 100644 index 0000000000..e4f3bdc465 --- /dev/null +++ b/zephyr/projects/intelrvp/mtlrvp/usbc.dts @@ -0,0 +1,76 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + usbc { + #address-cells = <1>; + #size-cells = <0>; + + usbc_port0: port0@0 { + compatible = "named-usbc-port"; + reg = <0>; + tcpc = <&tcpc_port0>; + chg = <&charger>; + usb-mux-chain-0 { + compatible = "cros-ec,usb-mux-chain"; + usb-muxes = <&usb_c0_hb_retimer + &virtual_mux_c0>; + }; + }; + port0-muxes { + virtual_mux_c0: virtual-mux-c0 { + compatible = "cros-ec,usbc-mux-virtual"; + }; + }; + + usbc_port1: port1@1 { + compatible = "named-usbc-port"; + reg = <1>; + tcpc = <&tcpc_port1>; + usb-mux-chain-1 { + compatible = "cros-ec,usb-mux-chain"; + usb-muxes = <&usb_c1_hb_retimer + &virtual_mux_c1>; + }; + }; + port1-muxes { + virtual_mux_c1: virtual-mux-c1 { + compatible = "cros-ec,usbc-mux-virtual"; + }; + }; + + usbc_port2: port2@2 { + compatible = "named-usbc-port"; + reg = <2>; + tcpc = <&tcpc_port2>; + usb-mux-chain-2 { + compatible = "cros-ec,usb-mux-chain"; + usb-muxes = <&usb_c2_hb_retimer + &virtual_mux_c2>; + }; + }; + port2-muxes { + virtual_mux_c2: virtual-mux-c2 { + compatible = "cros-ec,usbc-mux-virtual"; + }; + }; + + usbc_port3: port3@3 { + compatible = "named-usbc-port"; + reg = <3>; + tcpc = <&tcpc_port3>; + usb-mux-chain-3 { + compatible = "cros-ec,usb-mux-chain"; + usb-muxes = <&usb_c3_hb_retimer + &virtual_mux_c3>; + }; + }; + port3-muxes { + virtual_mux_c3: virtual-mux-c3 { + compatible = "cros-ec,usbc-mux-virtual"; + }; + }; + }; +}; diff --git a/zephyr/projects/intelrvp/prj.conf b/zephyr/projects/intelrvp/prj.conf new file mode 100644 index 0000000000..df04eca101 --- /dev/null +++ b/zephyr/projects/intelrvp/prj.conf @@ -0,0 +1,72 @@ +# Copyright 2022 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + + +CONFIG_CROS_EC=y +CONFIG_LTO=y +CONFIG_PLATFORM_EC=y +CONFIG_PLATFORM_EC_POWER_BUTTON=y +CONFIG_PLATFORM_EC_LID_SWITCH=y +CONFIG_PLATFORM_EC_EXTPOWER_GPIO=y +CONFIG_SHIMMED_TASKS=y + +# Battery +CONFIG_PLATFORM_EC_BATTERY=y +CONFIG_PLATFORM_EC_BATTERY_CUT_OFF=y +CONFIG_PLATFORM_EC_BATTERY_FUEL_GAUGE=y +CONFIG_PLATFORM_EC_BATTERY_PRESENT_GPIO=y +CONFIG_PLATFORM_EC_BATTERY_REVIVE_DISCONNECT=y +CONFIG_PLATFORM_EC_BATTERY_SMART=y +CONFIG_PLATFORM_EC_BATTERY_TYPE_NO_AUTO_DETECT=y +CONFIG_PLATFORM_EC_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT=15000 +CONFIG_PLATFORM_EC_CHARGER_MIN_POWER_MW_FOR_POWER_ON=15001 + +#Power Sequencing +CONFIG_PLATFORM_EC_BOARD_RESET_AFTER_POWER_ON=y + +# Host command +CONFIG_PLATFORM_EC_HOSTCMD_AP_RESET=y +CONFIG_PLATFORM_EC_PORT80=y + +# USB-C and PD +CONFIG_PLATFORM_EC_USB_VID=0x18d1 +CONFIG_PLATFORM_EC_USB_PID=0x8086 +CONFIG_PLATFORM_EC_USB_PD_REQUIRE_AP_MODE_ENTRY=y + +# I2C +CONFIG_I2C=y + +# eSPI +CONFIG_ESPI=y +CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S3=y +CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S4=y +CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S5=y + +# Keyboard +CONFIG_PLATFORM_EC_KEYBOARD=y +CONFIG_PLATFORM_EC_KEYBOARD_PROTOCOL_8042=y +CONFIG_PLATFORM_EC_KEYBOARD_COL2_INVERTED=y +CONFIG_PLATFORM_EC_KEYBOARD_PWRBTN_ASSERTS_KSI2=y +CONFIG_PLATFORM_EC_VOLUME_BUTTONS=y +CONFIG_PLATFORM_EC_CMD_BUTTON=n + +# Sensors +CONFIG_SENSOR=y +CONFIG_SENSOR_SHELL=n + +# Shell Commands +CONFIG_SHELL_HELP=y +CONFIG_SHELL_HISTORY=y +CONFIG_SHELL_TAB=y +CONFIG_SHELL_TAB_AUTOCOMPLETION=y +CONFIG_KERNEL_SHELL=y + +# Logging +CONFIG_LOG=y +CONFIG_LOG_MODE_MINIMAL=y + +# TODO +# Below conf are disabled to compile successfully +# These will be enabled in upcoming CLs +CONFIG_PLATFORM_EC_BACKLIGHT_LID=n diff --git a/zephyr/projects/intelrvp/src/chg_usb_pd.c b/zephyr/projects/intelrvp/src/chg_usb_pd.c new file mode 100644 index 0000000000..63a1853b4d --- /dev/null +++ b/zephyr/projects/intelrvp/src/chg_usb_pd.c @@ -0,0 +1,129 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Common USB PD charge configuration */ + +#include "charge_manager.h" +#include "charge_state_v2.h" +#include "gpio.h" +#include "hooks.h" +#include "intelrvp.h" +#include "tcpm/tcpci.h" + +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) + +bool is_typec_port(int port) +{ +#if CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0 + return !(port == DEDICATED_CHARGE_PORT || port == CHARGE_PORT_NONE); +#else + return !(port == CHARGE_PORT_NONE); +#endif /* CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0 */ +} + +static inline int board_dc_jack_present(void) +{ +#if CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0 + return gpio_get_level(GPIO_DC_JACK_PRESENT); +#else + return 0; +#endif /* CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0 */ +} + +static void board_dc_jack_handle(void) +{ +#if CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0 + struct charge_port_info charge_dc_jack; + + /* System is booted from DC Jack */ + if (board_dc_jack_present()) { + charge_dc_jack.current = + (PD_MAX_POWER_MW * 1000) / DC_JACK_MAX_VOLTAGE_MV; + charge_dc_jack.voltage = DC_JACK_MAX_VOLTAGE_MV; + } else { + charge_dc_jack.current = 0; + charge_dc_jack.voltage = USB_CHARGER_VOLTAGE_MV; + } + + charge_manager_update_charge(CHARGE_SUPPLIER_DEDICATED, + DEDICATED_CHARGE_PORT, &charge_dc_jack); +#endif /* CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0 */ +} + +void board_dc_jack_interrupt(enum gpio_signal signal) +{ + board_dc_jack_handle(); +} + +static void board_charge_init(void) +{ + int port, supplier; + struct charge_port_info charge_init = { + .current = 0, + .voltage = USB_CHARGER_VOLTAGE_MV, + }; + + /* Initialize all charge suppliers to seed the charge manager */ + for (port = 0; port < CHARGE_PORT_COUNT; port++) { + for (supplier = 0; supplier < CHARGE_SUPPLIER_COUNT; + supplier++) { + charge_manager_update_charge(supplier, port, + &charge_init); + } + } + + board_dc_jack_handle(); +} +DECLARE_HOOK(HOOK_INIT, board_charge_init, HOOK_PRIO_DEFAULT); + +int board_set_active_charge_port(int port) +{ + int i; + /* charge port is a realy physical port */ + int is_real_port = (port >= 0 && port < CHARGE_PORT_COUNT); + /* check if we are source vbus on that port */ + int source = board_vbus_source_enabled(port); + + if (is_real_port && source) { + CPRINTS("Skip enable p%d", port); + return EC_ERROR_INVAL; + } + +#if CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0 + /* + * Do not enable Type-C port if the DC Jack is present. + * When the Type-C is active port, hardware circuit will + * block DC jack from enabling +VADP_OUT. + */ + if (port != DEDICATED_CHARGE_PORT && board_dc_jack_present()) { + CPRINTS("DC Jack present, Skip enable p%d", port); + return EC_ERROR_INVAL; + } +#endif /* CONFIG_DEDICATED_CHARGE_PORT_COUNT */ + + /* Make sure non-charging ports are disabled */ + for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) { + if (i != port) { + board_charging_enable(i, 0); + } + } + + /* Enable charging port */ + if (is_typec_port(port)) { + board_charging_enable(port, 1); + } + + CPRINTS("New chg p%d", port); + + return EC_SUCCESS; +} + +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) +{ + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); +} diff --git a/zephyr/projects/intelrvp/src/chg_usb_pd_mecc_1_1.c b/zephyr/projects/intelrvp/src/chg_usb_pd_mecc_1_1.c new file mode 100644 index 0000000000..45fbbc6f65 --- /dev/null +++ b/zephyr/projects/intelrvp/src/chg_usb_pd_mecc_1_1.c @@ -0,0 +1,92 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Intel-RVP family-specific configuration */ + +#include "console.h" +#include "gpio/gpio_int.h" +#include "hooks.h" +#include "include/gpio.h" +#include "intelrvp.h" +#include "ioexpander.h" +#include "system.h" +#include "tcpm/tcpci.h" +#include "usbc_ppc.h" + +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) + +void tcpc_alert_event(enum gpio_signal signal) +{ + int i; + + for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) { + /* No alerts for embedded TCPC */ + if (tcpc_config[i].bus_type == EC_BUS_TYPE_EMBEDDED) { + continue; + } + + if (signal == tcpc_aic_gpios[i].tcpc_alert) { + schedule_deferred_pd_interrupt(i); + break; + } + } +} + +uint16_t tcpc_get_alert_status(void) +{ + uint16_t status = 0; + int i; + + /* Check which port has the ALERT line set */ + for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) { + /* No alerts for embdeded TCPC */ + if (tcpc_config[i].bus_type == EC_BUS_TYPE_EMBEDDED) { + continue; + } + + if (!gpio_get_level(tcpc_aic_gpios[i].tcpc_alert)) { + status |= PD_STATUS_TCPC_ALERT_0 << i; + } + } + + return status; +} + +int ppc_get_alert_status(int port) +{ + return tcpc_aic_gpios[port].ppc_intr_handler && + !gpio_get_level(tcpc_aic_gpios[port].ppc_alert); +} + +/* PPC support routines */ +void ppc_interrupt(enum gpio_signal signal) +{ + int i; + + for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) { + if (tcpc_aic_gpios[i].ppc_intr_handler && + signal == tcpc_aic_gpios[i].ppc_alert) { + tcpc_aic_gpios[i].ppc_intr_handler(i); + break; + } + } +} + +void board_charging_enable(int port, int enable) +{ + int rv; + + if (tcpc_aic_gpios[port].ppc_intr_handler) { + rv = ppc_vbus_sink_enable(port, enable); + } else { + rv = tcpc_config[port].drv->set_snk_ctrl(port, enable); + } + + if (rv) { + CPRINTS("C%d: sink path %s failed", port, + enable ? "en" : "dis"); + } +} diff --git a/zephyr/projects/intelrvp/src/intel_rvp_board_id.c b/zephyr/projects/intelrvp/src/intel_rvp_board_id.c new file mode 100644 index 0000000000..77d4e93afd --- /dev/null +++ b/zephyr/projects/intelrvp/src/intel_rvp_board_id.c @@ -0,0 +1,30 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <zephyr/devicetree.h> +#include "intel_rvp_board_id.h" + +#define DT_DRV_COMPAT intel_rvp_board_id + +BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) <= 1, + "Unsupported RVP Board ID instance"); + +#define RVP_ID_GPIO_DT_SPEC_GET(idx, node_id, prop) \ + GPIO_DT_SPEC_GET_BY_IDX(node_id, prop, idx), + +#define RVP_ID_CONFIG_LIST(node_id, prop) \ + LISTIFY(DT_PROP_LEN(node_id, prop), RVP_ID_GPIO_DT_SPEC_GET, (), \ + node_id, prop) + +#if DT_HAS_COMPAT_STATUS_OKAY(DT_DRV_COMPAT) +const struct gpio_dt_spec bom_id_config[] = { RVP_ID_CONFIG_LIST(DT_DRV_INST(0), + bom_gpios) }; + +const struct gpio_dt_spec fab_id_config[] = { RVP_ID_CONFIG_LIST(DT_DRV_INST(0), + fab_gpios) }; + +const struct gpio_dt_spec board_id_config[] = { RVP_ID_CONFIG_LIST( + DT_DRV_INST(0), board_gpios) }; +#endif /* #if DT_HAS_COMPAT_STATUS_OKAY */ diff --git a/zephyr/projects/intelrvp/src/intel_rvp_led.c b/zephyr/projects/intelrvp/src/intel_rvp_led.c new file mode 100644 index 0000000000..0e4d872963 --- /dev/null +++ b/zephyr/projects/intelrvp/src/intel_rvp_led.c @@ -0,0 +1,168 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "battery.h" +#include "charge_manager.h" +#include "charge_state.h" +#include "chipset.h" +#include "common.h" +#include "console.h" +#include "ec_commands.h" +#include "extpower.h" +#include "hooks.h" +#include "led_common.h" +#include "led_pwm.h" +#include "pwm.h" +#include "timer.h" +#include "util.h" + +/* Battery percentage thresholds to blink at different rates. */ +#define LOW_BATTERY_PERCENTAGE 10 +#define NORMAL_BATTERY_PERCENTAGE 90 + +#define LED_OFF -1 + +#define LED_PULSE_TICK (125 * MSEC) + +#define LED_FAST_PULSE_PERIOD (250 / 125) /* 250 ms */ +#define LED_SLOW_PULSE_PERIOD ((2 * MSEC) / 125) /* 2 sec */ + +struct led_pulse_data { + bool led_is_pulsing; + uint8_t led_pulse_period; + uint8_t led_tick_count; +}; + +static struct led_pulse_data rvp_led[CONFIG_LED_PWM_COUNT]; + +static void pulse_led_deferred(void); +DECLARE_DEFERRED(pulse_led_deferred); + +static void pulse_led_deferred(void) +{ + int i = 0; + bool call_deferred = false; + + for (i = 0; i < CONFIG_LED_PWM_COUNT; i++) { + if (!rvp_led[i].led_is_pulsing) { + rvp_led[i].led_tick_count = 0; + continue; + } + + /* + * LED will be in ON state first half of the pulse period + * and in OFF state in second half of the pulse period. + */ + if (rvp_led[i].led_tick_count < + (rvp_led[i].led_pulse_period >> 1)) + set_pwm_led_color(i, EC_LED_COLOR_GREEN); + else + set_pwm_led_color(i, LED_OFF); + + rvp_led[i].led_tick_count = (rvp_led[i].led_tick_count + 1) % + rvp_led[i].led_pulse_period; + call_deferred = true; + } + + if (call_deferred) + hook_call_deferred(&pulse_led_deferred_data, LED_PULSE_TICK); +} + +static void pulse_leds(enum pwm_led_id id, int period) +{ + rvp_led[id].led_pulse_period = period; + rvp_led[id].led_is_pulsing = true; + + pulse_led_deferred(); +} + +static void update_charger_led(enum pwm_led_id id) +{ + enum charge_state chg_st = charge_get_state(); + + /* + * The colors listed below are the default, but can be overridden. + * + * Fast Flash = Charging error + * Slow Flash = Discharging + * LED on = Charging + * LED off = No Charger connected + */ + if (chg_st == PWR_STATE_CHARGE || + chg_st == PWR_STATE_CHARGE_NEAR_FULL) { + /* Charging: LED ON */ + rvp_led[id].led_is_pulsing = false; + set_pwm_led_color(id, EC_LED_COLOR_GREEN); + } else if (chg_st == PWR_STATE_DISCHARGE || + chg_st == PWR_STATE_DISCHARGE_FULL) { + if (extpower_is_present()) { + /* Discharging: + * Flash slower (2 second period, 100% duty cycle) + */ + pulse_leds(id, LED_SLOW_PULSE_PERIOD); + } else { + /* No Charger connected: LED OFF */ + rvp_led[id].led_is_pulsing = false; + set_pwm_led_color(id, LED_OFF); + } + } else if (chg_st == PWR_STATE_ERROR) { + /* Charging error: + * Flash faster (250 ms period, 100% duty cycle) + */ + pulse_leds(id, LED_FAST_PULSE_PERIOD); + } else { + /* LED OFF */ + rvp_led[id].led_is_pulsing = false; + set_pwm_led_color(id, LED_OFF); + } +} + +static void update_battery_led(enum pwm_led_id id) +{ + /* + * Fast Flash = Low Battery + * Slow Flash = Normal Battery + * LED on = Full Battery + * LED off = No Battery + */ + if (battery_is_present() == BP_YES) { + int batt_percentage = charge_get_percent(); + + if (batt_percentage < LOW_BATTERY_PERCENTAGE) { + /* Low Battery: + * Flash faster (250 ms period, 100% duty cycle) + */ + pulse_leds(id, LED_FAST_PULSE_PERIOD); + } else if (batt_percentage < NORMAL_BATTERY_PERCENTAGE) { + /* Normal Battery: + * Flash slower (2 second period, 100% duty cycle) + */ + pulse_leds(id, LED_SLOW_PULSE_PERIOD); + } else { + /* Full Battery: LED ON */ + rvp_led[id].led_is_pulsing = false; + set_pwm_led_color(id, EC_LED_COLOR_GREEN); + } + } else { + /* No Battery: LED OFF */ + rvp_led[id].led_is_pulsing = false; + set_pwm_led_color(id, LED_OFF); + } +} + +static void init_rvp_leds_off(void) +{ + /* Turn off LEDs such that they are in a known state with zero duty. */ + set_pwm_led_color(PWM_LED0, LED_OFF); + set_pwm_led_color(PWM_LED1, LED_OFF); +} +DECLARE_HOOK(HOOK_INIT, init_rvp_leds_off, HOOK_PRIO_POST_PWM); + +static void update_led(void) +{ + update_battery_led(PWM_LED0); + update_charger_led(PWM_LED1); +} +DECLARE_HOOK(HOOK_SECOND, update_led, HOOK_PRIO_DEFAULT); diff --git a/zephyr/projects/intelrvp/src/intelrvp.c b/zephyr/projects/intelrvp/src/intelrvp.c new file mode 100644 index 0000000000..7098f26cbf --- /dev/null +++ b/zephyr/projects/intelrvp/src/intelrvp.c @@ -0,0 +1,25 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* TODO: b/218904113: Convert to using Zephyr GPIOs */ +#include "gpio.h" +#include "hooks.h" + +static void board_init(void) +{ + /* Enable SOC SPI */ + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(ec_spi_oe_mecc), 1); +} +DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_LAST); + +__override void intel_x86_sys_reset_delay(void) +{ + /* + * From MAX6818 Data sheet, Range of 'Debounce Duaration' is + * Minimum - 20 ms, Typical - 40 ms, Maximum - 80 ms. + * See b/153128296. + */ + udelay(60 * MSEC); +} diff --git a/zephyr/projects/intelrvp/src/usb_pd_policy_mecc_1_1.c b/zephyr/projects/intelrvp/src/usb_pd_policy_mecc_1_1.c new file mode 100644 index 0000000000..a194b358f1 --- /dev/null +++ b/zephyr/projects/intelrvp/src/usb_pd_policy_mecc_1_1.c @@ -0,0 +1,106 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "console.h" +#include "gpio.h" +#include "intelrvp.h" +#include "usb_mux.h" +#include "usbc_ppc.h" + +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) + +static inline void board_pd_set_vbus_discharge(int port, bool enable) +{ + if (tcpc_aic_gpios[port].ppc_intr_handler) { + ppc_discharge_vbus(port, enable); + } else { + tcpc_discharge_vbus(port, enable); + } +} + +int pd_set_power_supply_ready(int port) +{ + int rv; + + /* Disable charging. */ + if (tcpc_aic_gpios[port].ppc_intr_handler) { + rv = ppc_vbus_sink_enable(port, 0); + } else { + rv = tcpc_config[port].drv->set_snk_ctrl(port, 0); + } + + if (rv) { + return rv; + } + + board_pd_set_vbus_discharge(port, false); + + /* Provide Vbus. */ + if (tcpc_aic_gpios[port].ppc_intr_handler) { + rv = ppc_vbus_source_enable(port, 1); + } else { + tcpc_config[port].drv->set_src_ctrl(port, 1); + } + + if (rv) { + return rv; + } + + /* Notify host of power info change. */ + pd_send_host_event(PD_EVENT_POWER_CHANGE); + + return EC_SUCCESS; +} + +void pd_power_supply_reset(int port) +{ + int prev_en; + + prev_en = board_vbus_source_enabled(port); + + /* Disable VBUS. */ + if (tcpc_aic_gpios[port].ppc_intr_handler) { + ppc_vbus_source_enable(port, 0); + } else { + tcpc_config[port].drv->set_src_ctrl(port, 0); + } + + /* Enable discharge if we were previously sourcing 5V */ + if (prev_en) { + board_pd_set_vbus_discharge(port, true); + } + + /* Notify host of power info change. */ + pd_send_host_event(PD_EVENT_POWER_CHANGE); +} + +int pd_check_vconn_swap(int port) +{ + /* Only allow vconn swap if PP3300 rail is enabled */ + return gpio_get_level(GPIO_EN_PP3300_A); +} + +int pd_snk_is_vbus_provided(int port) +{ + if (tcpc_aic_gpios[port].ppc_intr_handler) { + return ppc_is_vbus_present(port); + } else { + return tcpc_config[port].drv->check_vbus_level(port, + VBUS_PRESENT); + } +} + +int board_vbus_source_enabled(int port) +{ + if (is_typec_port(port)) { + if (tcpc_aic_gpios[port].ppc_intr_handler) { + return ppc_is_sourcing_vbus(port); + } else { + return tcpc_config[port].drv->get_src_ctrl(port); + } + } + return 0; +} diff --git a/zephyr/projects/intelrvp/zephyr_ap_pwrseq.conf b/zephyr/projects/intelrvp/zephyr_ap_pwrseq.conf new file mode 100644 index 0000000000..1ef365a8fa --- /dev/null +++ b/zephyr/projects/intelrvp/zephyr_ap_pwrseq.conf @@ -0,0 +1,9 @@ +# Copyright 2022 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +# Zephyr Inbuilt AP Power Sequencing Config +CONFIG_AP_PWRSEQ=y +CONFIG_X86_NON_DSX_PWRSEQ_CONSOLE=y +CONFIG_X86_NON_DSX_PWRSEQ_HOST_CMD=y +CONFIG_AP_PWRSEQ_S0IX=y diff --git a/zephyr/projects/it8xxx2_evb/BUILD.py b/zephyr/projects/it8xxx2_evb/BUILD.py new file mode 100644 index 0000000000..ee89c75390 --- /dev/null +++ b/zephyr/projects/it8xxx2_evb/BUILD.py @@ -0,0 +1,18 @@ +# Copyright 2021 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +"""Define zmake projects for it8xxx2_evb.""" + +register_raw_project( + project_name="it8xxx2_evb", + zephyr_board="it81302bx", + dts_overlays=[ + "adc.dts", + "fan.dts", + "gpio.dts", + "i2c.dts", + "interrupts.dts", + "pwm.dts", + ], +) diff --git a/zephyr/projects/it8xxx2_evb/CMakeLists.txt b/zephyr/projects/it8xxx2_evb/CMakeLists.txt new file mode 100644 index 0000000000..170606a52d --- /dev/null +++ b/zephyr/projects/it8xxx2_evb/CMakeLists.txt @@ -0,0 +1,11 @@ +# Copyright 2021 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +cmake_minimum_required(VERSION 3.13.1) + +find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}") +project(it8xxx2_evb) + +# Include board specific header files +zephyr_include_directories(include) diff --git a/zephyr/projects/it8xxx2_evb/adc.dts b/zephyr/projects/it8xxx2_evb/adc.dts new file mode 100644 index 0000000000..509c9b9daf --- /dev/null +++ b/zephyr/projects/it8xxx2_evb/adc.dts @@ -0,0 +1,41 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + named-adc-channels { + compatible = "named-adc-channels"; + + adc_vbussa: vbussa { + enum-name = "ADC_VBUS"; + io-channels = <&adc0 0>; + }; + adc_vbussb: vbussb { + enum-name = "ADC_PSYS"; + io-channels = <&adc0 1>; + }; + adc_evb_ch_13: evb_ch_13 { + enum-name = "ADC_AMON_BMON"; + io-channels = <&adc0 2>; + }; + adc_evb_ch_14: evb_ch_14 { + enum-name = "ADC_TEMP_SENSOR_FAN"; + io-channels = <&adc0 3>; + }; + adc_evb_ch_15: evb_ch_15 { + enum-name = "ADC_TEMP_SENSOR_DDR_SOC"; + io-channels = <&adc0 4>; + }; + adc_evb_ch_16: evb_ch_16 { + enum-name = "ADC_TEMP_SENSOR_CHARGER"; + io-channels = <&adc0 5>; + }; + }; +}; + +&adc0 { + status = "okay"; + pinctrl-0 = <&adc0_ch3_gpi3_default>; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/it8xxx2_evb/fan.dts b/zephyr/projects/it8xxx2_evb/fan.dts new file mode 100644 index 0000000000..2551507ec3 --- /dev/null +++ b/zephyr/projects/it8xxx2_evb/fan.dts @@ -0,0 +1,27 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + fans { + compatible = "cros-ec,fans"; + + fan_0 { + pwms = <&pwm7 PWM_CHANNEL_7 PWM_KHZ(30) PWM_POLARITY_NORMAL>; + tach = <&tach0>; + rpm_min = <1500>; + rpm_start = <1500>; + rpm_max = <6500>; + }; + }; +}; + +/* fan tachometer sensor */ +&tach0 { + status = "okay"; + channel = <IT8XXX2_TACH_CHANNEL_A>; + pulses-per-round = <2>; + pinctrl-0 = <&tach0a_gpd6_default>; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/it8xxx2_evb/gpio.dts b/zephyr/projects/it8xxx2_evb/gpio.dts new file mode 100644 index 0000000000..85bb45d7a0 --- /dev/null +++ b/zephyr/projects/it8xxx2_evb/gpio.dts @@ -0,0 +1,169 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <dt-bindings/gpio_defines.h> + +/ { + aliases { + gpio-wp = &gpio_wp; + }; + + named-gpios { + compatible = "named-gpios"; + + power_button_l: power_button_l { + gpios = <&gpioe 4 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_POWER_BUTTON_L"; + }; + lid_open: lid_open { + gpios = <&gpioe 2 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_LID_OPEN"; + }; + gpio_wp: wp_l { + gpios = <&gpioi 4 (GPIO_INPUT_PULL_UP | + GPIO_ACTIVE_LOW)>; + }; + pch_pltrst_l { + gpios = <&gpioe 3 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_PCH_RSMRST_L"; + }; + sys_reset_l { + gpios = <&gpiob 6 GPIO_OUTPUT_HIGH>; + enum-name = "GPIO_SYS_RESET_L"; + }; + gpio_ec_pch_wake_odl: pch_wake_l { + gpios = <&gpiob 7 GPIO_OUTPUT_HIGH>; + }; + spi0_cs: spi0_cs { + gpios = <&gpiom 5 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; + }; + /* unimplemented GPIOs */ + entering-rw { + enum-name = "GPIO_ENTERING_RW"; + }; + }; + + hibernate-wake-pins { + compatible = "cros-ec,hibernate-wake-pins"; + wakeup-irqs = <&int_power_button + &int_lid_open>; + }; + + unused-pins { + compatible = "unused-gpios"; + + unused-gpios = + /* gpioa1 */ + <&gpioa 1 GPIO_INPUT_PULL_DOWN>, + /* gpioa2 */ + <&gpioa 2 GPIO_INPUT_PULL_DOWN>, + /* gpioa3 */ + <&gpioa 3 GPIO_INPUT_PULL_DOWN>, + /* gpioa4 */ + <&gpioa 4 GPIO_INPUT_PULL_DOWN>, + /* gpioa5 */ + <&gpioa 5 GPIO_INPUT_PULL_DOWN>, + + /* gpiob2 */ + <&gpiob 2 GPIO_INPUT_PULL_DOWN>, + /* gpiob5 */ + <&gpiob 5 GPIO_INPUT_PULL_DOWN>, + + /* gpioc0 */ + <&gpioc 0 GPIO_INPUT_PULL_DOWN>, + /* gpioc4 */ + <&gpioc 4 GPIO_INPUT_PULL_DOWN>, + /* gpioc6 */ + <&gpioc 6 GPIO_INPUT_PULL_DOWN>, + /* gpioc7 */ + <&gpioc 7 GPIO_INPUT_PULL_DOWN>, + + /* gpiod0 */ + <&gpiod 0 GPIO_INPUT_PULL_DOWN>, + /* gpiod1 */ + <&gpiod 1 GPIO_INPUT_PULL_DOWN>, + /* gpiod2 */ + <&gpiod 2 GPIO_INPUT_PULL_DOWN>, + /* gpiod3 */ + <&gpiod 3 GPIO_INPUT_PULL_DOWN>, + /* gpiod4 */ + <&gpiod 4 GPIO_INPUT_PULL_DOWN>, + /* gpiod5 */ + <&gpiod 5 GPIO_INPUT_PULL_DOWN>, + /* gpiod7 */ + <&gpiod 7 GPIO_INPUT_PULL_DOWN>, + + /* gpioe1 */ + <&gpioe 1 GPIO_INPUT_PULL_DOWN>, + /* gpioe5 */ + <&gpioe 5 GPIO_INPUT_PULL_DOWN>, + /* gpioe6 */ + <&gpioe 6 GPIO_INPUT_PULL_DOWN>, + + /* gpiof0 */ + <&gpiof 0 GPIO_INPUT_PULL_DOWN>, + /* gpiof1 */ + <&gpiof 1 GPIO_INPUT_PULL_DOWN>, + /* gpiof2 */ + <&gpiof 2 GPIO_INPUT_PULL_DOWN>, + /* gpiof3 */ + <&gpiof 3 GPIO_INPUT_PULL_DOWN>, + /* gpiof4 */ + <&gpiof 4 GPIO_INPUT_PULL_DOWN>, + /* gpiof5 */ + <&gpiof 5 GPIO_INPUT_PULL_DOWN>, + + /* gpiog1 */ + <&gpiog 1 GPIO_INPUT_PULL_DOWN>, + /* gpiog6 */ + <&gpiog 6 GPIO_INPUT_PULL_UP>, + + /* gpioh0 */ + <&gpioh 0 GPIO_INPUT_PULL_DOWN>, + /* gpioh3 */ + <&gpioh 3 GPIO_INPUT_PULL_DOWN>, + /* gpioh4 */ + <&gpioh 4 GPIO_INPUT_PULL_DOWN>, + /* gpioh5 */ + <&gpioh 5 GPIO_INPUT_PULL_DOWN>, + /* gpioh6 */ + <&gpioh 6 GPIO_INPUT_PULL_DOWN>, + + /* gpioi6 */ + <&gpioi 6 GPIO_INPUT_PULL_DOWN>, + /* gpioi7 */ + <&gpioi 7 GPIO_INPUT_PULL_DOWN>, + + /* gpioj0 */ + <&gpioj 0 GPIO_INPUT_PULL_DOWN>, + /* gpioj1 */ + <&gpioj 1 GPIO_INPUT_PULL_DOWN>, + /* gpioj2 */ + <&gpioj 2 GPIO_INPUT_PULL_DOWN>, + /* gpioj3 */ + <&gpioj 3 GPIO_INPUT_PULL_DOWN>, + /* gpioj4 */ + <&gpioj 4 GPIO_INPUT_PULL_DOWN>, + /* gpioj5 */ + <&gpioj 5 GPIO_INPUT_PULL_DOWN>, + /* gpioj6 */ + <&gpioj 6 GPIO_OUTPUT_LOW>, + /* gpioj7 */ + <&gpioj 7 GPIO_OUTPUT_LOW>, + + /* gpiom0 */ + <&gpiom 0 GPIO_INPUT_PULL_DOWN>, + /* gpiom1 */ + <&gpiom 1 GPIO_INPUT_PULL_DOWN>, + /* gpiom2 */ + <&gpiom 2 GPIO_INPUT_PULL_DOWN>, + /* gpiom3 */ + <&gpiom 3 GPIO_INPUT_PULL_DOWN>, + /* gpiom4 */ + <&gpiom 4 GPIO_INPUT_PULL_DOWN>, + /* gpiom6 */ + <&gpiom 6 GPIO_INPUT_PULL_DOWN>; + }; +}; diff --git a/zephyr/projects/it8xxx2_evb/i2c.dts b/zephyr/projects/it8xxx2_evb/i2c.dts new file mode 100644 index 0000000000..c08c543e44 --- /dev/null +++ b/zephyr/projects/it8xxx2_evb/i2c.dts @@ -0,0 +1,59 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + named-i2c-ports { + compatible = "named-i2c-ports"; + + battery { + i2c-port = <&i2c2>; + enum-names = "I2C_PORT_BATTERY"; + }; + evb-1 { + i2c-port = <&i2c0>; + enum-names = "I2C_PORT_EVB_1"; + }; + evb-2 { + i2c-port = <&i2c1>; + enum-names = "I2C_PORT_EVB_2"; + }; + opt-4 { + i2c-port = <&i2c4>; + enum-names = "I2C_PORT_OPT_4"; + }; + }; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <I2C_BITRATE_STANDARD>; + pinctrl-0 = <&i2c0_clk_gpb3_default + &i2c0_data_gpb4_default>; + pinctrl-names = "default"; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <I2C_BITRATE_STANDARD>; + pinctrl-0 = <&i2c1_clk_gpc1_default + &i2c1_data_gpc2_default>; + pinctrl-names = "default"; +}; + +&i2c2 { + status = "okay"; + clock-frequency = <I2C_BITRATE_STANDARD>; + pinctrl-0 = <&i2c2_clk_gpf6_default + &i2c2_data_gpf7_default>; + pinctrl-names = "default"; +}; + +&i2c4 { + status = "okay"; + clock-frequency = <I2C_BITRATE_STANDARD>; + pinctrl-0 = <&i2c4_clk_gpe0_default + &i2c4_data_gpe7_default>; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/it8xxx2_evb/include/i2c_map.h b/zephyr/projects/it8xxx2_evb/include/i2c_map.h new file mode 100644 index 0000000000..e83a238d3a --- /dev/null +++ b/zephyr/projects/it8xxx2_evb/include/i2c_map.h @@ -0,0 +1,16 @@ +/* Copyright 2021 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#ifndef __ZEPHYR_CHROME_I2C_MAP_H +#define __ZEPHYR_CHROME_I2C_MAP_H + +#include <zephyr/devicetree.h> + +#include "config.h" + +/* We need registers.h to get the chip specific defines for now */ +#include "i2c/i2c.h" + +#endif /* __ZEPHYR_CHROME_I2C_MAP_H */ diff --git a/zephyr/projects/it8xxx2_evb/interrupts.dts b/zephyr/projects/it8xxx2_evb/interrupts.dts new file mode 100644 index 0000000000..07fc0ed339 --- /dev/null +++ b/zephyr/projects/it8xxx2_evb/interrupts.dts @@ -0,0 +1,26 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + gpio-interrupts { + compatible = "cros-ec,gpio-interrupts"; + + int_power_button: power_button { + irq-pin = <&power_button_l>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "power_button_interrupt"; + }; + int_lid_open: lid_open { + irq-pin = <&lid_open>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "lid_interrupt"; + }; + int_spi0_cs: spi0_cs { + irq-pin = <&spi0_cs>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "spi_event"; + }; + }; +}; diff --git a/zephyr/projects/it8xxx2_evb/prj.conf b/zephyr/projects/it8xxx2_evb/prj.conf new file mode 100644 index 0000000000..d6d422e490 --- /dev/null +++ b/zephyr/projects/it8xxx2_evb/prj.conf @@ -0,0 +1,44 @@ +# Copyright 2021 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +CONFIG_CROS_EC=y +CONFIG_PLATFORM_EC=y +CONFIG_SHIMMED_TASKS=y + +# SoC configuration +CONFIG_AP=y +CONFIG_AP_ARM_MTK_MT8192=y + +# Lid switch +CONFIG_PLATFORM_EC_LID_SWITCH=y + +# Logging +CONFIG_LOG=y + +# Fan +CONFIG_SENSOR=y + +# I2C +CONFIG_I2C=y + +# PWM +CONFIG_PWM=y +CONFIG_PWM_SHELL=n + +# Power Button +CONFIG_PLATFORM_EC_POWER_BUTTON=y + +# TODO(b:185202623): bring these features up +CONFIG_PLATFORM_EC_BACKLIGHT_LID=n +CONFIG_PLATFORM_EC_BOARD_VERSION_CBI=n +CONFIG_PLATFORM_EC_BOARD_VERSION_GPIO=n +CONFIG_PLATFORM_EC_KEYBOARD=n +CONFIG_CROS_KB_RAW_ITE=n +CONFIG_PLATFORM_EC_SWITCH=n +CONFIG_PLATFORM_EC_VBOOT_EFS2=n +CONFIG_PLATFORM_EC_VBOOT_HASH=n + +# USB-C +CONFIG_PLATFORM_EC_USB_PD_TBT_COMPAT_MODE=n +CONFIG_PLATFORM_EC_USB_PD_USB4=n diff --git a/zephyr/projects/it8xxx2_evb/pwm.dts b/zephyr/projects/it8xxx2_evb/pwm.dts new file mode 100644 index 0000000000..c566e5c029 --- /dev/null +++ b/zephyr/projects/it8xxx2_evb/pwm.dts @@ -0,0 +1,31 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + pwmleds { + compatible = "pwm-leds"; + + /* NOTE: &pwm number needs same with channel number */ + pwm_led_test: pwm_led_test { + pwms = <&pwm0 PWM_CHANNEL_0 PWM_MSEC(20) PWM_POLARITY_NORMAL>; + }; + }; +}; + +/* pwm for test */ +&pwm0 { + status = "okay"; + prescaler-cx = <PWM_PRESCALER_C6>; + pinctrl-0 = <&pwm0_gpa0_default>; + pinctrl-names = "default"; +}; + +/* pwm for fan */ +&pwm7 { + status = "okay"; + prescaler-cx = <PWM_PRESCALER_C4>; + pinctrl-0 = <&pwm7_gpa7_default>; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/minimal/BUILD.py b/zephyr/projects/minimal/BUILD.py new file mode 100644 index 0000000000..5e892aa2d7 --- /dev/null +++ b/zephyr/projects/minimal/BUILD.py @@ -0,0 +1,22 @@ +# Copyright 2022 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +"""Minimal example project.""" + +register_host_project( + project_name="minimal-posix", + zephyr_board="native_posix", +) + +register_npcx_project( + project_name="minimal-npcx9", + zephyr_board="npcx9m3f", + dts_overlays=[here / "npcx9.dts"], +) + +register_binman_project( + project_name="minimal-it8xxx2", + zephyr_board="it81302bx", + dts_overlays=[here / "it8xxx2.dts"], +) diff --git a/zephyr/projects/minimal/CMakeLists.txt b/zephyr/projects/minimal/CMakeLists.txt new file mode 100644 index 0000000000..de3bec9428 --- /dev/null +++ b/zephyr/projects/minimal/CMakeLists.txt @@ -0,0 +1,9 @@ +# Copyright 2022 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +cmake_minimum_required(VERSION 3.20.5) +find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}") +project(ec) + +zephyr_include_directories("${CMAKE_CURRENT_SOURCE_DIR}/include") diff --git a/zephyr/projects/minimal/README.md b/zephyr/projects/minimal/README.md new file mode 100644 index 0000000000..72c092dfce --- /dev/null +++ b/zephyr/projects/minimal/README.md @@ -0,0 +1,32 @@ +# Minimal Example Zephyr EC Project + +This directory is intended to be an extremely minimal example of a +project. Should you like, you can use it as a bring up a new program, +or as reference as you require. + +If you're bringing up a new variant of a program, you don't need a +whole project directory with a `BUILD.py` and all, and this example is +likely not of use to you. Check out the [project config +documentation] for instructions on adding a new variant. + +[project config documentation]: ../../../docs/zephyr/project_config.md + +# Building + +To build the `native_posix` example, run: + +``` shellsession +(chroot) $ zmake build minimal-posix +``` + +To build the NPCX9 example, run: + +``` shellsession +(chroot) $ zmake build minimal-npcx9 +``` + +For the IT8XXX2 example, run: + +``` shellsession +(chroot) $ zmake build minimal-it8xxx2 +``` diff --git a/zephyr/projects/minimal/it8xxx2.dts b/zephyr/projects/minimal/it8xxx2.dts new file mode 100644 index 0000000000..3d2028afb2 --- /dev/null +++ b/zephyr/projects/minimal/it8xxx2.dts @@ -0,0 +1,22 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + aliases { + gpio-wp = &ec_wp_l; + }; + + named-gpios { + compatible = "named-gpios"; + + ec_wp_l: write-protect { + gpios = <&gpioa 0 GPIO_INPUT>; + }; + /* unimplemented GPIOs */ + entering-rw { + enum-name = "GPIO_ENTERING_RW"; + }; + }; +}; diff --git a/zephyr/projects/minimal/npcx9.dts b/zephyr/projects/minimal/npcx9.dts new file mode 100644 index 0000000000..3a9f3b26e4 --- /dev/null +++ b/zephyr/projects/minimal/npcx9.dts @@ -0,0 +1,28 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + aliases { + gpio-wp = &ec_wp_l; + }; + + named-gpios { + compatible = "named-gpios"; + + ec_wp_l: write-protect { + gpios = <&gpioa 0 GPIO_INPUT>; + }; + /* unimplemented GPIOs */ + entering-rw { + enum-name = "GPIO_ENTERING_RW"; + }; + }; +}; + +&cros_kb_raw { + status = "okay"; + pinctrl-0 = <>; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/minimal/prj.conf b/zephyr/projects/minimal/prj.conf new file mode 100644 index 0000000000..db7cac0cef --- /dev/null +++ b/zephyr/projects/minimal/prj.conf @@ -0,0 +1,18 @@ +# Copyright 2022 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +CONFIG_PLATFORM_EC=y +CONFIG_CROS_EC=y +CONFIG_SHIMMED_TASKS=y +CONFIG_SYSCON=y + +# Disable default features we don't want in a minimal example. +CONFIG_ADC=n +CONFIG_I2C=n +CONFIG_PWM=n +CONFIG_PLATFORM_EC_BACKLIGHT_LID=n +CONFIG_PLATFORM_EC_KEYBOARD=n +CONFIG_PLATFORM_EC_POWER_BUTTON=n +CONFIG_PLATFORM_EC_SWITCH=n +CONFIG_PLATFORM_EC_VBOOT_EFS2=n diff --git a/zephyr/projects/nissa/BUILD.py b/zephyr/projects/nissa/BUILD.py new file mode 100644 index 0000000000..b1affe7b4c --- /dev/null +++ b/zephyr/projects/nissa/BUILD.py @@ -0,0 +1,66 @@ +# Copyright 2021 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +"""Define zmake projects for nissa.""" + +# Nivviks and Craask, Pujjo, Xivu has NPCX993F, Nereid and Joxer, Yaviks has ITE81302 + + +def register_nissa_project( + project_name, + chip="it81302bx", +): + """Register a variant of nissa.""" + register_func = register_binman_project + if chip.startswith("npcx"): + register_func = register_npcx_project + + chip_kconfig = {"it81302bx": "it8xxx2", "npcx9m3f": "npcx"}[chip] + + return register_func( + project_name=project_name, + zephyr_board=chip, + dts_overlays=[here / project_name / "project.overlay"], + kconfig_files=[ + here / "program.conf", + here / f"{chip_kconfig}_program.conf", + here / project_name / "project.conf", + ], + ) + + +nivviks = register_nissa_project( + project_name="nivviks", + chip="npcx9m3f", +) + +nereid = register_nissa_project( + project_name="nereid", + chip="it81302bx", +) + +craask = register_nissa_project( + project_name="craask", + chip="npcx9m3f", +) + +pujjo = register_nissa_project( + project_name="pujjo", + chip="npcx9m3f", +) + +xivu = register_nissa_project( + project_name="xivu", + chip="npcx9m3f", +) + +joxer = register_nissa_project( + project_name="joxer", + chip="it81302bx", +) + +yaviks = register_nissa_project( + project_name="yaviks", + chip="it81302bx", +) diff --git a/zephyr/projects/nissa/CMakeLists.txt b/zephyr/projects/nissa/CMakeLists.txt new file mode 100644 index 0000000000..8769af58ba --- /dev/null +++ b/zephyr/projects/nissa/CMakeLists.txt @@ -0,0 +1,84 @@ +# Copyright 2021 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +cmake_minimum_required(VERSION 3.13.1) + +find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}") + +zephyr_include_directories(include) +zephyr_library_sources("src/common.c") +zephyr_library_sources("src/sub_board.c") +zephyr_library_sources_ifdef(CONFIG_AP_PWRSEQ "src/board_power.c") + +if(DEFINED CONFIG_BOARD_NIVVIKS) + project(nivviks) + zephyr_library_sources( + "nivviks/src/led.c" + "nivviks/src/form_factor.c" + "nivviks/src/keyboard.c" + ) + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_FAN "nivviks/src/fan.c") + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "nivviks/src/usbc.c") + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER "nivviks/src/charger.c") +endif() +if(DEFINED CONFIG_BOARD_NEREID) + project(nereid) + zephyr_library_sources( + "src/led.c" + "nereid/src/keyboard.c" + "nereid/src/hdmi.c" + ) + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "nereid/src/usbc.c") + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER "nereid/src/charger.c") +endif() +if(DEFINED CONFIG_BOARD_CRAASK) + zephyr_library_sources( + "craask/src/form_factor.c" + "craask/src/keyboard.c" + "craask/src/led.c" + ) + project(craask) + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "craask/src/usbc.c") + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER "craask/src/charger.c") +endif() +if(DEFINED CONFIG_BOARD_PUJJO) + project(pujjo) + zephyr_library_sources( + "pujjo/src/led.c" + "pujjo/src/keyboard.c" + "pujjo/src/hdmi.c" + "pujjo/src/form_factor.c" + ) + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_FAN "pujjo/src/fan.c") + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "pujjo/src/usbc.c") + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER "pujjo/src/charger.c") +endif() +if(DEFINED CONFIG_BOARD_XIVU) + project(xivu) + zephyr_library_sources( + "xivu/src/keyboard.c" + ) + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "xivu/src/usbc.c") + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER "xivu/src/charger.c") +endif() +if(DEFINED CONFIG_BOARD_JOXER) + project(joxer) + zephyr_library_sources( + "joxer/src/led.c" + "joxer/src/keyboard.c" + ) + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "joxer/src/usbc.c") + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER "joxer/src/charger.c") + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_FAN "joxer/src/fan.c") +endif() +if(DEFINED CONFIG_BOARD_YAVIKS) + project(yaviks) + zephyr_library_sources( + "yaviks/src/led.c" + "yaviks/src/keyboard.c" + ) + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "yaviks/src/usbc.c") + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER "yaviks/src/charger.c") + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_FAN "yaviks/src/fan.c") +endif()
\ No newline at end of file diff --git a/zephyr/projects/nissa/Kconfig b/zephyr/projects/nissa/Kconfig new file mode 100644 index 0000000000..9e9ffc2528 --- /dev/null +++ b/zephyr/projects/nissa/Kconfig @@ -0,0 +1,52 @@ +# Copyright 2021 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +config BOARD_NIVVIKS + bool "Google Nivviks Board" + help + Build Google Nivviks reference board. Nivviks has Intel ADL-N SoC + with NPCX993FA0BX EC. + +config BOARD_NEREID + bool "Google Nereid Board" + help + Build Google Nereid reference board. Nereid has Intel ADL-N SoC + with IT81302 EC. + +config BOARD_CRAASK + bool "Google Craask Board" + help + Build Google Craask board. Craask has Intel ADL-N SoC + with NPCX993FA0BX EC. + +config BOARD_PUJJO + bool "Google Pujjo Board" + help + Build Google Pujjo board. Pujjo has Intel ADL-N SoC + with NPCX993FA0BX EC. + +config BOARD_XIVU + bool "Google Xivu Board" + help + Build Google Xivu board. Xivu has Intel ADL-N SoC + with NPCX993FA0BX EC. + +config BOARD_JOXER + bool "Google Joxer Board" + help + Build Google Joxer reference board. Joxer has Intel ADL-N SoC + with IT81302 EC. + +config BOARD_YAVIKS + bool "Google Yaviks Board" + help + Build Google Yaviks board. Yaviks has Intel ADL-N SoC + with IT81302 EC. + + +module = NISSA +module-str = Nissa board-specific code +source "subsys/logging/Kconfig.template.log_config" + +source "Kconfig.zephyr" diff --git a/zephyr/projects/nissa/cbi.dtsi b/zephyr/projects/nissa/cbi.dtsi new file mode 100644 index 0000000000..d841be1624 --- /dev/null +++ b/zephyr/projects/nissa/cbi.dtsi @@ -0,0 +1,61 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + nissa-fw-config { + compatible = "cros-ec,cbi-fw-config"; + + /* + * FW_CONFIG field to indicate which sub-board + * is attached. + */ + sub-board { + enum-name = "FW_SUB_BOARD"; + start = <0>; + size = <2>; + + sub-board-1 { + compatible = "cros-ec,cbi-fw-config-value"; + enum-name = "FW_SUB_BOARD_1"; + value = <1>; + }; + sub-board-2 { + compatible = "cros-ec,cbi-fw-config-value"; + enum-name = "FW_SUB_BOARD_2"; + value = <2>; + }; + sub-board-3 { + compatible = "cros-ec,cbi-fw-config-value"; + enum-name = "FW_SUB_BOARD_3"; + value = <3>; + }; + }; + + /* + * FW_CONFIG field to enable fan or not. + */ + fan { + enum-name = "FW_FAN"; + start = <2>; + size = <1>; + + no-fan { + compatible = "cros-ec,cbi-fw-config-value"; + enum-name = "FW_FAN_NOT_PRESENT"; + value = <0>; + }; + fan-present { + compatible = "cros-ec,cbi-fw-config-value"; + enum-name = "FW_FAN_PRESENT"; + value = <1>; + /* + * Set as default so that unprovisioned + * configs will run the fan regardless. + */ + default; + }; + }; + }; +}; diff --git a/zephyr/projects/nissa/craask/cbi.dtsi b/zephyr/projects/nissa/craask/cbi.dtsi new file mode 100644 index 0000000000..4c2e052f4d --- /dev/null +++ b/zephyr/projects/nissa/craask/cbi.dtsi @@ -0,0 +1,107 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + /* Craask-specific fw_config fields. */ + nissa-fw-config { + /* + * FW_CONFIG field to describe Lid sensor orientation. + */ + lid-inversion { + enum-name = "FW_LID_INVERSION"; + start = <8>; + size = <1>; + + /* + * 0: regular placement of the lid sensor + * 1: rotate 180' of xy plane. + */ + regular { + compatible = "cros-ec,cbi-fw-config-value"; + enum-name = "FW_LID_REGULAR"; + value = <0>; + default; + }; + xy_rotate_180 { + compatible = "cros-ec,cbi-fw-config-value"; + enum-name = "FW_LID_XY_ROT_180"; + value = <1>; + }; + }; + /* + * FW_CONFIG field to describe Clamshell/Convertible. + */ + form_factor { + enum-name = "FORM_FACTOR"; + start = <9>; + size = <1>; + + /* + * 0: convertible, 1: clamshell + */ + convertible { + compatible = "cros-ec,cbi-fw-config-value"; + enum-name = "CONVERTIBLE"; + value = <0>; + }; + clamshell { + compatible = "cros-ec,cbi-fw-config-value"; + enum-name = "CLAMSHELL"; + value = <1>; + }; + }; + }; + /* Craask-specific ssfc fields. */ + cbi-ssfc { + compatible = "named-cbi-ssfc"; + /* + * SSFC bit0-1 was defined for AUDIO CODEC. + * 0: ALC5682I_VS + * 1: NAU8825 + */ + audio_codec { + enum-name = "AUDIO_CODEC"; + size = <2>; + }; + /* + * SSFC field to identify LID motion sensor. + */ + lid-sensor { + enum-name = "LID_SENSOR"; + size = <2>; + + lid_sensor_0: lis2dw12 { + compatible = "named-cbi-ssfc-value"; + status = "okay"; + value = <0>; + default; + }; + lid_sensor_1: bma422 { + compatible = "named-cbi-ssfc-value"; + status = "okay"; + value = <1>; + }; + }; + /* + * SSFC field to identify BASE motion sensor. + */ + base-sensor { + enum-name = "BASE_SENSOR"; + size = <2>; + + base_sensor_0: lsm6dso { + compatible = "named-cbi-ssfc-value"; + status = "okay"; + value = <0>; + default; + }; + base_sensor_1: bmi323 { + compatible = "named-cbi-ssfc-value"; + status = "okay"; + value = <1>; + }; + }; + }; +}; diff --git a/zephyr/projects/nissa/craask/generated.dtsi b/zephyr/projects/nissa/craask/generated.dtsi new file mode 100644 index 0000000000..4303bbd4c5 --- /dev/null +++ b/zephyr/projects/nissa/craask/generated.dtsi @@ -0,0 +1,288 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + + named-adc-channels { + compatible = "named-adc-channels"; + + adc_ec_vsense_pp1050_proc: ec_vsense_pp1050_proc { + enum-name = "ADC_PP1050_PROC"; + io-channels = <&adc0 4>; + }; + adc_ec_vsense_pp3300_s5: ec_vsense_pp3300_s5 { + enum-name = "ADC_PP3300_S5"; + io-channels = <&adc0 6>; + }; + adc_temp_sensor_1: temp_sensor_1 { + enum-name = "ADC_TEMP_SENSOR_1"; + io-channels = <&adc0 0>; + }; + adc_temp_sensor_2: temp_sensor_2 { + enum-name = "ADC_TEMP_SENSOR_2"; + io-channels = <&adc0 1>; + }; + adc_temp_sensor_3: temp_sensor_3 { + enum-name = "ADC_TEMP_SENSOR_3"; + io-channels = <&adc0 10>; + }; + }; + + named-gpios { + compatible = "named-gpios"; + + gpio_acc_int_l: acc_int_l { + gpios = <&gpio5 0 GPIO_INPUT>; + }; + gpio_all_sys_pwrgd: all_sys_pwrgd { + gpios = <&gpioa 7 GPIO_INPUT>; + }; + gpio_ccd_mode_odl: ccd_mode_odl { + gpios = <&gpioe 5 GPIO_INPUT>; + enum-name = "GPIO_CCD_MODE_ODL"; + }; + gpio_cpu_c10_gate_l: cpu_c10_gate_l { + gpios = <&gpio6 7 GPIO_INPUT>; + }; + gpio_ec_battery_pres_odl: ec_battery_pres_odl { + gpios = <&gpioa 3 GPIO_INPUT>; + enum-name = "GPIO_BATT_PRES_ODL"; + }; + gpio_ec_cbi_wp: ec_cbi_wp { + gpios = <&gpio7 4 GPIO_OUTPUT>; + }; + gpio_ec_edp_bl_en_od: ec_edp_bl_en_od { + gpios = <&gpiod 3 GPIO_ODR_HIGH>; + enum-name = "GPIO_ENABLE_BACKLIGHT"; + }; + gpio_ec_entering_rw: ec_entering_rw { + gpios = <&gpio0 3 GPIO_OUTPUT>; + enum-name = "GPIO_ENTERING_RW"; + }; + gpio_ec_gsc_packet_mode: ec_gsc_packet_mode { + gpios = <&gpio7 5 GPIO_OUTPUT>; + enum-name = "GPIO_PACKET_MODE_EN"; + }; + gpio_ec_kso_02_inv: ec_kso_02_inv { + gpios = <&gpio1 7 (GPIO_OUTPUT | GPIO_ACTIVE_LOW)>; + }; + gpio_ec_pch_wake_odl: ec_pch_wake_odl { + gpios = <&gpiob 0 GPIO_ODR_LOW>; + }; + gpio_ec_prochot_odl: ec_prochot_odl { + gpios = <&gpiof 1 GPIO_ODR_HIGH>; + }; + gpio_ec_soc_dsw_pwrok: ec_soc_dsw_pwrok { + gpios = <&gpio6 1 GPIO_OUTPUT>; + }; + gpio_ec_soc_hdmi_hpd: ec_soc_hdmi_hpd { + gpios = <&gpioe 4 GPIO_OUTPUT>; + }; + gpio_ec_soc_int_odl: ec_soc_int_odl { + gpios = <&gpio8 0 GPIO_ODR_HIGH>; + enum-name = "GPIO_EC_INT_L"; + }; + gpio_ec_soc_pch_pwrok_od: ec_soc_pch_pwrok_od { + gpios = <&gpio7 2 GPIO_ODR_HIGH>; + }; + gpio_ec_soc_pwr_btn_odl: ec_soc_pwr_btn_odl { + gpios = <&gpioc 1 GPIO_ODR_HIGH>; + enum-name = "GPIO_PCH_PWRBTN_L"; + }; + gpio_ec_soc_rsmrst_l: ec_soc_rsmrst_l { + gpios = <&gpioa 6 GPIO_OUTPUT>; + }; + gpio_ec_soc_rtcrst: ec_soc_rtcrst { + gpios = <&gpio7 6 GPIO_OUTPUT>; + }; + gpio_ec_soc_sys_pwrok: ec_soc_sys_pwrok { + gpios = <&gpio3 7 GPIO_OUTPUT>; + }; + gpio_ec_soc_vccst_pwrgd_od: ec_soc_vccst_pwrgd_od { + gpios = <&gpioa 4 GPIO_ODR_HIGH>; + }; + gpio_ec_wp_odl: ec_wp_odl { + gpios = <&gpioa 1 (GPIO_INPUT | GPIO_ACTIVE_LOW)>; + }; + gpio_en_kb_bl: en_kb_bl { + gpios = <&gpioa 0 GPIO_OUTPUT>; + enum-name = "GPIO_EN_KEYBOARD_BACKLIGHT"; + }; + gpio_en_pp3300_s5: en_pp3300_s5 { + gpios = <&gpiob 6 GPIO_OUTPUT>; + enum-name = "GPIO_TEMP_SENSOR_POWER"; + }; + gpio_en_pp5000_pen_x: en_pp5000_pen_x { + gpios = <&gpioe 2 GPIO_OUTPUT>; + }; + gpio_en_pp5000_s5: en_pp5000_s5 { + gpios = <&gpio4 0 GPIO_OUTPUT>; + }; + gpio_en_slp_z: en_slp_z { + gpios = <&gpioe 1 GPIO_OUTPUT>; + }; + gpio_en_usb_a0_vbus: en_usb_a0_vbus { + gpios = <&gpio9 1 GPIO_OUTPUT>; + }; + gpio_gsc_ec_pwr_btn_odl: gsc_ec_pwr_btn_odl { + gpios = <&gpio0 0 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_POWER_BUTTON_L"; + }; + gpio_hdmi_sel: hdmi_sel { + gpios = <&gpioc 6 GPIO_OUTPUT>; + }; + gpio_imu_int_l: imu_int_l { + gpios = <&gpio5 6 GPIO_INPUT>; + }; + gpio_imvp91_vrrdy_od: imvp91_vrrdy_od { + gpios = <&gpio4 3 GPIO_INPUT>; + }; + gpio_lid_open: lid_open { + gpios = <&gpiod 2 GPIO_INPUT>; + enum-name = "GPIO_LID_OPEN"; + }; + gpio_pen_detect_odl: pen_detect_odl { + gpios = <&gpio9 6 GPIO_INPUT_PULL_UP>; + }; + gpio_pg_pp1050_mem_s3_od: pg_pp1050_mem_s3_od { + gpios = <&gpiof 0 GPIO_INPUT>; + }; + gpio_pg_pp5000_s5_od: pg_pp5000_s5_od { + gpios = <&gpio4 2 GPIO_INPUT>; + }; + gpio_rsmrst_pwrgd_l: rsmrst_pwrgd_l { + gpios = <&gpio9 4 GPIO_INPUT_PULL_UP>; + }; + gpio_slp_s0_l: slp_s0_l { + gpios = <&gpio9 7 GPIO_INPUT>; + }; + gpio_slp_s3_l: slp_s3_l { + gpios = <&gpioa 5 GPIO_INPUT>; + }; + gpio_slp_s4_l: slp_s4_l { + gpios = <&gpio7 0 GPIO_INPUT>; + }; + gpio_slp_sus_l: slp_sus_l { + gpios = <&gpio6 2 GPIO_INPUT>; + }; + gpio_sub_usb_a1_ilimit_sdp: sub_usb_a1_ilimit_sdp { + gpios = <&gpiod 5 GPIO_OUTPUT>; + enum-name = "GPIO_USB2_ILIM_SEL"; + }; + gpio_sys_rst_odl: sys_rst_odl { + gpios = <&gpioc 5 GPIO_ODR_HIGH>; + }; + gpio_tablet_mode_l: tablet_mode_l { + gpios = <&gpio9 5 GPIO_INPUT>; + enum-name = "GPIO_TABLET_MODE_L"; + }; + gpio_usb_a0_ilimit_sdp: usb_a0_ilimit_sdp { + gpios = <&gpio8 5 GPIO_OUTPUT>; + enum-name = "GPIO_USB1_ILIM_SEL"; + }; + gpio_usb_c0_int_odl: usb_c0_int_odl { + gpios = <&gpio0 1 GPIO_INPUT_PULL_UP>; + }; + gpio_vccin_aux_vid0: vccin_aux_vid0 { + gpios = <&gpio9 2 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; + }; + gpio_vccin_aux_vid1: vccin_aux_vid1 { + gpios = <&gpioe 3 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; + }; + gpio_voldn_btn_odl: voldn_btn_odl { + gpios = <&gpio9 3 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_VOLUME_DOWN_L"; + }; + gpio_volup_btn_odl: volup_btn_odl { + gpios = <&gpioa 2 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_VOLUME_UP_L"; + }; + }; + + named-i2c-ports { + compatible = "named-i2c-ports"; + + i2c_ec_i2c_eeprom: ec_i2c_eeprom { + i2c-port = <&i2c0_0>; + enum-names = "I2C_PORT_EEPROM"; + }; + i2c_ec_i2c_sensor: ec_i2c_sensor { + i2c-port = <&i2c1_0>; + enum-names = "I2C_PORT_SENSOR"; + }; + i2c_ec_i2c_usb_c0: ec_i2c_usb_c0 { + i2c-port = <&i2c3_0>; + enum-names = "I2C_PORT_USB_C0_TCPC"; + }; + i2c_ec_i2c_sub_usb_c1: ec_i2c_sub_usb_c1 { + i2c-port = <&i2c5_1>; + enum-names = "I2C_PORT_USB_C1_TCPC"; + }; + i2c_ec_i2c_batt: ec_i2c_batt { + i2c-port = <&i2c7_0>; + enum-names = "I2C_PORT_BATTERY"; + }; + }; +}; + +&adc0 { + status = "okay"; + pinctrl-0 = <&adc0_chan0_gp45 + &adc0_chan1_gp44 + &adc0_chan4_gp41 + &adc0_chan6_gp34 + &adc0_chan10_gpe0>; + pinctrl-names = "default"; +}; + +&i2c0_0 { + status = "okay"; + pinctrl-0 = <&i2c0_0_sda_scl_gpb4_b5>; + pinctrl-names = "default"; +}; + +&i2c1_0 { + status = "okay"; + pinctrl-0 = <&i2c1_0_sda_scl_gp87_90>; + pinctrl-names = "default"; +}; + +&i2c3_0 { + status = "okay"; + pinctrl-0 = <&i2c3_0_sda_scl_gpd0_d1>; + pinctrl-names = "default"; +}; + +&i2c5_1 { + status = "okay"; + pinctrl-0 = <&i2c5_1_sda_scl_gpf4_f5>; + pinctrl-names = "default"; +}; + +&i2c7_0 { + status = "okay"; + pinctrl-0 = <&i2c7_0_sda_scl_gpb2_b3>; + pinctrl-names = "default"; +}; + +&i2c_ctrl0 { + status = "okay"; +}; + +&i2c_ctrl1 { + status = "okay"; +}; + +&i2c_ctrl3 { + status = "okay"; +}; + +&i2c_ctrl5 { + status = "okay"; +}; + +&i2c_ctrl7 { + status = "okay"; +}; diff --git a/zephyr/projects/nissa/craask/keyboard.dtsi b/zephyr/projects/nissa/craask/keyboard.dtsi new file mode 100644 index 0000000000..f9e46de1f2 --- /dev/null +++ b/zephyr/projects/nissa/craask/keyboard.dtsi @@ -0,0 +1,32 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +&cros_kb_raw { + status = "okay"; + /* No KSO2 (it's inverted and implemented by GPIO) */ + pinctrl-0 = < + &ksi0_gp31 + &ksi1_gp30 + &ksi2_gp27 + &ksi3_gp26 + &ksi4_gp25 + &ksi5_gp24 + &ksi6_gp23 + &ksi7_gp22 + &kso00_gp21 + &kso01_gp20 + &kso03_gp16 + &kso04_gp15 + &kso05_gp14 + &kso06_gp13 + &kso07_gp12 + &kso08_gp11 + &kso09_gp10 + &kso10_gp07 + &kso11_gp06 + &kso12_gp05 + >; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/nissa/craask/motionsense.dtsi b/zephyr/projects/nissa/craask/motionsense.dtsi new file mode 100644 index 0000000000..448aed6991 --- /dev/null +++ b/zephyr/projects/nissa/craask/motionsense.dtsi @@ -0,0 +1,257 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <dt-bindings/motionsense/utils.h> + + +/ { + aliases { + /* + * Interrupt bindings for sensor devices. + */ + lsm6dso-int = &base_accel; + lis2dw12-int = &lid_accel; + bmi3xx-int = &base_accel; + }; + + /* + * Declare mutexes used by sensor drivers. + * A mutex node is used to create an instance of mutex_t. + * A mutex node is referenced by a sensor node if the + * corresponding sensor driver needs to use the + * instance of the mutex. + */ + motionsense-mutex { + compatible = "cros-ec,motionsense-mutex"; + lid_mutex: lis2dw12-mutex { + }; + + lid_mutex_bma422: bma422-mutex { + }; + + base_mutex: base-mutex { + }; + + base_mutex_bmi323: bmi323-mutex { + }; + }; + + /* Rotation matrix used by drivers. */ + motionsense-rotation-ref { + compatible = "cros-ec,motionsense-rotation-ref"; + lid_rot_ref: lid-rotation-ref { + mat33 = <(-1) 0 0 + 0 1 0 + 0 0 (-1)>; + }; + + base_rot_ref: base-rotation-ref { + mat33 = <1 0 0 + 0 (-1) 0 + 0 0 (-1)>; + }; + + base_rot_ver1: base-rotation-ver1 { + mat33 = <(-1) 0 0 + 0 (-1) 0 + 0 0 1>; + }; + + lid_rot_bma422: lid-rotation-bma { + mat33 = <1 0 0 + 0 (-1) 0 + 0 0 (-1)>; + }; + + base_rot_bmi323: base-rotation-bmi323 { + mat33 = <1 0 0 + 0 (-1) 0 + 0 0 (-1)>; + }; + }; + + /* + * Driver specific data. A driver-specific data can be shared with + * different motion sensors while they are using the same driver. + * + * If a node's compatible starts with "cros-ec,accelgyro-", it is for + * a common structure defined in accelgyro.h. + * e.g) compatible = "cros-ec,accelgyro-als-drv-data" is for + * "struct als_drv_data_t" in accelgyro.h + */ + motionsense-sensor-data { + lsm6dso_accel_data: lsm6dso-accel-drv-data { + compatible = "cros-ec,drvdata-lsm6dso"; + status = "okay"; + }; + + lsm6dso_gyro_data: lsm6dso-gyro-drv-data { + compatible = "cros-ec,drvdata-lsm6dso"; + status = "okay"; + }; + + lis2dw12_data: lis2dw12-drv-data { + compatible = "cros-ec,drvdata-lis2dw12"; + status = "okay"; + }; + + bma422_data: bma4xx-drv-data { + compatible = "cros-ec,drvdata-bma4xx"; + status = "okay"; + }; + + bmi323_data: bmi323-drv-data { + compatible = "cros-ec,drvdata-bmi3xx"; + status = "okay"; + }; + }; + + /* + * List of motion sensors that creates motion_sensors array. + * The nodelabel "lid_accel" and "base_accel" are used to indicate + * motion sensor IDs for lid angle calculation. + * TODO(b/238139272): The first entries of the array must be + * accelerometers,then gyroscope. Fix this dependency in the DTS + * processing which makes the devicetree entries independent. + */ + motionsense-sensor { + lid_accel: lid-accel { + compatible = "cros-ec,lis2dw12"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_LID"; + mutex = <&lid_mutex>; + port = <&i2c_ec_i2c_sensor>; + rot-standard-ref = <&lid_rot_ref>; + default-range = <2>; + drv-data = <&lis2dw12_data>; + i2c-spi-addr-flags = "LIS2DWL_ADDR0_FLAGS"; + configs { + compatible = + "cros-ec,motionsense-sensor-config"; + ec-s0 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + ec-s3 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + }; + }; + + base_accel: base-accel { + compatible = "cros-ec,lsm6dso-accel"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_BASE"; + mutex = <&base_mutex>; + port = <&i2c_ec_i2c_sensor>; + rot-standard-ref = <&base_rot_ref>; + drv-data = <&lsm6dso_accel_data>; + configs { + compatible = + "cros-ec,motionsense-sensor-config"; + ec-s0 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + ec-s3 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + }; + }; + + base_gyro: base-gyro { + compatible = "cros-ec,lsm6dso-gyro"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_BASE"; + mutex = <&base_mutex>; + port = <&i2c_ec_i2c_sensor>; + rot-standard-ref = <&base_rot_ref>; + default-range = <(1000 | ROUND_UP_FLAG)>; /* dps */ + drv-data = <&lsm6dso_gyro_data>; + }; + }; + + motionsense-sensor-alt { + alt_lid_accel: alt-lid-accel { + compatible = "cros-ec,bma4xx"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_LID"; + mutex = <&lid_mutex_bma422>; + port = <&i2c_ec_i2c_sensor>; + rot-standard-ref = <&lid_rot_bma422>; + default-range = <2>; + drv-data = <&bma422_data>; + i2c-spi-addr-flags = "BMA4_I2C_ADDR_PRIMARY"; + alternate-for = <&lid_accel>; + alternate-ssfc-indicator = <&lid_sensor_1>; + configs { + compatible = + "cros-ec,motionsense-sensor-config"; + ec-s0 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + ec-s3 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + }; + }; + + alt_base_accel: alt-base-accel { + compatible = "cros-ec,bmi3xx-accel"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_BASE"; + mutex = <&base_mutex_bmi323>; + port = <&i2c_ec_i2c_sensor>; + rot-standard-ref = <&base_rot_bmi323>; + drv-data = <&bmi323_data>; + alternate-for = <&base_accel>; + alternate-ssfc-indicator = <&base_sensor_1>; + configs { + compatible = + "cros-ec,motionsense-sensor-config"; + ec-s0 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + ec-s3 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + }; + }; + + alt_base_gyro: alt-base-gyro { + compatible = "cros-ec,bmi3xx-gyro"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_BASE"; + mutex = <&base_mutex_bmi323>; + port = <&i2c_ec_i2c_sensor>; + rot-standard-ref = <&base_rot_bmi323>; + drv-data = <&bmi323_data>; + alternate-for = <&base_gyro>; + alternate-ssfc-indicator = <&base_sensor_1>; + }; + }; + + motionsense-sensor-info { + compatible = "cros-ec,motionsense-sensor-info"; + + /* + * list of GPIO interrupts that have to + * be enabled at initial stage + */ + sensor-irqs = <&int_imu>; + /* list of sensors in force mode */ + accel-force-mode-sensors = <&lid_accel>; + }; +}; diff --git a/zephyr/projects/nissa/craask/overlay.dtsi b/zephyr/projects/nissa/craask/overlay.dtsi new file mode 100644 index 0000000000..b3a510c111 --- /dev/null +++ b/zephyr/projects/nissa/craask/overlay.dtsi @@ -0,0 +1,360 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <cros/thermistor/thermistor.dtsi> + +/ { + aliases { + gpio-cbi-wp = &gpio_ec_cbi_wp; + gpio-wp = &gpio_ec_wp_odl; + int-wp = &int_wp_l; + gpio-kbd-kso2 = &gpio_ec_kso_02_inv; + }; + + ec-console { + compatible = "ec-console"; + disabled = "events", "lpc", "hostcmd"; + }; + + batteries { + default_battery: lgc { + compatible = "lgc,ap18c8k", "battery-smart"; + }; + cosmx { + compatible = "cosmx,ap20cbl", "battery-smart"; + }; + cosmx-2 { + compatible = "cosmx,ap20cbl-2", "battery-smart"; + }; + }; + + hibernate-wake-pins { + compatible = "cros-ec,hibernate-wake-pins"; + wakeup-irqs = < + &int_power_button + &int_lid_open + >; + }; + + gpio-interrupts { + compatible = "cros-ec,gpio-interrupts"; + + int_power_button: power_button { + irq-pin = <&gpio_gsc_ec_pwr_btn_odl>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "power_button_interrupt"; + }; + int_wp_l: wp_l { + irq-pin = <&gpio_ec_wp_odl>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "switch_interrupt"; + }; + int_lid_open: lid_open { + irq-pin = <&gpio_lid_open>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "lid_interrupt"; + }; + int_tablet_mode: tablet_mode { + irq-pin = <&gpio_tablet_mode_l>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "gmr_tablet_switch_isr"; + }; + int_imu: ec_imu { + irq-pin = <&gpio_imu_int_l>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "motion_interrupt"; + }; + int_vol_down: vol_down { + irq-pin = <&gpio_voldn_btn_odl>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "button_interrupt"; + }; + int_vol_up: vol_up { + irq-pin = <&gpio_volup_btn_odl>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "button_interrupt"; + }; + int_usb_c0: usb_c0 { + irq-pin = <&gpio_usb_c0_int_odl>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "usb_interrupt"; + }; + int_usb_c1: usb_c1 { + irq-pin = <&gpio_sb_1>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "usb_interrupt"; + }; + }; + + named-gpios { + gpio_sb_1: sb-1 { + gpios = <&gpio0 2 GPIO_PULL_UP>; + no-auto-init; + }; + + gpio_sb_2: sb-2 { + gpios = <&gpiod 4 GPIO_OUTPUT>; + no-auto-init; + }; + + /* + * Set I2C pins for type C sub-board to be low voltage (I2C5_1). + * We do this for all boards, since the pins are 3.3V tolerant, + * and the only 2 types of sub-boards used on nivviks both have + * type-C ports on them. + */ + gpio_sb_3: sb-3 { + gpios = <&gpiof 4 (GPIO_OPEN_DRAIN | GPIO_VOLTAGE_1P8)>; + no-auto-init; + }; + gpio_sb_4: sb-4 { + gpios = <&gpiof 5 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; + no-auto-init; + }; + ec-i2c-sensor-scl { + gpios = <&gpio9 0 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; + }; + ec-i2c-sensor-sda { + gpios = <&gpio8 7 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; + }; + }; + + /* + * Aliases used for sub-board GPIOs. + */ + aliases { + /* + * Input GPIO when used with type-C port 1 + * Output when used with HDMI sub-board + */ + gpio-usb-c1-int-odl = &gpio_sb_1; + gpio-en-rails-odl = &gpio_sb_1; + /* + * Sub-board with type A USB, enable. + */ + gpio-en-usb-a1-vbus = &gpio_sb_2; + /* + * HPD pins for HDMI sub-board. + */ + gpio-hdmi-en-odl = &gpio_sb_3; + gpio-hpd-odl = &gpio_sb_4; + /* + * Enable S5 rails for LTE sub-board + */ + gpio-en-sub-s5-rails = &gpio_sb_2; + }; + + temp_memory: memory { + compatible = "cros-ec,temp-sensor-thermistor"; + thermistor = <&thermistor_3V3_51K1_47K_4050B>; + adc = <&adc_temp_sensor_1>; + }; + temp_charger: charger { + compatible = "cros-ec,temp-sensor-thermistor"; + thermistor = <&thermistor_3V3_51K1_47K_4050B>; + adc = <&adc_temp_sensor_2>; + }; + temp_ambient: ambient { + compatible = "cros-ec,temp-sensor-thermistor"; + thermistor = <&thermistor_3V3_51K1_47K_4050B>; + adc = <&adc_temp_sensor_3>; + }; + + named-temp-sensors { + compatible = "cros-ec,temp-sensors"; + memory { + temp_fan_off = <35>; + temp_fan_max = <60>; + temp_host_high = <85>; + temp_host_halt = <90>; + temp_host_release_high = <80>; + power-good-pin = <&gpio_ec_soc_dsw_pwrok>; + sensor = <&temp_memory>; + }; + charger { + temp_fan_off = <35>; + temp_fan_max = <60>; + temp_host_high = <85>; + temp_host_halt = <90>; + temp_host_release_high = <80>; + power-good-pin = <&gpio_ec_soc_dsw_pwrok>; + sensor = <&temp_charger>; + }; + ambient { + temp_fan_off = <35>; + temp_fan_max = <60>; + temp_host_high = <85>; + temp_host_halt = <90>; + temp_host_release_high = <80>; + power-good-pin = <&gpio_ec_soc_dsw_pwrok>; + sensor = <&temp_ambient>; + }; + }; + + usba { + compatible = "cros-ec,usba-port-enable-pins"; + /* + * sb_2 is only configured as GPIO when USB-A1 is present, + * but it's still safe to control when disabled. + * + * ILIM_SEL pins are referred to by legacy enum name, + * GPIO_USB*_ILIM_SEL. The one for port A1 is unused on + * sub-boards that don't have USB-A so is safe to control + * regardless of system configuration. + */ + enable-pins = <&gpio_en_usb_a0_vbus &gpio_sb_2>; + status = "okay"; + }; + + usbc { + #address-cells = <1>; + #size-cells = <0>; + + port0@0 { + compatible = "named-usbc-port"; + reg = <0>; + bc12 = <&bc12_port0>; + chg = <&chg_port0>; + usb-mux-chain-0 { + compatible = "cros-ec,usb-mux-chain"; + usb-muxes = <&virtual_mux_0>; + }; + }; + port0-muxes { + virtual_mux_0: virtual-mux-0 { + compatible = "cros-ec,usbc-mux-virtual"; + }; + }; + /* + * TODO(b:211693800): port1 may not be present on some + * sub-boards. + */ + port1@1 { + compatible = "named-usbc-port"; + reg = <1>; + bc12 = <&bc12_port1>; + chg = <&chg_port1>; + usb-mux-chain-1 { + compatible = "cros-ec,usb-mux-chain"; + usb-muxes = <&virtual_mux_1 &anx7483_mux_1>; + }; + usb_mux_chain_1_no_mux: usb-mux-chain-1-no-mux { + compatible = "cros-ec,usb-mux-chain"; + alternative-chain; + usb-muxes = <&virtual_mux_1>; + }; + }; + port1-muxes { + virtual_mux_1: virtual-mux-1 { + compatible = "cros-ec,usbc-mux-virtual"; + }; + }; + }; + + kblight { + compatible = "cros-ec,kblight-pwm"; + pwms = <&pwm6 6 PWM_HZ(2400) PWM_POLARITY_NORMAL>; + }; +}; + +&thermistor_3V3_51K1_47K_4050B { + status = "okay"; +}; + +&adc_ec_vsense_pp3300_s5 { + /* + * Voltage divider on input has 47k upper and 220k lower legs with + * 2714 mV full-scale reading on the ADC. Apply the largest possible + * multiplier (without overflowing int32) to get the best possible + * approximation of the actual ratio, but derate by a factor of two to + * ensure unexpectedly high values won't overflow. + */ + mul = <(791261 / 2)>; + div = <(651975 / 2)>; +}; + +/* Set bus speeds for I2C */ +&i2c0_0 { + label = "I2C_EEPROM"; + clock-frequency = <I2C_BITRATE_FAST>; + + cbi_eeprom: eeprom@50 { + compatible = "atmel,at24"; + reg = <0x50>; + size = <2048>; + pagesize = <16>; + address-width = <8>; + timeout = <5>; + }; +}; + +&i2c1_0 { + label = "I2C_SENSOR"; + clock-frequency = <I2C_BITRATE_FAST>; +}; + +&i2c3_0 { + label = "I2C_USB_C0_TCPC"; + clock-frequency = <I2C_BITRATE_FAST_PLUS>; + + bc12_port0: pi3usb9201@5f { + compatible = "pericom,pi3usb9201"; + status = "okay"; + reg = <0x5f>; + /* + * BC1.2 interrupt is shared with TCPC, so + * IRQ is not specified here and handled by + * usb_c0_interrupt. + */ + }; + + chg_port0: isl923x@9 { + compatible = "intersil,isl923x"; + status = "okay"; + reg = <0x9>; + }; +}; + +&i2c5_1 { + label = "I2C_SUB_C1_TCPC"; + clock-frequency = <I2C_BITRATE_FAST_PLUS>; + + bc12_port1: pi3usb9201@5f { + compatible = "pericom,pi3usb9201"; + status = "okay"; + reg = <0x5f>; + }; + + chg_port1: isl923x@9 { + compatible = "intersil,isl923x"; + status = "okay"; + reg = <0x9>; + }; + + anx7483_mux_1: anx7483-mux-1@3e { + compatible = "analogix,anx7483"; + reg = <0x3e>; + board-set = "anx7483_set_default_tuning"; + }; +}; + +&i2c7_0 { + label = "I2C_BATTERY"; + clock-frequency = <I2C_BITRATE_STANDARD>; +}; + +&pwm6 { + status = "okay"; + clock-bus = "NPCX_CLOCK_BUS_LFCLK"; + pinctrl-0 = <&pwm6_gpc0>; + pinctrl-names = "default"; +}; + +/* host interface */ +&espi0 { + status = "okay"; + pinctrl-0 = <&espi_lpc_gp46_47_51_52_53_54_55_57>; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/nissa/craask/power_signals.dtsi b/zephyr/projects/nissa/craask/power_signals.dtsi new file mode 100644 index 0000000000..1d2b23069d --- /dev/null +++ b/zephyr/projects/nissa/craask/power_signals.dtsi @@ -0,0 +1,220 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + chosen { + intel-ap-pwrseq,espi = &espi0; + }; + + common-pwrseq { + compatible = "intel,ap-pwrseq"; + + sys-pwrok-delay = <10>; + all-sys-pwrgd-timeout = <20>; + }; + + pwr-en-pp5000-s5 { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "PP5000_S5 enable output to regulator"; + enum-name = "PWR_EN_PP5000_A"; + gpios = <&gpio4 0 0>; + output; + }; + pwr-en-pp3300-s5 { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "PP3300_S5 enable output to LS"; + enum-name = "PWR_EN_PP3300_A"; + gpios = <&gpiob 6 0>; + output; + }; + pwr-pg-ec-rsmrst-od { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "RSMRST power good from regulator"; + enum-name = "PWR_RSMRST"; + gpios = <&gpio9 4 0>; + interrupt-flags = <GPIO_INT_EDGE_BOTH>; + }; + pwr-ec-pch-rsmrst-odl { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "RSMRST output to PCH"; + enum-name = "PWR_EC_PCH_RSMRST"; + gpios = <&gpioa 6 0>; + output; + }; + pwr-slp-s0-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SLP_S0_L input from PCH"; + enum-name = "PWR_SLP_S0"; + gpios = <&gpio9 7 GPIO_ACTIVE_LOW>; + interrupt-flags = <GPIO_INT_EDGE_BOTH>; + }; + pwr-slp-s3-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SLP_S3_L input from PCH"; + enum-name = "PWR_SLP_S3"; + gpios = <&gpioa 5 GPIO_ACTIVE_LOW>; + interrupt-flags = <GPIO_INT_EDGE_BOTH>; + }; + pwr-slp-sus-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SLP_SUS_L input from PCH"; + enum-name = "PWR_SLP_SUS"; + gpios = <&gpio6 2 GPIO_ACTIVE_LOW>; + interrupt-flags = <GPIO_INT_EDGE_BOTH>; + }; + pwr-ec-soc-dsw-pwrok { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "DSW_PWROK output to PCH"; + enum-name = "PWR_EC_SOC_DSW_PWROK"; + gpios = <&gpio6 1 0>; + output; + }; + pwr-vccst-pwrgd-od { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "VCCST_PWRGD output to PCH"; + enum-name = "PWR_VCCST_PWRGD"; + gpios = <&gpioa 4 GPIO_OPEN_DRAIN>; + output; + }; + pwr-imvp9-vrrdy-od { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "VRRDY input from IMVP9"; + enum-name = "PWR_IMVP9_VRRDY"; + gpios = <&gpio4 3 0>; + }; + pwr-pch-pwrok { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "PCH_PWROK output to PCH"; + enum-name = "PWR_PCH_PWROK"; + gpios = <&gpio7 2 GPIO_OPEN_DRAIN>; + output; + }; + pwr-ec-pch-sys-pwrok { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SYS_PWROK output to PCH"; + enum-name = "PWR_EC_PCH_SYS_PWROK"; + gpios = <&gpio3 7 0>; + output; + }; + pwr-sys-rst-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SYS_RESET# output to PCH"; + enum-name = "PWR_SYS_RST"; + gpios = <&gpioc 5 (GPIO_ACTIVE_LOW|GPIO_OPEN_DRAIN)>; + output; + }; + pwr-slp-s4 { + compatible = "intel,ap-pwrseq-vw"; + dbg-label = "SLP_S4 virtual wire input from PCH"; + enum-name = "PWR_SLP_S4"; + virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S4"; + vw-invert; + }; + pwr-slp-s5 { + compatible = "intel,ap-pwrseq-vw"; + dbg-label = "SLP_S5 virtual wire input from PCH"; + enum-name = "PWR_SLP_S5"; + virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S5"; + vw-invert; + }; + pwr-all-sys-pwrgd { + compatible = "intel,ap-pwrseq-external"; + dbg-label = "Combined all power good"; + enum-name = "PWR_ALL_SYS_PWRGD"; + }; + pwr-adc-pp3300 { + compatible = "intel,ap-pwrseq-adc"; + dbg-label = "PP3300 PWROK (from ADC)"; + enum-name = "PWR_DSW_PWROK"; + trigger-high = <&cmp_pp3300_s5_high>; + trigger-low = <&cmp_pp3300_s5_low>; + }; + pwr-adc-pp1p05 { + compatible = "intel,ap-pwrseq-adc"; + dbg-label = "PP1P05 PWROK (from ADC)"; + enum-name = "PWR_PG_PP1P05"; + trigger-high = <&cmp_pp1p05_high>; + trigger-low = <&cmp_pp1p05_low>; + }; + + adc-cmp { + cmp_pp3300_s5_high: pp3300_high { + compatible = "nuvoton,adc-cmp"; + io-channels = <&adc0 6>; + comparison = "ADC_CMP_NPCX_GREATER"; + /* + * This is 90% of nominal voltage considering voltage + * divider on ADC input. + */ + threshold-mv = <2448>; + }; + cmp_pp3300_s5_low: pp3300_low { + compatible = "nuvoton,adc-cmp"; + io-channels = <&adc0 6>; + comparison = "ADC_CMP_NPCX_LESS_OR_EQUAL"; + threshold-mv = <2448>; + }; + cmp_pp1p05_high: pp1p05_high { + compatible = "nuvoton,adc-cmp"; + io-channels = <&adc0 4>; + comparison = "ADC_CMP_NPCX_GREATER"; + /* Setting at 90% of nominal voltage */ + threshold-mv = <945>; + }; + cmp_pp1p05_low: pp1p05_low { + compatible = "nuvoton,adc-cmp"; + io-channels = <&adc0 4>; + comparison = "ADC_CMP_NPCX_LESS_OR_EQUAL"; + threshold-mv = <945>; + }; + }; +}; + +/* + * Because the power signals directly reference the GPIOs, + * the correspinding named-gpios need to have no-auto-init set. + */ +&gpio_ec_soc_dsw_pwrok { + no-auto-init; +}; +&gpio_ec_soc_pch_pwrok_od { + no-auto-init; +}; +&gpio_ec_soc_rsmrst_l { + no-auto-init; +}; +&gpio_ec_soc_sys_pwrok { + no-auto-init; +}; +&gpio_ec_soc_vccst_pwrgd_od { + no-auto-init; +}; +&gpio_en_pp3300_s5 { + no-auto-init; +}; +&gpio_en_pp5000_s5 { + no-auto-init; +}; +&gpio_imvp91_vrrdy_od { + no-auto-init; +}; +&gpio_rsmrst_pwrgd_l { + no-auto-init; +}; +&gpio_slp_s0_l { + no-auto-init; +}; +&gpio_slp_s3_l { + no-auto-init; +}; +&gpio_slp_s4_l { + no-auto-init; +}; +&gpio_slp_sus_l { + no-auto-init; +}; +&gpio_sys_rst_odl { + no-auto-init; +}; diff --git a/zephyr/projects/nissa/craask/project.conf b/zephyr/projects/nissa/craask/project.conf new file mode 100644 index 0000000000..b7f31cee63 --- /dev/null +++ b/zephyr/projects/nissa/craask/project.conf @@ -0,0 +1,15 @@ +# Copyright 2022 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +CONFIG_BOARD_CRAASK=y +CONFIG_PLATFORM_EC_OCPC=y + +# Sensor drivers +CONFIG_PLATFORM_EC_ACCELGYRO_LSM6DSO=y +CONFIG_PLATFORM_EC_ACCEL_BMA4XX=y +CONFIG_PLATFORM_EC_ACCELGYRO_BMI_COMM_I2C=y +CONFIG_PLATFORM_EC_ACCELGYRO_BMI3XX=y +CONFIG_PLATFORM_EC_DYNAMIC_MOTION_SENSOR_COUNT=y + +CONFIG_PLATFORM_EC_BUTTONS_RUNTIME_CONFIG=y diff --git a/zephyr/projects/nissa/craask/project.overlay b/zephyr/projects/nissa/craask/project.overlay new file mode 100644 index 0000000000..9ca681d979 --- /dev/null +++ b/zephyr/projects/nissa/craask/project.overlay @@ -0,0 +1,14 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "../cbi.dtsi" + +#include "cbi.dtsi" +#include "generated.dtsi" +#include "keyboard.dtsi" +#include "motionsense.dtsi" +#include "overlay.dtsi" +#include "power_signals.dtsi" +#include "pwm_leds.dtsi" diff --git a/zephyr/projects/nissa/craask/pwm_leds.dtsi b/zephyr/projects/nissa/craask/pwm_leds.dtsi new file mode 100644 index 0000000000..e55aa1c9ef --- /dev/null +++ b/zephyr/projects/nissa/craask/pwm_leds.dtsi @@ -0,0 +1,62 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + pwmleds { + compatible = "pwm-leds"; + pwm_led0: pwm_led_0 { + pwms = <&pwm2 2 PWM_HZ(324) PWM_POLARITY_INVERTED>, + <&pwm0 0 PWM_HZ(324) PWM_POLARITY_INVERTED>, + <&pwm1 1 PWM_HZ(324) PWM_POLARITY_INVERTED>; + }; + }; + + cros-pwmleds { + compatible = "cros-ec,pwm-leds"; + + leds = <&pwm_led0>; + + /*<red green blue>*/ + color-map-red = <100 0 0>; + color-map-green = < 0 100 0>; + color-map-blue = < 0 0 100>; + color-map-yellow = < 0 50 50>; + color-map-white = <100 100 100>; + color-map-amber = < 90 10 0>; + + brightness-range = <100 100 100 0 0 0>; + + #address-cells = <1>; + #size-cells = <0>; + + pwm_led_0@0 { + reg = <0>; + ec-led-name = "EC_LED_ID_BATTERY_LED"; + }; + }; +}; + +/* Enable LEDs to work while CPU suspended */ + +&pwm0 { + status = "okay"; + clock-bus = "NPCX_CLOCK_BUS_LFCLK"; + pinctrl-0 = <&pwm0_gpc3>; + pinctrl-names = "default"; +}; + +&pwm1 { + status = "okay"; + clock-bus = "NPCX_CLOCK_BUS_LFCLK"; + pinctrl-0 = <&pwm1_gpc2>; + pinctrl-names = "default"; +}; + +&pwm2 { + status = "okay"; + clock-bus = "NPCX_CLOCK_BUS_LFCLK"; + pinctrl-0 = <&pwm2_gpc4>; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/nissa/craask/src/charger.c b/zephyr/projects/nissa/craask/src/charger.c new file mode 100644 index 0000000000..d4723e4a0a --- /dev/null +++ b/zephyr/projects/nissa/craask/src/charger.c @@ -0,0 +1,56 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <zephyr/logging/log.h> + +#include "battery.h" +#include "charger.h" +#include "charger/isl923x_public.h" +#include "console.h" +#include "extpower.h" +#include "usb_pd.h" +#include "nissa_common.h" + +LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL); + +int extpower_is_present(void) +{ + int port; + int rv; + bool acok; + + for (port = 0; port < board_get_usb_pd_port_count(); port++) { + rv = raa489000_is_acok(port, &acok); + if ((rv == EC_SUCCESS) && acok) + return 1; + } + + return 0; +} + +/* + * Craask does not have a GPIO indicating whether extpower is present, + * so detect using the charger(s). + */ +__override void board_check_extpower(void) +{ + static int last_extpower_present; + int extpower_present = extpower_is_present(); + + if (last_extpower_present ^ extpower_present) + extpower_handle_update(extpower_present); + + last_extpower_present = extpower_present; +} + +__override void board_hibernate(void) +{ + /* Shut down the chargers */ + if (board_get_usb_pd_port_count() == 2) + raa489000_hibernate(CHARGER_SECONDARY, true); + raa489000_hibernate(CHARGER_PRIMARY, true); + LOG_INF("Charger(s) hibernated"); + cflush(); +} diff --git a/zephyr/projects/nissa/craask/src/form_factor.c b/zephyr/projects/nissa/craask/src/form_factor.c new file mode 100644 index 0000000000..59869eaa2f --- /dev/null +++ b/zephyr/projects/nissa/craask/src/form_factor.c @@ -0,0 +1,121 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <zephyr/devicetree.h> +#include <zephyr/logging/log.h> + +#include "accelgyro.h" +#include "button.h" +#include "cros_board_info.h" +#include "cros_cbi.h" +#include "driver/accelgyro_bmi323.h" +#include "driver/accelgyro_lsm6dso.h" +#include "gpio/gpio_int.h" +#include "hooks.h" +#include "motionsense_sensors.h" +#include "motion_sense.h" +#include "tablet_mode.h" + +#include "nissa_common.h" + +LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL); + +/* + * Mainboard orientation support. + */ + +#define LIS_ALT_MAT SENSOR_ROT_STD_REF_NAME(DT_NODELABEL(lid_rot_bma422)) +#define BMA_ALT_MAT SENSOR_ROT_STD_REF_NAME(DT_NODELABEL(lid_rot_ref)) +#define ALT_MAT SENSOR_ROT_STD_REF_NAME(DT_NODELABEL(base_rot_ver1)) +#define LID_SENSOR SENSOR_ID(DT_NODELABEL(lid_accel)) +#define BASE_SENSOR SENSOR_ID(DT_NODELABEL(base_accel)) +#define BASE_GYRO SENSOR_ID(DT_NODELABEL(base_gyro)) +#define ALT_LID_S SENSOR_ID(DT_NODELABEL(alt_lid_accel)) + +static bool use_alt_sensor; + +void motion_interrupt(enum gpio_signal signal) +{ + if (use_alt_sensor) + bmi3xx_interrupt(signal); + else + lsm6dso_interrupt(signal); +} + +static void form_factor_init(void) +{ + int ret; + uint32_t val; + enum nissa_sub_board_type sb = nissa_get_sb_type(); + + ret = cbi_get_board_version(&val); + if (ret != EC_SUCCESS) { + LOG_ERR("Error retrieving CBI BOARD_VER."); + return; + } + /* + * The volume up/down button are exchanged on ver3 USB + * sub board. + * + * LTE: + * volup -> gpioa2, voldn -> gpio93 + * USB: + * volup -> gpio93, voldn -> gpioa2 + */ + if (val == 3 && sb == NISSA_SB_C_A) { + LOG_INF("Volume up/down btn exchanged on ver3 USB sku"); + buttons[BUTTON_VOLUME_UP].gpio = GPIO_VOLUME_DOWN_L; + buttons[BUTTON_VOLUME_DOWN].gpio = GPIO_VOLUME_UP_L; + } + + /* + * If the board version is 1 + * use ver1 rotation matrix. + */ + if (val == 1) { + LOG_INF("Switching to ver1 base"); + motion_sensors[BASE_SENSOR].rot_standard_ref = &ALT_MAT; + motion_sensors[BASE_GYRO].rot_standard_ref = &ALT_MAT; + } + + /* + * If the firmware config indicates + * an craaskbowl form factor, use the alternative + * rotation matrix. + */ + ret = cros_cbi_get_fw_config(FW_LID_INVERSION, &val); + if (ret != 0) { + LOG_ERR("Error retrieving CBI FW_CONFIG field %d", + FW_LID_INVERSION); + return; + } + if (val == FW_LID_XY_ROT_180) { + LOG_INF("Lid sensor placement rotate 180 on xy plane"); + motion_sensors[LID_SENSOR].rot_standard_ref = &LIS_ALT_MAT; + motion_sensors_alt[ALT_LID_S].rot_standard_ref = &BMA_ALT_MAT; + } + + /* check which base sensor is used for motion_interrupt */ + use_alt_sensor = cros_cbi_ssfc_check_match( + CBI_SSFC_VALUE_ID(DT_NODELABEL(base_sensor_1))); + + motion_sensors_check_ssfc(); + + /* Check if it's clamshell or convertible */ + ret = cros_cbi_get_fw_config(FORM_FACTOR, &val); + if (ret != 0) { + LOG_ERR("Error retrieving CBI FW_CONFIG field %d", FORM_FACTOR); + return; + } + if (val == CLAMSHELL) { + LOG_INF("Clamshell: disable motionsense function."); + motion_sensor_count = 0; + gmr_tablet_switch_disable(); + gpio_disable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_imu)); + gpio_pin_configure_dt(GPIO_DT_FROM_NODELABEL(gpio_imu_int_l), + GPIO_DISCONNECTED); + } +} +DECLARE_HOOK(HOOK_INIT, form_factor_init, HOOK_PRIO_POST_I2C); diff --git a/zephyr/projects/nissa/craask/src/keyboard.c b/zephyr/projects/nissa/craask/src/keyboard.c new file mode 100644 index 0000000000..65229eb43f --- /dev/null +++ b/zephyr/projects/nissa/craask/src/keyboard.c @@ -0,0 +1,29 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "ec_commands.h" + +static const struct ec_response_keybd_config craask_kb = { + .num_top_row_keys = 10, + .action_keys = { + TK_BACK, /* T1 */ + TK_REFRESH, /* T2 */ + TK_FULLSCREEN, /* T3 */ + TK_OVERVIEW, /* T4 */ + TK_SNAPSHOT, /* T5 */ + TK_BRIGHTNESS_DOWN, /* T6 */ + TK_BRIGHTNESS_UP, /* T7 */ + TK_VOL_MUTE, /* T8 */ + TK_VOL_DOWN, /* T9 */ + TK_VOL_UP, /* T10 */ + }, + .capabilities = KEYBD_CAP_SCRNLOCK_KEY, +}; + +__override const struct ec_response_keybd_config * +board_vivaldi_keybd_config(void) +{ + return &craask_kb; +} diff --git a/zephyr/projects/nissa/craask/src/led.c b/zephyr/projects/nissa/craask/src/led.c new file mode 100644 index 0000000000..0af0202cf4 --- /dev/null +++ b/zephyr/projects/nissa/craask/src/led.c @@ -0,0 +1,56 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + * + * Battery LED control for nissa + */ +#include "common.h" +#include "ec_commands.h" +#include "led_common.h" +#include "led_onoff_states.h" +#include "led_pwm.h" + +__override const int led_charge_lvl_1 = 5; +__override const int led_charge_lvl_2 = 97; +__override struct led_descriptor + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 3 * LED_ONE_SEC } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_AMBER, + 2 * LED_ONE_SEC }, + { EC_LED_COLOR_BLUE, + 2 * LED_ONE_SEC } }, + }; + +__override void led_set_color_battery(enum ec_led_colors color) +{ + switch (color) { + case EC_LED_COLOR_RED: + set_pwm_led_color(EC_LED_ID_BATTERY_LED, EC_LED_COLOR_RED); + break; + case EC_LED_COLOR_BLUE: + set_pwm_led_color(EC_LED_ID_BATTERY_LED, EC_LED_COLOR_BLUE); + break; + case EC_LED_COLOR_AMBER: + set_pwm_led_color(EC_LED_ID_BATTERY_LED, EC_LED_COLOR_AMBER); + break; + default: /* LED_OFF and other unsupported colors */ + set_pwm_led_color(EC_LED_ID_BATTERY_LED, -1); + break; + } +} diff --git a/zephyr/projects/nissa/craask/src/usbc.c b/zephyr/projects/nissa/craask/src/usbc.c new file mode 100644 index 0000000000..a15460a212 --- /dev/null +++ b/zephyr/projects/nissa/craask/src/usbc.c @@ -0,0 +1,277 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <zephyr/logging/log.h> + +#include "charge_state_v2.h" +#include "chipset.h" +#include "hooks.h" +#include "usb_mux.h" +#include "system.h" +#include "driver/charger/isl923x_public.h" +#include "driver/retimer/anx7483_public.h" +#include "driver/tcpm/tcpci.h" +#include "driver/tcpm/raa489000.h" + +#include "nissa_common.h" + +LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL); + +struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = { + { + .bus_type = EC_BUS_TYPE_I2C, + .i2c_info = { + .port = I2C_PORT_USB_C0_TCPC, + .addr_flags = RAA489000_TCPC0_I2C_FLAGS, + }, + .drv = &raa489000_tcpm_drv, + /* RAA489000 implements TCPCI 2.0 */ + .flags = TCPC_FLAGS_TCPCI_REV2_0 | + TCPC_FLAGS_VBUS_MONITOR, + }, + { /* sub-board */ + .bus_type = EC_BUS_TYPE_I2C, + .i2c_info = { + .port = I2C_PORT_USB_C1_TCPC, + .addr_flags = RAA489000_TCPC0_I2C_FLAGS, + }, + .drv = &raa489000_tcpm_drv, + /* RAA489000 implements TCPCI 2.0 */ + .flags = TCPC_FLAGS_TCPCI_REV2_0 | + TCPC_FLAGS_VBUS_MONITOR, + }, +}; + +int board_is_sourcing_vbus(int port) +{ + int regval; + + tcpc_read(port, TCPC_REG_POWER_STATUS, ®val); + return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS); +} + +int board_set_active_charge_port(int port) +{ + int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT); + int i; + int old_port; + + if (!is_real_port && port != CHARGE_PORT_NONE) + return EC_ERROR_INVAL; + + old_port = charge_manager_get_active_charge_port(); + + LOG_INF("New chg p%d", port); + + /* Disable all ports. */ + if (port == CHARGE_PORT_NONE) { + for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) { + tcpc_write(i, TCPC_REG_COMMAND, + TCPC_REG_COMMAND_SNK_CTRL_LOW); + raa489000_enable_asgate(i, false); + } + + return EC_SUCCESS; + } + + /* Check if port is sourcing VBUS. */ + if (board_is_sourcing_vbus(port)) { + LOG_WRN("Skip enable p%d", port); + return EC_ERROR_INVAL; + } + + /* + * Turn off the other ports' sink path FETs, before enabling the + * requested charge port. + */ + for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) { + if (i == port) + continue; + + if (tcpc_write(i, TCPC_REG_COMMAND, + TCPC_REG_COMMAND_SNK_CTRL_LOW)) + LOG_WRN("p%d: sink path disable failed.", i); + raa489000_enable_asgate(i, false); + } + + /* + * Stop the charger IC from switching while changing ports. Otherwise, + * we can overcurrent the adapter we're switching to. (crbug.com/926056) + */ + if (old_port != CHARGE_PORT_NONE) + charger_discharge_on_ac(1); + + /* Enable requested charge port. */ + if (raa489000_enable_asgate(port, true) || + tcpc_write(port, TCPC_REG_COMMAND, + TCPC_REG_COMMAND_SNK_CTRL_HIGH)) { + LOG_WRN("p%d: sink path enable failed.", port); + charger_discharge_on_ac(0); + return EC_ERROR_UNKNOWN; + } + + /* Allow the charger IC to begin/continue switching. */ + charger_discharge_on_ac(0); + + return EC_SUCCESS; +} + +uint16_t tcpc_get_alert_status(void) +{ + uint16_t status = 0; + int regval; + + /* + * The interrupt line is shared between the TCPC and BC1.2 detector IC. + * Therefore, go out and actually read the alert registers to report the + * alert status. + */ + if (!gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_c0_int_odl))) { + if (!tcpc_read16(0, TCPC_REG_ALERT, ®val)) { + /* The TCPCI Rev 1.0 spec says to ignore bits 14:12. */ + if (!(tcpc_config[0].flags & TCPC_FLAGS_TCPCI_REV2_0)) + regval &= ~((1 << 14) | (1 << 13) | (1 << 12)); + + if (regval) + status |= PD_STATUS_TCPC_ALERT_0; + } + } + + if (board_get_usb_pd_port_count() == 2 && + !gpio_pin_get_dt(GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl))) { + if (!tcpc_read16(1, TCPC_REG_ALERT, ®val)) { + /* TCPCI spec Rev 1.0 says to ignore bits 14:12. */ + if (!(tcpc_config[1].flags & TCPC_FLAGS_TCPCI_REV2_0)) + regval &= ~((1 << 14) | (1 << 13) | (1 << 12)); + + if (regval) + status |= PD_STATUS_TCPC_ALERT_1; + } + } + + return status; +} + +void pd_power_supply_reset(int port) +{ + /* Disable VBUS */ + tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_LOW); + + /* Notify host of power info change. */ + pd_send_host_event(PD_EVENT_POWER_CHANGE); +} + +__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp) +{ + if (port < 0 || port >= CONFIG_USB_PD_PORT_MAX_COUNT) + return; + + raa489000_set_output_current(port, rp); +} + +int pd_set_power_supply_ready(int port) +{ + int rv; + + if (port >= CONFIG_USB_PD_PORT_MAX_COUNT) + return EC_ERROR_INVAL; + + /* Disable charging. */ + rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW); + if (rv) + return rv; + + /* Our policy is not to source VBUS when the AP is off. */ + if (chipset_in_state(CHIPSET_STATE_ANY_OFF)) + return EC_ERROR_NOT_POWERED; + + /* Provide Vbus. */ + rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_HIGH); + if (rv) + return rv; + + rv = raa489000_enable_asgate(port, true); + if (rv) + return rv; + + /* Notify host of power info change. */ + pd_send_host_event(PD_EVENT_POWER_CHANGE); + + return EC_SUCCESS; +} + +void board_reset_pd_mcu(void) +{ + /* + * TODO(b:147316511): could send a reset command to the TCPC here + * if needed. + */ +} + +/* + * Because the TCPCs and BC1.2 chips share interrupt lines, it's possible + * for an interrupt to be lost if one asserts the IRQ, the other does the same + * then the first releases it: there will only be one falling edge to trigger + * the interrupt, and the line will be held low. We handle this by running a + * deferred check after a falling edge to see whether the IRQ is still being + * asserted. If it is, we assume an interrupt may have been lost and we need + * to poll each chip for events again. + */ +#define USBC_INT_POLL_DELAY_US 5000 + +static void poll_c0_int(void); +DECLARE_DEFERRED(poll_c0_int); +static void poll_c1_int(void); +DECLARE_DEFERRED(poll_c1_int); + +static void usbc_interrupt_trigger(int port) +{ + schedule_deferred_pd_interrupt(port); + usb_charger_task_set_event(port, USB_CHG_EVENT_BC12); +} + +static inline void poll_usb_gpio(int port, const struct gpio_dt_spec *gpio, + const struct deferred_data *ud) +{ + if (!gpio_pin_get_dt(gpio)) { + usbc_interrupt_trigger(port); + hook_call_deferred(ud, USBC_INT_POLL_DELAY_US); + } +} + +static void poll_c0_int(void) +{ + poll_usb_gpio(0, GPIO_DT_FROM_NODELABEL(gpio_usb_c0_int_odl), + &poll_c0_int_data); +} + +static void poll_c1_int(void) +{ + poll_usb_gpio(1, GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl), + &poll_c1_int_data); +} + +void usb_interrupt(enum gpio_signal signal) +{ + int port; + const struct deferred_data *ud; + + if (signal == GPIO_SIGNAL(DT_NODELABEL(gpio_usb_c0_int_odl))) { + port = 0; + ud = &poll_c0_int_data; + } else { + port = 1; + ud = &poll_c1_int_data; + } + /* + * We've just been called from a falling edge, so there's definitely + * no lost IRQ right now. Cancel any pending check. + */ + hook_call_deferred(ud, -1); + /* Trigger polling of TCPC and BC1.2 in respective tasks */ + usbc_interrupt_trigger(port); + /* Check for lost interrupts in a bit */ + hook_call_deferred(ud, USBC_INT_POLL_DELAY_US); +} diff --git a/zephyr/projects/nissa/include/nissa_common.h b/zephyr/projects/nissa/include/nissa_common.h new file mode 100644 index 0000000000..7cdaba2e50 --- /dev/null +++ b/zephyr/projects/nissa/include/nissa_common.h @@ -0,0 +1,23 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Nissa common declarations */ + +#ifndef __CROS_EC_NISSA_NISSA_COMMON_H__ +#define __CROS_EC_NISSA_NISSA_COMMON_H__ + +#include "usb_mux.h" + +enum nissa_sub_board_type { + NISSA_SB_UNKNOWN = -1, /* Uninitialised */ + NISSA_SB_NONE = 0, /* No board defined */ + NISSA_SB_C_A = 1, /* USB type C, USB type A */ + NISSA_SB_C_LTE = 2, /* USB type C, WWAN LTE */ + NISSA_SB_HDMI_A = 3, /* HDMI, USB type A */ +}; + +enum nissa_sub_board_type nissa_get_sb_type(void); + +#endif /* __CROS_EC_NISSA_NISSA_COMMON_H__ */ diff --git a/zephyr/projects/nissa/include/nissa_hdmi.h b/zephyr/projects/nissa/include/nissa_hdmi.h new file mode 100644 index 0000000000..9f2f533ba7 --- /dev/null +++ b/zephyr/projects/nissa/include/nissa_hdmi.h @@ -0,0 +1,55 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Nissa shared HDMI sub-board functionality */ + +#ifndef __CROS_EC_NISSA_NISSA_HDMI_H__ +#define __CROS_EC_NISSA_NISSA_HDMI_H__ + +#include "common.h" + +/** True if the board supports an HDMI sub-board. */ +#define NISSA_BOARD_HAS_HDMI_SUPPORT DT_NODE_EXISTS(DT_NODELABEL(gpio_hdmi_sel)) + +/** + * Configure the GPIO that controls core rails on the HDMI sub-board. + * + * This is the gpio_en_rails_odl pin, which is configured as active-low + * open-drain output to enable power to the HDMI sub-board (typically when the + * AP is in S5 or above). + * + * This function must be called if the pin is connected to the HDMI board and + * power is not enabled by default. + */ +void nissa_configure_hdmi_rails(void); + +/** + * Configure the GPIO that controls the HDMI VCC pin on the HDMI sub-board. + * + * This is the gpio_hdmi_en_odl pin, which is configured as active-low + * open-drain output to enable the VCC pin on the HDMI connector (typically when + * the AP is on, in S0 or S0ix). + * + * This function must be called if the pin is connected to the HDMI board and + * VCC is not enabled by default. + */ +void nissa_configure_hdmi_vcc(void); + +/** + * Configure the GPIOS controlling HDMI sub-board power (core rails and VCC). + * + * This function is called from shared code while configuring sub-boards, and + * used if an HDMI sub-board is present. The default implementation enables the + * core rails control pin (nissa_configure_hdmi_rails) but not VCC + * (nissa_configure_hdmi_vcc), assuming that the pin for VCC is not connected + * connected on most boards (and that VCC will be turned on whenever the core + * rails are turned on). + * + * A board should override this function if it needs to enable more IOs for + * HDMI, or if some pins need to be conditionally enabled. + */ +__override_proto void nissa_configure_hdmi_power_gpios(void); + +#endif /* __CROS_EC_NISSA_NISSA_HDMI_H__ */ diff --git a/zephyr/projects/nissa/it8xxx2_program.conf b/zephyr/projects/nissa/it8xxx2_program.conf new file mode 100644 index 0000000000..3272c04209 --- /dev/null +++ b/zephyr/projects/nissa/it8xxx2_program.conf @@ -0,0 +1,62 @@ +# Copyright 2022 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +CONFIG_CROS_FLASH_IT8XXX2=y +CONFIG_CROS_SYSTEM_IT8XXX2=y +CONFIG_ESPI_IT8XXX2=y +CONFIG_FPU=y +# rv32iafc/ilp32f is not supported by the toolchain, so use soft-float +CONFIG_FLOAT_HARD=n + +# EC performance is bad; limiting sensor data rate helps keep it from degrading +# so much that it causes problems. b/240485526, b/230818312 +CONFIG_PLATFORM_EC_MAX_SENSOR_FREQ_MILLIHZ=100000 + +# Allow more time for the charger to stabilise +CONFIG_PLATFORM_EC_POWER_BUTTON_INIT_TIMEOUT=5 + +# ITE has more space, so don't restrict shell +CONFIG_SHELL_MINIMAL=n + +# RAM savings, since this chip is tight on available RAM. +# It's useful to store a lot of logs for the host to request, but the default 4k +# is pretty large. +CONFIG_PLATFORM_EC_HOSTCMD_CONSOLE_BUF_SIZE=2048 +# Our threads have short names, save 20 bytes per thread +CONFIG_THREAD_MAX_NAME_LEN=12 +# Task stacks, tuned by experiment. Most expanded to prevent overflow, and a few +# shrunk to save RAM. +CONFIG_AP_PWRSEQ_STACK_SIZE=1408 +CONFIG_TASK_HOSTCMD_STACK_SIZE=1280 +CONFIG_TASK_MOTIONSENSE_STACK_SIZE=1280 +CONFIG_TASK_PD_INT_STACK_SIZE=1280 + +# TCPC+PPC: ITE on-chip for C0, PS8745 for optional C1 +CONFIG_PLATFORM_EC_USB_PD_TCPM_ITE_ON_CHIP=y +CONFIG_PLATFORM_EC_USB_PD_TCPM_DRIVER_IT8XXX2=y +CONFIG_PLATFORM_EC_USB_PD_TCPM_PS8745=y +CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_CHARGER=y +# SM5803 controls power path on both ports +CONFIG_PLATFORM_EC_USB_PD_5V_CHARGER_CTRL=y +# SM5803 can discharge VBUS, but not via one of the available options; +# pd_power_supply_reset() does discharge. +CONFIG_PLATFORM_EC_USB_PD_DISCHARGE=n +# The EC is put into programming mode while firmware is running +# (after releasing reset) and PD after being reset will hard-reset +# the port if a contract was already set up. If the system has no +# battery, this will prevent programming because it will brown out +# the system and reset. Inserting a delay gives the programmer more +# time to put the EC into programming mode. +CONFIG_PLATFORM_EC_USB_PD_STARTUP_DELAY_MS=2000 + +# Charger driver and configuration +CONFIG_PLATFORM_EC_OCPC=y +CONFIG_PLATFORM_EC_CHARGER_SM5803=y +CONFIG_PLATFORM_EC_OCPC_DEF_RBATT_MOHMS=21 +CONFIG_PLATFORM_EC_PD_MAX_VOLTAGE_MV=15000 + +# VSENSE: PP3300_S5 & PP1050_PROC +CONFIG_VCMP_IT8XXX2=y +CONFIG_SENSOR=y +CONFIG_SENSOR_SHELL=n diff --git a/zephyr/projects/nissa/joxer/cbi.dtsi b/zephyr/projects/nissa/joxer/cbi.dtsi new file mode 100644 index 0000000000..afbd125b32 --- /dev/null +++ b/zephyr/projects/nissa/joxer/cbi.dtsi @@ -0,0 +1,32 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + nissa-fw-config { + compatible = "cros-ec,cbi-fw-config"; + + /* + * FW_CONFIG field to indicate which keyboard layout + * should be used. + */ + keyboard { + enum-name = "FW_KB_LAYOUT"; + start = <3>; + size = <2>; + + layout-1 { + compatible = "cros-ec,cbi-fw-config-value"; + enum-name = "FW_KB_LAYOUT_DEFAULT"; + value = <0>; + default; + }; + layout-2 { + compatible = "cros-ec,cbi-fw-config-value"; + enum-name = "FW_KB_LAYOUT_US2"; + value = <1>; + }; + }; + }; +}; diff --git a/zephyr/projects/nissa/joxer/generated.dtsi b/zephyr/projects/nissa/joxer/generated.dtsi new file mode 100644 index 0000000000..22214b9726 --- /dev/null +++ b/zephyr/projects/nissa/joxer/generated.dtsi @@ -0,0 +1,260 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + * + * This file is auto-generated - do not edit! + */ + +/ { + + named-adc-channels { + compatible = "named-adc-channels"; + + adc_ec_vsense_pp1050_proc: ec_vsense_pp1050_proc { + enum-name = "ADC_PP1050_PROC"; + io-channels = <&adc0 14>; + }; + adc_ec_vsense_pp3300_s5: ec_vsense_pp3300_s5 { + enum-name = "ADC_PP3300_S5"; + io-channels = <&adc0 0>; + }; + adc_temp_sensor_1: temp_sensor_1 { + enum-name = "ADC_TEMP_SENSOR_1"; + io-channels = <&adc0 2>; + }; + adc_temp_sensor_2: temp_sensor_2 { + enum-name = "ADC_TEMP_SENSOR_2"; + io-channels = <&adc0 3>; + }; + adc_temp_sensor_3: temp_sensor_3 { + enum-name = "ADC_TEMP_SENSOR_3"; + io-channels = <&adc0 13>; + }; + }; + + named-gpios { + compatible = "named-gpios"; + + gpio_acc_int_l: acc_int_l { + gpios = <&gpioc 0 GPIO_INPUT>; + }; + gpio_all_sys_pwrgd: all_sys_pwrgd { + gpios = <&gpiob 7 GPIO_INPUT>; + }; + gpio_ccd_mode_odl: ccd_mode_odl { + gpios = <&gpioh 5 GPIO_INPUT>; + enum-name = "GPIO_CCD_MODE_ODL"; + }; + gpio_cpu_c10_gate_l: cpu_c10_gate_l { + gpios = <&gpiog 1 GPIO_INPUT>; + }; + gpio_ec_battery_pres_odl: ec_battery_pres_odl { + gpios = <&gpioi 4 GPIO_INPUT>; + enum-name = "GPIO_BATT_PRES_ODL"; + }; + gpio_ec_cbi_wp: ec_cbi_wp { + gpios = <&gpioj 5 GPIO_OUTPUT>; + }; + gpio_ec_edp_bl_en_od: ec_edp_bl_en_od { + gpios = <&gpiok 4 GPIO_ODR_HIGH>; + enum-name = "GPIO_ENABLE_BACKLIGHT"; + }; + gpio_ec_entering_rw: ec_entering_rw { + gpios = <&gpioc 7 GPIO_OUTPUT>; + enum-name = "GPIO_ENTERING_RW"; + }; + gpio_ec_gsc_packet_mode: ec_gsc_packet_mode { + gpios = <&gpioh 1 GPIO_OUTPUT>; + enum-name = "GPIO_PACKET_MODE_EN"; + }; + gpio_ec_pch_wake_odl: ec_pch_wake_odl { + gpios = <&gpiob 2 GPIO_ODR_LOW>; + }; + gpio_ec_prochot_odl: ec_prochot_odl { + gpios = <&gpioi 1 GPIO_ODR_HIGH>; + }; + gpio_ec_soc_dsw_pwrok: ec_soc_dsw_pwrok { + gpios = <&gpiol 7 GPIO_OUTPUT>; + }; + gpio_ec_soc_hdmi_hpd: ec_soc_hdmi_hpd { + gpios = <&gpiok 7 GPIO_OUTPUT>; + }; + gpio_ec_soc_int_odl: ec_soc_int_odl { + gpios = <&gpiod 5 GPIO_ODR_HIGH>; + enum-name = "GPIO_EC_INT_L"; + }; + gpio_ec_soc_pch_pwrok_od: ec_soc_pch_pwrok_od { + gpios = <&gpiod 6 GPIO_ODR_HIGH>; + }; + gpio_ec_soc_pwr_btn_odl: ec_soc_pwr_btn_odl { + gpios = <&gpiob 6 GPIO_ODR_HIGH>; + enum-name = "GPIO_PCH_PWRBTN_L"; + }; + gpio_ec_soc_rsmrst_l: ec_soc_rsmrst_l { + gpios = <&gpioh 0 GPIO_OUTPUT>; + }; + gpio_ec_soc_rtcrst: ec_soc_rtcrst { + gpios = <&gpiok 2 GPIO_OUTPUT>; + }; + gpio_ec_soc_sys_pwrok: ec_soc_sys_pwrok { + gpios = <&gpiof 2 GPIO_OUTPUT>; + }; + gpio_ec_soc_vccst_pwrgd_od: ec_soc_vccst_pwrgd_od { + gpios = <&gpioe 5 GPIO_ODR_HIGH>; + }; + gpio_ec_wp_odl: ec_wp_odl { + gpios = <&gpioa 6 (GPIO_INPUT | GPIO_ACTIVE_LOW)>; + }; + gpio_en_kb_bl: en_kb_bl { + gpios = <&gpioj 3 GPIO_OUTPUT>; + enum-name = "GPIO_EN_KEYBOARD_BACKLIGHT"; + }; + gpio_en_pp3300_s5: en_pp3300_s5 { + gpios = <&gpioc 5 GPIO_OUTPUT>; + enum-name = "GPIO_TEMP_SENSOR_POWER"; + }; + gpio_en_pp5000_pen_x: en_pp5000_pen_x { + gpios = <&gpiob 5 GPIO_OUTPUT>; + }; + gpio_en_pp5000_s5: en_pp5000_s5 { + gpios = <&gpiok 5 GPIO_OUTPUT>; + }; + gpio_en_slp_z: en_slp_z { + gpios = <&gpiok 3 GPIO_OUTPUT>; + }; + gpio_en_usb_a0_vbus: en_usb_a0_vbus { + gpios = <&gpiol 6 GPIO_OUTPUT>; + }; + gpio_en_usb_c0_cc1_vconn: en_usb_c0_cc1_vconn { + gpios = <&gpioh 4 GPIO_OUTPUT>; + }; + gpio_en_usb_c0_cc2_vconn: en_usb_c0_cc2_vconn { + gpios = <&gpioh 6 GPIO_OUTPUT>; + }; + gpio_gsc_ec_pwr_btn_odl: gsc_ec_pwr_btn_odl { + gpios = <&gpioe 2 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_POWER_BUTTON_L"; + }; + gpio_hdmi_sel: hdmi_sel { + gpios = <&gpioc 6 GPIO_OUTPUT>; + }; + gpio_imu_int_l: imu_int_l { + gpios = <&gpioj 0 GPIO_INPUT>; + }; + gpio_imvp91_vrrdy_od: imvp91_vrrdy_od { + gpios = <&gpioj 4 GPIO_INPUT>; + }; + gpio_lid_open: lid_open { + gpios = <&gpiof 3 GPIO_INPUT>; + enum-name = "GPIO_LID_OPEN"; + }; + gpio_pen_detect_odl: pen_detect_odl { + gpios = <&gpioj 1 GPIO_INPUT_PULL_UP>; + }; + gpio_pg_pp1050_mem_s3_od: pg_pp1050_mem_s3_od { + gpios = <&gpiod 3 GPIO_INPUT>; + }; + gpio_pg_pp5000_s5_od: pg_pp5000_s5_od { + gpios = <&gpioe 3 GPIO_INPUT>; + }; + gpio_rsmrst_pwrgd_l: rsmrst_pwrgd_l { + gpios = <&gpioe 1 GPIO_INPUT_PULL_UP>; + }; + gpio_slp_s0_l: slp_s0_l { + gpios = <&gpioe 4 GPIO_INPUT>; + }; + gpio_slp_s3_l: slp_s3_l { + gpios = <&gpioh 3 GPIO_INPUT>; + }; + gpio_slp_s4_l: slp_s4_l { + gpios = <&gpioi 5 GPIO_INPUT>; + }; + gpio_slp_sus_l: slp_sus_l { + gpios = <&gpiog 2 GPIO_INPUT>; + }; + gpio_sub_usb_a1_ilimit_sdp: sub_usb_a1_ilimit_sdp { + gpios = <&gpiof 1 GPIO_OUTPUT>; + enum-name = "GPIO_USB2_ILIM_SEL"; + }; + gpio_sys_rst_odl: sys_rst_odl { + gpios = <&gpiod 1 GPIO_ODR_HIGH>; + }; + gpio_tablet_mode_l: tablet_mode_l { + gpios = <&gpioj 7 GPIO_INPUT>; + enum-name = "GPIO_TABLET_MODE_L"; + }; + gpio_usb_a0_ilimit_sdp: usb_a0_ilimit_sdp { + gpios = <&gpiol 5 GPIO_OUTPUT>; + enum-name = "GPIO_USB1_ILIM_SEL"; + }; + gpio_usb_c0_frs: usb_c0_frs { + gpios = <&gpioc 4 GPIO_OUTPUT>; + }; + gpio_usb_c0_int_odl: usb_c0_int_odl { + gpios = <&gpiok 0 GPIO_INPUT_PULL_UP>; + }; + gpio_vccin_aux_vid0: vccin_aux_vid0 { + gpios = <&gpiod 0 GPIO_INPUT>; + }; + gpio_vccin_aux_vid1: vccin_aux_vid1 { + gpios = <&gpiok 1 GPIO_INPUT>; + }; + gpio_voldn_btn_odl: voldn_btn_odl { + gpios = <&gpioi 6 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_VOLUME_DOWN_L"; + }; + gpio_volup_btn_odl: volup_btn_odl { + gpios = <&gpioi 7 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_VOLUME_UP_L"; + }; + }; + + named-i2c-ports { + compatible = "named-i2c-ports"; + + i2c_ec_i2c_eeprom: ec_i2c_eeprom { + i2c-port = <&i2c0>; + enum-names = "I2C_PORT_EEPROM"; + }; + i2c_ec_i2c_batt: ec_i2c_batt { + i2c-port = <&i2c1>; + enum-names = "I2C_PORT_BATTERY"; + }; + i2c_ec_i2c_sensor: ec_i2c_sensor { + i2c-port = <&i2c2>; + enum-names = "I2C_PORT_SENSOR"; + }; + i2c_ec_i2c_sub_usb_c1: ec_i2c_sub_usb_c1 { + i2c-port = <&i2c4>; + enum-names = "I2C_PORT_USB_C1_TCPC"; + }; + i2c_ec_i2c_usb_c0: ec_i2c_usb_c0 { + i2c-port = <&i2c5>; + enum-names = "I2C_PORT_USB_C0_TCPC"; + }; + }; +}; + +&adc0 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; diff --git a/zephyr/projects/nissa/joxer/joxer_vif.xml b/zephyr/projects/nissa/joxer/joxer_vif.xml new file mode 100644 index 0000000000..cfbce5623a --- /dev/null +++ b/zephyr/projects/nissa/joxer/joxer_vif.xml @@ -0,0 +1,346 @@ +<?xml version="1.0" encoding="utf-8"?> +<vif:VIF xmlns:opt="http://usb.org/VendorInfoFileOptionalContent.xsd" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:vif="http://usb.org/VendorInfoFile.xsd"> + <vif:VIF_Specification>3.20</vif:VIF_Specification> + <vif:VIF_App> + <vif:Vendor>USB-IF</vif:Vendor> + <vif:Name>VIF Editor</vif:Name> + <vif:Version>3.3.0.0</vif:Version> + </vif:VIF_App> + <vif:Vendor_Name>Google</vif:Vendor_Name> + <vif:Model_Part_Number>Joxer</vif:Model_Part_Number> + <vif:Product_Revision>1</vif:Product_Revision> + <vif:TID>0</vif:TID> + <vif:VIF_Product_Type value="0">Port Product</vif:VIF_Product_Type> + <vif:Certification_Type value="1">Reference Platform</vif:Certification_Type> + <vif:Product> + <!--Product Level Content:--> + </vif:Product> + <vif:Component> + <!--Component 0: Port 0--> + <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;--> + <!--;Component--> + <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;--> + <vif:Port_Label>0</vif:Port_Label> + <vif:Connector_Type value="2">Type-C®</vif:Connector_Type> + <vif:USB4_Supported value="false" /> + <vif:USB_PD_Support value="true" /> + <vif:PD_Port_Type value="4">DRP</vif:PD_Port_Type> + <vif:Type_C_State_Machine value="2">DRP</vif:Type_C_State_Machine> + <vif:Port_Battery_Powered value="true" /> + <vif:BC_1_2_Support value="3">Both</vif:BC_1_2_Support> + <vif:Captive_Cable value="false" /> + <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;--> + <!--;General PD--> + <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;--> + <vif:PD_Spec_Revision_Major value="3" /> + <vif:PD_Spec_Revision_Minor value="1" /> + <vif:PD_Spec_Version_Major value="1" /> + <vif:PD_Spec_Version_Minor value="3" /> + <vif:PD_Specification_Revision value="2">Revision 3</vif:PD_Specification_Revision> + <vif:SOP_Capable value="true" /> + <vif:SOP_P_Capable value="true" /> + <vif:SOP_PP_Capable value="true" /> + <vif:SOP_P_Debug_Capable value="false" /> + <vif:SOP_PP_Debug_Capable value="false" /> + <vif:Manufacturer_Info_Supported_Port value="false" /> + <vif:Chunking_Implemented_SOP value="true" /> + <vif:Unchunked_Extended_Messages_Supported value="false" /> + <vif:Security_Msgs_Supported_SOP value="false" /> + <vif:Unconstrained_Power value="false" /> + <vif:Num_Fixed_Batteries value="1" /> + <vif:Num_Swappable_Battery_Slots value="1" /> + <vif:ID_Header_Connector_Type_SOP value="2">USB Type-C® Receptacle</vif:ID_Header_Connector_Type_SOP> + <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;--> + <!--;PD Capabilities--> + <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;--> + <vif:USB_Comms_Capable value="true" /> + <vif:DR_Swap_To_DFP_Supported value="true" /> + <vif:DR_Swap_To_UFP_Supported value="false" /> + <vif:VCONN_Swap_To_On_Supported value="true" /> + <vif:VCONN_Swap_To_Off_Supported value="true" /> + <vif:Responds_To_Discov_SOP_UFP value="false" /> + <vif:Responds_To_Discov_SOP_DFP value="true" /> + <vif:Attempts_Discov_SOP value="true" /> + <vif:Power_Interruption_Available value="0">No Interruption Possible</vif:Power_Interruption_Available> + <vif:Data_Reset_Supported value="false" /> + <vif:Enter_USB_Supported value="false" /> + <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;--> + <!--;USB Type-C®--> + <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;--> + <vif:Type_C_Can_Act_As_Host value="true" /> + <vif:Type_C_Can_Act_As_Device value="false" /> + <vif:Type_C_Implements_Try_SRC value="true" /> + <vif:Type_C_Implements_Try_SNK value="false" /> + <vif:Type_C_Supports_Audio_Accessory value="false" /> + <vif:Type_C_Is_VCONN_Powered_Accessory value="false" /> + <vif:Type_C_Is_Debug_Target_SRC value="true" /> + <vif:Type_C_Is_Debug_Target_SNK value="true" /> + <vif:RP_Value value="1">1.5A</vif:RP_Value> + <vif:Type_C_Port_On_Hub value="false" /> + <vif:Type_C_Power_Source value="2">Both</vif:Type_C_Power_Source> + <vif:Type_C_Sources_VCONN value="true" /> + <vif:Type_C_Is_Alt_Mode_Controller value="true" /> + <vif:Type_C_Is_Alt_Mode_Adapter value="false" /> + <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;--> + <!--;Product Power--> + <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;--> + <vif:Product_Total_Source_Power_mW value="15000">15000 mW</vif:Product_Total_Source_Power_mW> + <vif:Port_Source_Power_Type value="0">Assured</vif:Port_Source_Power_Type> + <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;--> + <!--;USB Host--> + <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;--> + <vif:Host_Supports_USB_Data value="true" /> + <vif:Host_Speed value="1">USB 3.2 Gen 1x1</vif:Host_Speed> + <vif:Host_Contains_Captive_Retimer value="false" /> + <vif:Host_Truncates_DP_For_tDHPResponse value="false" /> + <vif:Host_Is_Embedded value="false" /> + <vif:Host_Suspend_Supported value="true" /> + <vif:Is_DFP_On_Hub value="false" /> + <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;--> + <!--;Battery Charging 1.2--> + <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;--> + <vif:BC_1_2_Charging_Port_Type value="1">CDP</vif:BC_1_2_Charging_Port_Type> + <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;--> + <!--;PD Source--> + <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;--> + <vif:PD_Power_As_Source value="15000">15000 mW</vif:PD_Power_As_Source> + <vif:EPR_Supported_As_Src value="false" /> + <vif:USB_Suspend_May_Be_Cleared value="false" /> + <vif:Sends_Pings value="false" /> + <vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink value="0">FR_Swap not supported</vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink> + <vif:Master_Port value="false" /> + <vif:Num_Src_PDOs value="1" /> + <vif:PD_OC_Protection value="true" /> + <vif:PD_OCP_Method value="0">Over-Current Response</vif:PD_OCP_Method> + <!--Bundle: SrcPdoList--> + <vif:SrcPdoList> + <vif:SrcPDO> + <!--Source PDO 1--> + <vif:Src_PDO_Supply_Type value="0">Fixed</vif:Src_PDO_Supply_Type> + <vif:Src_PDO_Peak_Current value="0">100% IOC</vif:Src_PDO_Peak_Current> + <vif:Src_PDO_Voltage value="100">5000 mV</vif:Src_PDO_Voltage> + <vif:Src_PDO_Max_Current value="300">3000 mA</vif:Src_PDO_Max_Current> + <vif:Src_PD_OCP_OC_Debounce value="0">0 msec</vif:Src_PD_OCP_OC_Debounce> + <vif:Src_PD_OCP_OC_Threshold value="300">3000 mA</vif:Src_PD_OCP_OC_Threshold> + </vif:SrcPDO> + </vif:SrcPdoList> + <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;--> + <!--;PD Sink--> + <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;--> + <vif:PD_Power_As_Sink value="45000">45000 mW</vif:PD_Power_As_Sink> + <vif:EPR_Supported_As_Snk value="false" /> + <vif:No_USB_Suspend_May_Be_Set value="true" /> + <vif:GiveBack_May_Be_Set value="false" /> + <vif:Higher_Capability_Set value="false" /> + <vif:FR_Swap_Reqd_Type_C_Current_As_Initial_Source value="0">FR_Swap not supported</vif:FR_Swap_Reqd_Type_C_Current_As_Initial_Source> + <vif:Num_Snk_PDOs value="3" /> + <!--Bundle: SnkPdoList--> + <vif:SnkPdoList> + <vif:SnkPDO> + <!--Sink PDO 1--> + <vif:Snk_PDO_Supply_Type value="0">Fixed</vif:Snk_PDO_Supply_Type> + <vif:Snk_PDO_Voltage value="100">5000 mV</vif:Snk_PDO_Voltage> + <vif:Snk_PDO_Op_Current value="300">3000 mA</vif:Snk_PDO_Op_Current> + </vif:SnkPDO> + <vif:SnkPDO> + <!--Sink PDO 2--> + <vif:Snk_PDO_Supply_Type value="1">Battery</vif:Snk_PDO_Supply_Type> + <vif:Snk_PDO_Op_Power value="60">15000 mW</vif:Snk_PDO_Op_Power> + <vif:Snk_PDO_Min_Voltage value="95">4750 mV</vif:Snk_PDO_Min_Voltage> + <vif:Snk_PDO_Max_Voltage value="300">15000 mV</vif:Snk_PDO_Max_Voltage> + </vif:SnkPDO> + <vif:SnkPDO> + <!--Sink PDO 3--> + <vif:Snk_PDO_Supply_Type value="2">Variable</vif:Snk_PDO_Supply_Type> + <vif:Snk_PDO_Min_Voltage value="95">4750 mV</vif:Snk_PDO_Min_Voltage> + <vif:Snk_PDO_Max_Voltage value="300">15000 mV</vif:Snk_PDO_Max_Voltage> + <vif:Snk_PDO_Op_Current value="300">3000 mA</vif:Snk_PDO_Op_Current> + </vif:SnkPDO> + </vif:SnkPdoList> + <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;--> + <!--;Dual Role--> + <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;--> + <vif:Accepts_PR_Swap_As_Src value="true" /> + <vif:Accepts_PR_Swap_As_Snk value="true" /> + <vif:Requests_PR_Swap_As_Src value="true" /> + <vif:Requests_PR_Swap_As_Snk value="true" /> + <vif:FR_Swap_Supported_As_Initial_Sink value="false" /> + <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;--> + <!--;SOP Discover ID--> + <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;--> + <vif:XID_SOP value="0" /> + <vif:Data_Capable_As_USB_Host_SOP value="true" /> + <vif:Data_Capable_As_USB_Device_SOP value="false" /> + <vif:Product_Type_UFP_SOP value="0">Undefined</vif:Product_Type_UFP_SOP> + <vif:Product_Type_DFP_SOP value="2">PDUSB Host</vif:Product_Type_DFP_SOP> + <vif:DFP_VDO_Port_Number value="0" /> + <vif:Modal_Operation_Supported_SOP value="false" /> + <vif:USB_VID_SOP value="6353">18D1</vif:USB_VID_SOP> + <vif:PID_SOP value="20570">505A</vif:PID_SOP> + <vif:bcdDevice_SOP value="0">0000</vif:bcdDevice_SOP> + </vif:Component> + <vif:Component> + <!--Component 1: Port 1--> + <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;--> + <!--;Component--> + <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;--> + <vif:Port_Label>1</vif:Port_Label> + <vif:Connector_Type value="2">Type-C®</vif:Connector_Type> + <vif:USB4_Supported value="false" /> + <vif:USB_PD_Support value="true" /> + <vif:PD_Port_Type value="4">DRP</vif:PD_Port_Type> + <vif:Type_C_State_Machine value="2">DRP</vif:Type_C_State_Machine> + <vif:Port_Battery_Powered value="true" /> + <vif:BC_1_2_Support value="3">Both</vif:BC_1_2_Support> + <vif:Captive_Cable value="false" /> + <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;--> + <!--;General PD--> + <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;--> + <vif:PD_Spec_Revision_Major value="3" /> + <vif:PD_Spec_Revision_Minor value="1" /> + <vif:PD_Spec_Version_Major value="1" /> + <vif:PD_Spec_Version_Minor value="3" /> + <vif:PD_Specification_Revision value="2">Revision 3</vif:PD_Specification_Revision> + <vif:SOP_Capable value="true" /> + <vif:SOP_P_Capable value="true" /> + <vif:SOP_PP_Capable value="true" /> + <vif:SOP_P_Debug_Capable value="false" /> + <vif:SOP_PP_Debug_Capable value="false" /> + <vif:Manufacturer_Info_Supported_Port value="false" /> + <vif:Chunking_Implemented_SOP value="true" /> + <vif:Unchunked_Extended_Messages_Supported value="false" /> + <vif:Security_Msgs_Supported_SOP value="false" /> + <vif:Unconstrained_Power value="false" /> + <vif:Num_Fixed_Batteries value="1" /> + <vif:Num_Swappable_Battery_Slots value="1" /> + <vif:ID_Header_Connector_Type_SOP value="2">USB Type-C® Receptacle</vif:ID_Header_Connector_Type_SOP> + <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;--> + <!--;PD Capabilities--> + <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;--> + <vif:USB_Comms_Capable value="true" /> + <vif:DR_Swap_To_DFP_Supported value="true" /> + <vif:DR_Swap_To_UFP_Supported value="false" /> + <vif:VCONN_Swap_To_On_Supported value="true" /> + <vif:VCONN_Swap_To_Off_Supported value="true" /> + <vif:Responds_To_Discov_SOP_UFP value="false" /> + <vif:Responds_To_Discov_SOP_DFP value="true" /> + <vif:Attempts_Discov_SOP value="true" /> + <vif:Power_Interruption_Available value="0">No Interruption Possible</vif:Power_Interruption_Available> + <vif:Data_Reset_Supported value="false" /> + <vif:Enter_USB_Supported value="false" /> + <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;--> + <!--;USB Type-C®--> + <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;--> + <vif:Type_C_Can_Act_As_Host value="true" /> + <vif:Type_C_Can_Act_As_Device value="false" /> + <vif:Type_C_Implements_Try_SRC value="true" /> + <vif:Type_C_Implements_Try_SNK value="false" /> + <vif:Type_C_Supports_Audio_Accessory value="false" /> + <vif:Type_C_Is_VCONN_Powered_Accessory value="false" /> + <vif:Type_C_Is_Debug_Target_SRC value="true" /> + <vif:Type_C_Is_Debug_Target_SNK value="true" /> + <vif:RP_Value value="1">1.5A</vif:RP_Value> + <vif:Type_C_Port_On_Hub value="false" /> + <vif:Type_C_Power_Source value="2">Both</vif:Type_C_Power_Source> + <vif:Type_C_Sources_VCONN value="true" /> + <vif:Type_C_Is_Alt_Mode_Controller value="true" /> + <vif:Type_C_Is_Alt_Mode_Adapter value="false" /> + <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;--> + <!--;Product Power--> + <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;--> + <vif:Product_Total_Source_Power_mW value="15000">15000 mW</vif:Product_Total_Source_Power_mW> + <vif:Port_Source_Power_Type value="0">Assured</vif:Port_Source_Power_Type> + <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;--> + <!--;USB Host--> + <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;--> + <vif:Host_Supports_USB_Data value="true" /> + <vif:Host_Speed value="1">USB 3.2 Gen 1x1</vif:Host_Speed> + <vif:Host_Contains_Captive_Retimer value="true" /> + <vif:Host_Truncates_DP_For_tDHPResponse value="false" /> + <vif:Host_Is_Embedded value="false" /> + <vif:Host_Suspend_Supported value="true" /> + <vif:Is_DFP_On_Hub value="false" /> + <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;--> + <!--;Battery Charging 1.2--> + <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;--> + <vif:BC_1_2_Charging_Port_Type value="1">CDP</vif:BC_1_2_Charging_Port_Type> + <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;--> + <!--;PD Source--> + <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;--> + <vif:PD_Power_As_Source value="15000">15000 mW</vif:PD_Power_As_Source> + <vif:EPR_Supported_As_Src value="false" /> + <vif:USB_Suspend_May_Be_Cleared value="false" /> + <vif:Sends_Pings value="false" /> + <vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink value="0">FR_Swap not supported</vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink> + <vif:Master_Port value="false" /> + <vif:Num_Src_PDOs value="1" /> + <vif:PD_OC_Protection value="true" /> + <vif:PD_OCP_Method value="0">Over-Current Response</vif:PD_OCP_Method> + <!--Bundle: SrcPdoList--> + <vif:SrcPdoList> + <vif:SrcPDO> + <!--Source PDO 1--> + <vif:Src_PDO_Supply_Type value="0">Fixed</vif:Src_PDO_Supply_Type> + <vif:Src_PDO_Peak_Current value="0">100% IOC</vif:Src_PDO_Peak_Current> + <vif:Src_PDO_Voltage value="100">5000 mV</vif:Src_PDO_Voltage> + <vif:Src_PDO_Max_Current value="300">3000 mA</vif:Src_PDO_Max_Current> + <vif:Src_PD_OCP_OC_Debounce value="0">0 msec</vif:Src_PD_OCP_OC_Debounce> + <vif:Src_PD_OCP_OC_Threshold value="300">3000 mA</vif:Src_PD_OCP_OC_Threshold> + </vif:SrcPDO> + </vif:SrcPdoList> + <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;--> + <!--;PD Sink--> + <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;--> + <vif:PD_Power_As_Sink value="45000">45000 mW</vif:PD_Power_As_Sink> + <vif:EPR_Supported_As_Snk value="false" /> + <vif:No_USB_Suspend_May_Be_Set value="true" /> + <vif:GiveBack_May_Be_Set value="false" /> + <vif:Higher_Capability_Set value="false" /> + <vif:FR_Swap_Reqd_Type_C_Current_As_Initial_Source value="0">FR_Swap not supported</vif:FR_Swap_Reqd_Type_C_Current_As_Initial_Source> + <vif:Num_Snk_PDOs value="3" /> + <!--Bundle: SnkPdoList--> + <vif:SnkPdoList> + <vif:SnkPDO> + <!--Sink PDO 1--> + <vif:Snk_PDO_Supply_Type value="0">Fixed</vif:Snk_PDO_Supply_Type> + <vif:Snk_PDO_Voltage value="100">5000 mV</vif:Snk_PDO_Voltage> + <vif:Snk_PDO_Op_Current value="300">3000 mA</vif:Snk_PDO_Op_Current> + </vif:SnkPDO> + <vif:SnkPDO> + <!--Sink PDO 2--> + <vif:Snk_PDO_Supply_Type value="1">Battery</vif:Snk_PDO_Supply_Type> + <vif:Snk_PDO_Op_Power value="60">15000 mW</vif:Snk_PDO_Op_Power> + <vif:Snk_PDO_Min_Voltage value="95">4750 mV</vif:Snk_PDO_Min_Voltage> + <vif:Snk_PDO_Max_Voltage value="300">15000 mV</vif:Snk_PDO_Max_Voltage> + </vif:SnkPDO> + <vif:SnkPDO> + <!--Sink PDO 3--> + <vif:Snk_PDO_Supply_Type value="2">Variable</vif:Snk_PDO_Supply_Type> + <vif:Snk_PDO_Min_Voltage value="95">4750 mV</vif:Snk_PDO_Min_Voltage> + <vif:Snk_PDO_Max_Voltage value="300">15000 mV</vif:Snk_PDO_Max_Voltage> + <vif:Snk_PDO_Op_Current value="300">3000 mA</vif:Snk_PDO_Op_Current> + </vif:SnkPDO> + </vif:SnkPdoList> + <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;--> + <!--;Dual Role--> + <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;--> + <vif:Accepts_PR_Swap_As_Src value="true" /> + <vif:Accepts_PR_Swap_As_Snk value="true" /> + <vif:Requests_PR_Swap_As_Src value="true" /> + <vif:Requests_PR_Swap_As_Snk value="true" /> + <vif:FR_Swap_Supported_As_Initial_Sink value="false" /> + <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;--> + <!--;SOP Discover ID--> + <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;--> + <vif:XID_SOP value="0" /> + <vif:Data_Capable_As_USB_Host_SOP value="true" /> + <vif:Data_Capable_As_USB_Device_SOP value="false" /> + <vif:Product_Type_UFP_SOP value="0">Undefined</vif:Product_Type_UFP_SOP> + <vif:Product_Type_DFP_SOP value="2">PDUSB Host</vif:Product_Type_DFP_SOP> + <vif:DFP_VDO_Port_Number value="1" /> + <vif:Modal_Operation_Supported_SOP value="false" /> + <vif:USB_VID_SOP value="6353">18D1</vif:USB_VID_SOP> + <vif:PID_SOP value="20570">505A</vif:PID_SOP> + <vif:bcdDevice_SOP value="0">0000</vif:bcdDevice_SOP> + </vif:Component> +</vif:VIF>
\ No newline at end of file diff --git a/zephyr/projects/nissa/joxer/keyboard.dtsi b/zephyr/projects/nissa/joxer/keyboard.dtsi new file mode 100644 index 0000000000..04a620767a --- /dev/null +++ b/zephyr/projects/nissa/joxer/keyboard.dtsi @@ -0,0 +1,22 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + kblight { + compatible = "cros-ec,kblight-pwm"; + /* + * Use 324 Hz so that 32Khz clock source is used, + * which is not gated in power saving mode. + */ + pwms = <&pwm0 0 PWM_HZ(324) PWM_POLARITY_NORMAL>; + }; +}; + +&pwm0 { + status = "okay"; + prescaler-cx = <PWM_PRESCALER_C4>; + pinctrl-0 = <&pwm0_gpa0_default>; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/nissa/joxer/motionsense.dtsi b/zephyr/projects/nissa/joxer/motionsense.dtsi new file mode 100644 index 0000000000..537cc34451 --- /dev/null +++ b/zephyr/projects/nissa/joxer/motionsense.dtsi @@ -0,0 +1,149 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <dt-bindings/motionsense/utils.h> + + +/ { + aliases { + /* + * Interrupt bindings for sensor devices. + */ + bmi3xx-int = &base_accel; + }; + + /* + * Declare mutexes used by sensor drivers. + * A mutex node is used to create an instance of mutex_t. + * A mutex node is referenced by a sensor node if the + * corresponding sensor driver needs to use the + * instance of the mutex. + */ + motionsense-mutex { + compatible = "cros-ec,motionsense-mutex"; + lid_mutex: lid-mutex { + }; + + base_mutex: base-mutex { + }; + }; + + /* Rotation matrix used by drivers. */ + motionsense-rotation-ref { + compatible = "cros-ec,motionsense-rotation-ref"; + lid_rot_ref: lid-rotation-ref { + mat33 = <0 (-1) 0 + (-1) 0 0 + 0 0 (-1)>; + }; + + base_rot_ref: base-rotation-ref { + mat33 = <1 0 0 + 0 1 0 + 0 0 1>; + }; + }; + + /* + * Driver specific data. A driver-specific data can be shared with + * different motion sensors while they are using the same driver. + * + * If a node's compatible starts with "cros-ec,accelgyro-", it is for + * a common structure defined in accelgyro.h. + * e.g) compatible = "cros-ec,accelgyro-als-drv-data" is for + * "struct als_drv_data_t" in accelgyro.h + */ + motionsense-sensor-data { + bmi323_data: bmi323-drv-data { + compatible = "cros-ec,drvdata-bmi3xx"; + status = "okay"; + }; + + bma422_data: bma422-drv-data { + compatible = "cros-ec,drvdata-bma4xx"; + status = "okay"; + }; + }; + + /* + * List of motion sensors that creates motion_sensors array. + * The nodelabel "lid_accel" and "base_accel" are used to indicate + * motion sensor IDs for lid angle calculation. + * TODO(b/238139272): The first entries of the array must be + * accelerometers,then gyroscope. Fix this dependency in the DTS + * processing which makes the devicetree entries independent. + */ + motionsense-sensor { + lid_accel: lid-accel { + compatible = "cros-ec,bma4xx"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_LID"; + mutex = <&lid_mutex>; + port = <&i2c_ec_i2c_sensor>; + rot-standard-ref = <&lid_rot_ref>; + default-range = <2>; + drv-data = <&bma422_data>; + i2c-spi-addr-flags = "BMA4_I2C_ADDR_SECONDARY"; + configs { + compatible = + "cros-ec,motionsense-sensor-config"; + ec-s0 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + ec-s3 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + }; + }; + + base_accel: base-accel { + compatible = "cros-ec,bmi3xx-accel"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_BASE"; + mutex = <&base_mutex>; + port = <&i2c_ec_i2c_sensor>; + rot-standard-ref = <&base_rot_ref>; + drv-data = <&bmi323_data>; + configs { + compatible = + "cros-ec,motionsense-sensor-config"; + ec-s0 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + ec-s3 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + }; + }; + + base_gyro: base-gyro { + compatible = "cros-ec,bmi3xx-gyro"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_BASE"; + mutex = <&base_mutex>; + port = <&i2c_ec_i2c_sensor>; + rot-standard-ref = <&base_rot_ref>; + drv-data = <&bmi323_data>; + }; + }; + + motionsense-sensor-info { + compatible = "cros-ec,motionsense-sensor-info"; + + /* + * list of GPIO interrupts that have to + * be enabled at initial stage + */ + sensor-irqs = <&int_imu>; + /* list of sensors in force mode */ + accel-force-mode-sensors = <&lid_accel>; + }; +}; diff --git a/zephyr/projects/nissa/joxer/overlay.dtsi b/zephyr/projects/nissa/joxer/overlay.dtsi new file mode 100644 index 0000000000..b587da8fb1 --- /dev/null +++ b/zephyr/projects/nissa/joxer/overlay.dtsi @@ -0,0 +1,445 @@ +/* Copyright 2021 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <cros/thermistor/thermistor.dtsi> + +/ { + aliases { + gpio-cbi-wp = &gpio_ec_cbi_wp; + gpio-wp = &gpio_ec_wp_odl; + int-wp = &int_wp_l; + /* + * USB-C: interrupt input. + * I2C pins are on i2c_ec_i2c_sub_usb_c1 + */ + gpio-usb-c1-int-odl = &gpio_sb_1; + /* + * USB-A: VBUS enable output + * LTE: power enable output + */ + gpio-en-usb-a1-vbus = &gpio_sb_2; + /* + * HDMI: power enable output, HDMI enable output, + * and HPD input + */ + gpio-en-rails-odl = &gpio_sb_1; + gpio-hdmi-en-odl = &gpio_sb_4; + gpio-hpd-odl = &gpio_sb_3; + /* + * Enable S5 rails for LTE sub-board + */ + gpio-en-sub-s5-rails = &gpio_sb_2; + }; + + ec-console { + compatible = "ec-console"; + disabled = "events", "lpc", "hostcmd"; + }; + + batteries { + default_battery: cosmx { + compatible = "cosmx,gh02047xl", "battery-smart"; + }; + dynapack_atl_gh02047xl { + compatible = "dynapack,atl_gh02047xl", "battery-smart"; + }; + dynapack_cosmx_gh02047xl { + compatible = "dynapack,cosmx_gh02047xl", "battery-smart"; + }; + smp_coslight_gh02047xl { + compatible = "smp,coslight_gh02047xl", "battery-smart"; + }; + smp_highpower_gh02047xl { + compatible = "smp,highpower_gh02047xl", "battery-smart"; + }; + }; + + hibernate-wake-pins { + compatible = "cros-ec,hibernate-wake-pins"; + wakeup-irqs = < + &int_power_button + &int_lid_open + >; + }; + + gpio-interrupts { + compatible = "cros-ec,gpio-interrupts"; + + int_power_button: power_button { + irq-pin = <&gpio_gsc_ec_pwr_btn_odl>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "power_button_interrupt"; + }; + int_vol_down: vol_down { + irq-pin = <&gpio_voldn_btn_odl>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "button_interrupt"; + }; + int_vol_up: vol_up { + irq-pin = <&gpio_volup_btn_odl>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "button_interrupt"; + }; + int_wp_l: wp_l { + irq-pin = <&gpio_ec_wp_odl>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "switch_interrupt"; + }; + int_lid_open: lid_open { + irq-pin = <&gpio_lid_open>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "lid_interrupt"; + }; + int_tablet_mode: tablet_mode { + irq-pin = <&gpio_tablet_mode_l>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "gmr_tablet_switch_isr"; + }; + int_imu: ec_imu { + irq-pin = <&gpio_imu_int_l>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "bmi3xx_interrupt"; + }; + int_usb_c0: usb_c0 { + irq-pin = <&gpio_usb_c0_int_odl>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "usb_c0_interrupt"; + }; + int_usb_c1: usb_c1 { + irq-pin = <&gpio_sb_1>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "usb_c1_interrupt"; + }; + }; + + unused-pins { + compatible = "unused-gpios"; + unused-gpios = <&gpioc 3 0>, + <&gpiod 4 0>, + <&gpioh 2 0>, + <&gpiol 4 0>; + }; + + named-gpios { + /* + * EC doesn't take any specific action on CC/SBU disconnect due to + * fault, but this definition is useful for hardware testing. + */ + gpio_usb_c0_prot_fault_odl: usb_c0_prot_fault_odl { + gpios = <&gpiok 6 GPIO_INPUT_PULL_UP>; + }; + + gpio_sb_1: sb_1 { + gpios = <&gpioe 6 0>; + no-auto-init; + }; + gpio_sb_2: sb_2 { + gpios = <&gpiof 0 0>; + no-auto-init; + }; + + gpio_sb_3: sb_3 { + gpios = <&gpioe 7 0>; + no-auto-init; + }; + gpio_sb_4: sb_4 { + gpios = <&gpioe 0 0>; + no-auto-init; + }; + gpio_fan_enable: fan-enable { + gpios = <&gpiol 4 GPIO_OUTPUT>; + no-auto-init; + }; + gpio_power_led_gate: power_led_gate { + gpios = <&gpiof 1 GPIO_OUTPUT_LOW>; + }; + gpio_led_1_odl: led_1_odl { + gpios = <&gpioa 1 GPIO_OUTPUT_HIGH>; + }; + gpio_led_2_odl: led_2_odl { + gpios = <&gpioa 2 GPIO_OUTPUT_HIGH>; + }; + gpio_led_3_l: led_3_l { + gpios = <&gpiol 2 GPIO_OUTPUT_HIGH>; + }; + gpio_led_4_l: led_4_l { + gpios = <&gpiol 3 GPIO_OUTPUT_HIGH>; + }; + }; + + temp_memory: memory { + compatible = "cros-ec,temp-sensor-thermistor"; + thermistor = <&thermistor_3V3_51K1_47K_4050B>; + adc = <&adc_temp_sensor_1>; + }; + temp_charger: charger { + compatible = "cros-ec,temp-sensor-thermistor"; + thermistor = <&thermistor_3V3_51K1_47K_4050B>; + adc = <&adc_temp_sensor_2>; + }; + temp_ambient: ambient { + compatible = "cros-ec,temp-sensor-thermistor"; + thermistor = <&thermistor_3V3_51K1_47K_4050B>; + adc = <&adc_temp_sensor_3>; + }; + + named-temp-sensors { + compatible = "cros-ec,temp-sensors"; + memory { + temp_fan_off = <35>; + temp_fan_max = <60>; + temp_host_high = <85>; + temp_host_halt = <90>; + temp_host_release_high = <80>; + power-good-pin = <&gpio_ec_soc_dsw_pwrok>; + sensor = <&temp_memory>; + }; + charger { + temp_fan_off = <35>; + temp_fan_max = <60>; + temp_host_high = <85>; + temp_host_halt = <90>; + temp_host_release_high = <80>; + power-good-pin = <&gpio_ec_soc_dsw_pwrok>; + sensor = <&temp_charger>; + }; + ambient { + temp_fan_off = <35>; + temp_fan_max = <60>; + temp_host_high = <85>; + temp_host_halt = <90>; + temp_host_release_high = <80>; + power-good-pin = <&gpio_ec_soc_dsw_pwrok>; + sensor = <&temp_ambient>; + }; + }; + + usba { + compatible = "cros-ec,usba-port-enable-pins"; + /* + * sb_2 is only configured as GPIO when USB-A1 is present, + * but it's still safe to control when disabled. + * + * ILIM_SEL pins are referred to by legacy enum name, + * GPIO_USB*_ILIM_SEL. The one for port A1 is unused on + * sub-boards that don't have USB-A so is safe to control + * regardless of system configuration. + */ + enable-pins = <&gpio_en_usb_a0_vbus &gpio_sb_2>; + status = "okay"; + }; + + usbc { + #address-cells = <1>; + #size-cells = <0>; + + port0@0 { + compatible = "named-usbc-port"; + reg = <0>; + bc12 = <&bc12_port0>; + chg = <&chg_port0>; + usb-mux-chain-0 { + compatible = "cros-ec,usb-mux-chain"; + usb-muxes = <&virtual_mux_0>; + }; + }; + port0-muxes { + virtual_mux_0: virtual-mux-0 { + compatible = "cros-ec,usbc-mux-virtual"; + }; + }; + port1@1 { + compatible = "named-usbc-port"; + reg = <1>; + bc12 = <&bc12_port1>; + chg = <&chg_port1>; + usb-mux-chain-1 { + compatible = "cros-ec,usb-mux-chain"; + usb-muxes = <&virtual_mux_1 &tcpci_mux_1>; + }; + usb_mux_chain_1_no_mux: usb-mux-chain-1-no-mux { + compatible = "cros-ec,usb-mux-chain"; + alternative-chain; + usb-muxes = <&virtual_mux_1>; + }; + }; + port1-muxes { + virtual_mux_1: virtual-mux-1 { + compatible = "cros-ec,usbc-mux-virtual"; + }; + tcpci_mux_1: tcpci-mux-1 { + compatible = "parade,usbc-mux-ps8xxx"; + }; + }; + }; + fans { + compatible = "cros-ec,fans"; + + fan_0 { + pwms = <&pwm7 PWM_CHANNEL_7 PWM_KHZ(30) PWM_POLARITY_NORMAL>; + tach = <&tach1>; + rpm_min = <1500>; + rpm_start = <1500>; + rpm_max = <6500>; + enable_gpio = <&gpio_fan_enable>; + }; + }; +}; + +&gpio_acc_int_l { + gpios = <&gpioc 0 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; +}; +&gpio_imu_int_l { + gpios = <&gpioj 0 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; +}; +&gpio_vccin_aux_vid0 { + gpios = <&gpiod 0 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; +}; +&gpio_vccin_aux_vid1 { + gpios = <&gpiok 1 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; +}; + +&gpio_ec_prochot_odl { + gpios = <&gpioi 1 (GPIO_ODR_HIGH | GPIO_VOLTAGE_1P8)>; +}; + +&thermistor_3V3_51K1_47K_4050B { + status = "okay"; +}; + +&adc_ec_vsense_pp3300_s5 { + /* + * Voltage divider on input has 47k upper and 220k lower legs with 3 V + * full-scale reading on the ADC. Apply the largest possible multiplier + * (without overflowing int32) to get the best possible approximation + * of the actual ratio, but derate by a factor of two to ensure + * unexpectedly high values won't overflow. + */ + mul = <(715828 / 2)>; + div = <(589820 / 2)>; +}; + +&adc0 { + pinctrl-0 = <&adc0_ch0_gpi0_default + &adc0_ch2_gpi2_default + &adc0_ch3_gpi3_default + &adc0_ch13_gpl0_default + &adc0_ch14_gpl1_default>; + pinctrl-names = "default"; +}; + +&pinctrl { + i2c2_clk_gpf6_default: i2c2_clk_gpf6_default { + gpio-voltage = "1v8"; + }; + i2c2_data_gpf7_default: i2c2_data_gpf7_default { + gpio-voltage = "1v8"; + }; +}; + + +&i2c0 { + label = "I2C_EEPROM"; + clock-frequency = <I2C_BITRATE_FAST>; + + cbi_eeprom: eeprom@50 { + compatible = "atmel,at24"; + reg = <0x50>; + size = <2048>; + pagesize = <16>; + address-width = <8>; + timeout = <5>; + }; + pinctrl-0 = <&i2c0_clk_gpb3_default + &i2c0_data_gpb4_default>; + pinctrl-names = "default"; +}; + +&i2c1 { + label = "I2C_BATTERY"; + clock-frequency = <50000>; + pinctrl-0 = <&i2c1_clk_gpc1_default + &i2c1_data_gpc2_default>; + pinctrl-names = "default"; +}; + +&i2c2 { + label = "I2C_SENSOR"; + clock-frequency = <I2C_BITRATE_FAST>; + pinctrl-0 = <&i2c2_clk_gpf6_default + &i2c2_data_gpf7_default>; + pinctrl-names = "default"; +}; + +&i2c4 { + label = "I2C_SUB_C1_TCPC"; + clock-frequency = <I2C_BITRATE_FAST_PLUS>; + pinctrl-0 = <&i2c4_clk_gpe0_default + &i2c4_data_gpe7_default>; + pinctrl-names = "default"; + + bc12_port1: pi3usb9201@5f { + compatible = "pericom,pi3usb9201"; + status = "okay"; + reg = <0x5f>; + }; + + chg_port1: sm5803@32 { + compatible = "siliconmitus,sm5803"; + status = "okay"; + reg = <0x32>; + }; +}; + +&i2c_ec_i2c_sub_usb_c1 { + /* + * Dynamic speed setting is used for AP-controlled firmware update + * of PS8745 TCPC/redriver: the AP lowers speed to 400 kHz in order + * to use more efficient window programming, then sets it back when + * done. + */ + dynamic-speed; +}; + +&i2c5 { + label = "I2C_USB_C0_TCPC"; + clock-frequency = <I2C_BITRATE_FAST_PLUS>; + pinctrl-0 = <&i2c5_clk_gpa4_default + &i2c5_data_gpa5_default>; + pinctrl-names = "default"; + + bc12_port0: pi3usb9201@5f { + compatible = "pericom,pi3usb9201"; + status = "okay"; + reg = <0x5f>; + }; + + chg_port0: sm5803@32 { + compatible = "siliconmitus,sm5803"; + status = "okay"; + reg = <0x32>; + }; +}; + +/* pwm for fan */ +&pwm7 { + status = "okay"; + prescaler-cx = <PWM_PRESCALER_C6>; + pinctrl-0 = <&pwm7_gpa7_default>; + pinctrl-names = "default"; +}; + +/* fan tachometer sensor */ +&tach1 { + status = "okay"; + channel = <IT8XXX2_TACH_CHANNEL_A>; + pulses-per-round = <2>; + pinctrl-0 = <&tach1a_gpd7_default>; + pinctrl-names = "default"; +}; + +&usbpd0 { + status = "okay"; +}; diff --git a/zephyr/projects/nissa/joxer/power_signals.dtsi b/zephyr/projects/nissa/joxer/power_signals.dtsi new file mode 100644 index 0000000000..8affae03b1 --- /dev/null +++ b/zephyr/projects/nissa/joxer/power_signals.dtsi @@ -0,0 +1,223 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + chosen { + intel-ap-pwrseq,espi = &espi0; + }; + + common-pwrseq { + compatible = "intel,ap-pwrseq"; + + sys-pwrok-delay = <10>; + all-sys-pwrgd-timeout = <20>; + }; + + pwr-en-pp5000-s5 { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "PP5000_S5 enable output to regulator"; + enum-name = "PWR_EN_PP5000_A"; + gpios = <&gpiok 5 0>; + output; + }; + pwr-en-pp3300-s5 { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "PP3300_S5 enable output to LS"; + enum-name = "PWR_EN_PP3300_A"; + gpios = <&gpioc 5 0>; + output; + }; + pwr-pg-ec-rsmrst-odl { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "RSMRST power good from regulator"; + enum-name = "PWR_RSMRST"; + gpios = <&gpioe 1 0>; + interrupt-flags = <GPIO_INT_EDGE_BOTH>; + }; + pwr-ec-pch-rsmrst-odl { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "RSMRST output to PCH"; + enum-name = "PWR_EC_PCH_RSMRST"; + gpios = <&gpioh 0 0>; + output; + }; + pwr-slp-s0-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SLP_S0_L input from PCH"; + enum-name = "PWR_SLP_S0"; + gpios = <&gpioe 4 GPIO_ACTIVE_LOW>; + interrupt-flags = <GPIO_INT_EDGE_BOTH>; + }; + pwr-slp-s3-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SLP_S3_L input from PCH"; + enum-name = "PWR_SLP_S3"; + gpios = <&gpioh 3 GPIO_ACTIVE_LOW>; + interrupt-flags = <GPIO_INT_EDGE_BOTH>; + }; + pwr-slp-sus-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SLP_SUS_L input from PCH"; + enum-name = "PWR_SLP_SUS"; + gpios = <&gpiog 2 GPIO_ACTIVE_LOW>; + interrupt-flags = <GPIO_INT_EDGE_BOTH>; + }; + pwr-ec-soc-dsw-pwrok { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "DSW_PWROK output to PCH"; + enum-name = "PWR_EC_SOC_DSW_PWROK"; + gpios = <&gpiol 7 0>; + output; + }; + pwr-vccst-pwrgd-od { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "VCCST_PWRGD output to PCH"; + enum-name = "PWR_VCCST_PWRGD"; + gpios = <&gpioe 5 (GPIO_OPEN_DRAIN | GPIO_VOLTAGE_1P8)>; + output; + }; + pwr-imvp9-vrrdy-od { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "VRRDY input from IMVP9"; + enum-name = "PWR_IMVP9_VRRDY"; + gpios = <&gpioj 4 0>; + }; + pwr-pch-pwrok { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "PCH_PWROK output to PCH"; + enum-name = "PWR_PCH_PWROK"; + gpios = <&gpiod 6 GPIO_OPEN_DRAIN>; + output; + }; + pwr-ec-pch-sys-pwrok { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SYS_PWROK output to PCH"; + enum-name = "PWR_EC_PCH_SYS_PWROK"; + gpios = <&gpiof 2 0>; + output; + }; + pwr-sys-rst-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SYS_RESET# output to PCH"; + enum-name = "PWR_SYS_RST"; + gpios = <&gpiod 1 (GPIO_ACTIVE_LOW|GPIO_OPEN_DRAIN)>; + output; + }; + pwr-slp-s4 { + compatible = "intel,ap-pwrseq-vw"; + dbg-label = "SLP_S4 virtual wire input from PCH"; + enum-name = "PWR_SLP_S4"; + virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S4"; + vw-invert; + }; + pwr-slp-s5 { + compatible = "intel,ap-pwrseq-vw"; + dbg-label = "SLP_S5 virtual wire input from PCH"; + enum-name = "PWR_SLP_S5"; + virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S5"; + vw-invert; + }; + pwr-all-sys-pwrgd { + /* + * This is a board level signal, since this + * signal needs some special processing. + */ + compatible = "intel,ap-pwrseq-external"; + dbg-label = "Combined all power good"; + enum-name = "PWR_ALL_SYS_PWRGD"; + }; + pwr-adc-pp3300 { + compatible = "intel,ap-pwrseq-adc"; + dbg-label = "PP3300_PROC"; + enum-name = "PWR_DSW_PWROK"; + trigger-high = <&vcmp0>; + trigger-low = <&vcmp1>; + }; + pwr-adc-pp1p05 { + compatible = "intel,ap-pwrseq-adc"; + dbg-label = "PP1P05_PROC"; + enum-name = "PWR_PG_PP1P05"; + trigger-high = <&vcmp2>; + trigger-low = <&vcmp3>; + }; + +}; + +/* + * Because the power signals directly reference the GPIOs, + * the correspinding named-gpios need to have no-auto-init set. + */ +&gpio_ec_soc_dsw_pwrok { + no-auto-init; +}; +&gpio_ec_soc_pch_pwrok_od { + no-auto-init; +}; +&gpio_ec_soc_rsmrst_l { + no-auto-init; +}; +&gpio_ec_soc_sys_pwrok { + no-auto-init; +}; +&gpio_ec_soc_vccst_pwrgd_od { + no-auto-init; +}; +&gpio_en_pp3300_s5 { + no-auto-init; +}; +&gpio_en_pp5000_s5 { + no-auto-init; +}; +&gpio_imvp91_vrrdy_od { + no-auto-init; +}; +&gpio_rsmrst_pwrgd_l { + no-auto-init; +}; +&gpio_slp_s0_l { + no-auto-init; +}; +&gpio_slp_s3_l { + no-auto-init; +}; +&gpio_slp_sus_l { + no-auto-init; +}; +&gpio_sys_rst_odl { + no-auto-init; +}; +&vcmp0 { + status = "okay"; + scan-period = <IT8XXX2_VCMP_SCAN_PERIOD_600US>; + comparison = <IT8XXX2_VCMP_GREATER>; + /* + * This is 90% of nominal voltage considering voltage + * divider on ADC input. + */ + threshold-mv = <2448>; + io-channels = <&adc0 0>; +}; +&vcmp1 { + status = "okay"; + scan-period = <IT8XXX2_VCMP_SCAN_PERIOD_600US>; + comparison = <IT8XXX2_VCMP_LESS_OR_EQUAL>; + threshold-mv = <2448>; + io-channels = <&adc0 0>; +}; +&vcmp2 { + status = "okay"; + scan-period = <IT8XXX2_VCMP_SCAN_PERIOD_600US>; + comparison = <IT8XXX2_VCMP_GREATER>; + /* Setting at 90% of nominal voltage */ + threshold-mv = <945>; + io-channels = <&adc0 14>; +}; +&vcmp3 { + status = "okay"; + scan-period = <IT8XXX2_VCMP_SCAN_PERIOD_600US>; + comparison = <IT8XXX2_VCMP_LESS_OR_EQUAL>; + threshold-mv = <945>; + io-channels = <&adc0 14>; +}; diff --git a/zephyr/projects/nissa/joxer/project.conf b/zephyr/projects/nissa/joxer/project.conf new file mode 100644 index 0000000000..a0de72294c --- /dev/null +++ b/zephyr/projects/nissa/joxer/project.conf @@ -0,0 +1,19 @@ +# Copyright 2021 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +CONFIG_BOARD_JOXER=y + +# Ensure recovery key combination (esc+refresh+power) is reliable: b/236580049 +CONFIG_PLATFORM_EC_KEYBOARD_PWRBTN_ASSERTS_KSI3=y +CONFIG_PLATFORM_EC_KEYBOARD_REFRESH_ROW3=y + +# Sensor drivers +CONFIG_PLATFORM_EC_ACCELGYRO_BMI_COMM_I2C=y +CONFIG_PLATFORM_EC_ACCELGYRO_BMI3XX=y +CONFIG_PLATFORM_EC_ACCEL_BMA4XX=y +CONFIG_PLATFORM_EC_MAX_SENSOR_FREQ_MILLIHZ=100000 + +# LED +CONFIG_PLATFORM_EC_LED_PWM=n +CONFIG_PLATFORM_EC_LED_COMMON=y diff --git a/zephyr/projects/nissa/joxer/project.overlay b/zephyr/projects/nissa/joxer/project.overlay new file mode 100644 index 0000000000..9ca681d979 --- /dev/null +++ b/zephyr/projects/nissa/joxer/project.overlay @@ -0,0 +1,14 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "../cbi.dtsi" + +#include "cbi.dtsi" +#include "generated.dtsi" +#include "keyboard.dtsi" +#include "motionsense.dtsi" +#include "overlay.dtsi" +#include "power_signals.dtsi" +#include "pwm_leds.dtsi" diff --git a/zephyr/projects/nissa/joxer/pwm_leds.dtsi b/zephyr/projects/nissa/joxer/pwm_leds.dtsi new file mode 100644 index 0000000000..aa4a76b271 --- /dev/null +++ b/zephyr/projects/nissa/joxer/pwm_leds.dtsi @@ -0,0 +1,60 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + pwmleds { + compatible = "pwm-leds"; + pwm_led0: pwm_led_0 { + pwms = <&pwm1 1 PWM_HZ(1296) PWM_POLARITY_INVERTED>, + <&pwm2 2 PWM_HZ(1296) PWM_POLARITY_INVERTED>, + <&pwm3 3 PWM_HZ(1296) PWM_POLARITY_INVERTED>; + }; + }; + + cros-pwmleds { + compatible = "cros-ec,pwm-leds"; + + leds = <&pwm_led0>; + + /*<red green blue>*/ + color-map-red = <100 0 0>; + color-map-green = < 0 100 0>; + color-map-blue = < 0 0 100>; + color-map-yellow = < 0 50 50>; + color-map-white = <100 100 100>; + color-map-amber = <100 15 0>; + + brightness-range = <100 100 100 0 0 0>; + + #address-cells = <1>; + #size-cells = <0>; + + pwm_led_0@0 { + reg = <0>; + ec-led-name = "EC_LED_ID_BATTERY_LED"; + }; + }; +}; + +&pwm1 { + status = "okay"; + prescaler-cx = <PWM_PRESCALER_C4>; + pinctrl-0 = <&pwm1_gpa1_default>; + pinctrl-names = "default"; +}; + +&pwm2 { + status = "okay"; + prescaler-cx = <PWM_PRESCALER_C4>; + pinctrl-0 = <&pwm2_gpa2_default>; + pinctrl-names = "default"; +}; + +&pwm3 { + status = "okay"; + prescaler-cx = <PWM_PRESCALER_C4>; + pinctrl-0 = <&pwm3_gpa3_default>; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/nissa/joxer/src/charger.c b/zephyr/projects/nissa/joxer/src/charger.c new file mode 100644 index 0000000000..b9454d8b80 --- /dev/null +++ b/zephyr/projects/nissa/joxer/src/charger.c @@ -0,0 +1,56 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <zephyr/logging/log.h> + +#include "battery.h" +#include "charger.h" +#include "console.h" +#include "driver/charger/sm5803.h" +#include "extpower.h" +#include "usb_pd.h" +#include "nissa_common.h" + +LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL); + +int extpower_is_present(void) +{ + int port; + int rv; + bool acok; + + for (port = 0; port < board_get_usb_pd_port_count(); port++) { + rv = sm5803_is_acok(port, &acok); + if ((rv == EC_SUCCESS) && acok) + return 1; + } + + return 0; +} + +/* + * Joxer not have a GPIO indicating whether extpower is present, + * so detect using the charger(s). + */ +__override void board_check_extpower(void) +{ + static int last_extpower_present; + int extpower_present = extpower_is_present(); + + if (last_extpower_present ^ extpower_present) + extpower_handle_update(extpower_present); + + last_extpower_present = extpower_present; +} + +__override void board_hibernate(void) +{ + /* Shut down the chargers */ + if (board_get_usb_pd_port_count() == 2) + sm5803_hibernate(CHARGER_SECONDARY); + sm5803_hibernate(CHARGER_PRIMARY); + LOG_INF("Charger(s) hibernated"); + cflush(); +} diff --git a/zephyr/projects/nissa/joxer/src/fan.c b/zephyr/projects/nissa/joxer/src/fan.c new file mode 100644 index 0000000000..6d234b2fc3 --- /dev/null +++ b/zephyr/projects/nissa/joxer/src/fan.c @@ -0,0 +1,43 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <zephyr/devicetree.h> +#include <zephyr/drivers/gpio.h> +#include <zephyr/logging/log.h> + +#include "cros_cbi.h" +#include "fan.h" +#include "gpio/gpio.h" +#include "hooks.h" + +#include "nissa_common.h" + +LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL); + +/* + * Joxer fan support + */ +static void fan_init(void) +{ + int ret; + uint32_t val; + /* + * Retrieve the fan config. + */ + ret = cros_cbi_get_fw_config(FW_FAN, &val); + if (ret != 0) { + LOG_ERR("Error retrieving CBI FW_CONFIG field %d", FW_FAN); + return; + } + if (val != FW_FAN_PRESENT) { + /* Disable the fan */ + fan_set_count(0); + } else { + /* Configure the fan enable GPIO */ + gpio_pin_configure_dt(GPIO_DT_FROM_NODELABEL(gpio_fan_enable), + GPIO_OUTPUT); + } +} +DECLARE_HOOK(HOOK_INIT, fan_init, HOOK_PRIO_POST_FIRST); diff --git a/zephyr/projects/nissa/joxer/src/keyboard.c b/zephyr/projects/nissa/joxer/src/keyboard.c new file mode 100644 index 0000000000..48db40f53f --- /dev/null +++ b/zephyr/projects/nissa/joxer/src/keyboard.c @@ -0,0 +1,68 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <zephyr/devicetree.h> +#include <zephyr/drivers/gpio.h> +#include <zephyr/logging/log.h> + +#include "cros_cbi.h" +#include "ec_commands.h" +#include "gpio/gpio.h" +#include "hooks.h" +#include "keyboard_8042_sharedlib.h" +#include "nissa_common.h" + +LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL); + +static const struct ec_response_keybd_config joxer_kb_legacy = { + .num_top_row_keys = 13, + .action_keys = { + TK_BACK, /* T1 */ + TK_REFRESH, /* T2 */ + TK_FULLSCREEN, /* T3 */ + TK_OVERVIEW, /* T4 */ + TK_SNAPSHOT, /* T5 */ + TK_BRIGHTNESS_DOWN, /* T6 */ + TK_BRIGHTNESS_UP, /* T7 */ + TK_KBD_BKLIGHT_TOGGLE, /* T8 */ + TK_PLAY_PAUSE, /* T9 */ + TK_MICMUTE, /* T10 */ + TK_VOL_MUTE, /* T11 */ + TK_VOL_DOWN, /* T12 */ + TK_VOL_UP, /* T13 */ + }, + .capabilities = KEYBD_CAP_SCRNLOCK_KEY, +}; + +__override const struct ec_response_keybd_config * +board_vivaldi_keybd_config(void) +{ + return &joxer_kb_legacy; +} + +/* + * Keyboard layout decided by FW config. + */ +static void kb_layout_init(void) +{ + int ret; + uint32_t val; + /* + * Retrieve the kb layout config. + */ + ret = cros_cbi_get_fw_config(FW_KB_LAYOUT, &val); + if (ret != 0) { + LOG_ERR("Error retrieving CBI FW_CONFIG field %d", + FW_KB_LAYOUT); + return; + } + /* + * If keyboard is US2(FW_KB_LAYOUT_US2), we need translate right ctrl + * to backslash(\|) key. + */ + if (val == FW_KB_LAYOUT_US2) + set_scancode_set2(4, 0, get_scancode_set2(2, 7)); +} +DECLARE_HOOK(HOOK_INIT, kb_layout_init, HOOK_PRIO_POST_FIRST); diff --git a/zephyr/projects/nissa/joxer/src/led.c b/zephyr/projects/nissa/joxer/src/led.c new file mode 100644 index 0000000000..d66e5b27a6 --- /dev/null +++ b/zephyr/projects/nissa/joxer/src/led.c @@ -0,0 +1,181 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + * + * Battery LED control for nissa + */ +#include <stdint.h> + +#include "charge_manager.h" +#include "common.h" +#include "compile_time_macros.h" +#include "ec_commands.h" +#include "gpio.h" +#include "led_common.h" +#include "led_onoff_states.h" +#include "pwm.h" +#include "util.h" + +#define BAT_LED_ON_LVL 0 +#define BAT_LED_OFF_LVL 1 + +#define PWR_LED_ON_LVL 1 +#define PWR_LED_OFF_LVL 0 + +#define LED_SIDESEL_MB_PORT 0 +#define LED_SIDESEL_DB_PORT 1 + +__override const int led_charge_lvl_1 = 5; +__override const int led_charge_lvl_2 = 95; + +__override struct led_descriptor + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER, + 0.5 * LED_ONE_SEC }, + { LED_OFF, 0.5 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + }; + +__override const struct led_descriptor + led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { + [PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } }, + [PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [PWR_LED_STATE_SUSPEND_NO_AC] = { { EC_LED_COLOR_WHITE, + 1 * LED_ONE_SEC }, + { LED_OFF, + 1 * LED_ONE_SEC } }, + [PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } }, + }; + +const enum ec_led_id supported_led_ids[] = { + EC_LED_ID_BATTERY_LED, + EC_LED_ID_POWER_LED, +}; + +const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); + +__override void led_set_color_battery(enum ec_led_colors color) +{ + int port; + + /* There are four battery leds, LED1/LED2 are on MB side and + * LED3/LED4 are on DB side. All leds are OFF by default. + */ + int led1, led2, led3, led4; + + led1 = led2 = led3 = led4 = BAT_LED_OFF_LVL; + + /* Check which port is the charging port, + * and turn on the corresponding led. + */ + if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) { + port = charge_manager_get_active_charge_port(); + switch (port) { + case LED_SIDESEL_MB_PORT: + switch (color) { + case EC_LED_COLOR_AMBER: + led1 = BAT_LED_ON_LVL; + break; + case EC_LED_COLOR_WHITE: + led2 = BAT_LED_ON_LVL; + break; + default: /* LED_OFF and other unsupported colors */ + break; + } + break; + case LED_SIDESEL_DB_PORT: + switch (color) { + case EC_LED_COLOR_AMBER: + led3 = BAT_LED_ON_LVL; + break; + case EC_LED_COLOR_WHITE: + led4 = BAT_LED_ON_LVL; + break; + default: /* LED_OFF and other unsupported colors */ + break; + } + break; + default: /* Unknown charging port */ + break; + } + } else { + switch (color) { + case EC_LED_COLOR_AMBER: + led1 = BAT_LED_ON_LVL; + led3 = BAT_LED_ON_LVL; + break; + case EC_LED_COLOR_WHITE: + led2 = BAT_LED_ON_LVL; + led4 = BAT_LED_ON_LVL; + break; + default: /* LED_OFF and other unsupported colors */ + break; + } + } + + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_led_1_odl), led1); + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_led_2_odl), led2); + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_led_3_l), led3); + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_led_4_l), led4); +} + +__override void led_set_color_power(enum ec_led_colors color) +{ + if (color == EC_LED_COLOR_WHITE) + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_power_led_gate), + PWR_LED_ON_LVL); + else + /* LED_OFF and unsupported colors */ + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_power_led_gate), + PWR_LED_OFF_LVL); +} + +void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range) +{ + if (led_id == EC_LED_ID_BATTERY_LED) { + brightness_range[EC_LED_COLOR_AMBER] = 1; + brightness_range[EC_LED_COLOR_WHITE] = 1; + } else if (led_id == EC_LED_ID_POWER_LED) { + brightness_range[EC_LED_COLOR_WHITE] = 1; + } +} + +int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness) +{ + if (led_id == EC_LED_ID_BATTERY_LED) { + led_auto_control(led_id, 0); + if (brightness[EC_LED_COLOR_AMBER] != 0) + led_set_color_battery(EC_LED_COLOR_AMBER); + else if (brightness[EC_LED_COLOR_WHITE] != 0) + led_set_color_battery(EC_LED_COLOR_WHITE); + else if (brightness[LED_OFF] != 0) + led_set_color_battery(LED_OFF); + else { + led_auto_control(led_id, 1); + led_set_color_battery(LED_OFF); + } + } else if (led_id == EC_LED_ID_POWER_LED) { + if (brightness[EC_LED_COLOR_WHITE] != 0) + led_set_color_power(EC_LED_COLOR_WHITE); + else + led_set_color_power(LED_OFF); + } + + return EC_SUCCESS; +} diff --git a/zephyr/projects/nissa/joxer/src/usbc.c b/zephyr/projects/nissa/joxer/src/usbc.c new file mode 100644 index 0000000000..5fec9ab544 --- /dev/null +++ b/zephyr/projects/nissa/joxer/src/usbc.c @@ -0,0 +1,392 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <zephyr/logging/log.h> +#include <ap_power/ap_power.h> + +#include "charge_state_v2.h" +#include "chipset.h" +#include "hooks.h" +#include "usb_mux.h" +#include "system.h" +#include "driver/charger/sm5803.h" +#include "driver/tcpm/it83xx_pd.h" +#include "driver/tcpm/ps8xxx_public.h" +#include "driver/tcpm/tcpci.h" + +#include "nissa_common.h" + +LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL); + +struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = { + { + .bus_type = EC_BUS_TYPE_EMBEDDED, + /* TCPC is embedded within EC so no i2c config needed */ + .drv = &it8xxx2_tcpm_drv, + /* Alert is active-low, push-pull */ + .flags = 0, + }, + { + /* + * Sub-board: optional PS8745 TCPC+redriver. Behaves the same + * as PS8815. + */ + .bus_type = EC_BUS_TYPE_I2C, + .i2c_info = { + .port = I2C_PORT_USB_C1_TCPC, + .addr_flags = PS8XXX_I2C_ADDR1_FLAGS, + }, + .drv = &ps8xxx_tcpm_drv, + /* PS8745 implements TCPCI 2.0 */ + .flags = TCPC_FLAGS_TCPCI_REV2_0, + }, +}; + +/* Vconn control for integrated ITE TCPC */ +void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled) +{ + /* Vconn control is only for port 0 */ + if (port) + return; + + if (cc_pin == USBPD_CC_PIN_1) + gpio_pin_set_dt( + GPIO_DT_FROM_NODELABEL(gpio_en_usb_c0_cc1_vconn), + !!enabled); + else + gpio_pin_set_dt( + GPIO_DT_FROM_NODELABEL(gpio_en_usb_c0_cc2_vconn), + !!enabled); +} + +__override bool pd_check_vbus_level(int port, enum vbus_level level) +{ + return sm5803_check_vbus_level(port, level); +} + +/* + * Putting chargers into LPM when in suspend reduces power draw by about 8mW + * per charger, but also seems critical to correct operation in source mode: + * if chargers are not in LPM when a sink is first connected, VBUS sourcing + * works even if the partner is later removed (causing LPM entry) and + * reconnected (causing LPM exit). If in LPM initially, sourcing VBUS + * consistently causes the charger to report (apparently spurious) overcurrent + * failures. + * + * In short, this is important to making things work correctly but we don't + * understand why. + */ +static void board_chargers_suspend(struct ap_power_ev_callback *const cb, + const struct ap_power_ev_data data) +{ + void (*fn)(int chgnum); + + switch (data.event) { + case AP_POWER_SUSPEND: + fn = sm5803_enable_low_power_mode; + break; + case AP_POWER_RESUME: + fn = sm5803_disable_low_power_mode; + break; + default: + LOG_WRN("%s: power event %d is not recognized", __func__, + data.event); + return; + } + + fn(CHARGER_PRIMARY); + if (board_get_charger_chip_count() > 1) + fn(CHARGER_SECONDARY); +} + +static int board_chargers_suspend_init(const struct device *unused) +{ + static struct ap_power_ev_callback cb = { + .handler = board_chargers_suspend, + .events = AP_POWER_SUSPEND | AP_POWER_RESUME, + }; + ap_power_ev_add_callback(&cb); + return 0; +} +SYS_INIT(board_chargers_suspend_init, APPLICATION, 0); + +int board_set_active_charge_port(int port) +{ + int is_real_port = (port >= 0 && port < board_get_usb_pd_port_count()); + int i; + int old_port; + int rv; + + if (!is_real_port && port != CHARGE_PORT_NONE) + return EC_ERROR_INVAL; + + old_port = charge_manager_get_active_charge_port(); + LOG_INF("Charge update: p%d -> p%d", old_port, port); + + /* Check if port is sourcing VBUS. */ + if (port != CHARGE_PORT_NONE && charger_is_sourcing_otg_power(port)) { + LOG_WRN("Skip enable p%d: already sourcing", port); + return EC_ERROR_INVAL; + } + + /* Disable sinking on all ports except the desired one */ + for (i = 0; i < board_get_usb_pd_port_count(); i++) { + if (i == port) + continue; + + if (sm5803_vbus_sink_enable(i, 0)) + /* + * Do not early-return because this can fail during + * power-on which would put us into a loop. + */ + LOG_WRN("p%d: sink path disable failed.", i); + } + + /* Don't enable anything (stop here) if no ports were requested */ + if ((port == CHARGE_PORT_NONE) || (old_port == port)) + return EC_SUCCESS; + + /* + * Stop the charger IC from switching while changing ports. Otherwise, + * we can overcurrent the adapter we're switching to. (crbug.com/926056) + */ + if (old_port != CHARGE_PORT_NONE) + charger_discharge_on_ac(1); + + /* Enable requested charge port. */ + rv = sm5803_vbus_sink_enable(port, 1); + if (rv) + LOG_WRN("p%d: sink path enable failed: code %d", port, rv); + + /* Allow the charger IC to begin/continue switching. */ + charger_discharge_on_ac(0); + + return rv; +} + +uint16_t tcpc_get_alert_status(void) +{ + /* + * TCPC 0 is embedded in the EC and processes interrupts in the chip + * code (it83xx/intc.c). This function only needs to poll port C1 if + * present. + */ + uint16_t status = 0; + int regval; + + /* Is the C1 port present and its IRQ line asserted? */ + if (board_get_usb_pd_port_count() == 2 && + !gpio_pin_get_dt(GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl))) { + /* + * C1 IRQ is shared between BC1.2 and TCPC; poll TCPC to see if + * it asserted the IRQ. + */ + if (!tcpc_read16(1, TCPC_REG_ALERT, ®val)) { + if (regval) + status = PD_STATUS_TCPC_ALERT_1; + } + } + + return status; +} + +void pd_power_supply_reset(int port) +{ + int prev_en; + + if (port < 0 || port >= board_get_usb_pd_port_count()) + return; + + prev_en = charger_is_sourcing_otg_power(port); + + /* Disable Vbus */ + charger_enable_otg_power(port, 0); + + /* Discharge Vbus if previously enabled */ + if (prev_en) + sm5803_set_vbus_disch(port, 1); + + /* Notify host of power info change. */ + pd_send_host_event(PD_EVENT_POWER_CHANGE); +} + +int pd_set_power_supply_ready(int port) +{ + enum ec_error_list rv; + + if (port < 0 || port > board_get_usb_pd_port_count()) { + LOG_WRN("Port C%d does not exist, cannot enable VBUS", port); + return EC_ERROR_INVAL; + } + + /* Disable sinking */ + rv = sm5803_vbus_sink_enable(port, 0); + if (rv) { + LOG_WRN("C%d failed to disable sinking: %d", port, rv); + return rv; + } + + /* Disable Vbus discharge */ + rv = sm5803_set_vbus_disch(port, 0); + if (rv) { + LOG_WRN("C%d failed to clear VBUS discharge: %d", port, rv); + return rv; + } + + /* Provide Vbus */ + rv = charger_enable_otg_power(port, 1); + if (rv) { + LOG_WRN("C%d failed to enable VBUS sourcing: %d", port, rv); + return rv; + } + + /* Notify host of power info change. */ + pd_send_host_event(PD_EVENT_POWER_CHANGE); + + return EC_SUCCESS; +} + +__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp) +{ + int rv; + const int current = rp == TYPEC_RP_3A0 ? 3000 : 1500; + + rv = charger_set_otg_current_voltage(port, current, 5000); + if (rv != EC_SUCCESS) { + LOG_WRN("Failed to set source ilimit on port %d to %d: %d", + port, current, rv); + } +} + +void board_reset_pd_mcu(void) +{ + /* + * Do nothing. The integrated TCPC for C0 lacks a dedicated reset + * command, and C1 (if present) doesn't have a reset pin connected + * to the EC. + */ +} + +#define INT_RECHECK_US 5000 + +/* C0 interrupt line shared by BC 1.2 and charger */ + +static void check_c0_line(void); +DECLARE_DEFERRED(check_c0_line); + +static void notify_c0_chips(void) +{ + usb_charger_task_set_event(0, USB_CHG_EVENT_BC12); + sm5803_interrupt(0); +} + +static void check_c0_line(void) +{ + /* + * If line is still being held low, see if there's more to process from + * one of the chips + */ + if (!gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_c0_int_odl))) { + notify_c0_chips(); + hook_call_deferred(&check_c0_line_data, INT_RECHECK_US); + } +} + +void usb_c0_interrupt(enum gpio_signal s) +{ + /* Cancel any previous calls to check the interrupt line */ + hook_call_deferred(&check_c0_line_data, -1); + + /* Notify all chips using this line that an interrupt came in */ + notify_c0_chips(); + + /* Check the line again in 5ms */ + hook_call_deferred(&check_c0_line_data, INT_RECHECK_US); +} + +/* C1 interrupt line shared by BC 1.2, TCPC, and charger */ +static void check_c1_line(void); +DECLARE_DEFERRED(check_c1_line); + +static void notify_c1_chips(void) +{ + schedule_deferred_pd_interrupt(1); + usb_charger_task_set_event(1, USB_CHG_EVENT_BC12); + /* Charger is handled in board_process_pd_alert */ +} + +static void check_c1_line(void) +{ + /* + * If line is still being held low, see if there's more to process from + * one of the chips. + */ + if (!gpio_pin_get_dt(GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl))) { + notify_c1_chips(); + hook_call_deferred(&check_c1_line_data, INT_RECHECK_US); + } +} + +void usb_c1_interrupt(enum gpio_signal s) +{ + /* Cancel any previous calls to check the interrupt line */ + hook_call_deferred(&check_c1_line_data, -1); + + /* Notify all chips using this line that an interrupt came in */ + notify_c1_chips(); + + /* Check the line again in 5ms */ + hook_call_deferred(&check_c1_line_data, INT_RECHECK_US); +} + +/* + * Check state of IRQ lines at startup, ensuring an IRQ that happened before + * the EC started up won't get lost (leaving the IRQ line asserted and blocking + * any further interrupts on the port). + * + * Although the PD task will check for pending TCPC interrupts on startup, + * the charger sharing the IRQ will not be polled automatically. + */ +void board_handle_initial_typec_irq(void) +{ + check_c0_line(); + check_c1_line(); +} +/* + * This must run after sub-board detection (which happens in EC main()), + * but isn't depended on by anything else either. + */ +DECLARE_HOOK(HOOK_INIT, board_handle_initial_typec_irq, HOOK_PRIO_LAST); + +/* + * Handle charger interrupts in the PD task. Not doing so can lead to a priority + * inversion where we fail to respond to TCPC alerts quickly enough because we + * don't get another edge on a shared IRQ until the charger interrupt is cleared + * (or the IRQ is polled again), which happens in the low-priority charger task: + * the high-priority type-C handler is thus blocked on the lower-priority + * charger. + * + * To avoid that, we run charger interrupts at the same priority. + */ +void board_process_pd_alert(int port) +{ + /* + * Port 0 doesn't use an external TCPC, so its interrupts don't need + * this special handling. + */ + if (port == 1 && + !gpio_pin_get_dt(GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl))) { + sm5803_handle_interrupt(port); + } +} + +int pd_snk_is_vbus_provided(int port) +{ + int chg_det = 0; + + sm5803_get_chg_det(port, &chg_det); + + return chg_det; +} diff --git a/zephyr/projects/nissa/nereid/generated.dtsi b/zephyr/projects/nissa/nereid/generated.dtsi new file mode 100644 index 0000000000..bca58c478e --- /dev/null +++ b/zephyr/projects/nissa/nereid/generated.dtsi @@ -0,0 +1,260 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + * + * This file is auto-generated - do not edit! + */ + +/ { + + named-adc-channels { + compatible = "named-adc-channels"; + + adc_ec_vsense_pp1050_proc: ec_vsense_pp1050_proc { + enum-name = "ADC_PP1050_PROC"; + io-channels = <&adc0 14>; + }; + adc_ec_vsense_pp3300_s5: ec_vsense_pp3300_s5 { + enum-name = "ADC_PP3300_S5"; + io-channels = <&adc0 0>; + }; + adc_temp_sensor_1: temp_sensor_1 { + enum-name = "ADC_TEMP_SENSOR_1"; + io-channels = <&adc0 2>; + }; + adc_temp_sensor_2: temp_sensor_2 { + enum-name = "ADC_TEMP_SENSOR_2"; + io-channels = <&adc0 3>; + }; + adc_temp_sensor_3: temp_sensor_3 { + enum-name = "ADC_TEMP_SENSOR_3"; + io-channels = <&adc0 13>; + }; + }; + + named-gpios { + compatible = "named-gpios"; + + gpio_acc_int_l: acc_int_l { + gpios = <&gpioc 0 GPIO_INPUT>; + }; + gpio_all_sys_pwrgd: all_sys_pwrgd { + gpios = <&gpiob 7 GPIO_INPUT>; + }; + gpio_ccd_mode_odl: ccd_mode_odl { + gpios = <&gpioh 5 GPIO_INPUT>; + enum-name = "GPIO_CCD_MODE_ODL"; + }; + gpio_cpu_c10_gate_l: cpu_c10_gate_l { + gpios = <&gpiog 1 GPIO_INPUT>; + }; + gpio_ec_battery_pres_odl: ec_battery_pres_odl { + gpios = <&gpioi 4 GPIO_INPUT>; + enum-name = "GPIO_BATT_PRES_ODL"; + }; + gpio_ec_cbi_wp: ec_cbi_wp { + gpios = <&gpioj 5 GPIO_OUTPUT>; + }; + gpio_ec_edp_bl_en_od: ec_edp_bl_en_od { + gpios = <&gpiok 4 GPIO_ODR_HIGH>; + enum-name = "GPIO_ENABLE_BACKLIGHT"; + }; + gpio_ec_entering_rw: ec_entering_rw { + gpios = <&gpioc 7 GPIO_OUTPUT>; + enum-name = "GPIO_ENTERING_RW"; + }; + gpio_ec_gsc_packet_mode: ec_gsc_packet_mode { + gpios = <&gpioh 1 GPIO_OUTPUT>; + enum-name = "GPIO_PACKET_MODE_EN"; + }; + gpio_ec_pch_wake_odl: ec_pch_wake_odl { + gpios = <&gpiob 2 GPIO_ODR_LOW>; + }; + gpio_ec_prochot_odl: ec_prochot_odl { + gpios = <&gpioi 1 GPIO_ODR_HIGH>; + }; + gpio_ec_soc_dsw_pwrok: ec_soc_dsw_pwrok { + gpios = <&gpiol 7 GPIO_OUTPUT>; + }; + gpio_ec_soc_hdmi_hpd: ec_soc_hdmi_hpd { + gpios = <&gpiok 7 GPIO_OUTPUT>; + }; + gpio_ec_soc_int_odl: ec_soc_int_odl { + gpios = <&gpiod 5 GPIO_ODR_HIGH>; + enum-name = "GPIO_EC_INT_L"; + }; + gpio_ec_soc_pch_pwrok_od: ec_soc_pch_pwrok_od { + gpios = <&gpiod 6 GPIO_ODR_HIGH>; + }; + gpio_ec_soc_pwr_btn_odl: ec_soc_pwr_btn_odl { + gpios = <&gpiob 6 GPIO_ODR_HIGH>; + enum-name = "GPIO_PCH_PWRBTN_L"; + }; + gpio_ec_soc_rsmrst_l: ec_soc_rsmrst_l { + gpios = <&gpioh 0 GPIO_OUTPUT>; + }; + gpio_ec_soc_rtcrst: ec_soc_rtcrst { + gpios = <&gpiok 2 GPIO_OUTPUT>; + }; + gpio_ec_soc_sys_pwrok: ec_soc_sys_pwrok { + gpios = <&gpiof 2 GPIO_OUTPUT>; + }; + gpio_ec_soc_vccst_pwrgd_od: ec_soc_vccst_pwrgd_od { + gpios = <&gpioe 5 GPIO_ODR_HIGH>; + }; + gpio_ec_wp_odl: ec_wp_odl { + gpios = <&gpioa 6 (GPIO_INPUT | GPIO_ACTIVE_LOW)>; + }; + gpio_en_kb_bl: en_kb_bl { + gpios = <&gpioj 3 GPIO_OUTPUT>; + enum-name = "GPIO_EN_KEYBOARD_BACKLIGHT"; + }; + gpio_en_pp3300_s5: en_pp3300_s5 { + gpios = <&gpioc 5 GPIO_OUTPUT>; + enum-name = "GPIO_TEMP_SENSOR_POWER"; + }; + gpio_en_pp5000_pen_x: en_pp5000_pen_x { + gpios = <&gpiob 5 GPIO_OUTPUT>; + }; + gpio_en_pp5000_s5: en_pp5000_s5 { + gpios = <&gpiok 5 GPIO_OUTPUT>; + }; + gpio_en_slp_z: en_slp_z { + gpios = <&gpiok 3 GPIO_OUTPUT>; + }; + gpio_en_usb_a0_vbus: en_usb_a0_vbus { + gpios = <&gpiol 6 GPIO_OUTPUT>; + }; + gpio_en_usb_c0_cc1_vconn: en_usb_c0_cc1_vconn { + gpios = <&gpioh 4 GPIO_OUTPUT>; + }; + gpio_en_usb_c0_cc2_vconn: en_usb_c0_cc2_vconn { + gpios = <&gpioh 6 GPIO_OUTPUT>; + }; + gpio_gsc_ec_pwr_btn_odl: gsc_ec_pwr_btn_odl { + gpios = <&gpioe 2 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_POWER_BUTTON_L"; + }; + gpio_hdmi_sel: hdmi_sel { + gpios = <&gpioc 6 GPIO_OUTPUT>; + }; + gpio_imu_int_l: imu_int_l { + gpios = <&gpioj 0 GPIO_INPUT>; + }; + gpio_imvp91_vrrdy_od: imvp91_vrrdy_od { + gpios = <&gpioj 4 GPIO_INPUT>; + }; + gpio_lid_open: lid_open { + gpios = <&gpiof 3 GPIO_INPUT>; + enum-name = "GPIO_LID_OPEN"; + }; + gpio_pen_detect_odl: pen_detect_odl { + gpios = <&gpioj 1 GPIO_INPUT_PULL_UP>; + }; + gpio_pg_pp1050_mem_s3_od: pg_pp1050_mem_s3_od { + gpios = <&gpiod 3 GPIO_INPUT>; + }; + gpio_pg_pp5000_s5_od: pg_pp5000_s5_od { + gpios = <&gpioe 3 GPIO_INPUT>; + }; + gpio_rsmrst_pwrgd_l: rsmrst_pwrgd_l { + gpios = <&gpioe 1 GPIO_INPUT_PULL_UP>; + }; + gpio_slp_s0_l: slp_s0_l { + gpios = <&gpioe 4 GPIO_INPUT>; + }; + gpio_slp_s3_l: slp_s3_l { + gpios = <&gpioh 3 GPIO_INPUT>; + }; + gpio_slp_s4_l: slp_s4_l { + gpios = <&gpioi 5 GPIO_INPUT>; + }; + gpio_slp_sus_l: slp_sus_l { + gpios = <&gpiog 2 GPIO_INPUT>; + }; + gpio_sub_usb_a1_ilimit_sdp: sub_usb_a1_ilimit_sdp { + gpios = <&gpiof 1 GPIO_OUTPUT>; + enum-name = "GPIO_USB2_ILIM_SEL"; + }; + gpio_sys_rst_odl: sys_rst_odl { + gpios = <&gpiod 1 GPIO_ODR_HIGH>; + }; + gpio_tablet_mode_l: tablet_mode_l { + gpios = <&gpioa 7 GPIO_INPUT>; + enum-name = "GPIO_TABLET_MODE_L"; + }; + gpio_usb_a0_ilimit_sdp: usb_a0_ilimit_sdp { + gpios = <&gpiol 5 GPIO_OUTPUT>; + enum-name = "GPIO_USB1_ILIM_SEL"; + }; + gpio_usb_c0_frs: usb_c0_frs { + gpios = <&gpioc 4 GPIO_OUTPUT>; + }; + gpio_usb_c0_int_odl: usb_c0_int_odl { + gpios = <&gpiok 0 GPIO_INPUT_PULL_UP>; + }; + gpio_vccin_aux_vid0: vccin_aux_vid0 { + gpios = <&gpiod 0 GPIO_INPUT>; + }; + gpio_vccin_aux_vid1: vccin_aux_vid1 { + gpios = <&gpiok 1 GPIO_INPUT>; + }; + gpio_voldn_btn_odl: voldn_btn_odl { + gpios = <&gpioi 6 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_VOLUME_DOWN_L"; + }; + gpio_volup_btn_odl: volup_btn_odl { + gpios = <&gpioi 7 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_VOLUME_UP_L"; + }; + }; + + named-i2c-ports { + compatible = "named-i2c-ports"; + + i2c_ec_i2c_eeprom: ec_i2c_eeprom { + i2c-port = <&i2c0>; + enum-names = "I2C_PORT_EEPROM"; + }; + i2c_ec_i2c_batt: ec_i2c_batt { + i2c-port = <&i2c1>; + enum-names = "I2C_PORT_BATTERY"; + }; + i2c_ec_i2c_sensor: ec_i2c_sensor { + i2c-port = <&i2c2>; + enum-names = "I2C_PORT_SENSOR"; + }; + i2c_ec_i2c_sub_usb_c1: ec_i2c_sub_usb_c1 { + i2c-port = <&i2c4>; + enum-names = "I2C_PORT_USB_C1_TCPC"; + }; + i2c_ec_i2c_usb_c0: ec_i2c_usb_c0 { + i2c-port = <&i2c5>; + enum-names = "I2C_PORT_USB_C0_TCPC"; + }; + }; +}; + +&adc0 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; diff --git a/zephyr/projects/nissa/nereid/keyboard.dtsi b/zephyr/projects/nissa/nereid/keyboard.dtsi new file mode 100644 index 0000000000..04a620767a --- /dev/null +++ b/zephyr/projects/nissa/nereid/keyboard.dtsi @@ -0,0 +1,22 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + kblight { + compatible = "cros-ec,kblight-pwm"; + /* + * Use 324 Hz so that 32Khz clock source is used, + * which is not gated in power saving mode. + */ + pwms = <&pwm0 0 PWM_HZ(324) PWM_POLARITY_NORMAL>; + }; +}; + +&pwm0 { + status = "okay"; + prescaler-cx = <PWM_PRESCALER_C4>; + pinctrl-0 = <&pwm0_gpa0_default>; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/nissa/nereid/motionsense.dtsi b/zephyr/projects/nissa/nereid/motionsense.dtsi new file mode 100644 index 0000000000..a65bb48fbd --- /dev/null +++ b/zephyr/projects/nissa/nereid/motionsense.dtsi @@ -0,0 +1,147 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <dt-bindings/motionsense/utils.h> + + +/ { + aliases { + /* + * Interrupt bindings for sensor devices. + */ + bmi3xx-int = &base_accel; + bma4xx-int = &lid_accel; + }; + + /* + * Declare mutexes used by sensor drivers. + * A mutex node is used to create an instance of mutex_t. + * A mutex node is referenced by a sensor node if the + * corresponding sensor driver needs to use the + * instance of the mutex. + */ + motionsense-mutex { + compatible = "cros-ec,motionsense-mutex"; + lid_mutex: lid-mutex { + }; + + base_mutex: base-mutex { + }; + }; + + /* Rotation matrix used by drivers. */ + motionsense-rotation-ref { + compatible = "cros-ec,motionsense-rotation-ref"; + lid_rot_ref: lid-rotation-ref { + mat33 = <0 (-1) 0 + (-1) 0 0 + 0 0 (-1)>; + }; + + base_rot_ref: base-rotation-ref { + mat33 = <0 1 0 + (-1) 0 0 + 0 0 1>; + }; + }; + + /* + * Driver specific data. A driver-specific data can be shared with + * different motion sensors while they are using the same driver. + * + * If a node's compatible starts with "cros-ec,accelgyro-", it is for + * a common structure defined in accelgyro.h. + * e.g) compatible = "cros-ec,accelgyro-als-drv-data" is for + * "struct als_drv_data_t" in accelgyro.h + */ + motionsense-sensor-data { + bmi323_data: bmi323-drv-data { + compatible = "cros-ec,drvdata-bmi3xx"; + status = "okay"; + }; + + bma422_data: bma422-drv-data { + compatible = "cros-ec,drvdata-bma4xx"; + status = "okay"; + }; + }; + + /* + * List of motion sensors that creates motion_sensors array. + * The nodelabel "lid_accel" and "base_accel" are used to indicate + * motion sensor IDs for lid angle calculation. + * TODO(b/238139272): The first entries of the array must be + * accelerometers,then gyroscope. Fix this dependency in the DTS + * processing which makes the devicetree entries independent. + */ + motionsense-sensor { + lid_accel: lid-accel { + compatible = "cros-ec,bma4xx"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_LID"; + mutex = <&lid_mutex>; + port = <&i2c_ec_i2c_sensor>; + rot-standard-ref = <&lid_rot_ref>; + default-range = <2>; + drv-data = <&bma422_data>; + configs { + compatible = + "cros-ec,motionsense-sensor-config"; + ec-s0 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + ec-s3 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + }; + }; + + base_accel: base-accel { + compatible = "cros-ec,bmi3xx-accel"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_BASE"; + mutex = <&base_mutex>; + port = <&i2c_ec_i2c_sensor>; + rot-standard-ref = <&base_rot_ref>; + drv-data = <&bmi323_data>; + configs { + compatible = + "cros-ec,motionsense-sensor-config"; + ec-s0 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + ec-s3 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + }; + }; + + base_gyro: base-gyro { + compatible = "cros-ec,bmi3xx-gyro"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_BASE"; + mutex = <&base_mutex>; + port = <&i2c_ec_i2c_sensor>; + rot-standard-ref = <&base_rot_ref>; + drv-data = <&bmi323_data>; + }; + }; + + motionsense-sensor-info { + compatible = "cros-ec,motionsense-sensor-info"; + + /* + * list of GPIO interrupts that have to + * be enabled at initial stage + */ + sensor-irqs = <&int_imu &int_lid_imu>; + }; +}; diff --git a/zephyr/projects/nissa/nereid/nereid_vif.xml b/zephyr/projects/nissa/nereid/nereid_vif.xml new file mode 100644 index 0000000000..91c8dbe68b --- /dev/null +++ b/zephyr/projects/nissa/nereid/nereid_vif.xml @@ -0,0 +1,350 @@ +<?xml version="1.0" encoding="utf-8"?>
+<vif:VIF xmlns:opt="http://usb.org/VendorInfoFileOptionalContent.xsd" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:vif="http://usb.org/VendorInfoFile.xsd">
+ <vif:VIF_Specification>3.19</vif:VIF_Specification>
+ <vif:VIF_App>
+ <vif:Vendor>USB-IF</vif:Vendor>
+ <vif:Name>VIF Editor</vif:Name>
+ <vif:Version>3.2.4.0</vif:Version>
+ </vif:VIF_App>
+ <vif:Vendor_Name>Google</vif:Vendor_Name>
+ <vif:Model_Part_Number>Nereid</vif:Model_Part_Number>
+ <vif:Product_Revision>1</vif:Product_Revision>
+ <vif:TID>0</vif:TID>
+ <vif:VIF_Product_Type value="0">Port Product</vif:VIF_Product_Type>
+ <vif:Certification_Type value="1">Reference Platform</vif:Certification_Type>
+ <vif:Product>
+ <!--Product Level Content:-->
+ </vif:Product>
+ <vif:Component>
+ <!--Component 0: Port 0-->
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <!--;Component-->
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <vif:Port_Label>0</vif:Port_Label>
+ <vif:Connector_Type value="2">Type-C®</vif:Connector_Type>
+ <vif:USB4_Supported value="false" />
+ <vif:USB_PD_Support value="true" />
+ <vif:PD_Port_Type value="4">DRP</vif:PD_Port_Type>
+ <vif:Type_C_State_Machine value="2">DRP</vif:Type_C_State_Machine>
+ <vif:Port_Battery_Powered value="true" />
+ <vif:BC_1_2_Support value="2">Charging Port</vif:BC_1_2_Support>
+ <vif:Captive_Cable value="false" />
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <!--;General PD-->
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <vif:PD_Spec_Revision_Major value="3" />
+ <vif:PD_Spec_Revision_Minor value="1" />
+ <vif:PD_Spec_Version_Major value="1" />
+ <vif:PD_Spec_Version_Minor value="3" />
+ <vif:PD_Specification_Revision value="2">Revision 3</vif:PD_Specification_Revision>
+ <vif:SOP_Capable value="true" />
+ <vif:SOP_P_Capable value="true" />
+ <vif:SOP_PP_Capable value="true" />
+ <vif:SOP_P_Debug_Capable value="false" />
+ <vif:SOP_PP_Debug_Capable value="false" />
+ <vif:Manufacturer_Info_Supported_Port value="true" />
+ <vif:Manufacturer_Info_VID_Port value="6353">18D1</vif:Manufacturer_Info_VID_Port>
+ <vif:Manufacturer_Info_PID_Port value="20570">505A</vif:Manufacturer_Info_PID_Port>
+ <vif:Chunking_Implemented_SOP value="true" />
+ <vif:Unchunked_Extended_Messages_Supported value="false" />
+ <vif:Security_Msgs_Supported_SOP value="false" />
+ <vif:Unconstrained_Power value="false" />
+ <vif:Num_Fixed_Batteries value="1" />
+ <vif:Num_Swappable_Battery_Slots value="0" />
+ <vif:ID_Header_Connector_Type_SOP value="2">USB Type-C® Receptacle</vif:ID_Header_Connector_Type_SOP>
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <!--;PD Capabilities-->
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <vif:USB_Comms_Capable value="true" />
+ <vif:DR_Swap_To_DFP_Supported value="true" />
+ <vif:DR_Swap_To_UFP_Supported value="false" />
+ <vif:VCONN_Swap_To_On_Supported value="true" />
+ <vif:VCONN_Swap_To_Off_Supported value="true" />
+ <vif:Responds_To_Discov_SOP_UFP value="false" />
+ <vif:Responds_To_Discov_SOP_DFP value="true" />
+ <vif:Attempts_Discov_SOP value="true" />
+ <vif:Power_Interruption_Available value="0">No Interruption Possible</vif:Power_Interruption_Available>
+ <vif:Data_Reset_Supported value="false" />
+ <vif:Enter_USB_Supported value="false" />
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <!--;USB Type-C®-->
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <vif:Type_C_Can_Act_As_Host value="true" />
+ <vif:Type_C_Can_Act_As_Device value="false" />
+ <vif:Type_C_Implements_Try_SRC value="true" />
+ <vif:Type_C_Implements_Try_SNK value="false" />
+ <vif:Type_C_Supports_Audio_Accessory value="false" />
+ <vif:Type_C_Is_VCONN_Powered_Accessory value="false" />
+ <vif:Type_C_Is_Debug_Target_SRC value="true" />
+ <vif:Type_C_Is_Debug_Target_SNK value="true" />
+ <vif:RP_Value value="1">1.5A</vif:RP_Value>
+ <vif:Type_C_Port_On_Hub value="false" />
+ <vif:Type_C_Power_Source value="2">Both</vif:Type_C_Power_Source>
+ <vif:Type_C_Sources_VCONN value="true" />
+ <vif:Type_C_Is_Alt_Mode_Controller value="true" />
+ <vif:Type_C_Is_Alt_Mode_Adapter value="false" />
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <!--;Product Power-->
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <vif:Product_Total_Source_Power_mW value="15000">15000 mW</vif:Product_Total_Source_Power_mW>
+ <vif:Port_Source_Power_Type value="0">Assured</vif:Port_Source_Power_Type>
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <!--;USB Host-->
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <vif:Host_Supports_USB_Data value="true" />
+ <vif:Host_Speed value="1">USB 3.2 Gen 1x1</vif:Host_Speed>
+ <vif:Host_Contains_Captive_Retimer value="false" />
+ <vif:Host_Truncates_DP_For_tDHPResponse value="false" />
+ <vif:Host_Is_Embedded value="false" />
+ <vif:Host_Suspend_Supported value="true" />
+ <vif:Is_DFP_On_Hub value="false" />
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <!--;Battery Charging 1.2-->
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <vif:BC_1_2_Charging_Port_Type value="1">CDP</vif:BC_1_2_Charging_Port_Type>
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <!--;PD Source-->
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <vif:PD_Power_As_Source value="15000">15000 mW</vif:PD_Power_As_Source>
+ <vif:EPR_Supported_As_Src value="false" />
+ <vif:USB_Suspend_May_Be_Cleared value="false" />
+ <vif:Sends_Pings value="false" />
+ <vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink value="0">FR_Swap not supported</vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink>
+ <vif:Master_Port value="false" />
+ <vif:Num_Src_PDOs value="1" />
+ <vif:PD_OC_Protection value="true" />
+ <vif:PD_OCP_Method value="0">Over-Current Response</vif:PD_OCP_Method>
+ <!--Bundle: SrcPdoList-->
+ <vif:SrcPdoList>
+ <vif:SrcPDO>
+ <!--Source PDO 1-->
+ <vif:Src_PDO_Supply_Type value="0">Fixed</vif:Src_PDO_Supply_Type>
+ <vif:Src_PDO_Peak_Current value="0">100% IOC</vif:Src_PDO_Peak_Current>
+ <vif:Src_PDO_Voltage value="100">5000 mV</vif:Src_PDO_Voltage>
+ <vif:Src_PDO_Max_Current value="300">3000 mA</vif:Src_PDO_Max_Current>
+ <vif:Src_PD_OCP_OC_Debounce value="0">0 msec</vif:Src_PD_OCP_OC_Debounce>
+ <vif:Src_PD_OCP_OC_Threshold value="300">3000 mA</vif:Src_PD_OCP_OC_Threshold>
+ </vif:SrcPDO>
+ </vif:SrcPdoList>
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <!--;PD Sink-->
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <vif:PD_Power_As_Sink value="45000">45000 mW</vif:PD_Power_As_Sink>
+ <vif:EPR_Supported_As_Snk value="false" />
+ <vif:No_USB_Suspend_May_Be_Set value="true" />
+ <vif:GiveBack_May_Be_Set value="false" />
+ <vif:Higher_Capability_Set value="false" />
+ <vif:FR_Swap_Reqd_Type_C_Current_As_Initial_Source value="0">FR_Swap not supported</vif:FR_Swap_Reqd_Type_C_Current_As_Initial_Source>
+ <vif:Num_Snk_PDOs value="3" />
+ <!--Bundle: SnkPdoList-->
+ <vif:SnkPdoList>
+ <vif:SnkPDO>
+ <!--Sink PDO 1-->
+ <vif:Snk_PDO_Supply_Type value="0">Fixed</vif:Snk_PDO_Supply_Type>
+ <vif:Snk_PDO_Voltage value="100">5000 mV</vif:Snk_PDO_Voltage>
+ <vif:Snk_PDO_Op_Current value="300">3000 mA</vif:Snk_PDO_Op_Current>
+ </vif:SnkPDO>
+ <vif:SnkPDO>
+ <!--Sink PDO 2-->
+ <vif:Snk_PDO_Supply_Type value="1">Battery</vif:Snk_PDO_Supply_Type>
+ <vif:Snk_PDO_Op_Power value="60">15000 mW</vif:Snk_PDO_Op_Power>
+ <vif:Snk_PDO_Min_Voltage value="95">4750 mV</vif:Snk_PDO_Min_Voltage>
+ <vif:Snk_PDO_Max_Voltage value="300">15000 mV</vif:Snk_PDO_Max_Voltage>
+ </vif:SnkPDO>
+ <vif:SnkPDO>
+ <!--Sink PDO 3-->
+ <vif:Snk_PDO_Supply_Type value="2">Variable</vif:Snk_PDO_Supply_Type>
+ <vif:Snk_PDO_Min_Voltage value="95">4750 mV</vif:Snk_PDO_Min_Voltage>
+ <vif:Snk_PDO_Max_Voltage value="300">15000 mV</vif:Snk_PDO_Max_Voltage>
+ <vif:Snk_PDO_Op_Current value="300">3000 mA</vif:Snk_PDO_Op_Current>
+ </vif:SnkPDO>
+ </vif:SnkPdoList>
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <!--;Dual Role-->
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <vif:Accepts_PR_Swap_As_Src value="true" />
+ <vif:Accepts_PR_Swap_As_Snk value="true" />
+ <vif:Requests_PR_Swap_As_Src value="true" />
+ <vif:Requests_PR_Swap_As_Snk value="true" />
+ <vif:FR_Swap_Supported_As_Initial_Sink value="false" />
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <!--;SOP Discover ID-->
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <vif:XID_SOP value="0" />
+ <vif:Data_Capable_As_USB_Host_SOP value="true" />
+ <vif:Data_Capable_As_USB_Device_SOP value="false" />
+ <vif:Product_Type_UFP_SOP value="0">Undefined</vif:Product_Type_UFP_SOP>
+ <vif:Product_Type_DFP_SOP value="2">PDUSB Host</vif:Product_Type_DFP_SOP>
+ <vif:DFP_VDO_Port_Number value="0" />
+ <vif:Modal_Operation_Supported_SOP value="false" />
+ <vif:USB_VID_SOP value="6353">18D1</vif:USB_VID_SOP>
+ <vif:PID_SOP value="20570">505A</vif:PID_SOP>
+ <vif:bcdDevice_SOP value="0">0000</vif:bcdDevice_SOP>
+ </vif:Component>
+ <vif:Component>
+ <!--Component 1: Port 1-->
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <!--;Component-->
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <vif:Port_Label>1</vif:Port_Label>
+ <vif:Connector_Type value="2">Type-C®</vif:Connector_Type>
+ <vif:USB4_Supported value="false" />
+ <vif:USB_PD_Support value="true" />
+ <vif:PD_Port_Type value="4">DRP</vif:PD_Port_Type>
+ <vif:Type_C_State_Machine value="2">DRP</vif:Type_C_State_Machine>
+ <vif:Port_Battery_Powered value="true" />
+ <vif:BC_1_2_Support value="2">Charging Port</vif:BC_1_2_Support>
+ <vif:Captive_Cable value="false" />
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <!--;General PD-->
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <vif:PD_Spec_Revision_Major value="3" />
+ <vif:PD_Spec_Revision_Minor value="1" />
+ <vif:PD_Spec_Version_Major value="1" />
+ <vif:PD_Spec_Version_Minor value="3" />
+ <vif:PD_Specification_Revision value="2">Revision 3</vif:PD_Specification_Revision>
+ <vif:SOP_Capable value="true" />
+ <vif:SOP_P_Capable value="true" />
+ <vif:SOP_PP_Capable value="true" />
+ <vif:SOP_P_Debug_Capable value="false" />
+ <vif:SOP_PP_Debug_Capable value="false" />
+ <vif:Manufacturer_Info_Supported_Port value="true" />
+ <vif:Manufacturer_Info_VID_Port value="6353">18D1</vif:Manufacturer_Info_VID_Port>
+ <vif:Manufacturer_Info_PID_Port value="20570">505A</vif:Manufacturer_Info_PID_Port>
+ <vif:Chunking_Implemented_SOP value="true" />
+ <vif:Unchunked_Extended_Messages_Supported value="false" />
+ <vif:Security_Msgs_Supported_SOP value="false" />
+ <vif:Unconstrained_Power value="false" />
+ <vif:Num_Fixed_Batteries value="1" />
+ <vif:Num_Swappable_Battery_Slots value="0" />
+ <vif:ID_Header_Connector_Type_SOP value="2">USB Type-C® Receptacle</vif:ID_Header_Connector_Type_SOP>
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <!--;PD Capabilities-->
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <vif:USB_Comms_Capable value="true" />
+ <vif:DR_Swap_To_DFP_Supported value="true" />
+ <vif:DR_Swap_To_UFP_Supported value="false" />
+ <vif:VCONN_Swap_To_On_Supported value="true" />
+ <vif:VCONN_Swap_To_Off_Supported value="true" />
+ <vif:Responds_To_Discov_SOP_UFP value="false" />
+ <vif:Responds_To_Discov_SOP_DFP value="true" />
+ <vif:Attempts_Discov_SOP value="true" />
+ <vif:Power_Interruption_Available value="0">No Interruption Possible</vif:Power_Interruption_Available>
+ <vif:Data_Reset_Supported value="false" />
+ <vif:Enter_USB_Supported value="false" />
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <!--;USB Type-C®-->
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <vif:Type_C_Can_Act_As_Host value="true" />
+ <vif:Type_C_Can_Act_As_Device value="false" />
+ <vif:Type_C_Implements_Try_SRC value="true" />
+ <vif:Type_C_Implements_Try_SNK value="false" />
+ <vif:Type_C_Supports_Audio_Accessory value="false" />
+ <vif:Type_C_Is_VCONN_Powered_Accessory value="false" />
+ <vif:Type_C_Is_Debug_Target_SRC value="true" />
+ <vif:Type_C_Is_Debug_Target_SNK value="true" />
+ <vif:RP_Value value="1">1.5A</vif:RP_Value>
+ <vif:Type_C_Port_On_Hub value="false" />
+ <vif:Type_C_Power_Source value="2">Both</vif:Type_C_Power_Source>
+ <vif:Type_C_Sources_VCONN value="true" />
+ <vif:Type_C_Is_Alt_Mode_Controller value="true" />
+ <vif:Type_C_Is_Alt_Mode_Adapter value="false" />
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <!--;Product Power-->
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <vif:Product_Total_Source_Power_mW value="15000">15000 mW</vif:Product_Total_Source_Power_mW>
+ <vif:Port_Source_Power_Type value="0">Assured</vif:Port_Source_Power_Type>
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <!--;USB Host-->
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <vif:Host_Supports_USB_Data value="true" />
+ <vif:Host_Speed value="1">USB 3.2 Gen 1x1</vif:Host_Speed>
+ <vif:Host_Contains_Captive_Retimer value="true" />
+ <vif:Host_Truncates_DP_For_tDHPResponse value="false" />
+ <vif:Host_Is_Embedded value="false" />
+ <vif:Host_Suspend_Supported value="true" />
+ <vif:Is_DFP_On_Hub value="false" />
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <!--;Battery Charging 1.2-->
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <vif:BC_1_2_Charging_Port_Type value="1">CDP</vif:BC_1_2_Charging_Port_Type>
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <!--;PD Source-->
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <vif:PD_Power_As_Source value="15000">15000 mW</vif:PD_Power_As_Source>
+ <vif:EPR_Supported_As_Src value="false" />
+ <vif:USB_Suspend_May_Be_Cleared value="false" />
+ <vif:Sends_Pings value="false" />
+ <vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink value="0">FR_Swap not supported</vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink>
+ <vif:Master_Port value="false" />
+ <vif:Num_Src_PDOs value="1" />
+ <vif:PD_OC_Protection value="true" />
+ <vif:PD_OCP_Method value="0">Over-Current Response</vif:PD_OCP_Method>
+ <!--Bundle: SrcPdoList-->
+ <vif:SrcPdoList>
+ <vif:SrcPDO>
+ <!--Source PDO 1-->
+ <vif:Src_PDO_Supply_Type value="0">Fixed</vif:Src_PDO_Supply_Type>
+ <vif:Src_PDO_Peak_Current value="0">100% IOC</vif:Src_PDO_Peak_Current>
+ <vif:Src_PDO_Voltage value="100">5000 mV</vif:Src_PDO_Voltage>
+ <vif:Src_PDO_Max_Current value="300">3000 mA</vif:Src_PDO_Max_Current>
+ <vif:Src_PD_OCP_OC_Debounce value="0">0 msec</vif:Src_PD_OCP_OC_Debounce>
+ <vif:Src_PD_OCP_OC_Threshold value="300">3000 mA</vif:Src_PD_OCP_OC_Threshold>
+ </vif:SrcPDO>
+ </vif:SrcPdoList>
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <!--;PD Sink-->
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <vif:PD_Power_As_Sink value="45000">45000 mW</vif:PD_Power_As_Sink>
+ <vif:EPR_Supported_As_Snk value="false" />
+ <vif:No_USB_Suspend_May_Be_Set value="true" />
+ <vif:GiveBack_May_Be_Set value="false" />
+ <vif:Higher_Capability_Set value="false" />
+ <vif:FR_Swap_Reqd_Type_C_Current_As_Initial_Source value="0">FR_Swap not supported</vif:FR_Swap_Reqd_Type_C_Current_As_Initial_Source>
+ <vif:Num_Snk_PDOs value="3" />
+ <!--Bundle: SnkPdoList-->
+ <vif:SnkPdoList>
+ <vif:SnkPDO>
+ <!--Sink PDO 1-->
+ <vif:Snk_PDO_Supply_Type value="0">Fixed</vif:Snk_PDO_Supply_Type>
+ <vif:Snk_PDO_Voltage value="100">5000 mV</vif:Snk_PDO_Voltage>
+ <vif:Snk_PDO_Op_Current value="300">3000 mA</vif:Snk_PDO_Op_Current>
+ </vif:SnkPDO>
+ <vif:SnkPDO>
+ <!--Sink PDO 2-->
+ <vif:Snk_PDO_Supply_Type value="1">Battery</vif:Snk_PDO_Supply_Type>
+ <vif:Snk_PDO_Op_Power value="60">15000 mW</vif:Snk_PDO_Op_Power>
+ <vif:Snk_PDO_Min_Voltage value="95">4750 mV</vif:Snk_PDO_Min_Voltage>
+ <vif:Snk_PDO_Max_Voltage value="300">15000 mV</vif:Snk_PDO_Max_Voltage>
+ </vif:SnkPDO>
+ <vif:SnkPDO>
+ <!--Sink PDO 3-->
+ <vif:Snk_PDO_Supply_Type value="2">Variable</vif:Snk_PDO_Supply_Type>
+ <vif:Snk_PDO_Min_Voltage value="95">4750 mV</vif:Snk_PDO_Min_Voltage>
+ <vif:Snk_PDO_Max_Voltage value="300">15000 mV</vif:Snk_PDO_Max_Voltage>
+ <vif:Snk_PDO_Op_Current value="300">3000 mA</vif:Snk_PDO_Op_Current>
+ </vif:SnkPDO>
+ </vif:SnkPdoList>
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <!--;Dual Role-->
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <vif:Accepts_PR_Swap_As_Src value="true" />
+ <vif:Accepts_PR_Swap_As_Snk value="true" />
+ <vif:Requests_PR_Swap_As_Src value="true" />
+ <vif:Requests_PR_Swap_As_Snk value="true" />
+ <vif:FR_Swap_Supported_As_Initial_Sink value="false" />
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <!--;SOP Discover ID-->
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <vif:XID_SOP value="0" />
+ <vif:Data_Capable_As_USB_Host_SOP value="true" />
+ <vif:Data_Capable_As_USB_Device_SOP value="false" />
+ <vif:Product_Type_UFP_SOP value="0">Undefined</vif:Product_Type_UFP_SOP>
+ <vif:Product_Type_DFP_SOP value="2">PDUSB Host</vif:Product_Type_DFP_SOP>
+ <vif:DFP_VDO_Port_Number value="1" />
+ <vif:Modal_Operation_Supported_SOP value="false" />
+ <vif:USB_VID_SOP value="6353">18D1</vif:USB_VID_SOP>
+ <vif:PID_SOP value="20570">505A</vif:PID_SOP>
+ <vif:bcdDevice_SOP value="0">0000</vif:bcdDevice_SOP>
+ </vif:Component>
+</vif:VIF>
\ No newline at end of file diff --git a/zephyr/projects/nissa/nereid/overlay.dtsi b/zephyr/projects/nissa/nereid/overlay.dtsi new file mode 100644 index 0000000000..a44a3e01bd --- /dev/null +++ b/zephyr/projects/nissa/nereid/overlay.dtsi @@ -0,0 +1,400 @@ +/* Copyright 2021 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <cros/thermistor/thermistor.dtsi> + +/ { + aliases { + gpio-cbi-wp = &gpio_ec_cbi_wp; + gpio-wp = &gpio_ec_wp_odl; + int-wp = &int_wp_l; + /* + * USB-C: interrupt input. + * I2C pins are on i2c_ec_i2c_sub_usb_c1 + */ + gpio-usb-c1-int-odl = &gpio_sb_1; + /* + * USB-A: VBUS enable output + * LTE: power enable output + */ + gpio-en-usb-a1-vbus = &gpio_sb_2; + /* + * HDMI: power enable output, HDMI enable output, + * and HPD input + */ + gpio-en-rails-odl = &gpio_sb_1; + gpio-hdmi-en-odl = &gpio_sb_4; + gpio-hpd-odl = &gpio_sb_3; + /* + * Enable S5 rails for LTE sub-board + */ + gpio-en-sub-s5-rails = &gpio_sb_2; + }; + + + ec-console { + compatible = "ec-console"; + disabled = "events", "lpc", "hostcmd"; + }; + + batteries { + default_battery: smp { + compatible = "smp,l20m3pg0", "battery-smart"; + }; + }; + + hibernate-wake-pins { + compatible = "cros-ec,hibernate-wake-pins"; + wakeup-irqs = < + &int_power_button + &int_lid_open + >; + }; + + gpio-interrupts { + compatible = "cros-ec,gpio-interrupts"; + + int_power_button: power_button { + irq-pin = <&gpio_gsc_ec_pwr_btn_odl>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "power_button_interrupt"; + }; + int_vol_down: vol_down { + irq-pin = <&gpio_voldn_btn_odl>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "button_interrupt"; + }; + int_vol_up: vol_up { + irq-pin = <&gpio_volup_btn_odl>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "button_interrupt"; + }; + int_wp_l: wp_l { + irq-pin = <&gpio_ec_wp_odl>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "switch_interrupt"; + }; + int_lid_open: lid_open { + irq-pin = <&gpio_lid_open>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "lid_interrupt"; + }; + int_tablet_mode: tablet_mode { + irq-pin = <&gpio_tablet_mode_l>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "gmr_tablet_switch_isr"; + }; + int_imu: ec_imu { + irq-pin = <&gpio_imu_int_l>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "bmi3xx_interrupt"; + }; + int_lid_imu: lid_imu { + irq-pin = <&gpio_acc_int_l>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "bma4xx_interrupt"; + }; + int_usb_c0: usb_c0 { + irq-pin = <&gpio_usb_c0_int_odl>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "usb_c0_interrupt"; + }; + int_usb_c1: usb_c1 { + irq-pin = <&gpio_sb_1>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "usb_c1_interrupt"; + }; + }; + + unused-pins { + compatible = "unused-gpios"; + unused-gpios = <&gpioc 3 0>, + <&gpiod 4 0>, + <&gpiod 7 0>, + <&gpioh 2 0>, + <&gpioj 7 0>, + <&gpiol 4 0>; + }; + + named-gpios { + /* + * EC doesn't take any specific action on CC/SBU disconnect due to + * fault, but this definition is useful for hardware testing. + */ + gpio_usb_c0_prot_fault_odl: usb_c0_prot_fault_odl { + gpios = <&gpiok 6 GPIO_INPUT_PULL_UP>; + }; + + gpio_sb_1: sb_1 { + gpios = <&gpioe 6 0>; + no-auto-init; + }; + gpio_sb_2: sb_2 { + gpios = <&gpiof 0 0>; + no-auto-init; + }; + + gpio_sb_3: sb_3 { + gpios = <&gpioe 7 0>; + no-auto-init; + }; + gpio_sb_4: sb_4 { + gpios = <&gpioe 0 0>; + no-auto-init; + }; + }; + + temp_memory: memory { + compatible = "cros-ec,temp-sensor-thermistor"; + thermistor = <&thermistor_3V3_51K1_47K_4050B>; + adc = <&adc_temp_sensor_1>; + }; + temp_charger: charger { + compatible = "cros-ec,temp-sensor-thermistor"; + thermistor = <&thermistor_3V3_51K1_47K_4050B>; + adc = <&adc_temp_sensor_2>; + }; + temp_ambient: ambient { + compatible = "cros-ec,temp-sensor-thermistor"; + thermistor = <&thermistor_3V3_51K1_47K_4050B>; + adc = <&adc_temp_sensor_3>; + }; + + named-temp-sensors { + compatible = "cros-ec,temp-sensors"; + memory { + temp_fan_off = <35>; + temp_fan_max = <60>; + temp_host_high = <85>; + temp_host_halt = <90>; + temp_host_release_high = <80>; + power-good-pin = <&gpio_ec_soc_dsw_pwrok>; + sensor = <&temp_memory>; + }; + charger { + temp_fan_off = <35>; + temp_fan_max = <60>; + temp_host_high = <85>; + temp_host_halt = <90>; + temp_host_release_high = <80>; + power-good-pin = <&gpio_ec_soc_dsw_pwrok>; + sensor = <&temp_charger>; + }; + ambient { + temp_fan_off = <35>; + temp_fan_max = <60>; + temp_host_high = <85>; + temp_host_halt = <90>; + temp_host_release_high = <80>; + power-good-pin = <&gpio_ec_soc_dsw_pwrok>; + sensor = <&temp_ambient>; + }; + }; + + usba { + compatible = "cros-ec,usba-port-enable-pins"; + /* + * sb_2 is only configured as GPIO when USB-A1 is present, + * but it's still safe to control when disabled. + * + * ILIM_SEL pins are referred to by legacy enum name, + * GPIO_USB*_ILIM_SEL. The one for port A1 is unused on + * sub-boards that don't have USB-A so is safe to control + * regardless of system configuration. + */ + enable-pins = <&gpio_en_usb_a0_vbus &gpio_sb_2>; + status = "okay"; + }; + + usbc { + #address-cells = <1>; + #size-cells = <0>; + + port0@0 { + compatible = "named-usbc-port"; + reg = <0>; + bc12 = <&bc12_port0>; + chg = <&chg_port0>; + usb-mux-chain-0 { + compatible = "cros-ec,usb-mux-chain"; + usb-muxes = <&virtual_mux_0>; + }; + }; + port0-muxes { + virtual_mux_0: virtual-mux-0 { + compatible = "cros-ec,usbc-mux-virtual"; + }; + }; + port1@1 { + compatible = "named-usbc-port"; + reg = <1>; + bc12 = <&bc12_port1>; + chg = <&chg_port1>; + usb-mux-chain-1 { + compatible = "cros-ec,usb-mux-chain"; + usb-muxes = <&virtual_mux_1 &tcpci_mux_1>; + }; + usb_mux_chain_1_no_mux: usb-mux-chain-1-no-mux { + compatible = "cros-ec,usb-mux-chain"; + alternative-chain; + usb-muxes = <&virtual_mux_1>; + }; + }; + port1-muxes { + virtual_mux_1: virtual-mux-1 { + compatible = "cros-ec,usbc-mux-virtual"; + }; + tcpci_mux_1: tcpci-mux-1 { + compatible = "parade,usbc-mux-ps8xxx"; + }; + }; + }; +}; + +&gpio_acc_int_l { + gpios = <&gpioc 0 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; +}; +&gpio_imu_int_l { + gpios = <&gpioj 0 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; +}; +&gpio_vccin_aux_vid0 { + gpios = <&gpiod 0 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; +}; +&gpio_vccin_aux_vid1 { + gpios = <&gpiok 1 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; +}; + +&gpio_ec_prochot_odl { + gpios = <&gpioi 1 (GPIO_ODR_HIGH | GPIO_VOLTAGE_1P8)>; +}; + +&thermistor_3V3_51K1_47K_4050B { + status = "okay"; +}; + +&adc_ec_vsense_pp3300_s5 { + /* + * Voltage divider on input has 47k upper and 220k lower legs with 3 V + * full-scale reading on the ADC. Apply the largest possible multiplier + * (without overflowing int32) to get the best possible approximation + * of the actual ratio, but derate by a factor of two to ensure + * unexpectedly high values won't overflow. + */ + mul = <(715828 / 2)>; + div = <(589820 / 2)>; +}; + +&adc0 { + pinctrl-0 = <&adc0_ch0_gpi0_default + &adc0_ch2_gpi2_default + &adc0_ch3_gpi3_default + &adc0_ch13_gpl0_default + &adc0_ch14_gpl1_default>; + pinctrl-names = "default"; +}; + +&pinctrl { + i2c4_clk_gpe0_sleep: i2c4_clk_gpe0_sleep { + pinmuxs = <&pinctrle 0 IT8XXX2_ALT_DEFAULT>; + }; + i2c4_data_gpe7_sleep: i2c4_data_gpe7_sleep { + pinmuxs = <&pinctrle 7 IT8XXX2_ALT_DEFAULT>; + }; + i2c2_clk_gpf6_default: i2c2_clk_gpf6_default { + gpio-voltage = "1v8"; + }; + i2c2_data_gpf7_default: i2c2_data_gpf7_default { + gpio-voltage = "1v8"; + }; +}; + +&i2c0 { + label = "I2C_EEPROM"; + clock-frequency = <I2C_BITRATE_FAST>; + + cbi_eeprom: eeprom@50 { + compatible = "atmel,at24"; + reg = <0x50>; + size = <2048>; + pagesize = <16>; + address-width = <8>; + timeout = <5>; + }; + pinctrl-0 = <&i2c0_clk_gpb3_default + &i2c0_data_gpb4_default>; + pinctrl-names = "default"; +}; + +&i2c1 { + label = "I2C_BATTERY"; + clock-frequency = <50000>; + pinctrl-0 = <&i2c1_clk_gpc1_default + &i2c1_data_gpc2_default>; + pinctrl-names = "default"; +}; + +&i2c2 { + label = "I2C_SENSOR"; + clock-frequency = <I2C_BITRATE_FAST>; + pinctrl-0 = <&i2c2_clk_gpf6_default + &i2c2_data_gpf7_default>; + pinctrl-names = "default"; +}; + +&i2c4 { + label = "I2C_SUB_C1_TCPC"; + clock-frequency = <I2C_BITRATE_FAST_PLUS>; + pinctrl-0 = <&i2c4_clk_gpe0_default + &i2c4_data_gpe7_default>; + pinctrl-1 = <&i2c4_clk_gpe0_sleep + &i2c4_data_gpe7_sleep>; + pinctrl-names = "default", "sleep"; + + bc12_port1: pi3usb9201@5f { + compatible = "pericom,pi3usb9201"; + status = "okay"; + reg = <0x5f>; + }; + + chg_port1: sm5803@32 { + compatible = "siliconmitus,sm5803"; + status = "okay"; + reg = <0x32>; + }; +}; + +&i2c_ec_i2c_sub_usb_c1 { + /* + * Dynamic speed setting is used for AP-controlled firmware update + * of PS8745 TCPC/redriver: the AP lowers speed to 400 kHz in order + * to use more efficient window programming, then sets it back when + * done. + */ + dynamic-speed; +}; + +&i2c5 { + label = "I2C_USB_C0_TCPC"; + clock-frequency = <I2C_BITRATE_FAST_PLUS>; + pinctrl-0 = <&i2c5_clk_gpa4_default + &i2c5_data_gpa5_default>; + pinctrl-names = "default"; + + bc12_port0: pi3usb9201@5f { + compatible = "pericom,pi3usb9201"; + status = "okay"; + reg = <0x5f>; + }; + + chg_port0: sm5803@32 { + compatible = "siliconmitus,sm5803"; + status = "okay"; + reg = <0x32>; + }; +}; + +&usbpd0 { + status = "okay"; +}; diff --git a/zephyr/projects/nissa/nereid/power_signals.dtsi b/zephyr/projects/nissa/nereid/power_signals.dtsi new file mode 100644 index 0000000000..8affae03b1 --- /dev/null +++ b/zephyr/projects/nissa/nereid/power_signals.dtsi @@ -0,0 +1,223 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + chosen { + intel-ap-pwrseq,espi = &espi0; + }; + + common-pwrseq { + compatible = "intel,ap-pwrseq"; + + sys-pwrok-delay = <10>; + all-sys-pwrgd-timeout = <20>; + }; + + pwr-en-pp5000-s5 { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "PP5000_S5 enable output to regulator"; + enum-name = "PWR_EN_PP5000_A"; + gpios = <&gpiok 5 0>; + output; + }; + pwr-en-pp3300-s5 { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "PP3300_S5 enable output to LS"; + enum-name = "PWR_EN_PP3300_A"; + gpios = <&gpioc 5 0>; + output; + }; + pwr-pg-ec-rsmrst-odl { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "RSMRST power good from regulator"; + enum-name = "PWR_RSMRST"; + gpios = <&gpioe 1 0>; + interrupt-flags = <GPIO_INT_EDGE_BOTH>; + }; + pwr-ec-pch-rsmrst-odl { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "RSMRST output to PCH"; + enum-name = "PWR_EC_PCH_RSMRST"; + gpios = <&gpioh 0 0>; + output; + }; + pwr-slp-s0-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SLP_S0_L input from PCH"; + enum-name = "PWR_SLP_S0"; + gpios = <&gpioe 4 GPIO_ACTIVE_LOW>; + interrupt-flags = <GPIO_INT_EDGE_BOTH>; + }; + pwr-slp-s3-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SLP_S3_L input from PCH"; + enum-name = "PWR_SLP_S3"; + gpios = <&gpioh 3 GPIO_ACTIVE_LOW>; + interrupt-flags = <GPIO_INT_EDGE_BOTH>; + }; + pwr-slp-sus-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SLP_SUS_L input from PCH"; + enum-name = "PWR_SLP_SUS"; + gpios = <&gpiog 2 GPIO_ACTIVE_LOW>; + interrupt-flags = <GPIO_INT_EDGE_BOTH>; + }; + pwr-ec-soc-dsw-pwrok { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "DSW_PWROK output to PCH"; + enum-name = "PWR_EC_SOC_DSW_PWROK"; + gpios = <&gpiol 7 0>; + output; + }; + pwr-vccst-pwrgd-od { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "VCCST_PWRGD output to PCH"; + enum-name = "PWR_VCCST_PWRGD"; + gpios = <&gpioe 5 (GPIO_OPEN_DRAIN | GPIO_VOLTAGE_1P8)>; + output; + }; + pwr-imvp9-vrrdy-od { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "VRRDY input from IMVP9"; + enum-name = "PWR_IMVP9_VRRDY"; + gpios = <&gpioj 4 0>; + }; + pwr-pch-pwrok { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "PCH_PWROK output to PCH"; + enum-name = "PWR_PCH_PWROK"; + gpios = <&gpiod 6 GPIO_OPEN_DRAIN>; + output; + }; + pwr-ec-pch-sys-pwrok { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SYS_PWROK output to PCH"; + enum-name = "PWR_EC_PCH_SYS_PWROK"; + gpios = <&gpiof 2 0>; + output; + }; + pwr-sys-rst-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SYS_RESET# output to PCH"; + enum-name = "PWR_SYS_RST"; + gpios = <&gpiod 1 (GPIO_ACTIVE_LOW|GPIO_OPEN_DRAIN)>; + output; + }; + pwr-slp-s4 { + compatible = "intel,ap-pwrseq-vw"; + dbg-label = "SLP_S4 virtual wire input from PCH"; + enum-name = "PWR_SLP_S4"; + virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S4"; + vw-invert; + }; + pwr-slp-s5 { + compatible = "intel,ap-pwrseq-vw"; + dbg-label = "SLP_S5 virtual wire input from PCH"; + enum-name = "PWR_SLP_S5"; + virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S5"; + vw-invert; + }; + pwr-all-sys-pwrgd { + /* + * This is a board level signal, since this + * signal needs some special processing. + */ + compatible = "intel,ap-pwrseq-external"; + dbg-label = "Combined all power good"; + enum-name = "PWR_ALL_SYS_PWRGD"; + }; + pwr-adc-pp3300 { + compatible = "intel,ap-pwrseq-adc"; + dbg-label = "PP3300_PROC"; + enum-name = "PWR_DSW_PWROK"; + trigger-high = <&vcmp0>; + trigger-low = <&vcmp1>; + }; + pwr-adc-pp1p05 { + compatible = "intel,ap-pwrseq-adc"; + dbg-label = "PP1P05_PROC"; + enum-name = "PWR_PG_PP1P05"; + trigger-high = <&vcmp2>; + trigger-low = <&vcmp3>; + }; + +}; + +/* + * Because the power signals directly reference the GPIOs, + * the correspinding named-gpios need to have no-auto-init set. + */ +&gpio_ec_soc_dsw_pwrok { + no-auto-init; +}; +&gpio_ec_soc_pch_pwrok_od { + no-auto-init; +}; +&gpio_ec_soc_rsmrst_l { + no-auto-init; +}; +&gpio_ec_soc_sys_pwrok { + no-auto-init; +}; +&gpio_ec_soc_vccst_pwrgd_od { + no-auto-init; +}; +&gpio_en_pp3300_s5 { + no-auto-init; +}; +&gpio_en_pp5000_s5 { + no-auto-init; +}; +&gpio_imvp91_vrrdy_od { + no-auto-init; +}; +&gpio_rsmrst_pwrgd_l { + no-auto-init; +}; +&gpio_slp_s0_l { + no-auto-init; +}; +&gpio_slp_s3_l { + no-auto-init; +}; +&gpio_slp_sus_l { + no-auto-init; +}; +&gpio_sys_rst_odl { + no-auto-init; +}; +&vcmp0 { + status = "okay"; + scan-period = <IT8XXX2_VCMP_SCAN_PERIOD_600US>; + comparison = <IT8XXX2_VCMP_GREATER>; + /* + * This is 90% of nominal voltage considering voltage + * divider on ADC input. + */ + threshold-mv = <2448>; + io-channels = <&adc0 0>; +}; +&vcmp1 { + status = "okay"; + scan-period = <IT8XXX2_VCMP_SCAN_PERIOD_600US>; + comparison = <IT8XXX2_VCMP_LESS_OR_EQUAL>; + threshold-mv = <2448>; + io-channels = <&adc0 0>; +}; +&vcmp2 { + status = "okay"; + scan-period = <IT8XXX2_VCMP_SCAN_PERIOD_600US>; + comparison = <IT8XXX2_VCMP_GREATER>; + /* Setting at 90% of nominal voltage */ + threshold-mv = <945>; + io-channels = <&adc0 14>; +}; +&vcmp3 { + status = "okay"; + scan-period = <IT8XXX2_VCMP_SCAN_PERIOD_600US>; + comparison = <IT8XXX2_VCMP_LESS_OR_EQUAL>; + threshold-mv = <945>; + io-channels = <&adc0 14>; +}; diff --git a/zephyr/projects/nissa/nereid/project.conf b/zephyr/projects/nissa/nereid/project.conf new file mode 100644 index 0000000000..75a5faba5d --- /dev/null +++ b/zephyr/projects/nissa/nereid/project.conf @@ -0,0 +1,17 @@ +# Copyright 2021 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +CONFIG_BOARD_NEREID=y + +# Ensure recovery key combination (esc+refresh+power) is reliable: b/236580049 +CONFIG_PLATFORM_EC_KEYBOARD_PWRBTN_ASSERTS_KSI2=y + +# Sensor drivers +CONFIG_PLATFORM_EC_ACCELGYRO_BMI_COMM_I2C=y +CONFIG_PLATFORM_EC_ACCELGYRO_BMI3XX=y +CONFIG_PLATFORM_EC_ACCEL_BMA4XX=y +CONFIG_PLATFORM_EC_MAX_SENSOR_FREQ_MILLIHZ=100000 + +# No fan supported, and tach is default-enabled +CONFIG_TACH_IT8XXX2=n diff --git a/zephyr/projects/nissa/nereid/project.overlay b/zephyr/projects/nissa/nereid/project.overlay new file mode 100644 index 0000000000..0aceac1c47 --- /dev/null +++ b/zephyr/projects/nissa/nereid/project.overlay @@ -0,0 +1,13 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "../cbi.dtsi" + +#include "generated.dtsi" +#include "keyboard.dtsi" +#include "motionsense.dtsi" +#include "overlay.dtsi" +#include "power_signals.dtsi" +#include "pwm_leds.dtsi" diff --git a/zephyr/projects/nissa/nereid/pwm_leds.dtsi b/zephyr/projects/nissa/nereid/pwm_leds.dtsi new file mode 100644 index 0000000000..aa4a76b271 --- /dev/null +++ b/zephyr/projects/nissa/nereid/pwm_leds.dtsi @@ -0,0 +1,60 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + pwmleds { + compatible = "pwm-leds"; + pwm_led0: pwm_led_0 { + pwms = <&pwm1 1 PWM_HZ(1296) PWM_POLARITY_INVERTED>, + <&pwm2 2 PWM_HZ(1296) PWM_POLARITY_INVERTED>, + <&pwm3 3 PWM_HZ(1296) PWM_POLARITY_INVERTED>; + }; + }; + + cros-pwmleds { + compatible = "cros-ec,pwm-leds"; + + leds = <&pwm_led0>; + + /*<red green blue>*/ + color-map-red = <100 0 0>; + color-map-green = < 0 100 0>; + color-map-blue = < 0 0 100>; + color-map-yellow = < 0 50 50>; + color-map-white = <100 100 100>; + color-map-amber = <100 15 0>; + + brightness-range = <100 100 100 0 0 0>; + + #address-cells = <1>; + #size-cells = <0>; + + pwm_led_0@0 { + reg = <0>; + ec-led-name = "EC_LED_ID_BATTERY_LED"; + }; + }; +}; + +&pwm1 { + status = "okay"; + prescaler-cx = <PWM_PRESCALER_C4>; + pinctrl-0 = <&pwm1_gpa1_default>; + pinctrl-names = "default"; +}; + +&pwm2 { + status = "okay"; + prescaler-cx = <PWM_PRESCALER_C4>; + pinctrl-0 = <&pwm2_gpa2_default>; + pinctrl-names = "default"; +}; + +&pwm3 { + status = "okay"; + prescaler-cx = <PWM_PRESCALER_C4>; + pinctrl-0 = <&pwm3_gpa3_default>; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/nissa/nereid/src/charger.c b/zephyr/projects/nissa/nereid/src/charger.c new file mode 100644 index 0000000000..181e9a61fd --- /dev/null +++ b/zephyr/projects/nissa/nereid/src/charger.c @@ -0,0 +1,56 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <zephyr/logging/log.h> + +#include "battery.h" +#include "charger.h" +#include "console.h" +#include "driver/charger/sm5803.h" +#include "extpower.h" +#include "usb_pd.h" +#include "nissa_common.h" + +LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL); + +int extpower_is_present(void) +{ + int port; + int rv; + bool acok; + + for (port = 0; port < board_get_usb_pd_port_count(); port++) { + rv = sm5803_is_acok(port, &acok); + if ((rv == EC_SUCCESS) && acok) + return 1; + } + + return 0; +} + +/* + * Nereid does not have a GPIO indicating whether extpower is present, + * so detect using the charger(s). + */ +__override void board_check_extpower(void) +{ + static int last_extpower_present; + int extpower_present = extpower_is_present(); + + if (last_extpower_present ^ extpower_present) + extpower_handle_update(extpower_present); + + last_extpower_present = extpower_present; +} + +__override void board_hibernate(void) +{ + /* Shut down the chargers */ + if (board_get_usb_pd_port_count() == 2) + sm5803_hibernate(CHARGER_SECONDARY); + sm5803_hibernate(CHARGER_PRIMARY); + LOG_INF("Charger(s) hibernated"); + cflush(); +} diff --git a/zephyr/projects/nissa/nereid/src/hdmi.c b/zephyr/projects/nissa/nereid/src/hdmi.c new file mode 100644 index 0000000000..7e5708c6eb --- /dev/null +++ b/zephyr/projects/nissa/nereid/src/hdmi.c @@ -0,0 +1,28 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <cros_board_info.h> +#include "nissa_hdmi.h" + +__override void nissa_configure_hdmi_power_gpios(void) +{ + /* + * Nereid versions before 2 need hdmi-en-odl to be + * pulled down to enable VCC on the HDMI port, but later + * versions (and other boards) disconnect this so + * the port's VCC directly follows en-rails-odl. Only + * configure the GPIO if needed, to save power. + */ + uint32_t board_version = 0; + + /* CBI errors ignored, will configure the pin */ + cbi_get_board_version(&board_version); + if (board_version < 2) { + nissa_configure_hdmi_vcc(); + } + + /* Still always need core rails controlled */ + nissa_configure_hdmi_rails(); +} diff --git a/zephyr/projects/nissa/nereid/src/keyboard.c b/zephyr/projects/nissa/nereid/src/keyboard.c new file mode 100644 index 0000000000..b69bb4da33 --- /dev/null +++ b/zephyr/projects/nissa/nereid/src/keyboard.c @@ -0,0 +1,29 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "ec_commands.h" + +static const struct ec_response_keybd_config nereid_kb_legacy = { + .num_top_row_keys = 10, + .action_keys = { + TK_BACK, /* T1 */ + TK_FORWARD, /* T2 */ + TK_REFRESH, /* T3 */ + TK_FULLSCREEN, /* T4 */ + TK_OVERVIEW, /* T5 */ + TK_BRIGHTNESS_DOWN, /* T6 */ + TK_BRIGHTNESS_UP, /* T7 */ + TK_VOL_MUTE, /* T8 */ + TK_VOL_DOWN, /* T9 */ + TK_VOL_UP, /* T10 */ + }, + .capabilities = KEYBD_CAP_SCRNLOCK_KEY, +}; + +__override const struct ec_response_keybd_config * +board_vivaldi_keybd_config(void) +{ + return &nereid_kb_legacy; +} diff --git a/zephyr/projects/nissa/nereid/src/usbc.c b/zephyr/projects/nissa/nereid/src/usbc.c new file mode 100644 index 0000000000..48f7cfd9cb --- /dev/null +++ b/zephyr/projects/nissa/nereid/src/usbc.c @@ -0,0 +1,393 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <zephyr/logging/log.h> +#include <ap_power/ap_power.h> + +#include "charge_state_v2.h" +#include "chipset.h" +#include "hooks.h" +#include "usb_mux.h" +#include "system.h" +#include "driver/charger/sm5803.h" +#include "driver/tcpm/it83xx_pd.h" +#include "driver/tcpm/ps8xxx_public.h" +#include "driver/tcpm/tcpci.h" + +#include "nissa_common.h" + +LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL); + +struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = { + { + .bus_type = EC_BUS_TYPE_EMBEDDED, + /* TCPC is embedded within EC so no i2c config needed */ + .drv = &it8xxx2_tcpm_drv, + /* Alert is active-low, push-pull */ + .flags = 0, + }, + { + /* + * Sub-board: optional PS8745 TCPC+redriver. Behaves the same + * as PS8815. + */ + .bus_type = EC_BUS_TYPE_I2C, + .i2c_info = { + .port = I2C_PORT_USB_C1_TCPC, + .addr_flags = PS8XXX_I2C_ADDR1_FLAGS, + }, + .drv = &ps8xxx_tcpm_drv, + /* PS8745 implements TCPCI 2.0 */ + .flags = TCPC_FLAGS_TCPCI_REV2_0, + }, +}; + +/* Vconn control for integrated ITE TCPC */ +void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled) +{ + /* Vconn control is only for port 0 */ + if (port) + return; + + if (cc_pin == USBPD_CC_PIN_1) + gpio_pin_set_dt( + GPIO_DT_FROM_NODELABEL(gpio_en_usb_c0_cc1_vconn), + !!enabled); + else + gpio_pin_set_dt( + GPIO_DT_FROM_NODELABEL(gpio_en_usb_c0_cc2_vconn), + !!enabled); +} + +__override bool pd_check_vbus_level(int port, enum vbus_level level) +{ + return sm5803_check_vbus_level(port, level); +} + +/* + * Putting chargers into LPM when in suspend reduces power draw by about 8mW + * per charger, but also seems critical to correct operation in source mode: + * if chargers are not in LPM when a sink is first connected, VBUS sourcing + * works even if the partner is later removed (causing LPM entry) and + * reconnected (causing LPM exit). If in LPM initially, sourcing VBUS + * consistently causes the charger to report (apparently spurious) overcurrent + * failures. + * + * In short, this is important to making things work correctly but we don't + * understand why. + */ +static void board_chargers_suspend(struct ap_power_ev_callback *const cb, + const struct ap_power_ev_data data) +{ + void (*fn)(int chgnum); + + switch (data.event) { + case AP_POWER_SUSPEND: + fn = sm5803_enable_low_power_mode; + break; + case AP_POWER_RESUME: + fn = sm5803_disable_low_power_mode; + break; + default: + LOG_WRN("%s: power event %d is not recognized", __func__, + data.event); + return; + } + + fn(CHARGER_PRIMARY); + if (board_get_charger_chip_count() > 1) + fn(CHARGER_SECONDARY); +} + +static int board_chargers_suspend_init(const struct device *unused) +{ + static struct ap_power_ev_callback cb = { + .handler = board_chargers_suspend, + .events = AP_POWER_SUSPEND | AP_POWER_RESUME, + }; + ap_power_ev_add_callback(&cb); + return 0; +} +SYS_INIT(board_chargers_suspend_init, APPLICATION, 0); + +int board_set_active_charge_port(int port) +{ + int is_real_port = (port >= 0 && port < board_get_usb_pd_port_count()); + int i; + int old_port; + int rv; + + if (!is_real_port && port != CHARGE_PORT_NONE) + return EC_ERROR_INVAL; + + old_port = charge_manager_get_active_charge_port(); + LOG_INF("Charge update: p%d -> p%d", old_port, port); + + /* Check if port is sourcing VBUS. */ + if (port != CHARGE_PORT_NONE && charger_is_sourcing_otg_power(port)) { + LOG_WRN("Skip enable p%d: already sourcing", port); + return EC_ERROR_INVAL; + } + + /* Disable sinking on all ports except the desired one */ + for (i = 0; i < board_get_usb_pd_port_count(); i++) { + if (i == port) + continue; + + if (sm5803_vbus_sink_enable(i, 0)) + /* + * Do not early-return because this can fail during + * power-on which would put us into a loop. + */ + LOG_WRN("p%d: sink path disable failed.", i); + } + + /* Don't enable anything (stop here) if no ports were requested */ + if ((port == CHARGE_PORT_NONE) || (old_port == port)) + return EC_SUCCESS; + + /* + * Stop the charger IC from switching while changing ports. Otherwise, + * we can overcurrent the adapter we're switching to. (crbug.com/926056) + */ + if (old_port != CHARGE_PORT_NONE) + charger_discharge_on_ac(1); + + /* Enable requested charge port. */ + rv = sm5803_vbus_sink_enable(port, 1); + if (rv) + LOG_WRN("p%d: sink path enable failed: code %d", port, rv); + + /* Allow the charger IC to begin/continue switching. */ + charger_discharge_on_ac(0); + + return rv; +} + +uint16_t tcpc_get_alert_status(void) +{ + /* + * TCPC 0 is embedded in the EC and processes interrupts in the chip + * code (it83xx/intc.c). This function only needs to poll port C1 if + * present. + */ + uint16_t status = 0; + int regval; + + /* Is the C1 port present and its IRQ line asserted? */ + if (board_get_usb_pd_port_count() == 2 && + !gpio_pin_get_dt(GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl))) { + /* + * C1 IRQ is shared between BC1.2 and TCPC; poll TCPC to see if + * it asserted the IRQ. + */ + if (!tcpc_read16(1, TCPC_REG_ALERT, ®val)) { + if (regval) + status = PD_STATUS_TCPC_ALERT_1; + } + } + + return status; +} + +void pd_power_supply_reset(int port) +{ + int prev_en; + + if (port < 0 || port >= board_get_usb_pd_port_count()) + return; + + prev_en = charger_is_sourcing_otg_power(port); + + /* Disable Vbus */ + charger_enable_otg_power(port, 0); + + /* Discharge Vbus if previously enabled */ + if (prev_en) + sm5803_set_vbus_disch(port, 1); + + /* Notify host of power info change. */ + pd_send_host_event(PD_EVENT_POWER_CHANGE); +} + +int pd_set_power_supply_ready(int port) +{ + enum ec_error_list rv; + + if (port < 0 || port > board_get_usb_pd_port_count()) { + LOG_WRN("Port C%d does not exist, cannot enable VBUS", port); + return EC_ERROR_INVAL; + } + + /* Disable sinking */ + rv = sm5803_vbus_sink_enable(port, 0); + if (rv) { + LOG_WRN("C%d failed to disable sinking: %d", port, rv); + return rv; + } + + /* Disable Vbus discharge */ + rv = sm5803_set_vbus_disch(port, 0); + if (rv) { + LOG_WRN("C%d failed to clear VBUS discharge: %d", port, rv); + return rv; + } + + /* Provide Vbus */ + rv = charger_enable_otg_power(port, 1); + if (rv) { + LOG_WRN("C%d failed to enable VBUS sourcing: %d", port, rv); + return rv; + } + + /* Notify host of power info change. */ + pd_send_host_event(PD_EVENT_POWER_CHANGE); + + return EC_SUCCESS; +} + +__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp) +{ + int rv; + const int current = rp == TYPEC_RP_3A0 ? 3000 : 1500; + + rv = charger_set_otg_current_voltage(port, current, 5000); + if (rv != EC_SUCCESS) { + LOG_WRN("Failed to set source ilimit on port %d to %d: %d", + port, current, rv); + } +} + +void board_reset_pd_mcu(void) +{ + /* + * Do nothing. The integrated TCPC for C0 lacks a dedicated reset + * command, and C1 (if present) doesn't have a reset pin connected + * to the EC. + */ +} + +#define INT_RECHECK_US 5000 + +/* C0 interrupt line shared by BC 1.2 and charger */ + +static void check_c0_line(void); +DECLARE_DEFERRED(check_c0_line); + +static void notify_c0_chips(void) +{ + usb_charger_task_set_event(0, USB_CHG_EVENT_BC12); + sm5803_interrupt(0); +} + +static void check_c0_line(void) +{ + /* + * If line is still being held low, see if there's more to process from + * one of the chips + */ + if (!gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_c0_int_odl))) { + notify_c0_chips(); + hook_call_deferred(&check_c0_line_data, INT_RECHECK_US); + } +} + +void usb_c0_interrupt(enum gpio_signal s) +{ + /* Cancel any previous calls to check the interrupt line */ + hook_call_deferred(&check_c0_line_data, -1); + + /* Notify all chips using this line that an interrupt came in */ + notify_c0_chips(); + + /* Check the line again in 5ms */ + hook_call_deferred(&check_c0_line_data, INT_RECHECK_US); +} + +/* C1 interrupt line shared by BC 1.2, TCPC, and charger */ +static void check_c1_line(void); +DECLARE_DEFERRED(check_c1_line); + +static void notify_c1_chips(void) +{ + schedule_deferred_pd_interrupt(1); + usb_charger_task_set_event(1, USB_CHG_EVENT_BC12); + /* Charger is handled in board_process_pd_alert */ +} + +static void check_c1_line(void) +{ + /* + * If line is still being held low, see if there's more to process from + * one of the chips. + */ + if (!gpio_pin_get_dt(GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl))) { + notify_c1_chips(); + hook_call_deferred(&check_c1_line_data, INT_RECHECK_US); + } +} + +void usb_c1_interrupt(enum gpio_signal s) +{ + /* Cancel any previous calls to check the interrupt line */ + hook_call_deferred(&check_c1_line_data, -1); + + /* Notify all chips using this line that an interrupt came in */ + notify_c1_chips(); + + /* Check the line again in 5ms */ + hook_call_deferred(&check_c1_line_data, INT_RECHECK_US); +} + +/* + * Check state of IRQ lines at startup, ensuring an IRQ that happened before + * the EC started up won't get lost (leaving the IRQ line asserted and blocking + * any further interrupts on the port). + * + * Although the PD task will check for pending TCPC interrupts on startup, + * the charger sharing the IRQ will not be polled automatically. + */ +void board_handle_initial_typec_irq(void) +{ + check_c0_line(); + if (board_get_usb_pd_port_count() == 2) + check_c1_line(); +} +/* + * This must run after sub-board detection (which happens in EC main()), + * but isn't depended on by anything else either. + */ +DECLARE_HOOK(HOOK_INIT, board_handle_initial_typec_irq, HOOK_PRIO_LAST); + +/* + * Handle charger interrupts in the PD task. Not doing so can lead to a priority + * inversion where we fail to respond to TCPC alerts quickly enough because we + * don't get another edge on a shared IRQ until the charger interrupt is cleared + * (or the IRQ is polled again), which happens in the low-priority charger task: + * the high-priority type-C handler is thus blocked on the lower-priority + * charger. + * + * To avoid that, we run charger interrupts at the same priority. + */ +void board_process_pd_alert(int port) +{ + /* + * Port 0 doesn't use an external TCPC, so its interrupts don't need + * this special handling. + */ + if (port == 1 && + !gpio_pin_get_dt(GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl))) { + sm5803_handle_interrupt(port); + } +} + +int pd_snk_is_vbus_provided(int port) +{ + int chg_det = 0; + + sm5803_get_chg_det(port, &chg_det); + + return chg_det; +} diff --git a/zephyr/projects/nissa/nissa.csv b/zephyr/projects/nissa/nissa.csv new file mode 100644 index 0000000000..45b73ea229 --- /dev/null +++ b/zephyr/projects/nissa/nissa.csv @@ -0,0 +1,122 @@ +Signal Name,Subsystem,Description,DIR,Int,I/O Type,Internal PU,I/O Voltage,ICs attached,NPCX993 (Nivviks),NPCX993 (Nirwen),IT81302 (Nereid),Type,Enum,SW Notes,HW Notes
+ESPI_SOC_CLK,ESPI,ESPI clock,IN,no,--,N,1.80 V,,M1,M1,L1,OTHER,,,
+ESPI_SOC_CS_EC_L,ESPI,ESPI chip select,IN,F,--,N,1.80 V,,L2,L2,J2,OTHER,,,
+ESPI_SOC_D0_EC,ESPI,ESPI DATA0,I/O,,TTL,N,1.80 V,,H1,H1,L2,OTHER,,,
+ESPI_SOC_D1_EC,ESPI,ESPI DATA1,I/O,,TTL,N,1.80 V,,J1,J1,K1,OTHER,,,
+ESPI_SOC_D2_EC,ESPI,ESPI DATA2,I/O,,TTL,N,1.80 V,,K1,K1,K2,OTHER,,,
+ESPI_SOC_D3_EC,ESPI,ESPI DATA3,I/O,,TTL,N,1.80 V,,L1,L1,J1,OTHER,,,
+ESPI_SOC_RST_EC_L,ESPI,ESPI reset,IN,F,,N,1.80 V,,K3,K3,R5,OTHER,,,
+ESPI_EC_ALERT_SOC_L,ESPI,ESPI Alert,OUT,,TTL,N,1.80 V,,L3,L3,H1,OTHER,,,
+GSC_EC_PWR_BTN_ODL,GSC,Power Button input from GSC,IN,both,--,Y,3.30 V,,E7,E7,B13,INPUT_PU,GPIO_POWER_BUTTON_L,GPIO00,
+EC_RST_ODL,GSC,Reset signal for EC from GSC,IN,no,--,N,3.30 V,GSC,K6,K6,M2,OTHER,,,
+EC_GSC_PACKET_MODE,GSC,Wakes/interrupts GSC and (maybe) vice-versa,I/O,both,--,N,3.30 V,,J6,J6,F9,OUTPUT,GPIO_PACKET_MODE_EN,,
+EC_I2C_EEPROM_SCL,I2C,"I2C clock for CBI, reading INAs, programming EC (ITE only)",I/O,,OD,N,3.30 V,"EEPROMs, INAs",C12,C12,A5,I2C_CLOCK,I2C_PORT_EEPROM,,
+EC_I2C_EEPROM_SDA,I2C,"I2C data for CBI, reading INAs, programming EC (ITE only)",I/O,,OD,N,3.30 V,"EEPROMs, INAs",B12,B12,B3,I2C_DATA,,,
+EC_I2C_BATT_SDA,I2C,I2C data for battery pack,I/O,,OD,N,3.30 V,Battery Pack,K10,K10,A3,I2C_DATA,,,
+EC_I2C_BATT_SCL,I2C,I2C clock for battery pack,I/O,,OD,N,3.30 V,Battery Pack,J10,J10,A4,I2C_CLOCK,I2C_PORT_BATTERY,,
+EC_I2C_SENSOR_SCL,I2C,I2C clock for sensors,I/O,,OD,N,3.30 V,"IMU, accel, lid accel, kb bl",K8,K8,C2,I2C_CLOCK,I2C_PORT_SENSOR,,
+EC_I2C_SENSOR_SDA,I2C,I2C data for sensors,I/O,,OD,N,3.30 V,"IMU, accel, lid accel, kb bl",K7,K7,D2,I2C_DATA,,,
+EC_I2C_USB_C0_SDA,I2C,I2C clock for USB-C C0 and USB-A A0 port ICs,I/O,,OD,N,3.30 V,"TCPC, BC1.2, Charger",F9,F9,K7,I2C_DATA,,,
+EC_I2C_USB_C0_SCL,I2C,I2C data for USB-C C0 and USB-A A0 port ICs,I/O,,OD,N,3.30 V,"TCPC, BC1.2, Charger",F8,F8,L7,I2C_CLOCK,I2C_PORT_USB_C0_TCPC,,
+EC_I2C_SUB_USB_C1_SDA,I2C,I2C clock for USB-C C1 and USB-A A1 port ICs (HDMI: HDMI_EN_SUB_ODL - enable HDMI retimer/output/active low),I/O,,OD,N,3.30 V,"TCPC, BC1.2, Charger",E9,E9,R4,I2C_DATA,,,
+EC_I2C_SUB_USB_C1_SCL,I2C,"I2C data for USB-C C1 and USB-A A1 port ICs (HDMI_HPD_SUB_ODL, hot-plug detection/input (interrupt)/active low)",I/O,,OD,N,3.30 V,"TCPC, BC1.2, Charger",E8,E8,P3,I2C_CLOCK,I2C_PORT_USB_C1_TCPC,,
+EC_KSI_00,Keyboard,Keyboard Input,IN,no,--,Y,3.30 V,,A2,A2,K15,OTHER,,,
+KSI_01,Keyboard,Keyboard Input,IN,no,--,Y,3.30 V,,A3,A3,K14,OTHER,,,
+EC_KSI_02,Keyboard,Keyboard Input,IN,no,--,Y,3.30 V,,A4,A4,K10,OTHER,,,
+EC_KSI_03,Keyboard,Keyboard Input,IN,no,--,Y,3.30 V,,B3,B3,J15,OTHER,,,Vivaldi Support
+KSI_04,Keyboard,Keyboard Input,IN,no,--,Y,3.30 V,,B4,B4,J10,OTHER,,,
+KSI_05,Keyboard,Keyboard Input,IN,no,--,Y,3.30 V,,C3,C3,J11,OTHER,,,
+KSI_06,Keyboard,Keyboard Input,IN,no,--,Y,3.30 V,,C4,C4,J14,OTHER,,,
+KSI_07,Keyboard,Keyboard Input,IN,no,--,Y,3.30 V,,C5,C5,H10,OTHER,,,
+KSO_00,Keyboard,Keyboard Output,OUT,,OD,N,3.30 V,,B5,B5,R9,OTHER,,,
+KSO_01,Keyboard,Keyboard Output,OUT,,OD,N,3.30 V,,B6,B6,K8,OTHER,,,
+EC_KSO_02_INV,Keyboard,Keyboard Output,OUT,,TTL,N,3.30 V,,B7,B7,P10,OUTPUT_L,,KEYBOARD_COL2_INVERTED,
+KSO_03,Keyboard,Keyboard Output,OUT,,OD,N,3.30 V,,B8,B8,R10,OTHER,,,
+KSO_04,Keyboard,Keyboard Output,OUT,,OD,N,3.30 V,,C7,C7,L9,OTHER,,,
+KSO_05,Keyboard,Keyboard Output,OUT,,OD,N,3.30 V,,C6,C6,K9,OTHER,,,
+KSO_06,Keyboard,Keyboard Output,OUT,,OD,N,3.30 V,,C8,C8,P11,OTHER,,,
+KSO_07,Keyboard,Keyboard Output,OUT,,OD,N,3.30 V,,B9,B9,R11,OTHER,,,
+KSO_08,Keyboard,Keyboard Output,OUT,,OD,N,3.30 V,,C9,C9,P12,OTHER,,,
+KSO_09,Keyboard,Keyboard Output,OUT,,OD,N,3.30 V,,C10,C10,L10,OTHER,,,
+KSO_10,Keyboard,Keyboard Output,OUT,,OD,N,3.30 V,,B11,B11,P13,OTHER,,,
+KSO_11,Keyboard,Keyboard Output,OUT,,OD,N,3.30 V,,B10,B10,P14,OTHER,,,
+KSO_12,Keyboard,Keyboard Output,OUT,,OD,N,3.30 V,,C11,C11,N14,OTHER,,,
+KSO_13,Keyboard,Keyboard Output,OUT,,OD,N,3.30 V,,D11,D11,M15,OTHER,,,Required only for NUM PAD
+KSO_14,Keyboard,Keyboard Output,OUT,,OD,N,3.30 V,,D6,D6,M14,OTHER,,,Required only for NUM PAD
+EN_KB_BL,MISC,Enable Keyboard backlight,OUT,,TTL,N,3.30 V,,G11,G11,D14,OUTPUT,GPIO_EN_KEYBOARD_BACKLIGHT,,
+VOLDN_BTN_ODL,MISC,Volume down signal,IN,both,--,Y,3.30 V,Button,F12,E11,G15,INPUT_PU,GPIO_VOLUME_DOWN_L,,
+VOLUP_BTN_ODL,MISC,Volume up signal,IN,both,--,Y,3.30 V,Button,E11,F12,F14,INPUT_PU,GPIO_VOLUME_UP_L,,
+LID_OPEN,MISC,Indicator from lid switch that lid is open,IN,both,--,N,3.30 V,,G7,G7,A11,INPUT,GPIO_LID_OPEN,,
+TABLET_MODE_L,MISC,Indicator from lid switch that lid is flipped all the way around,IN,both,--,N,3.30 V,,M12,M12,L8,INPUT,GPIO_TABLET_MODE_L,,Not required to connect to EC?
+IMU_INT_L,MISC,Interrupt from base intertial measurement unit,IN,falling,,N,1.80 V,IMU,M2,M2,F15,INPUT,,,
+ACC_INT_L,MISC,Interrupt from lid accel (only in convertibles),IN,falling,,N,1.80 V,ACC,G10,G10,E2,INPUT,,,Not required from Dedede?
+EC_WP_ODL,MISC,Write protection status from GSC,IN,no,--,N,3.30 V,GSC,L12,L12,R8,INPUT_L,,,
+EC_EDP_BL_EN_OD,MISC,EC override of backlight enable,OUT,,OD,N,3.30 V,,E10,E10,R15,OUTPUT_ODR,GPIO_ENABLE_BACKLIGHT,,
+TEMP_SENSOR_1,MISC,NTC 1 - near memory,IN,no,ADC,N,ANA,,F2,F2,H15,ADC,ADC_TEMP_SENSOR_1,,
+TEMP_SENSOR_2,MISC,NTC 2 - near chassis hot spot,IN,no,ADC,N,ANA,,E3,E3,G10,ADC,ADC_TEMP_SENSOR_2,,
+TEMP_SENSOR_3,MISC,NTC 3 - Ambient/skin temp,IN,no,ADC,N,ANA,,,F4,A13,ADC,ADC_TEMP_SENSOR_3,,
+USB_C0_INT_ODL,MISC,Interrupt for all ICs for Type-C port 0,IN,,--,Y,3.30 V,,E6,E6,P1,INPUT_PU,,,
+USB_C0_PROT_FAULT_ODL,MISC,Fault out of the USB C0 protection IC,IN,falling,OD,Y,3.30 V,,,#N/A,,,,,
+"SUB_USB_C1_INT_ODL
+(HDMI: EN_SUB_RAILS_ODL)",MISC,"Interrupt for all ICs for Type-C port 1 or the sub-board
+HDMI: Enable 5V power rail/output/active low",IN,,--,Y,3.30 V,,F7,F7,N2,OTHER,,,
+HDMI_SEL,MISC,Configures AUX to be HDMI DDC,OUT,,TTL,N,3.30 V,,D10,D10,F2,OUTPUT,,,
+CCD_MODE_ODL,MISC,Indicates whether H1 is using SBU lines for debug. Also can trigger CCD if the EC decides to.,I/O,falling,--/OD,N,3.30 V,GSC,A12,A12,B9,INPUT,GPIO_CCD_MODE_ODL,,
+EC_BATTERY_PRES_ODL,MISC,or BATT_TEMP - indication of battery presence,IN,,--,N,3.30 V,Battery pack,K12,K12,G14,INPUT,GPIO_BATT_PRES_ODL,,
+EC_ENTERING_RW,MISC,Indicate when EC is transitioning to RW code,OUT,,TTL,N,3.30 V,GSC,D9,D9,N1,OUTPUT,GPIO_ENTERING_RW,,
+EN_USB_A0_VBUS,MISC,,OUT,,TTL,N,3.30 V,,K9,K9,B1,OUTPUT,,,
+USB_A0_ILIMIT_SDP,MISC,,OUT,,TTL,N,3.30 V,,J8,J8,A1,OUTPUT,GPIO_USB1_ILIM_SEL,??,
+EN_SUB_USB_A1_VBUS,MISC,,OUT,,TTL,N,3.30 V,,A9,A9,B12,OTHER,,??,
+SUB_USB_A1_ILIMIT_SDP,MISC,,OUT,,TTL,N,3.30 V,,A10,A10,A12,OUTPUT,GPIO_USB2_ILIM_SEL,??,
+PWM_FAN,MISC,,OUT,,PWM,N,3.30 V,,,J7,,PWM,,,
+EC_FAN_TACH,MISC,,IN,,,,5.00 V,,,G5,,TACH,,,
+EN_PP5000_FAN_X,MISC,,OUT,,TTL,N,3.30 V,,,J2,,OUTPUT,,,
+EC_CBI_WP,MISC,Updated EC WP method,OUT,,TTL,N,3.30 V,,H5,H5,D15,OUTPUT,,cbi_latch_eeprom_wp,
+IMVP91_VRRDY_OD,POWER SEQUENCE,,IN,,,,,,E2,E2,C14,INPUT,,,
+EC_SOC_SYS_PWROK,POWER SEQUENCE,"Generic power good input to PCH (platform specific), system ready to exit reset.",OUT,,TTL,N,3.30 V,SOC,C1,C1,B11,OUTPUT,,PCH_PWROK,
+EN_SLP_Z,POWER SEQUENCE,Enable Sleep State (Active high). For ITE only.,OUT,,TTL,N,3.30 V,,F3,F3,R3,OUTPUT,,,
+EN_PP5000_S5,POWER SEQUENCE,"Enable PP5000_S5. Figure 523, states this has to come after 3.3V , why?",OUT,,TTL,N,3.30 V,,E5,E5,R14,OUTPUT,,,
+EN_PP3300_S5,POWER SEQUENCE,Enable PP3300_S5.,OUT,,TTL,N,3.30 V,,L9,L9,K11,OUTPUT,GPIO_TEMP_SENSOR_POWER,,
+EC_SOC_DSW_PWROK,POWER SEQUENCE,DSW Power is OK to AP (diode logic with PP3300_PG),OUT,,TTL,N,3.30 V,SOC,K4,K4,C1,OUTPUT,,,
+EC_SOC_RSMRST_L,POWER SEQUENCE,"Asserted after S5-rails are stable, buffered to SOC from EC",OUT,,TTL,N,3.30 V,SOC,F11,F11,E9,OUTPUT,,,
+RSMRST_PWRGD_L,POWER SEQUENCE,,IN,both,--,Y,3.30 V,,M11,M11,B14,INPUT_PU,,,
+SLP_SUS_L,POWER SEQUENCE,"If high, EC must keep S5 on, used in both DSx and non-DSx platforms.",IN,both,--,N,3.30 V,,H2,H2,F8,INPUT,,,No virtual wire over eSPI
+SLP_S4_L,POWER SEQUENCE,"PCH S4 Sleep control. When low, shut-off power to all non critical systems in S4 and lower.",IN,both,--,N,3.30 V,,J4,J4,G11,INPUT,,,This signal is also virtual wire on the eSPI interface.
+SLP_S3_L,POWER SEQUENCE,"PCH S3 Sleep control. When low, shut-off power to all non critical systems in S3 and lower.",IN,both,--,N,3.30 V,,K11,K11,B10,INPUT,,,This signal is also virtual wire on the eSPI interface.
+SLP_S0_L,POWER SEQUENCE,"PCH S0 Sleep control, asserted when PCH = idle & CPU = C10",IN,both,--,N,3.30 V,,L10,L10,F1,INPUT,,,No virtual wire over eSPI
+CPU_C10_GATE_L,POWER SEQUENCE,Asserted low when going into CPU_C10,IN,both,--,N,3.30 V,"SOC, VRs, LS",J3,J3,B6,INPUT,,??,
+EC_VSENSE_PP3300_S5,POWER SEQUENCE,Voltage sense (or PGOOD) for PP3300_S5,IN,no,ADC,N,ANA,,B2,B2,H11,ADC,ADC_PP3300_S5,??,"Nuvoton VREF=2.816V, ITE VREF = AVCC or AVCC/1.1 (3V)"
+PG_PP5000_S5_OD,POWER SEQUENCE,PP5000_S5 power good signal.,IN,,--,N,3.30 V,,D3,D3,C15,INPUT,,,
+EC_SOC_VCCST_PWRGD_OD,POWER SEQUENCE,,OUT,,OD,N,1.05 V,,H11,H11,P9,OUTPUT_ODR,,,
+EC_SOC_PCH_PWROK_OD,POWER SEQUENCE,,OUT,,OD,N,3.30 V,,M4,M4,R12,OUTPUT_ODR,,,
+ALL_SYS_PWRGD,POWER SEQUENCE,,IN,both,,N,3.30 V,,J11,J11,B2,INPUT,,,Figure 398 PDG 0.5
+PG_PP1050_MEM_S3_OD,POWER SEQUENCE,,IN,both,--,N,3.30 V,,D2,D2,P5,INPUT,,??,
+EC_VSENSE_PP1050_PROC,POWER SEQUENCE,,IN,no,ADC,N,ANA,SOC,C2,C2,A14,ADC,ADC_PP1050_PROC,PP1050_PROC monitoring from FIVR output,
+SYS_RST_ODL,POWER SEQUENCE,Reset for SOC,OUT,,OD,N,3.30 V,SOC,H7,H7,P4,OUTPUT_ODR,,,
+EC_PCH_WAKE_ODL,POWER SEQUENCE,"Allows EC to wake AP (e.g., keyboard out of S0ix)",OUT,,OD,N,3.30 V,SOC,L11,L11,E1,OUTPUT_ODL,,EC_SOC_WAKE_ODL on schematic; software uses PCH_WAKE name,
+EC_SOC_RTCRST,POWER SEQUENCE,Allows EC to reset logic on the AP's RTC well,OUT,,TTL,N,3.30 V,SOC,J5,J5,R2,OUTPUT,,,
+VCCIN_AUX_VID0,POWER SEQUENCE,Debug purposes,IN,both,,N,1.80 V,,L8,L8,P2,INPUT,,,
+VCCIN_AUX_VID1,POWER SEQUENCE,Debug purposes,IN,both,,N,1.80 V,,L7,L7,R1,INPUT,,,
+PWM_KB_BL,PWM,Keyboard backlight PWM control signal,OUT,,PWM,N,3.30 V,,H8,H8,R6,PWM,,,
+PWM_LED_1_ODL,PWM,LED 1,OUT,,PWM,N,3.30 V,,G8,G8,P6,PWM_INVERT,,,
+PWM_LED_2_ODL,PWM,LED 2,OUT,,PWM,N,3.30 V,,G9,G9,R7,PWM_INVERT,,,
+PWM_LED_3_ODL,PWM,LED 3,OUT,,PWM,N,3.30 V,,H10,H10,P7,PWM_INVERT,,,
+EC_PSYS,PWM,System power monitoring output,OUT,,PWM,N,ANA,"Charger, IMVP9.1",G6,G6,E15,OTHER,,,
+EC_SOC_PWR_BTN_ODL,SOC,Buffered power button signal from EC to SOC,OUT,,OD,N,3.30 V,SOC,H9,H9,J5,OUTPUT_ODR,GPIO_PCH_PWRBTN_L,,
+EC_SOC_HDMI_HPD,SOC,HPD buffer output for HDMI,OUT,,TTL,N,3.30 V,,L6,L6,P15,OUTPUT,,,
+EC_PROCHOT_ODL,SOC,Allows us to send/read PROCHOT,I/O,both,OD,N,1.05 V,SOC,G3,G3,H14,OUTPUT_ODR,,,
+EC_PCHHOT_ODL,SOC,Allows us to send/read PCHHOT,,,,,,,#N/A,#N/A,#N/A,OTHER,,,Intel confirmed that this feature is not used.
+EC_SOC_INT_ODL,SOC,EC interrupt to SOC,OUT,,OD,N,,,K5,K5,P8,OUTPUT_ODR,GPIO_EC_INT_L,,Is this needed?
+UART_GSC_DBG_RX_EC_TX,UART,UART signal from EC to debugger,OUT,,TTL,N,3.30 V,,H4,H4,B4,OTHER,,,
+UART_GSC_DBG_TX_EC_RX,UART,UART signal from debugger to EC,IN,,--,N,3.30 V,,G4,G4,B5,OTHER,,,
+EN_PP5000_PEN_X,MISC,Enable signal for 5V PEN charging rail,OUT,,TTL,N,3.30 V,,A11,A11,G2,OUTPUT,,,
+PEN_DETECT_ODL,MISC,"PEN detect signal. Internal debouncing, if required.",IN,both,--,Y,3.30 V,,G12,G12,E14,INPUT_PU,,,
+USB_C0_CC1,USB-PD,CC1 for IT81302 only,I/O,,CC,PD,ANA,,#N/A,#N/A,E10,OTHER,,,
+USB_C0_CC2,USB-PD,CC2 for IT81302 only,I/O,,CC,PD,ANA,,#N/A,#N/A,A10,OTHER,,,
+USB_C0_FRS,USB-PD,FRS for IT81302 only,OUT,,TTL,N,3.30 V,,#N/A,#N/A,D1,OUTPUT,,,
+EN_USB_C0_CC1_VCONN,USB-PD,CC1 vconn en for IT81302 only,OUT,,TTL,N,3.30 V,,#N/A,#N/A,A9,OUTPUT,,,
+EN_USB_C0_CC2_VCONN,USB-PD,CC2 vconn en for IT81302 only,OUT,,TTL,N,3.30 V,,#N/A,#N/A,A8,OUTPUT,,,
+EC_TRIS_L,DEBUG,Debug for NPCX993,,,,,,,E4,E4,#N/A,OTHER,,,
+EC_TEST_L,DEBUG,Debug for NPCX994,,,,,,,K2,K2,#N/A,OTHER,,,
+EC_32KXOUT,DEBUG,Debug for NPCX995,,,,,,,M5,M5,#N/A,OTHER,,,
+EC_SHDF_ESPI_L,DEBUG,Debug for NPCX996,,,,,,,H3,H3,#N/A,OTHER,,,
\ No newline at end of file diff --git a/zephyr/projects/nissa/nivviks/cbi.dtsi b/zephyr/projects/nissa/nivviks/cbi.dtsi new file mode 100644 index 0000000000..112a2a885c --- /dev/null +++ b/zephyr/projects/nissa/nivviks/cbi.dtsi @@ -0,0 +1,30 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + /* Nivviks-specific fw_config fields. */ + nissa-fw-config { + /* + * FW_CONFIG field to describe mainboard orientation in chassis. + */ + base-inversion { + enum-name = "FW_BASE_INVERSION"; + start = <3>; + size = <1>; + + inverted { + compatible = "cros-ec,cbi-fw-config-value"; + enum-name = "FW_BASE_INVERTED"; + value = <0>; + }; + regular { + compatible = "cros-ec,cbi-fw-config-value"; + enum-name = "FW_BASE_REGULAR"; + value = <1>; + default; + }; + }; + }; +}; diff --git a/zephyr/projects/nissa/nivviks/generated.dtsi b/zephyr/projects/nissa/nivviks/generated.dtsi new file mode 100644 index 0000000000..91718302b4 --- /dev/null +++ b/zephyr/projects/nissa/nivviks/generated.dtsi @@ -0,0 +1,291 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + * + * This file is auto-generated - do not edit! + */ + +/ { + + named-adc-channels { + compatible = "named-adc-channels"; + + adc_ec_vsense_pp1050_proc: ec_vsense_pp1050_proc { + enum-name = "ADC_PP1050_PROC"; + io-channels = <&adc0 4>; + }; + adc_ec_vsense_pp3300_s5: ec_vsense_pp3300_s5 { + enum-name = "ADC_PP3300_S5"; + io-channels = <&adc0 6>; + }; + adc_temp_sensor_1: temp_sensor_1 { + enum-name = "ADC_TEMP_SENSOR_1"; + io-channels = <&adc0 0>; + }; + adc_temp_sensor_2: temp_sensor_2 { + enum-name = "ADC_TEMP_SENSOR_2"; + io-channels = <&adc0 1>; + }; + adc_temp_sensor_3: temp_sensor_3 { + enum-name = "ADC_TEMP_SENSOR_3"; + io-channels = <&adc0 10>; + }; + }; + + named-gpios { + compatible = "named-gpios"; + + gpio_acc_int_l: acc_int_l { + gpios = <&gpio5 0 GPIO_INPUT>; + }; + gpio_all_sys_pwrgd: all_sys_pwrgd { + gpios = <&gpioa 7 GPIO_INPUT>; + }; + gpio_ccd_mode_odl: ccd_mode_odl { + gpios = <&gpioe 5 GPIO_INPUT>; + enum-name = "GPIO_CCD_MODE_ODL"; + }; + gpio_cpu_c10_gate_l: cpu_c10_gate_l { + gpios = <&gpio6 7 GPIO_INPUT>; + }; + gpio_ec_battery_pres_odl: ec_battery_pres_odl { + gpios = <&gpioa 3 GPIO_INPUT>; + enum-name = "GPIO_BATT_PRES_ODL"; + }; + gpio_ec_cbi_wp: ec_cbi_wp { + gpios = <&gpio7 4 GPIO_OUTPUT>; + }; + gpio_ec_edp_bl_en_od: ec_edp_bl_en_od { + gpios = <&gpiod 3 GPIO_ODR_HIGH>; + enum-name = "GPIO_ENABLE_BACKLIGHT"; + }; + gpio_ec_entering_rw: ec_entering_rw { + gpios = <&gpio0 3 GPIO_OUTPUT>; + enum-name = "GPIO_ENTERING_RW"; + }; + gpio_ec_gsc_packet_mode: ec_gsc_packet_mode { + gpios = <&gpio7 5 GPIO_OUTPUT>; + enum-name = "GPIO_PACKET_MODE_EN"; + }; + gpio_ec_kso_02_inv: ec_kso_02_inv { + gpios = <&gpio1 7 (GPIO_OUTPUT_LOW | GPIO_ACTIVE_LOW)>; + }; + gpio_ec_pch_wake_odl: ec_pch_wake_odl { + gpios = <&gpiob 0 GPIO_ODR_LOW>; + }; + gpio_ec_prochot_odl: ec_prochot_odl { + gpios = <&gpiof 1 GPIO_ODR_HIGH>; + }; + gpio_ec_soc_dsw_pwrok: ec_soc_dsw_pwrok { + gpios = <&gpio6 1 GPIO_OUTPUT>; + }; + gpio_ec_soc_hdmi_hpd: ec_soc_hdmi_hpd { + gpios = <&gpioe 4 GPIO_OUTPUT>; + }; + gpio_ec_soc_int_odl: ec_soc_int_odl { + gpios = <&gpio8 0 GPIO_ODR_HIGH>; + enum-name = "GPIO_EC_INT_L"; + }; + gpio_ec_soc_pch_pwrok_od: ec_soc_pch_pwrok_od { + gpios = <&gpio7 2 GPIO_ODR_HIGH>; + }; + gpio_ec_soc_pwr_btn_odl: ec_soc_pwr_btn_odl { + gpios = <&gpioc 1 GPIO_ODR_HIGH>; + enum-name = "GPIO_PCH_PWRBTN_L"; + }; + gpio_ec_soc_rsmrst_l: ec_soc_rsmrst_l { + gpios = <&gpioa 6 GPIO_OUTPUT>; + }; + gpio_ec_soc_rtcrst: ec_soc_rtcrst { + gpios = <&gpio7 6 GPIO_OUTPUT>; + }; + gpio_ec_soc_sys_pwrok: ec_soc_sys_pwrok { + gpios = <&gpio3 7 GPIO_OUTPUT>; + }; + gpio_ec_soc_vccst_pwrgd_od: ec_soc_vccst_pwrgd_od { + gpios = <&gpioa 4 GPIO_ODR_HIGH>; + }; + gpio_ec_wp_odl: ec_wp_odl { + gpios = <&gpioa 1 (GPIO_INPUT | GPIO_ACTIVE_LOW)>; + }; + gpio_en_kb_bl: en_kb_bl { + gpios = <&gpioa 0 GPIO_OUTPUT>; + enum-name = "GPIO_EN_KEYBOARD_BACKLIGHT"; + }; + gpio_en_pp3300_s5: en_pp3300_s5 { + gpios = <&gpiob 6 GPIO_OUTPUT>; + enum-name = "GPIO_TEMP_SENSOR_POWER"; + }; + gpio_en_pp5000_pen_x: en_pp5000_pen_x { + gpios = <&gpioe 2 GPIO_OUTPUT>; + }; + gpio_en_pp5000_s5: en_pp5000_s5 { + gpios = <&gpio4 0 GPIO_OUTPUT>; + }; + gpio_en_slp_z: en_slp_z { + gpios = <&gpioe 1 GPIO_OUTPUT>; + }; + gpio_en_usb_a0_vbus: en_usb_a0_vbus { + gpios = <&gpio9 1 GPIO_OUTPUT>; + }; + gpio_gsc_ec_pwr_btn_odl: gsc_ec_pwr_btn_odl { + gpios = <&gpio0 0 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_POWER_BUTTON_L"; + }; + gpio_hdmi_sel: hdmi_sel { + gpios = <&gpioc 6 GPIO_OUTPUT>; + }; + gpio_imu_int_l: imu_int_l { + gpios = <&gpio5 6 GPIO_INPUT>; + }; + gpio_imvp91_vrrdy_od: imvp91_vrrdy_od { + gpios = <&gpio4 3 GPIO_INPUT>; + }; + gpio_lid_open: lid_open { + gpios = <&gpiod 2 GPIO_INPUT>; + enum-name = "GPIO_LID_OPEN"; + }; + gpio_pen_detect_odl: pen_detect_odl { + gpios = <&gpio9 6 GPIO_INPUT_PULL_UP>; + }; + gpio_pg_pp1050_mem_s3_od: pg_pp1050_mem_s3_od { + gpios = <&gpiof 0 GPIO_INPUT>; + }; + gpio_pg_pp5000_s5_od: pg_pp5000_s5_od { + gpios = <&gpio4 2 GPIO_INPUT>; + }; + gpio_rsmrst_pwrgd_l: rsmrst_pwrgd_l { + gpios = <&gpio9 4 GPIO_INPUT_PULL_UP>; + }; + gpio_slp_s0_l: slp_s0_l { + gpios = <&gpio9 7 GPIO_INPUT>; + }; + gpio_slp_s3_l: slp_s3_l { + gpios = <&gpioa 5 GPIO_INPUT>; + }; + gpio_slp_s4_l: slp_s4_l { + gpios = <&gpio7 0 GPIO_INPUT>; + }; + gpio_slp_sus_l: slp_sus_l { + gpios = <&gpio6 2 GPIO_INPUT>; + }; + gpio_sub_usb_a1_ilimit_sdp: sub_usb_a1_ilimit_sdp { + gpios = <&gpiod 5 GPIO_OUTPUT>; + enum-name = "GPIO_USB2_ILIM_SEL"; + }; + gpio_sys_rst_odl: sys_rst_odl { + gpios = <&gpioc 5 GPIO_ODR_HIGH>; + }; + gpio_tablet_mode_l: tablet_mode_l { + gpios = <&gpio9 5 GPIO_INPUT>; + enum-name = "GPIO_TABLET_MODE_L"; + }; + gpio_usb_a0_ilimit_sdp: usb_a0_ilimit_sdp { + gpios = <&gpio8 5 GPIO_OUTPUT>; + enum-name = "GPIO_USB1_ILIM_SEL"; + }; + gpio_usb_c0_int_odl: usb_c0_int_odl { + gpios = <&gpio0 1 GPIO_INPUT_PULL_UP>; + }; + gpio_vccin_aux_vid0: vccin_aux_vid0 { + gpios = <&gpio9 2 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; + }; + gpio_vccin_aux_vid1: vccin_aux_vid1 { + gpios = <&gpioe 3 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; + }; + gpio_voldn_btn_odl: voldn_btn_odl { + gpios = <&gpioa 2 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_VOLUME_DOWN_L"; + }; + gpio_volup_btn_odl: volup_btn_odl { + gpios = <&gpio9 3 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_VOLUME_UP_L"; + }; + }; + + named-i2c-ports { + compatible = "named-i2c-ports"; + + i2c_ec_i2c_eeprom: ec_i2c_eeprom { + i2c-port = <&i2c0_0>; + enum-names = "I2C_PORT_EEPROM"; + }; + i2c_ec_i2c_sensor: ec_i2c_sensor { + i2c-port = <&i2c1_0>; + enum-names = "I2C_PORT_SENSOR"; + }; + i2c_ec_i2c_usb_c0: ec_i2c_usb_c0 { + i2c-port = <&i2c3_0>; + enum-names = "I2C_PORT_USB_C0_TCPC"; + }; + i2c_ec_i2c_sub_usb_c1: ec_i2c_sub_usb_c1 { + i2c-port = <&i2c5_1>; + enum-names = "I2C_PORT_USB_C1_TCPC"; + }; + i2c_ec_i2c_batt: ec_i2c_batt { + i2c-port = <&i2c7_0>; + enum-names = "I2C_PORT_BATTERY"; + }; + }; +}; + +&adc0 { + status = "okay"; + pinctrl-0 = <&adc0_chan0_gp45 + &adc0_chan1_gp44 + &adc0_chan4_gp41 + &adc0_chan6_gp34 + &adc0_chan10_gpe0>; + pinctrl-names = "default"; +}; + + +&i2c0_0 { + status = "okay"; + pinctrl-0 = <&i2c0_0_sda_scl_gpb4_b5>; + pinctrl-names = "default"; +}; + +&i2c1_0 { + status = "okay"; + pinctrl-0 = <&i2c1_0_sda_scl_gp87_90>; + pinctrl-names = "default"; +}; + +&i2c3_0 { + status = "okay"; + pinctrl-0 = <&i2c3_0_sda_scl_gpd0_d1>; + pinctrl-names = "default"; +}; + +&i2c5_1 { + status = "okay"; + pinctrl-0 = <&i2c5_1_sda_scl_gpf4_f5>; + pinctrl-names = "default"; +}; + +&i2c7_0 { + status = "okay"; + pinctrl-0 = <&i2c7_0_sda_scl_gpb2_b3>; + pinctrl-names = "default"; +}; + +&i2c_ctrl0 { + status = "okay"; +}; + +&i2c_ctrl1 { + status = "okay"; +}; + +&i2c_ctrl3 { + status = "okay"; +}; + +&i2c_ctrl5 { + status = "okay"; +}; + +&i2c_ctrl7 { + status = "okay"; +}; diff --git a/zephyr/projects/nissa/nivviks/keyboard.dtsi b/zephyr/projects/nissa/nivviks/keyboard.dtsi new file mode 100644 index 0000000000..00610e4e18 --- /dev/null +++ b/zephyr/projects/nissa/nivviks/keyboard.dtsi @@ -0,0 +1,48 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + kblight { + compatible = "cros-ec,kblight-pwm"; + pwms = <&pwm6 6 PWM_HZ(2400) PWM_POLARITY_NORMAL>; + }; +}; + +&pwm6 { + status = "okay"; + clock-bus = "NPCX_CLOCK_BUS_LFCLK"; + pinctrl-0 = <&pwm6_gpc0>; + pinctrl-names = "default"; +}; + +&cros_kb_raw { + status = "okay"; + /* No KSO2 (it's inverted and implemented by GPIO) */ + pinctrl-0 = < + &ksi0_gp31 + &ksi1_gp30 + &ksi2_gp27 + &ksi3_gp26 + &ksi4_gp25 + &ksi5_gp24 + &ksi6_gp23 + &ksi7_gp22 + &kso00_gp21 + &kso01_gp20 + &kso03_gp16 + &kso04_gp15 + &kso05_gp14 + &kso06_gp13 + &kso07_gp12 + &kso08_gp11 + &kso09_gp10 + &kso10_gp07 + &kso11_gp06 + &kso12_gp05 + &kso13_gp04 + &kso14_gp82 + >; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/nissa/nivviks/motionsense.dtsi b/zephyr/projects/nissa/nivviks/motionsense.dtsi new file mode 100644 index 0000000000..6297a07bf5 --- /dev/null +++ b/zephyr/projects/nissa/nivviks/motionsense.dtsi @@ -0,0 +1,166 @@ +/* Copyright 2021 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <dt-bindings/motionsense/utils.h> + + +/ { + aliases { + /* + * Interrupt bindings for sensor devices. + */ + lsm6dso-int = &base_accel; + lis2dw12-int = &lid_accel; + }; + + /* + * Declare mutexes used by sensor drivers. + * A mutex node is used to create an instance of mutex_t. + * A mutex node is referenced by a sensor node if the + * corresponding sensor driver needs to use the + * instance of the mutex. + */ + motionsense-mutex { + compatible = "cros-ec,motionsense-mutex"; + lid_mutex: lid-mutex { + }; + + base_mutex: base-mutex { + }; + }; + + /* Rotation matrix used by drivers. */ + motionsense-rotation-ref { + compatible = "cros-ec,motionsense-rotation-ref"; + lid_rot_ref: lid-rotation-ref { + mat33 = <(-1) 0 0 + 0 1 0 + 0 0 (-1)>; + }; + + base_rot_ref: base-rot-ref { + mat33 = <(-1) 0 0 + 0 (-1) 0 + 0 0 1>; + }; + + base_rot_inverted: base-rotation-inverted { + mat33 = <1 0 0 + 0 (-1) 0 + 0 0 (-1)>; + }; + }; + + /* + * Driver specific data. A driver-specific data can be shared with + * different motion sensors while they are using the same driver. + * + * If a node's compatible starts with "cros-ec,accelgyro-", it is for + * a common structure defined in accelgyro.h. + * e.g) compatible = "cros-ec,accelgyro-als-drv-data" is for + * "struct als_drv_data_t" in accelgyro.h + */ + motionsense-sensor-data { + lsm6dso_accel_data: lsm6dso-accel-drv-data { + compatible = "cros-ec,drvdata-lsm6dso"; + status = "okay"; + }; + + lsm6dso_gyro_data: lsm6dso-gyro-drv-data { + compatible = "cros-ec,drvdata-lsm6dso"; + status = "okay"; + }; + + lis2dw12_data: lis2dw12-drv-data { + compatible = "cros-ec,drvdata-lis2dw12"; + status = "okay"; + }; + }; + + /* + * List of motion sensors that creates motion_sensors array. + * The nodelabel "lid_accel" and "base_accel" are used to indicate + * motion sensor IDs for lid angle calculation. + * TODO(b/238139272): The first entries of the array must be + * accelerometers,then gyroscope. Fix this dependency in the DTS + * processing which makes the devicetree entries independent. + */ + motionsense-sensor { + lid_accel: lid-accel { + compatible = "cros-ec,lis2dw12"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_LID"; + mutex = <&lid_mutex>; + port = <&i2c_ec_i2c_sensor>; + rot-standard-ref = <&lid_rot_ref>; + default-range = <2>; + drv-data = <&lis2dw12_data>; + i2c-spi-addr-flags = "LIS2DWL_ADDR0_FLAGS"; + configs { + compatible = + "cros-ec,motionsense-sensor-config"; + ec-s0 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + ec-s3 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + }; + }; + + base_accel: base-accel { + compatible = "cros-ec,lsm6dso-accel"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_BASE"; + mutex = <&base_mutex>; + port = <&i2c_ec_i2c_sensor>; + /* + * May be replaced by alternate depending + * on board config. + */ + rot-standard-ref = <&base_rot_ref>; + drv-data = <&lsm6dso_accel_data>; + configs { + compatible = + "cros-ec,motionsense-sensor-config"; + ec-s0 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + ec-s3 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + }; + }; + + base_gyro: base-gyro { + compatible = "cros-ec,lsm6dso-gyro"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_BASE"; + mutex = <&base_mutex>; + port = <&i2c_ec_i2c_sensor>; + rot-standard-ref = <&base_rot_ref>; + default-range = <(1000 | ROUND_UP_FLAG)>; /* dps */ + drv-data = <&lsm6dso_gyro_data>; + }; + }; + + motionsense-sensor-info { + compatible = "cros-ec,motionsense-sensor-info"; + + /* + * list of GPIO interrupts that have to + * be enabled at initial stage + */ + sensor-irqs = <&int_imu>; + /* list of sensors in force mode */ + accel-force-mode-sensors = <&lid_accel>; + }; +}; diff --git a/zephyr/projects/nissa/nivviks/overlay.dtsi b/zephyr/projects/nissa/nivviks/overlay.dtsi new file mode 100644 index 0000000000..c2d5e3f24b --- /dev/null +++ b/zephyr/projects/nissa/nivviks/overlay.dtsi @@ -0,0 +1,418 @@ +/* Copyright 2021 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <cros/thermistor/thermistor.dtsi> + +/ { + aliases { + gpio-cbi-wp = &gpio_ec_cbi_wp; + gpio-wp = &gpio_ec_wp_odl; + int-wp = &int_wp_l; + gpio-kbd-kso2 = &gpio_ec_kso_02_inv; + }; + + ec-console { + compatible = "ec-console"; + disabled = "events", "lpc", "hostcmd"; + }; + + batteries { + default_battery: lgc { + compatible = "lgc,ap18c8k", "battery-smart"; + }; + lgc_ap19b8m { + compatible = "lgc,ap19b8m", "battery-smart"; + }; + }; + + hibernate-wake-pins { + compatible = "cros-ec,hibernate-wake-pins"; + wakeup-irqs = < + &int_power_button + &int_lid_open + >; + }; + + gpio-interrupts { + compatible = "cros-ec,gpio-interrupts"; + + int_power_button: power_button { + irq-pin = <&gpio_gsc_ec_pwr_btn_odl>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "power_button_interrupt"; + }; + int_wp_l: wp_l { + irq-pin = <&gpio_ec_wp_odl>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "switch_interrupt"; + }; + int_lid_open: lid_open { + irq-pin = <&gpio_lid_open>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "lid_interrupt"; + }; + int_tablet_mode: tablet_mode { + irq-pin = <&gpio_tablet_mode_l>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "gmr_tablet_switch_isr"; + }; + int_imu: ec_imu { + irq-pin = <&gpio_imu_int_l>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "lsm6dso_interrupt"; + }; + int_vol_down: vol_down { + irq-pin = <&gpio_voldn_btn_odl>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "button_interrupt"; + }; + int_vol_up: vol_up { + irq-pin = <&gpio_volup_btn_odl>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "button_interrupt"; + }; + int_usb_c0: usb_c0 { + irq-pin = <&gpio_usb_c0_int_odl>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "usb_interrupt"; + }; + int_usb_c1: usb_c1 { + irq-pin = <&gpio_sb_1>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "usb_interrupt"; + }; + }; + + named-gpios { + gpio_sb_1: sb-1 { + gpios = <&gpio0 2 GPIO_PULL_UP>; + no-auto-init; + }; + + gpio_sb_2: sb-2 { + gpios = <&gpiod 4 GPIO_OUTPUT>; + no-auto-init; + }; + + /* + * Set I2C pins for type C sub-board to be low voltage (I2C5_1). + * We do this for all boards, since the pins are 3.3V tolerant, + * and the only 2 types of sub-boards used on nivviks both have + * type-C ports on them. + */ + gpio_sb_3: sb-3 { + gpios = <&gpiof 4 (GPIO_OPEN_DRAIN | GPIO_VOLTAGE_1P8)>; + no-auto-init; + }; + gpio_sb_4: sb-4 { + gpios = <&gpiof 5 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; + no-auto-init; + }; + gpio_fan_enable: fan-enable { + gpios = <&gpio6 3 GPIO_OUTPUT>; + no-auto-init; + }; + ec-i2c-sensor-scl { + gpios = <&gpio9 0 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; + }; + ec-i2c-sensor-sda { + gpios = <&gpio8 7 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; + }; + }; + + /* + * Aliases used for sub-board GPIOs. + */ + aliases { + /* + * Input GPIO when used with type-C port 1 + * Output when used with HDMI sub-board + */ + gpio-usb-c1-int-odl = &gpio_sb_1; + gpio-en-rails-odl = &gpio_sb_1; + /* + * Sub-board with type A USB, enable. + */ + gpio-en-usb-a1-vbus = &gpio_sb_2; + /* + * HPD pins for HDMI sub-board. + */ + gpio-hdmi-en-odl = &gpio_sb_3; + gpio-hpd-odl = &gpio_sb_4; + /* + * Enable S5 rails for LTE sub-board + */ + gpio-en-sub-s5-rails = &gpio_sb_2; + }; + + temp_memory: memory { + compatible = "cros-ec,temp-sensor-thermistor"; + thermistor = <&thermistor_3V3_51K1_47K_4050B>; + adc = <&adc_temp_sensor_1>; + }; + temp_charger: charger { + compatible = "cros-ec,temp-sensor-thermistor"; + thermistor = <&thermistor_3V3_51K1_47K_4050B>; + adc = <&adc_temp_sensor_2>; + }; + temp_ambient: ambient { + compatible = "cros-ec,temp-sensor-thermistor"; + thermistor = <&thermistor_3V3_51K1_47K_4050B>; + adc = <&adc_temp_sensor_3>; + }; + + named-temp-sensors { + compatible = "cros-ec,temp-sensors"; + memory { + temp_fan_off = <35>; + temp_fan_max = <60>; + temp_host_high = <85>; + temp_host_halt = <90>; + temp_host_release_high = <80>; + power-good-pin = <&gpio_ec_soc_dsw_pwrok>; + sensor = <&temp_memory>; + }; + charger { + temp_fan_off = <35>; + temp_fan_max = <60>; + temp_host_high = <85>; + temp_host_halt = <90>; + temp_host_release_high = <80>; + power-good-pin = <&gpio_ec_soc_dsw_pwrok>; + sensor = <&temp_charger>; + }; + ambient { + temp_fan_off = <35>; + temp_fan_max = <60>; + temp_host_high = <85>; + temp_host_halt = <90>; + temp_host_release_high = <80>; + power-good-pin = <&gpio_ec_soc_dsw_pwrok>; + sensor = <&temp_ambient>; + }; + }; + + usba { + compatible = "cros-ec,usba-port-enable-pins"; + /* + * sb_2 is only configured as GPIO when USB-A1 is present, + * but it's still safe to control when disabled. + * + * ILIM_SEL pins are referred to by legacy enum name, + * GPIO_USB*_ILIM_SEL. The one for port A1 is unused on + * sub-boards that don't have USB-A so is safe to control + * regardless of system configuration. + */ + enable-pins = <&gpio_en_usb_a0_vbus &gpio_sb_2>; + status = "okay"; + }; + + usbc { + #address-cells = <1>; + #size-cells = <0>; + + port0@0 { + compatible = "named-usbc-port"; + reg = <0>; + bc12 = <&bc12_port0>; + chg = <&chg_port0>; + usb-mux-chain-0 { + compatible = "cros-ec,usb-mux-chain"; + usb-muxes = <&virtual_mux_0>; + }; + }; + port0-muxes { + virtual_mux_0: virtual-mux-0 { + compatible = "cros-ec,usbc-mux-virtual"; + }; + }; + /* + * TODO(b:211693800): port1 may not be present on some + * sub-boards. + */ + port1@1 { + compatible = "named-usbc-port"; + reg = <1>; + bc12 = <&bc12_port1>; + chg = <&chg_port1>; + usb-mux-chain-1 { + compatible = "cros-ec,usb-mux-chain"; + usb-muxes = <&virtual_mux_1 &anx7483_mux_1>; + }; + usb_mux_chain_1_no_mux: usb-mux-chain-1-no-mux { + compatible = "cros-ec,usb-mux-chain"; + alternative-chain; + usb-muxes = <&virtual_mux_1>; + }; + }; + port1-muxes { + virtual_mux_1: virtual-mux-1 { + compatible = "cros-ec,usbc-mux-virtual"; + }; + }; + }; + + fans { + compatible = "cros-ec,fans"; + + fan_0 { + pwms = <&pwm5 5 PWM_KHZ(1) PWM_POLARITY_NORMAL>; + rpm_min = <2200>; + rpm_start = <2200>; + rpm_max = <4200>; + tach = <&tach2>; + enable_gpio = <&gpio_fan_enable>; + }; + }; + + /* + * Declare unused GPIOs so that they are shut down + * and use minimal power + */ + unused-pins { + compatible = "unused-gpios"; + unused-gpios = + <&gpio3 2 0>, + <&gpio3 3 0>, + <&gpio3 5 0>, + <&gpio3 6 0>, + <&gpio5 7 0>, + <&gpio6 0 0>, + <&gpio6 3 0>, + <&gpio6 6 0>, + <&gpio7 3 0>, + <&gpio8 3 0>, + <&gpio8 6 0>, + <&gpiob 1 0>, + <&gpiob 7 0>, + <&gpioc 7 0>, + <&gpiof 2 0>, + <&gpiof 3 0>; + }; +}; + +&thermistor_3V3_51K1_47K_4050B { + status = "okay"; +}; + +&adc_ec_vsense_pp3300_s5 { + /* + * Voltage divider on input has 47k upper and 220k lower legs with + * 2714 mV full-scale reading on the ADC. Apply the largest possible + * multiplier (without overflowing int32) to get the best possible + * approximation of the actual ratio, but derate by a factor of two to + * ensure unexpectedly high values won't overflow. + */ + mul = <(791261 / 2)>; + div = <(651975 / 2)>; +}; + +/* Set bus speeds for I2C */ +&i2c0_0 { + label = "I2C_EEPROM"; + clock-frequency = <I2C_BITRATE_FAST>; + + cbi_eeprom: eeprom@50 { + compatible = "atmel,at24"; + reg = <0x50>; + size = <2048>; + pagesize = <16>; + address-width = <8>; + timeout = <5>; + }; +}; + +&i2c1_0 { + label = "I2C_SENSOR"; + clock-frequency = <I2C_BITRATE_FAST>; +}; + +&i2c3_0 { + label = "I2C_USB_C0_TCPC"; + clock-frequency = <I2C_BITRATE_FAST_PLUS>; + + bc12_port0: pi3usb9201@5f { + compatible = "pericom,pi3usb9201"; + status = "okay"; + reg = <0x5f>; + /* + * BC1.2 interrupt is shared with TCPC, so + * IRQ is not specified here and handled by + * usb_c0_interrupt. + */ + }; + + chg_port0: isl923x@9 { + compatible = "intersil,isl923x"; + status = "okay"; + reg = <0x9>; + }; +}; + +&i2c5_1 { + label = "I2C_SUB_C1_TCPC"; + clock-frequency = <I2C_BITRATE_FAST_PLUS>; + + bc12_port1: pi3usb9201@5f { + compatible = "pericom,pi3usb9201"; + status = "okay"; + reg = <0x5f>; + }; + + chg_port1: isl923x@9 { + compatible = "intersil,isl923x"; + status = "okay"; + reg = <0x9>; + }; + + anx7483_mux_1: anx7483-mux-1@3e { + compatible = "analogix,anx7483"; + reg = <0x3e>; + board-set = "anx7483_set_default_tuning"; + }; +}; + +&i2c7_0 { + label = "I2C_BATTERY"; + clock-frequency = <I2C_BITRATE_STANDARD>; +}; + +&pwm5_gpb7 { + drive-open-drain; +}; + +&pwm5 { + status = "okay"; + clock-bus = "NPCX_CLOCK_BUS_LFCLK"; + pinctrl-0 = <&pwm5_gpb7>; + pinctrl-names = "default"; +}; + +/* Tachometer for fan speed measurement */ +&tach2 { + status = "okay"; + pinctrl-0 = <&ta2_1_in_gp73>; + pinctrl-names = "default"; + port = <NPCX_TACH_PORT_A>; /* port-A is selected */ + sample-clk = <NPCX_TACH_FREQ_LFCLK>; /* Use LFCLK as sampling clock */ + pulses-per-round = <2>; /* number of pulses per round of encoder */ +}; + +/* host interface */ +&espi0 { + status = "okay"; + pinctrl-0 = <&espi_lpc_gp46_47_51_52_53_54_55_57>; + pinctrl-names = "default"; +}; + +/* + * Declare GPIOs that have leakage current caused by board issues here. NPCX ec + * will disable their input buffers before entering deep sleep and restore them + * after waking up automatically for better power consumption. + */ +&power_leakage_io { + leak-gpios = <&gpioa 4 0 + &gpiof 1 0>; +}; diff --git a/zephyr/projects/nissa/nivviks/power_signals.dtsi b/zephyr/projects/nissa/nivviks/power_signals.dtsi new file mode 100644 index 0000000000..1d2b23069d --- /dev/null +++ b/zephyr/projects/nissa/nivviks/power_signals.dtsi @@ -0,0 +1,220 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + chosen { + intel-ap-pwrseq,espi = &espi0; + }; + + common-pwrseq { + compatible = "intel,ap-pwrseq"; + + sys-pwrok-delay = <10>; + all-sys-pwrgd-timeout = <20>; + }; + + pwr-en-pp5000-s5 { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "PP5000_S5 enable output to regulator"; + enum-name = "PWR_EN_PP5000_A"; + gpios = <&gpio4 0 0>; + output; + }; + pwr-en-pp3300-s5 { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "PP3300_S5 enable output to LS"; + enum-name = "PWR_EN_PP3300_A"; + gpios = <&gpiob 6 0>; + output; + }; + pwr-pg-ec-rsmrst-od { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "RSMRST power good from regulator"; + enum-name = "PWR_RSMRST"; + gpios = <&gpio9 4 0>; + interrupt-flags = <GPIO_INT_EDGE_BOTH>; + }; + pwr-ec-pch-rsmrst-odl { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "RSMRST output to PCH"; + enum-name = "PWR_EC_PCH_RSMRST"; + gpios = <&gpioa 6 0>; + output; + }; + pwr-slp-s0-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SLP_S0_L input from PCH"; + enum-name = "PWR_SLP_S0"; + gpios = <&gpio9 7 GPIO_ACTIVE_LOW>; + interrupt-flags = <GPIO_INT_EDGE_BOTH>; + }; + pwr-slp-s3-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SLP_S3_L input from PCH"; + enum-name = "PWR_SLP_S3"; + gpios = <&gpioa 5 GPIO_ACTIVE_LOW>; + interrupt-flags = <GPIO_INT_EDGE_BOTH>; + }; + pwr-slp-sus-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SLP_SUS_L input from PCH"; + enum-name = "PWR_SLP_SUS"; + gpios = <&gpio6 2 GPIO_ACTIVE_LOW>; + interrupt-flags = <GPIO_INT_EDGE_BOTH>; + }; + pwr-ec-soc-dsw-pwrok { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "DSW_PWROK output to PCH"; + enum-name = "PWR_EC_SOC_DSW_PWROK"; + gpios = <&gpio6 1 0>; + output; + }; + pwr-vccst-pwrgd-od { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "VCCST_PWRGD output to PCH"; + enum-name = "PWR_VCCST_PWRGD"; + gpios = <&gpioa 4 GPIO_OPEN_DRAIN>; + output; + }; + pwr-imvp9-vrrdy-od { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "VRRDY input from IMVP9"; + enum-name = "PWR_IMVP9_VRRDY"; + gpios = <&gpio4 3 0>; + }; + pwr-pch-pwrok { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "PCH_PWROK output to PCH"; + enum-name = "PWR_PCH_PWROK"; + gpios = <&gpio7 2 GPIO_OPEN_DRAIN>; + output; + }; + pwr-ec-pch-sys-pwrok { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SYS_PWROK output to PCH"; + enum-name = "PWR_EC_PCH_SYS_PWROK"; + gpios = <&gpio3 7 0>; + output; + }; + pwr-sys-rst-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SYS_RESET# output to PCH"; + enum-name = "PWR_SYS_RST"; + gpios = <&gpioc 5 (GPIO_ACTIVE_LOW|GPIO_OPEN_DRAIN)>; + output; + }; + pwr-slp-s4 { + compatible = "intel,ap-pwrseq-vw"; + dbg-label = "SLP_S4 virtual wire input from PCH"; + enum-name = "PWR_SLP_S4"; + virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S4"; + vw-invert; + }; + pwr-slp-s5 { + compatible = "intel,ap-pwrseq-vw"; + dbg-label = "SLP_S5 virtual wire input from PCH"; + enum-name = "PWR_SLP_S5"; + virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S5"; + vw-invert; + }; + pwr-all-sys-pwrgd { + compatible = "intel,ap-pwrseq-external"; + dbg-label = "Combined all power good"; + enum-name = "PWR_ALL_SYS_PWRGD"; + }; + pwr-adc-pp3300 { + compatible = "intel,ap-pwrseq-adc"; + dbg-label = "PP3300 PWROK (from ADC)"; + enum-name = "PWR_DSW_PWROK"; + trigger-high = <&cmp_pp3300_s5_high>; + trigger-low = <&cmp_pp3300_s5_low>; + }; + pwr-adc-pp1p05 { + compatible = "intel,ap-pwrseq-adc"; + dbg-label = "PP1P05 PWROK (from ADC)"; + enum-name = "PWR_PG_PP1P05"; + trigger-high = <&cmp_pp1p05_high>; + trigger-low = <&cmp_pp1p05_low>; + }; + + adc-cmp { + cmp_pp3300_s5_high: pp3300_high { + compatible = "nuvoton,adc-cmp"; + io-channels = <&adc0 6>; + comparison = "ADC_CMP_NPCX_GREATER"; + /* + * This is 90% of nominal voltage considering voltage + * divider on ADC input. + */ + threshold-mv = <2448>; + }; + cmp_pp3300_s5_low: pp3300_low { + compatible = "nuvoton,adc-cmp"; + io-channels = <&adc0 6>; + comparison = "ADC_CMP_NPCX_LESS_OR_EQUAL"; + threshold-mv = <2448>; + }; + cmp_pp1p05_high: pp1p05_high { + compatible = "nuvoton,adc-cmp"; + io-channels = <&adc0 4>; + comparison = "ADC_CMP_NPCX_GREATER"; + /* Setting at 90% of nominal voltage */ + threshold-mv = <945>; + }; + cmp_pp1p05_low: pp1p05_low { + compatible = "nuvoton,adc-cmp"; + io-channels = <&adc0 4>; + comparison = "ADC_CMP_NPCX_LESS_OR_EQUAL"; + threshold-mv = <945>; + }; + }; +}; + +/* + * Because the power signals directly reference the GPIOs, + * the correspinding named-gpios need to have no-auto-init set. + */ +&gpio_ec_soc_dsw_pwrok { + no-auto-init; +}; +&gpio_ec_soc_pch_pwrok_od { + no-auto-init; +}; +&gpio_ec_soc_rsmrst_l { + no-auto-init; +}; +&gpio_ec_soc_sys_pwrok { + no-auto-init; +}; +&gpio_ec_soc_vccst_pwrgd_od { + no-auto-init; +}; +&gpio_en_pp3300_s5 { + no-auto-init; +}; +&gpio_en_pp5000_s5 { + no-auto-init; +}; +&gpio_imvp91_vrrdy_od { + no-auto-init; +}; +&gpio_rsmrst_pwrgd_l { + no-auto-init; +}; +&gpio_slp_s0_l { + no-auto-init; +}; +&gpio_slp_s3_l { + no-auto-init; +}; +&gpio_slp_s4_l { + no-auto-init; +}; +&gpio_slp_sus_l { + no-auto-init; +}; +&gpio_sys_rst_odl { + no-auto-init; +}; diff --git a/zephyr/projects/nissa/nivviks/project.conf b/zephyr/projects/nissa/nivviks/project.conf new file mode 100644 index 0000000000..af9e4e2586 --- /dev/null +++ b/zephyr/projects/nissa/nivviks/project.conf @@ -0,0 +1,8 @@ +# Copyright 2021 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +CONFIG_BOARD_NIVVIKS=y +CONFIG_PLATFORM_EC_OCPC=y + +CONFIG_PLATFORM_EC_ACCELGYRO_LSM6DSO=y diff --git a/zephyr/projects/nissa/nivviks/project.overlay b/zephyr/projects/nissa/nivviks/project.overlay new file mode 100644 index 0000000000..9ca681d979 --- /dev/null +++ b/zephyr/projects/nissa/nivviks/project.overlay @@ -0,0 +1,14 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "../cbi.dtsi" + +#include "cbi.dtsi" +#include "generated.dtsi" +#include "keyboard.dtsi" +#include "motionsense.dtsi" +#include "overlay.dtsi" +#include "power_signals.dtsi" +#include "pwm_leds.dtsi" diff --git a/zephyr/projects/nissa/nivviks/pwm_leds.dtsi b/zephyr/projects/nissa/nivviks/pwm_leds.dtsi new file mode 100644 index 0000000000..a265a5929e --- /dev/null +++ b/zephyr/projects/nissa/nivviks/pwm_leds.dtsi @@ -0,0 +1,62 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + pwmleds { + compatible = "pwm-leds"; + pwm_led0: pwm_led_0 { + pwms = <&pwm2 2 PWM_HZ(324) PWM_POLARITY_INVERTED>, + <&pwm0 0 PWM_HZ(324) PWM_POLARITY_INVERTED>, + <&pwm1 1 PWM_HZ(324) PWM_POLARITY_INVERTED>; + }; + }; + + cros-pwmleds { + compatible = "cros-ec,pwm-leds"; + + leds = <&pwm_led0>; + + /*<red green blue>*/ + color-map-red = <100 0 0>; + color-map-green = < 0 100 0>; + color-map-blue = < 0 0 100>; + color-map-yellow = < 0 50 50>; + color-map-white = <100 100 100>; + color-map-amber = <100 0 0>; + + brightness-range = <0 0 100 0 0 100>; + + #address-cells = <1>; + #size-cells = <0>; + + pwm_led_0@0 { + reg = <0>; + ec-led-name = "EC_LED_ID_BATTERY_LED"; + }; + }; +}; + +/* Enable LEDs to work while CPU suspended */ + +&pwm0 { + status = "okay"; + clock-bus = "NPCX_CLOCK_BUS_LFCLK"; + pinctrl-0 = <&pwm0_gpc3>; + pinctrl-names = "default"; +}; + +&pwm1 { + status = "okay"; + clock-bus = "NPCX_CLOCK_BUS_LFCLK"; + pinctrl-0 = <&pwm1_gpc2>; + pinctrl-names = "default"; +}; + +&pwm2 { + status = "okay"; + clock-bus = "NPCX_CLOCK_BUS_LFCLK"; + pinctrl-0 = <&pwm2_gpc4>; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/nissa/nivviks/src/charger.c b/zephyr/projects/nissa/nivviks/src/charger.c new file mode 100644 index 0000000000..e2f9f966e7 --- /dev/null +++ b/zephyr/projects/nissa/nivviks/src/charger.c @@ -0,0 +1,56 @@ +/* Copyright 2021 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <zephyr/logging/log.h> + +#include "battery.h" +#include "charger.h" +#include "charger/isl923x_public.h" +#include "console.h" +#include "extpower.h" +#include "usb_pd.h" +#include "nissa_common.h" + +LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL); + +int extpower_is_present(void) +{ + int port; + int rv; + bool acok; + + for (port = 0; port < board_get_usb_pd_port_count(); port++) { + rv = raa489000_is_acok(port, &acok); + if ((rv == EC_SUCCESS) && acok) + return 1; + } + + return 0; +} + +/* + * Nivviks does not have a GPIO indicating whether extpower is present, + * so detect using the charger(s). + */ +__override void board_check_extpower(void) +{ + static int last_extpower_present; + int extpower_present = extpower_is_present(); + + if (last_extpower_present ^ extpower_present) + extpower_handle_update(extpower_present); + + last_extpower_present = extpower_present; +} + +__override void board_hibernate(void) +{ + /* Shut down the chargers */ + if (board_get_usb_pd_port_count() == 2) + raa489000_hibernate(CHARGER_SECONDARY, true); + raa489000_hibernate(CHARGER_PRIMARY, true); + LOG_INF("Charger(s) hibernated"); + cflush(); +} diff --git a/zephyr/projects/nissa/nivviks/src/fan.c b/zephyr/projects/nissa/nivviks/src/fan.c new file mode 100644 index 0000000000..840049722c --- /dev/null +++ b/zephyr/projects/nissa/nivviks/src/fan.c @@ -0,0 +1,43 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <zephyr/devicetree.h> +#include <zephyr/drivers/gpio.h> +#include <zephyr/logging/log.h> + +#include "cros_cbi.h" +#include "fan.h" +#include "gpio/gpio.h" +#include "hooks.h" + +#include "nissa_common.h" + +LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL); + +/* + * Nirwen fan support + */ +static void fan_init(void) +{ + int ret; + uint32_t val; + /* + * Retrieve the fan config. + */ + ret = cros_cbi_get_fw_config(FW_FAN, &val); + if (ret != 0) { + LOG_ERR("Error retrieving CBI FW_CONFIG field %d", FW_FAN); + return; + } + if (val != FW_FAN_PRESENT) { + /* Disable the fan */ + fan_set_count(0); + } else { + /* Configure the fan enable GPIO */ + gpio_pin_configure_dt(GPIO_DT_FROM_NODELABEL(gpio_fan_enable), + GPIO_OUTPUT); + } +} +DECLARE_HOOK(HOOK_INIT, fan_init, HOOK_PRIO_POST_FIRST); diff --git a/zephyr/projects/nissa/nivviks/src/form_factor.c b/zephyr/projects/nissa/nivviks/src/form_factor.c new file mode 100644 index 0000000000..602b22baff --- /dev/null +++ b/zephyr/projects/nissa/nivviks/src/form_factor.c @@ -0,0 +1,47 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <zephyr/devicetree.h> +#include <zephyr/logging/log.h> + +#include "accelgyro.h" +#include "cros_cbi.h" +#include "hooks.h" +#include "motionsense_sensors.h" + +#include "nissa_common.h" + +LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL); + +/* + * Mainboard orientation support. + */ + +#define ALT_MAT SENSOR_ROT_STD_REF_NAME(DT_NODELABEL(base_rot_inverted)) +#define BASE_SENSOR SENSOR_ID(DT_NODELABEL(base_accel)) +#define BASE_GYRO SENSOR_ID(DT_NODELABEL(base_gyro)) + +static void form_factor_init(void) +{ + int ret; + uint32_t val; + /* + * If the firmware config indicates + * an inverted form factor, use the alternative + * rotation matrix. + */ + ret = cros_cbi_get_fw_config(FW_BASE_INVERSION, &val); + if (ret != 0) { + LOG_ERR("Error retrieving CBI FW_CONFIG field %d", + FW_BASE_INVERSION); + return; + } + if (val == FW_BASE_INVERTED) { + LOG_INF("Switching to inverted base"); + motion_sensors[BASE_SENSOR].rot_standard_ref = &ALT_MAT; + motion_sensors[BASE_GYRO].rot_standard_ref = &ALT_MAT; + } +} +DECLARE_HOOK(HOOK_INIT, form_factor_init, HOOK_PRIO_POST_I2C); diff --git a/zephyr/projects/nissa/nivviks/src/keyboard.c b/zephyr/projects/nissa/nivviks/src/keyboard.c new file mode 100644 index 0000000000..f13d5bf78c --- /dev/null +++ b/zephyr/projects/nissa/nivviks/src/keyboard.c @@ -0,0 +1,29 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "ec_commands.h" + +static const struct ec_response_keybd_config nivviks_kb = { + .num_top_row_keys = 10, + .action_keys = { + TK_BACK, /* T1 */ + TK_REFRESH, /* T2 */ + TK_FULLSCREEN, /* T3 */ + TK_OVERVIEW, /* T4 */ + TK_SNAPSHOT, /* T5 */ + TK_BRIGHTNESS_DOWN, /* T6 */ + TK_BRIGHTNESS_UP, /* T7 */ + TK_VOL_MUTE, /* T8 */ + TK_VOL_DOWN, /* T9 */ + TK_VOL_UP, /* T10 */ + }, + .capabilities = KEYBD_CAP_SCRNLOCK_KEY, +}; + +__override const struct ec_response_keybd_config * +board_vivaldi_keybd_config(void) +{ + return &nivviks_kb; +} diff --git a/zephyr/projects/nissa/nivviks/src/led.c b/zephyr/projects/nissa/nivviks/src/led.c new file mode 100644 index 0000000000..9087982604 --- /dev/null +++ b/zephyr/projects/nissa/nivviks/src/led.c @@ -0,0 +1,51 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + * + * Battery LED control for nissa + */ +#include "common.h" +#include "ec_commands.h" +#include "led_common.h" +#include "led_onoff_states.h" +#include "led_pwm.h" + +__override const int led_charge_lvl_1 = 5; +__override const int led_charge_lvl_2 = 97; +__override struct led_descriptor + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_AMBER, + 2 * LED_ONE_SEC }, + { EC_LED_COLOR_BLUE, + 2 * LED_ONE_SEC } }, + }; + +__override void led_set_color_battery(enum ec_led_colors color) +{ + switch (color) { + case EC_LED_COLOR_BLUE: + set_pwm_led_color(EC_LED_ID_BATTERY_LED, EC_LED_COLOR_BLUE); + break; + case EC_LED_COLOR_AMBER: + set_pwm_led_color(EC_LED_ID_BATTERY_LED, EC_LED_COLOR_AMBER); + break; + default: /* LED_OFF and other unsupported colors */ + set_pwm_led_color(EC_LED_ID_BATTERY_LED, -1); + break; + } +} diff --git a/zephyr/projects/nissa/nivviks/src/usbc.c b/zephyr/projects/nissa/nivviks/src/usbc.c new file mode 100644 index 0000000000..14fc5a071d --- /dev/null +++ b/zephyr/projects/nissa/nivviks/src/usbc.c @@ -0,0 +1,277 @@ +/* Copyright 2021 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <zephyr/logging/log.h> + +#include "charge_state_v2.h" +#include "chipset.h" +#include "hooks.h" +#include "usb_mux.h" +#include "system.h" +#include "driver/charger/isl923x_public.h" +#include "driver/retimer/anx7483_public.h" +#include "driver/tcpm/tcpci.h" +#include "driver/tcpm/raa489000.h" + +#include "nissa_common.h" + +LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL); + +struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = { + { + .bus_type = EC_BUS_TYPE_I2C, + .i2c_info = { + .port = I2C_PORT_USB_C0_TCPC, + .addr_flags = RAA489000_TCPC0_I2C_FLAGS, + }, + .drv = &raa489000_tcpm_drv, + /* RAA489000 implements TCPCI 2.0 */ + .flags = TCPC_FLAGS_TCPCI_REV2_0 | + TCPC_FLAGS_VBUS_MONITOR, + }, + { /* sub-board */ + .bus_type = EC_BUS_TYPE_I2C, + .i2c_info = { + .port = I2C_PORT_USB_C1_TCPC, + .addr_flags = RAA489000_TCPC0_I2C_FLAGS, + }, + .drv = &raa489000_tcpm_drv, + /* RAA489000 implements TCPCI 2.0 */ + .flags = TCPC_FLAGS_TCPCI_REV2_0 | + TCPC_FLAGS_VBUS_MONITOR, + }, +}; + +int board_is_sourcing_vbus(int port) +{ + int regval; + + tcpc_read(port, TCPC_REG_POWER_STATUS, ®val); + return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS); +} + +int board_set_active_charge_port(int port) +{ + int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT); + int i; + int old_port; + + if (!is_real_port && port != CHARGE_PORT_NONE) + return EC_ERROR_INVAL; + + old_port = charge_manager_get_active_charge_port(); + + LOG_INF("New chg p%d", port); + + /* Disable all ports. */ + if (port == CHARGE_PORT_NONE) { + for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) { + tcpc_write(i, TCPC_REG_COMMAND, + TCPC_REG_COMMAND_SNK_CTRL_LOW); + raa489000_enable_asgate(i, false); + } + + return EC_SUCCESS; + } + + /* Check if port is sourcing VBUS. */ + if (board_is_sourcing_vbus(port)) { + LOG_WRN("Skip enable p%d", port); + return EC_ERROR_INVAL; + } + + /* + * Turn off the other ports' sink path FETs, before enabling the + * requested charge port. + */ + for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) { + if (i == port) + continue; + + if (tcpc_write(i, TCPC_REG_COMMAND, + TCPC_REG_COMMAND_SNK_CTRL_LOW)) + LOG_WRN("p%d: sink path disable failed.", i); + raa489000_enable_asgate(i, false); + } + + /* + * Stop the charger IC from switching while changing ports. Otherwise, + * we can overcurrent the adapter we're switching to. (crbug.com/926056) + */ + if (old_port != CHARGE_PORT_NONE) + charger_discharge_on_ac(1); + + /* Enable requested charge port. */ + if (raa489000_enable_asgate(port, true) || + tcpc_write(port, TCPC_REG_COMMAND, + TCPC_REG_COMMAND_SNK_CTRL_HIGH)) { + LOG_WRN("p%d: sink path enable failed.", port); + charger_discharge_on_ac(0); + return EC_ERROR_UNKNOWN; + } + + /* Allow the charger IC to begin/continue switching. */ + charger_discharge_on_ac(0); + + return EC_SUCCESS; +} + +uint16_t tcpc_get_alert_status(void) +{ + uint16_t status = 0; + int regval; + + /* + * The interrupt line is shared between the TCPC and BC1.2 detector IC. + * Therefore, go out and actually read the alert registers to report the + * alert status. + */ + if (!gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_c0_int_odl))) { + if (!tcpc_read16(0, TCPC_REG_ALERT, ®val)) { + /* The TCPCI Rev 1.0 spec says to ignore bits 14:12. */ + if (!(tcpc_config[0].flags & TCPC_FLAGS_TCPCI_REV2_0)) + regval &= ~((1 << 14) | (1 << 13) | (1 << 12)); + + if (regval) + status |= PD_STATUS_TCPC_ALERT_0; + } + } + + if (board_get_usb_pd_port_count() == 2 && + !gpio_pin_get_dt(GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl))) { + if (!tcpc_read16(1, TCPC_REG_ALERT, ®val)) { + /* TCPCI spec Rev 1.0 says to ignore bits 14:12. */ + if (!(tcpc_config[1].flags & TCPC_FLAGS_TCPCI_REV2_0)) + regval &= ~((1 << 14) | (1 << 13) | (1 << 12)); + + if (regval) + status |= PD_STATUS_TCPC_ALERT_1; + } + } + + return status; +} + +void pd_power_supply_reset(int port) +{ + /* Disable VBUS */ + tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_LOW); + + /* Notify host of power info change. */ + pd_send_host_event(PD_EVENT_POWER_CHANGE); +} + +__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp) +{ + if (port < 0 || port >= CONFIG_USB_PD_PORT_MAX_COUNT) + return; + + raa489000_set_output_current(port, rp); +} + +int pd_set_power_supply_ready(int port) +{ + int rv; + + if (port >= CONFIG_USB_PD_PORT_MAX_COUNT) + return EC_ERROR_INVAL; + + /* Disable charging. */ + rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW); + if (rv) + return rv; + + /* Our policy is not to source VBUS when the AP is off. */ + if (chipset_in_state(CHIPSET_STATE_ANY_OFF)) + return EC_ERROR_NOT_POWERED; + + /* Provide Vbus. */ + rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_HIGH); + if (rv) + return rv; + + rv = raa489000_enable_asgate(port, true); + if (rv) + return rv; + + /* Notify host of power info change. */ + pd_send_host_event(PD_EVENT_POWER_CHANGE); + + return EC_SUCCESS; +} + +void board_reset_pd_mcu(void) +{ + /* + * TODO(b:147316511): could send a reset command to the TCPC here + * if needed. + */ +} + +/* + * Because the TCPCs and BC1.2 chips share interrupt lines, it's possible + * for an interrupt to be lost if one asserts the IRQ, the other does the same + * then the first releases it: there will only be one falling edge to trigger + * the interrupt, and the line will be held low. We handle this by running a + * deferred check after a falling edge to see whether the IRQ is still being + * asserted. If it is, we assume an interrupt may have been lost and we need + * to poll each chip for events again. + */ +#define USBC_INT_POLL_DELAY_US 5000 + +static void poll_c0_int(void); +DECLARE_DEFERRED(poll_c0_int); +static void poll_c1_int(void); +DECLARE_DEFERRED(poll_c1_int); + +static void usbc_interrupt_trigger(int port) +{ + schedule_deferred_pd_interrupt(port); + usb_charger_task_set_event(port, USB_CHG_EVENT_BC12); +} + +static inline void poll_usb_gpio(int port, const struct gpio_dt_spec *gpio, + const struct deferred_data *ud) +{ + if (!gpio_pin_get_dt(gpio)) { + usbc_interrupt_trigger(port); + hook_call_deferred(ud, USBC_INT_POLL_DELAY_US); + } +} + +static void poll_c0_int(void) +{ + poll_usb_gpio(0, GPIO_DT_FROM_NODELABEL(gpio_usb_c0_int_odl), + &poll_c0_int_data); +} + +static void poll_c1_int(void) +{ + poll_usb_gpio(1, GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl), + &poll_c1_int_data); +} + +void usb_interrupt(enum gpio_signal signal) +{ + int port; + const struct deferred_data *ud; + + if (signal == GPIO_SIGNAL(DT_NODELABEL(gpio_usb_c0_int_odl))) { + port = 0; + ud = &poll_c0_int_data; + } else { + port = 1; + ud = &poll_c1_int_data; + } + /* + * We've just been called from a falling edge, so there's definitely + * no lost IRQ right now. Cancel any pending check. + */ + hook_call_deferred(ud, -1); + /* Trigger polling of TCPC and BC1.2 in respective tasks */ + usbc_interrupt_trigger(port); + /* Check for lost interrupts in a bit */ + hook_call_deferred(ud, USBC_INT_POLL_DELAY_US); +} diff --git a/zephyr/projects/nissa/npcx_program.conf b/zephyr/projects/nissa/npcx_program.conf new file mode 100644 index 0000000000..5e0dd99501 --- /dev/null +++ b/zephyr/projects/nissa/npcx_program.conf @@ -0,0 +1,47 @@ +# Copyright 2022 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +# EC chip configuration: NPCX993 +CONFIG_CROS_FLASH_NPCX=y +CONFIG_CROS_SYSTEM_NPCX=y +CONFIG_SOC_SERIES_NPCX9=y +CONFIG_PLATFORM_EC_WORKAROUND_FLASH_DOWNLOAD_API=y +CONFIG_SYSCON=y +CONFIG_TACH_NPCX=y +CONFIG_SHELL_BACKEND_SERIAL_RX_RING_BUFFER_SIZE=256 + +# Common sensor drivers +CONFIG_PLATFORM_EC_ACCEL_LIS2DW12=y + +# Keyboard +CONFIG_CROS_KB_RAW_NPCX=y +CONFIG_PLATFORM_EC_KBLIGHT_ENABLE_PIN=y +# Ensure recovery key combination (esc+refresh+power) is reliable +CONFIG_PLATFORM_EC_KEYBOARD_PWRBTN_ASSERTS_KSI3=y +CONFIG_PLATFORM_EC_KEYBOARD_REFRESH_ROW3=y + +# TCPC+PPC: both C0 and C1 (if present) are RAA489000 +CONFIG_PLATFORM_EC_USB_PD_TCPM_RAA489000=y +CONFIG_PLATFORM_EC_USB_PD_DISCHARGE_TCPC=y +CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_TCPC=y +CONFIG_PLATFORM_EC_USB_PD_TCPC_LPM_EXIT_DEBOUNCE_US=100000 +# RAA489000 uses TCPCI but not a separate PPC, so custom function is required +CONFIG_PLATFORM_EC_USB_PD_5V_EN_CUSTOM=y +# type C port 1 redriver +CONFIG_PLATFORM_EC_USBC_RETIMER_ANX7483=y +# Save some space +CONFIG_SHELL_MINIMAL=y + +# FRS enable +CONFIG_PLATFORM_EC_USB_PD_FRS=y +CONFIG_PLATFORM_EC_USB_PD_FRS_TCPC=y + +# Charger driver and configuration +CONFIG_PLATFORM_EC_CHARGER_RAA489000=y +CONFIG_PLATFORM_EC_OCPC_DEF_RBATT_MOHMS=22 + +# VSENSE: PP3300_S5 & PP1050_PROC +CONFIG_ADC_CMP_NPCX=y +CONFIG_SENSOR=y +CONFIG_SENSOR_SHELL=n diff --git a/zephyr/projects/nissa/program.conf b/zephyr/projects/nissa/program.conf new file mode 100644 index 0000000000..c23a7f1381 --- /dev/null +++ b/zephyr/projects/nissa/program.conf @@ -0,0 +1,156 @@ +# Copyright 2021 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +# Core EC configuration: build the EC application, using ECOS shims +# (which are currently required for a number of features). +CONFIG_CROS_EC=y +CONFIG_PLATFORM_EC=y +CONFIG_SHIMMED_TASKS=y +CONFIG_LTO=y + +# Debug options and features; can be disabled to save memory or once bringup +# is complete. +CONFIG_LOG=y +CONFIG_LOG_MODE_MINIMAL=y + +# RAM-saving options +# flash shell command is unused, allocated a 4kB buffer for flash test +CONFIG_FLASH_SHELL=n +# EC default 1kB buffer seems unnecessarily large, Zephyr default is 8 bytes +CONFIG_SHELL_BACKEND_SERIAL_TX_RING_BUFFER_SIZE=128 + +# Standard shimmed features +CONFIG_PLATFORM_EC_BACKLIGHT_LID=y +CONFIG_PLATFORM_EC_CONSOLE_CMD_SYSINFO=y +CONFIG_PLATFORM_EC_EEPROM_CBI_WP=y +CONFIG_PLATFORM_EC_LID_SWITCH=y +CONFIG_PLATFORM_EC_POWER_BUTTON=y +CONFIG_PLATFORM_EC_SWITCH=y +CONFIG_PLATFORM_EC_GMR_TABLET_MODE=y +CONFIG_PLATFORM_EC_TABLET_MODE=y +CONFIG_PLATFORM_EC_TABLET_MODE_SWITCH=y +CONFIG_PLATFORM_EC_VBOOT_EFS2=y +CONFIG_PLATFORM_EC_VBOOT_HASH=y + +# Application processor; communicates with EC via eSPI +CONFIG_AP=y +CONFIG_AP_X86_INTEL_ADL=y +CONFIG_ESPI=y +CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S4=y +CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S5=y +CONFIG_PLATFORM_EC_HOSTCMD=y +CONFIG_HCDEBUG_OFF=y +CONFIG_PLATFORM_EC_THROTTLE_AP=y +CONFIG_PLATFORM_EC_PORT80=y +CONFIG_PLATFORM_EC_PORT80_QUIET=y + +# AP Power Sequencing +CONFIG_AP_PWRSEQ=y +CONFIG_X86_NON_DSX_PWRSEQ_ADL=y +CONFIG_X86_NON_DSX_PWRSEQ_CONSOLE=y +CONFIG_X86_NON_DSX_PWRSEQ_HOST_CMD=y +CONFIG_AP_PWRSEQ_S0IX=y +CONFIG_AP_PWRSEQ_S0IX_ERROR_RECOVERY=y + +# I2C +CONFIG_I2C=y + +# Keyboard support +CONFIG_PLATFORM_EC_KBLIGHT_ENABLE_PIN=y +CONFIG_PLATFORM_EC_KEYBOARD=y +CONFIG_PLATFORM_EC_KEYBOARD_PROTOCOL_8042=y +CONFIG_PLATFORM_EC_VOLUME_BUTTONS=y +CONFIG_PLATFORM_EC_CMD_BUTTON=n +# Column 2 is driven through the GSC, which inverts the signal going through it +CONFIG_PLATFORM_EC_KEYBOARD_COL2_INVERTED=y + +# LED +CONFIG_PLATFORM_EC_LED_COMMON=y +CONFIG_PLATFORM_EC_LED_PWM=y +CONFIG_PLATFORM_EC_LED_ONOFF_STATES=y +CONFIG_PLATFORM_EC_CONSOLE_CMD_LEDTEST=n + +# MKBP event +CONFIG_PLATFORM_EC_MKBP_EVENT=y +CONFIG_PLATFORM_EC_MKBP_INPUT_DEVICES=y +CONFIG_PLATFORM_EC_MKBP_USE_GPIO_AND_HOST_EVENT=y + +# Temperature sensor support +CONFIG_PLATFORM_EC_TEMP_SENSOR=y +CONFIG_PLATFORM_EC_THERMISTOR=y +CONFIG_PLATFORM_EC_TEMP_SENSOR_FIRST_READ_DELAY=y + +# CBI EEPROM support +CONFIG_EEPROM=y +CONFIG_EEPROM_AT24=y +CONFIG_EEPROM_SHELL=n +CONFIG_PLATFORM_EC_CBI_EEPROM=y +CONFIG_PLATFORM_EC_BOARD_VERSION_CBI=y + + +# PWM support +CONFIG_PWM=y +CONFIG_PWM_SHELL=y + +# TODO(b/188605676): bring these features up +CONFIG_PLATFORM_EC_BACKLIGHT_LID=n + +# Sensors support +CONFIG_PLATFORM_EC_LID_ANGLE=y +CONFIG_PLATFORM_EC_LID_ANGLE_UPDATE=y +CONFIG_PLATFORM_EC_MOTIONSENSE=y +CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCELS=y +CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCEL_INFO=y +CONFIG_PLATFORM_EC_ACCEL_FIFO=y +CONFIG_PLATFORM_EC_SENSOR_TIGHT_TIMESTAMPS=y + +# USB-C: enable PD on up to two ports +CONFIG_PLATFORM_EC_USBC=y +CONFIG_PLATFORM_EC_USBC_PPC=n +CONFIG_PLATFORM_EC_USB_VID=0x18d1 +CONFIG_PLATFORM_EC_USB_PID=0x505a +# USB4 and TBT are unsupported +CONFIG_PLATFORM_EC_USB_PD_USB4=n +CONFIG_PLATFORM_EC_USB_PD_TBT_COMPAT_MODE=n + +CONFIG_PLATFORM_EC_USB_MUX_RUNTIME_CONFIG=y +CONFIG_PLATFORM_EC_USB_MUX_VIRTUAL=y +# ADL integrated muxes are slow: unblock PD +CONFIG_PLATFORM_EC_USB_MUX_TASK=y +CONFIG_PLATFORM_EC_BC12_DETECT_PI3USB9201=y + +# USB-C TCPC and PPC standard options +CONFIG_PLATFORM_EC_USB_PD_TCPC_LOW_POWER=y +CONFIG_PLATFORM_EC_USB_PD_VBUS_MEASURE_CHARGER=y + +# USB-A host ports +CONFIG_PLATFORM_EC_USBA=y +CONFIG_PLATFORM_EC_USB_PORT_ENABLE_DYNAMIC=y +# Both ports use a smart switch with CTL1..3 fixed high, for SDP2 or CDP only: +# either SLGC55545 or PI5USB2546. +CONFIG_PLATFORM_EC_USB_PORT_POWER_SMART=y +CONFIG_PLATFORM_EC_USB_PORT_POWER_SMART_CDP_SDP_ONLY=y +CONFIG_PLATFORM_EC_USB_PORT_POWER_SMART_DEFAULT_CDP=y +CONFIG_PLATFORM_EC_USB_PORT_POWER_SMART_INVERTED=y + +# Battery support +CONFIG_PLATFORM_EC_BATTERY=y +CONFIG_PLATFORM_EC_BATTERY_CUT_OFF=y +CONFIG_PLATFORM_EC_BATTERY_PRESENT_GPIO=y +CONFIG_PLATFORM_EC_BATTERY_FUEL_GAUGE=y +CONFIG_PLATFORM_EC_BATTERY_SMART=y +CONFIG_PLATFORM_EC_BATTERY_REVIVE_DISCONNECT=y + +# Charger support +CONFIG_PLATFORM_EC_CHARGER=y +CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR=10 +CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR_AC=10 +CONFIG_PLATFORM_EC_CHARGER_DISCHARGE_ON_AC=y +CONFIG_PLATFORM_EC_CHARGER_DISCHARGE_ON_AC_CHARGER=y + +# Dynamically select PD voltage to maximize charger efficiency +CONFIG_PLATFORM_EC_USB_PD_DPS=y +# Reduce logging so that state transitions do not cause protocol issues +# pd dump [1-3] can be used to increase the debugging level +CONFIG_PLATFORM_EC_USB_PD_INITIAL_DEBUG_LEVEL=0 diff --git a/zephyr/projects/nissa/pujjo/cbi.dtsi b/zephyr/projects/nissa/pujjo/cbi.dtsi new file mode 100644 index 0000000000..b5ba92bd9e --- /dev/null +++ b/zephyr/projects/nissa/pujjo/cbi.dtsi @@ -0,0 +1,190 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + /* Pujjo-specific fw_config fields. */ + nissa-fw-config { + /* + * FW_CONFIG field to enable KB back light or not. + */ + kb-bl { + enum-name = "FW_KB_BL"; + start = <3>; + size = <1>; + + no-kb-bl { + compatible = "cros-ec,cbi-fw-config-value"; + enum-name = "FW_KB_BL_NOT_PRESENT"; + value = <0>; + }; + kb-bl-present { + compatible = "cros-ec,cbi-fw-config-value"; + enum-name = "FW_KB_BL_PRESENT"; + value = <1>; + }; + }; + + /* + * FW_CONFIG field for KB PWB present or not. + */ + kb-pwb { + enum-name = "FW_KB_PWB"; + start = <4>; + size = <1>; + + no-kb-pwb { + compatible = "cros-ec,cbi-fw-config-value"; + enum-name = "FW_KB_PWB_NOT_PRESENT"; + value = <0>; + }; + kb-pwb-present { + compatible = "cros-ec,cbi-fw-config-value"; + enum-name = "FW_KB_PWB_PRESENT"; + value = <1>; + }; + }; + + /* + * FW_CONFIG field for tablet present or not. + */ + tablet { + enum-name = "FW_TABLET"; + start = <5>; + size = <1>; + + no-tablet { + compatible = "cros-ec,cbi-fw-config-value"; + enum-name = "FW_TABLET_NOT_PRESENT"; + value = <0>; + }; + tablet-present { + compatible = "cros-ec,cbi-fw-config-value"; + enum-name = "FW_TABLET_PRESENT"; + value = <1>; + }; + }; + + /* + * FW_CONFIG field for LTE board present or not. + * + * start = <6>; + * size = <1>; + */ + + /* + * FW_CONFIG field for SD card present or not. + * + * start = <7>; + * size = <1>; + */ + + /* + * FW_CONFIG field for pen present or not. + */ + pen { + enum-name = "FW_PEN"; + start = <8>; + size = <1>; + + no-pen { + compatible = "cros-ec,cbi-fw-config-value"; + enum-name = "FW_PEN_NOT_PRESENT"; + value = <0>; + }; + pen-present { + compatible = "cros-ec,cbi-fw-config-value"; + enum-name = "FW_PEN_PRESENT"; + value = <1>; + }; + }; + + /* + * FW_CONFIG field for WF camera present or not. + * + * start = <9>; + * size = <1>; + */ + + /* + * FW_CONFIG field for multiple thermal table. + */ + therm-table { + enum-name = "THERM_TABLE"; + start = <10>; + size = <2>; + + therm-table-1 { + compatible = "cros-ec,cbi-fw-config-value"; + enum-name = "THERM_TABLE_1"; + value = <1>; + }; + }; + + /* + * FW_CONFIG field for multiple audio module. + * + * start = <12>; + * size = <3>; + */ + + /* + * FW_CONFIG field for EXT_VR. + * + * start = <15>; + * size = <1>; + */ + + /* + * FW_CONFIG field for multiple wi-fi SAR. + * + * start = <16>; + * size = <2>; + */ + }; + + /* Pujjo-specific ssfc fields. */ + cbi-ssfc { + compatible = "named-cbi-ssfc"; + /* + * SSFC field to identify BASE motion sensor. + */ + base-sensor { + enum-name = "BASE_SENSOR"; + size = <2>; + + base_sensor_0: bmi323 { + compatible = "named-cbi-ssfc-value"; + status = "okay"; + value = <0>; + default; + }; + base_sensor_1: lsm6dsm { + compatible = "named-cbi-ssfc-value"; + status = "okay"; + value = <1>; + }; + }; + + /* + * SSFC field to identify LID motion sensor. + */ + lid-sensor { + enum-name = "LID_SENSOR"; + size = <2>; + + lid_sensor_0: bma422 { + compatible = "named-cbi-ssfc-value"; + status = "okay"; + value = <0>; + default; + }; + lid_sensor_1: lis2dw12 { + compatible = "named-cbi-ssfc-value"; + status = "okay"; + value = <1>; + }; + }; + }; +}; diff --git a/zephyr/projects/nissa/pujjo/generated.dtsi b/zephyr/projects/nissa/pujjo/generated.dtsi new file mode 100644 index 0000000000..727d2d3d53 --- /dev/null +++ b/zephyr/projects/nissa/pujjo/generated.dtsi @@ -0,0 +1,277 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + * + * This file is auto-generated - do not edit! + */ + +/ { + + named-adc-channels { + compatible = "named-adc-channels"; + + adc_ec_vsense_pp1050_proc: ec_vsense_pp1050_proc { + enum-name = "ADC_PP1050_PROC"; + io-channels = <&adc0 4>; + }; + adc_ec_vsense_pp3300_s5: ec_vsense_pp3300_s5 { + enum-name = "ADC_PP3300_S5"; + io-channels = <&adc0 6>; + }; + adc_temp_sensor_1: temp_sensor_1 { + enum-name = "ADC_TEMP_SENSOR_1"; + io-channels = <&adc0 0>; + }; + adc_temp_sensor_2: temp_sensor_2 { + enum-name = "ADC_TEMP_SENSOR_2"; + io-channels = <&adc0 1>; + }; + adc_temp_sensor_3: temp_sensor_3 { + enum-name = "ADC_TEMP_SENSOR_3"; + io-channels = <&adc0 10>; + }; + }; + + named-gpios { + compatible = "named-gpios"; + + gpio_acc_int_l: acc_int_l { + gpios = <&gpio5 0 GPIO_INPUT>; + }; + gpio_all_sys_pwrgd: all_sys_pwrgd { + gpios = <&gpioa 7 GPIO_INPUT>; + }; + gpio_ccd_mode_odl: ccd_mode_odl { + gpios = <&gpioe 5 GPIO_INPUT>; + enum-name = "GPIO_CCD_MODE_ODL"; + }; + gpio_cpu_c10_gate_l: cpu_c10_gate_l { + gpios = <&gpio6 7 GPIO_INPUT>; + }; + gpio_ec_battery_pres_odl: ec_battery_pres_odl { + gpios = <&gpioa 3 GPIO_INPUT>; + enum-name = "GPIO_BATT_PRES_ODL"; + }; + gpio_ec_cbi_wp: ec_cbi_wp { + gpios = <&gpio7 4 GPIO_OUTPUT>; + }; + gpio_ec_edp_bl_en_od: ec_edp_bl_en_od { + gpios = <&gpiod 3 GPIO_ODR_HIGH>; + enum-name = "GPIO_ENABLE_BACKLIGHT"; + }; + gpio_ec_entering_rw: ec_entering_rw { + gpios = <&gpio0 3 GPIO_OUTPUT>; + enum-name = "GPIO_ENTERING_RW"; + }; + gpio_ec_gsc_packet_mode: ec_gsc_packet_mode { + gpios = <&gpio7 5 GPIO_OUTPUT>; + enum-name = "GPIO_PACKET_MODE_EN"; + }; + gpio_ec_kso_02_inv: ec_kso_02_inv { + gpios = <&gpio1 7 (GPIO_OUTPUT_LOW | GPIO_ACTIVE_LOW)>; + }; + gpio_ec_pch_wake_odl: ec_pch_wake_odl { + gpios = <&gpiob 0 GPIO_ODR_LOW>; + }; + gpio_ec_prochot_odl: ec_prochot_odl { + gpios = <&gpiof 1 GPIO_ODR_HIGH>; + }; + gpio_ec_soc_dsw_pwrok: ec_soc_dsw_pwrok { + gpios = <&gpio6 1 GPIO_OUTPUT>; + }; + gpio_ec_soc_hdmi_hpd: ec_soc_hdmi_hpd { + gpios = <&gpioe 4 GPIO_OUTPUT>; + }; + gpio_ec_soc_int_odl: ec_soc_int_odl { + gpios = <&gpio8 0 GPIO_ODR_HIGH>; + enum-name = "GPIO_EC_INT_L"; + }; + gpio_ec_soc_pch_pwrok_od: ec_soc_pch_pwrok_od { + gpios = <&gpio7 2 GPIO_ODR_HIGH>; + }; + gpio_ec_soc_pwr_btn_odl: ec_soc_pwr_btn_odl { + gpios = <&gpioc 1 GPIO_ODR_HIGH>; + enum-name = "GPIO_PCH_PWRBTN_L"; + }; + gpio_ec_soc_rsmrst_l: ec_soc_rsmrst_l { + gpios = <&gpioa 6 GPIO_OUTPUT>; + }; + gpio_ec_soc_rtcrst: ec_soc_rtcrst { + gpios = <&gpio7 6 GPIO_OUTPUT>; + }; + gpio_ec_soc_sys_pwrok: ec_soc_sys_pwrok { + gpios = <&gpio3 7 GPIO_OUTPUT>; + }; + gpio_ec_soc_vccst_pwrgd_od: ec_soc_vccst_pwrgd_od { + gpios = <&gpioa 4 GPIO_ODR_HIGH>; + }; + gpio_ec_wp_odl: ec_wp_odl { + gpios = <&gpioa 1 (GPIO_INPUT | GPIO_ACTIVE_LOW)>; + }; + gpio_en_kb_bl: en_kb_bl { + gpios = <&gpioa 0 GPIO_OUTPUT>; + enum-name = "GPIO_EN_KEYBOARD_BACKLIGHT"; + }; + gpio_en_pp3300_s5: en_pp3300_s5 { + gpios = <&gpiob 6 GPIO_OUTPUT>; + enum-name = "GPIO_TEMP_SENSOR_POWER"; + }; + gpio_en_pp5000_pen_x: en_pp5000_pen_x { + gpios = <&gpioe 2 GPIO_OUTPUT>; + }; + gpio_en_pp5000_s5: en_pp5000_s5 { + gpios = <&gpio4 0 GPIO_OUTPUT>; + }; + gpio_en_slp_z: en_slp_z { + gpios = <&gpioe 1 GPIO_OUTPUT>; + }; + gpio_en_usb_a0_vbus: en_usb_a0_vbus { + gpios = <&gpio9 1 GPIO_OUTPUT>; + }; + gpio_gsc_ec_pwr_btn_odl: gsc_ec_pwr_btn_odl { + gpios = <&gpio0 0 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_POWER_BUTTON_L"; + }; + gpio_hdmi_sel: hdmi_sel { + gpios = <&gpioc 6 GPIO_OUTPUT>; + }; + gpio_imu_int_l: imu_int_l { + gpios = <&gpio5 6 GPIO_INPUT>; + }; + gpio_imvp91_vrrdy_od: imvp91_vrrdy_od { + gpios = <&gpio4 3 GPIO_INPUT>; + }; + gpio_lid_open: lid_open { + gpios = <&gpiod 2 GPIO_INPUT>; + enum-name = "GPIO_LID_OPEN"; + }; + gpio_pen_detect_odl: pen_detect_odl { + gpios = <&gpio9 6 GPIO_INPUT_PULL_UP>; + }; + gpio_pg_pp1050_mem_s3_od: pg_pp1050_mem_s3_od { + gpios = <&gpiof 0 GPIO_INPUT>; + }; + gpio_pg_pp5000_s5_od: pg_pp5000_s5_od { + gpios = <&gpio4 2 GPIO_INPUT>; + }; + gpio_rsmrst_pwrgd_l: rsmrst_pwrgd_l { + gpios = <&gpio9 4 GPIO_INPUT_PULL_UP>; + }; + gpio_slp_s0_l: slp_s0_l { + gpios = <&gpio9 7 GPIO_INPUT>; + }; + gpio_slp_s3_l: slp_s3_l { + gpios = <&gpioa 5 GPIO_INPUT>; + }; + gpio_slp_s4_l: slp_s4_l { + gpios = <&gpio7 0 GPIO_INPUT>; + }; + gpio_slp_sus_l: slp_sus_l { + gpios = <&gpio6 2 GPIO_INPUT>; + }; + gpio_sub_usb_a1_ilimit_sdp: sub_usb_a1_ilimit_sdp { + gpios = <&gpiod 5 GPIO_OUTPUT>; + enum-name = "GPIO_USB2_ILIM_SEL"; + }; + gpio_sys_rst_odl: sys_rst_odl { + gpios = <&gpioc 5 GPIO_ODR_HIGH>; + }; + gpio_tablet_mode_l: tablet_mode_l { + gpios = <&gpio9 5 GPIO_INPUT>; + enum-name = "GPIO_TABLET_MODE_L"; + }; + gpio_usb_a0_ilimit_sdp: usb_a0_ilimit_sdp { + gpios = <&gpio8 5 GPIO_OUTPUT>; + enum-name = "GPIO_USB1_ILIM_SEL"; + }; + gpio_usb_c0_int_odl: usb_c0_int_odl { + gpios = <&gpio0 1 GPIO_INPUT_PULL_UP>; + }; + gpio_vccin_aux_vid0: vccin_aux_vid0 { + gpios = <&gpio9 2 GPIO_INPUT>; + }; + gpio_vccin_aux_vid1: vccin_aux_vid1 { + gpios = <&gpioe 3 GPIO_INPUT>; + }; + gpio_voldn_btn_odl: voldn_btn_odl { + gpios = <&gpio9 3 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_VOLUME_DOWN_L"; + }; + gpio_volup_btn_odl: volup_btn_odl { + gpios = <&gpioa 2 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_VOLUME_UP_L"; + }; + }; + + named-i2c-ports { + compatible = "named-i2c-ports"; + + i2c_ec_i2c_eeprom: ec_i2c_eeprom { + i2c-port = <&i2c0_0>; + enum-names = "I2C_PORT_EEPROM"; + }; + i2c_ec_i2c_sensor: ec_i2c_sensor { + i2c-port = <&i2c1_0>; + enum-names = "I2C_PORT_SENSOR"; + }; + i2c_ec_i2c_usb_c0: ec_i2c_usb_c0 { + i2c-port = <&i2c3_0>; + enum-names = "I2C_PORT_USB_C0_TCPC"; + }; + i2c_ec_i2c_batt: ec_i2c_batt { + i2c-port = <&i2c7_0>; + enum-names = "I2C_PORT_BATTERY"; + }; + }; +}; + +&adc0 { + status = "okay"; + pinctrl-0 = <&adc0_chan0_gp45 + &adc0_chan1_gp44 + &adc0_chan4_gp41 + &adc0_chan6_gp34 + &adc0_chan10_gpe0>; + pinctrl-names = "default"; +}; + + +&i2c0_0 { + status = "okay"; + pinctrl-0 = <&i2c0_0_sda_scl_gpb4_b5>; + pinctrl-names = "default"; +}; + +&i2c1_0 { + status = "okay"; + pinctrl-0 = <&i2c1_0_sda_scl_gp87_90>; + pinctrl-names = "default"; +}; + +&i2c3_0 { + status = "okay"; + pinctrl-0 = <&i2c3_0_sda_scl_gpd0_d1>; + pinctrl-names = "default"; +}; + +&i2c7_0 { + status = "okay"; + pinctrl-0 = <&i2c7_0_sda_scl_gpb2_b3>; + pinctrl-names = "default"; +}; + +&i2c_ctrl0 { + status = "okay"; +}; + +&i2c_ctrl1 { + status = "okay"; +}; + +&i2c_ctrl3 { + status = "okay"; +}; + +&i2c_ctrl7 { + status = "okay"; +}; diff --git a/zephyr/projects/nissa/pujjo/keyboard.dtsi b/zephyr/projects/nissa/pujjo/keyboard.dtsi new file mode 100644 index 0000000000..00610e4e18 --- /dev/null +++ b/zephyr/projects/nissa/pujjo/keyboard.dtsi @@ -0,0 +1,48 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + kblight { + compatible = "cros-ec,kblight-pwm"; + pwms = <&pwm6 6 PWM_HZ(2400) PWM_POLARITY_NORMAL>; + }; +}; + +&pwm6 { + status = "okay"; + clock-bus = "NPCX_CLOCK_BUS_LFCLK"; + pinctrl-0 = <&pwm6_gpc0>; + pinctrl-names = "default"; +}; + +&cros_kb_raw { + status = "okay"; + /* No KSO2 (it's inverted and implemented by GPIO) */ + pinctrl-0 = < + &ksi0_gp31 + &ksi1_gp30 + &ksi2_gp27 + &ksi3_gp26 + &ksi4_gp25 + &ksi5_gp24 + &ksi6_gp23 + &ksi7_gp22 + &kso00_gp21 + &kso01_gp20 + &kso03_gp16 + &kso04_gp15 + &kso05_gp14 + &kso06_gp13 + &kso07_gp12 + &kso08_gp11 + &kso09_gp10 + &kso10_gp07 + &kso11_gp06 + &kso12_gp05 + &kso13_gp04 + &kso14_gp82 + >; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/nissa/pujjo/motionsense.dtsi b/zephyr/projects/nissa/pujjo/motionsense.dtsi new file mode 100644 index 0000000000..2dfca337c4 --- /dev/null +++ b/zephyr/projects/nissa/pujjo/motionsense.dtsi @@ -0,0 +1,245 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <dt-bindings/motionsense/utils.h> + + +/ { + aliases { + /* + * Interrupt bindings for sensor devices. + */ + bmi3xx-int = &base_accel; + lsm6dsm-int = &base_accel; + lis2dw12-int = &lid_accel; + }; + + /* + * Declare mutexes used by sensor drivers. + * A mutex node is used to create an instance of mutex_t. + * A mutex node is referenced by a sensor node if the + * corresponding sensor driver needs to use the + * instance of the mutex. + */ + motionsense-mutex { + compatible = "cros-ec,motionsense-mutex"; + lid_mutex: lid-mutex { + }; + + base_mutex: base-mutex { + }; + }; + + /* Rotation matrix used by drivers. */ + motionsense-rotation-ref { + compatible = "cros-ec,motionsense-rotation-ref"; + lid_rot_ref: lid-rotation-ref { + mat33 = <0 (-1) 0 + (-1) 0 0 + 0 0 (-1)>; + }; + + lid_rot_lis2dw12: lid-rotation-lis2dw12 { + mat33 = <0 (-1) 0 + (-1) 0 0 + 0 0 (-1)>; + }; + + base_rot_ref: base-rotation-ref { + mat33 = <0 1 0 + (-1) 0 0 + 0 0 1>; + }; + + base_rot_lsm6dsm: base-rotation-lsm6dsm { + mat33 = <1 0 0 + 0 1 0 + 0 0 1>; + }; + }; + + /* + * Driver specific data. A driver-specific data can be shared with + * different motion sensors while they are using the same driver. + * + * If a node's compatible starts with "cros-ec,accelgyro-", it is for + * a common structure defined in accelgyro.h. + * e.g) compatible = "cros-ec,accelgyro-als-drv-data" is for + * "struct als_drv_data_t" in accelgyro.h + */ + motionsense-sensor-data { + bmi323_data: bmi323-drv-data { + compatible = "cros-ec,drvdata-bmi3xx"; + status = "okay"; + }; + + lsm6dsm_data_accel: lsm6dsm-accel-drv-data { + compatible = "cros-ec,drvdata-lsm6dsm"; + status = "okay"; + }; + + lsm6dsm_data_gyro: lsm6dsm-gyro-drv-data { + compatible = "cros-ec,drvdata-lsm6dsm"; + status = "okay"; + }; + + bma422_data: bma422-drv-data { + compatible = "cros-ec,drvdata-bma4xx"; + status = "okay"; + }; + + lis2dw12_data: lis2dw12-drv-data { + compatible = "cros-ec,drvdata-lis2dw12"; + status = "okay"; + }; + }; + + /* + * List of motion sensors that creates motion_sensors array. + * The nodelabel "lid_accel" and "base_accel" are used to indicate + * motion sensor IDs for lid angle calculation. + * TODO(b/238139272): The first entries of the array must be + * accelerometers,then gyroscope. Fix this dependency in the DTS + * processing which makes the devicetree entries independent. + */ + motionsense-sensor { + lid_accel: lid-accel { + compatible = "cros-ec,bma4xx"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_LID"; + mutex = <&lid_mutex>; + port = <&i2c_ec_i2c_sensor>; + rot-standard-ref = <&lid_rot_ref>; + default-range = <2>; + drv-data = <&bma422_data>; + configs { + compatible = + "cros-ec,motionsense-sensor-config"; + ec-s0 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + ec-s3 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + }; + }; + + base_accel: base-accel { + compatible = "cros-ec,bmi3xx-accel"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_BASE"; + mutex = <&base_mutex>; + port = <&i2c_ec_i2c_sensor>; + rot-standard-ref = <&base_rot_ref>; + drv-data = <&bmi323_data>; + configs { + compatible = + "cros-ec,motionsense-sensor-config"; + ec-s0 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + ec-s3 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + }; + }; + + base_gyro: base-gyro { + compatible = "cros-ec,bmi3xx-gyro"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_BASE"; + mutex = <&base_mutex>; + port = <&i2c_ec_i2c_sensor>; + rot-standard-ref = <&base_rot_ref>; + drv-data = <&bmi323_data>; + }; + }; + + motionsense-sensor-alt { + alt_lid_accel: alt-lid-accel { + compatible = "cros-ec,lis2dw12"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_LID"; + mutex = <&lid_mutex>; + port = <&i2c_ec_i2c_sensor>; + rot-standard-ref = <&lid_rot_lis2dw12>; + default-range = <2>; + drv-data = <&lis2dw12_data>; + i2c-spi-addr-flags = "LIS2DWL_ADDR1_FLAGS"; + alternate-for = <&lid_accel>; + alternate-ssfc-indicator = <&lid_sensor_1>; + configs { + compatible = + "cros-ec,motionsense-sensor-config"; + ec-s0 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + ec-s3 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + }; + }; + + alt_base_accel: alt-base-accel { + compatible = "cros-ec,lsm6dsm-accel"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_BASE"; + mutex = <&base_mutex>; + port = <&i2c_ec_i2c_sensor>; + rot-standard-ref = <&base_rot_lsm6dsm>; + drv-data = <&lsm6dsm_data_accel>; + alternate-for = <&base_accel>; + alternate-ssfc-indicator = <&base_sensor_1>; + configs { + compatible = + "cros-ec,motionsense-sensor-config"; + ec-s0 { + odr = <(10000 | ROUND_UP_FLAG)>; + ec-rate = <(100 * USEC_PER_MSEC)>; + }; + ec-s3 { + odr = <(10000 | ROUND_UP_FLAG)>; + ec-rate = <0>; + }; + }; + }; + + alt_base_gyro: alt-base-gyro { + compatible = "cros-ec,lsm6dsm-gyro"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_BASE"; + mutex = <&base_mutex>; + port = <&i2c_ec_i2c_sensor>; + rot-standard-ref = <&base_rot_lsm6dsm>; + drv-data = <&lsm6dsm_data_gyro>; + alternate-for = <&base_gyro>; + alternate-ssfc-indicator = <&base_sensor_1>; + }; + }; + + motionsense-sensor-info { + compatible = "cros-ec,motionsense-sensor-info"; + + /* + * list of GPIO interrupts that have to + * be enabled at initial stage + */ + sensor-irqs = <&int_imu>; + /* list of sensors in force mode */ + accel-force-mode-sensors = <&lid_accel>; + }; +}; diff --git a/zephyr/projects/nissa/pujjo/overlay.dtsi b/zephyr/projects/nissa/pujjo/overlay.dtsi new file mode 100644 index 0000000000..60b3b60003 --- /dev/null +++ b/zephyr/projects/nissa/pujjo/overlay.dtsi @@ -0,0 +1,350 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <cros/thermistor/thermistor.dtsi> + +/ { + aliases { + gpio-cbi-wp = &gpio_ec_cbi_wp; + gpio-wp = &gpio_ec_wp_odl; + int-wp = &int_wp_l; + gpio-kbd-kso2 = &gpio_ec_kso_02_inv; + }; + + ec-console { + compatible = "ec-console"; + disabled = "events", "lpc", "hostcmd"; + }; + + batteries { + default_battery: smp { + compatible = "smp,l22m3pg0", "battery-smart"; + }; + smp_l22m3pg1 { + compatible = "smp,l22m3pg1", "battery-smart"; + }; + sunwoda_l22d3pg0 { + compatible = "sunwoda,l22d3pg0", "battery-smart"; + }; + sunwoda_l22d3pg1 { + compatible = "sunwoda,l22d3pg1", "battery-smart"; + }; + celxpert_l22c3pg0 { + compatible = "celxpert,l22c3pg0", "battery-smart"; + }; + }; + + hibernate-wake-pins { + compatible = "cros-ec,hibernate-wake-pins"; + wakeup-irqs = < + &int_power_button + &int_lid_open + >; + }; + + gpio-interrupts { + compatible = "cros-ec,gpio-interrupts"; + + int_power_button: power_button { + irq-pin = <&gpio_gsc_ec_pwr_btn_odl>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "power_button_interrupt"; + }; + int_wp_l: wp_l { + irq-pin = <&gpio_ec_wp_odl>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "switch_interrupt"; + }; + int_lid_open: lid_open { + irq-pin = <&gpio_lid_open>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "lid_interrupt"; + }; + int_tablet_mode: tablet_mode { + irq-pin = <&gpio_tablet_mode_l>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "gmr_tablet_switch_isr"; + }; + int_imu: ec_imu { + irq-pin = <&gpio_imu_int_l>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "motion_interrupt"; + }; + int_vol_down: vol_down { + irq-pin = <&gpio_voldn_btn_odl>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "button_interrupt"; + }; + int_vol_up: vol_up { + irq-pin = <&gpio_volup_btn_odl>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "button_interrupt"; + }; + int_usb_c0: usb_c0 { + irq-pin = <&gpio_usb_c0_int_odl>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "usb_interrupt"; + }; + }; + + named-gpios { + gpio_sb_2: sb_2 { + gpios = <&gpiod 4 GPIO_OUTPUT>; + no-auto-init; + }; + + gpio_sb_3: sb_3 { + gpios = <&gpiof 5 GPIO_OPEN_DRAIN>; + no-auto-init; + }; + gpio_sb_4: sb_4 { + gpios = <&gpiof 4 GPIO_INPUT>; + no-auto-init; + }; + gpio_fan_enable: fan-enable { + gpios = <&gpio6 3 GPIO_OUTPUT>; + no-auto-init; + }; + gpio_power_led: power_led { + gpios = <&gpioc 2 GPIO_OUTPUT_LOW>; + }; + gpio_led_1_odl: led_1_odl { + gpios = <&gpioc 4 GPIO_OUTPUT_LOW>; + }; + gpio_led_2_odl: led_2_odl { + gpios = <&gpioc 3 GPIO_OUTPUT_LOW>; + }; + }; + + /* + * Aliases used for sub-board GPIOs. + */ + aliases { + /* + * Sub-board with type A USB, enable. + */ + gpio-en-usb-a1-vbus = &gpio_sb_2; + /* + * HPD pins for HDMI sub-board. + */ + gpio-hdmi-en-odl = &gpio_sb_3; + gpio-hpd-odl = &gpio_sb_4; + /* + * Enable S5 rails for LTE sub-board + */ + gpio-en-sub-s5-rails = &gpio_sb_2; + }; + + temp_cpu: cpu { + compatible = "cros-ec,temp-sensor-thermistor"; + thermistor = <&thermistor_3V3_51K1_47K_4050B>; + adc = <&adc_temp_sensor_1>; + }; + temp_ddr: ddr { + compatible = "cros-ec,temp-sensor-thermistor"; + thermistor = <&thermistor_3V3_51K1_47K_4050B>; + adc = <&adc_temp_sensor_2>; + }; + temp_ambient: ambient { + compatible = "cros-ec,temp-sensor-thermistor"; + thermistor = <&thermistor_3V3_51K1_47K_4050B>; + adc = <&adc_temp_sensor_3>; + }; + + named-temp-sensors { + compatible = "cros-ec,temp-sensors"; + cpu { + temp_fan_off = <35>; + temp_fan_max = <60>; + temp_host_high = <90>; + temp_host_halt = <100>; + temp_host_release_high = <85>; + power-good-pin = <&gpio_ec_soc_dsw_pwrok>; + sensor = <&temp_cpu>; + }; + ddr { + temp_fan_off = <35>; + temp_fan_max = <60>; + temp_host_high = <90>; + temp_host_halt = <100>; + temp_host_release_high = <85>; + power-good-pin = <&gpio_ec_soc_dsw_pwrok>; + sensor = <&temp_ddr>; + }; + ambient { + temp_fan_off = <35>; + temp_fan_max = <60>; + temp_host_high = <90>; + temp_host_halt = <100>; + temp_host_release_high = <85>; + power-good-pin = <&gpio_ec_soc_dsw_pwrok>; + sensor = <&temp_ambient>; + }; + }; + + usba { + compatible = "cros-ec,usba-port-enable-pins"; + /* + * sb_2 is only configured as GPIO when USB-A1 is present, + * but it's still safe to control when disabled. + * + * ILIM_SEL pins are referred to by legacy enum name, + * GPIO_USB*_ILIM_SEL. The one for port A1 is unused on + * sub-boards that don't have USB-A so is safe to control + * regardless of system configuration. + */ + enable-pins = <&gpio_en_usb_a0_vbus &gpio_sb_2>; + status = "okay"; + }; + + usbc { + #address-cells = <1>; + #size-cells = <0>; + + port0@0 { + compatible = "named-usbc-port"; + reg = <0>; + bc12 = <&bc12_port0>; + chg = <&chg_port0>; + usb-mux-chain-0 { + compatible = "cros-ec,usb-mux-chain"; + usb-muxes = <&virtual_mux_0>; + }; + }; + port0-muxes { + virtual_mux_0: virtual-mux-0 { + compatible = "cros-ec,usbc-mux-virtual"; + }; + }; + }; + + fans { + compatible = "cros-ec,fans"; + + fan_0 { + pwms = <&pwm5 5 PWM_KHZ(1) PWM_POLARITY_NORMAL>; + rpm_min = <2200>; + rpm_start = <2200>; + rpm_max = <4200>; + tach = <&tach2>; + enable_gpio = <&gpio_fan_enable>; + }; + }; + + /* + * Declare unused GPIOs so that they are shut down + * and use minimal power + */ + unused-pins { + compatible = "unused-gpios"; + unused-gpios = + <&gpio3 3 0>, + <&gpio3 6 0>, + <&gpiod 7 0>, + <&gpiof 2 0>, + <&gpiof 3 0>; + }; +}; + +&thermistor_3V3_51K1_47K_4050B { + status = "okay"; +}; + +&adc_ec_vsense_pp3300_s5 { + /* + * Voltage divider on input has 47k upper and 220k lower legs with + * 2714 mV full-scale reading on the ADC. Apply the largest possible + * multiplier (without overflowing int32) to get the best possible + * approximation of the actual ratio, but derate by a factor of two to + * ensure unexpectedly high values won't overflow. + */ + mul = <(791261 / 2)>; + div = <(651975 / 2)>; +}; + +/* Set bus speeds for I2C */ +&i2c0_0 { + label = "I2C_EEPROM"; + clock-frequency = <I2C_BITRATE_FAST>; + + cbi_eeprom: eeprom@50 { + compatible = "atmel,at24"; + reg = <0x50>; + size = <2048>; + pagesize = <16>; + address-width = <8>; + timeout = <5>; + }; +}; + +&i2c1_0 { + label = "I2C_SENSOR"; + clock-frequency = <I2C_BITRATE_FAST>; +}; + +&i2c3_0 { + label = "I2C_USB_C0_TCPC"; + clock-frequency = <I2C_BITRATE_FAST_PLUS>; + + bc12_port0: pi3usb9201@5f { + compatible = "pericom,pi3usb9201"; + status = "okay"; + reg = <0x5f>; + /* + * BC1.2 interrupt is shared with TCPC, so + * IRQ is not specified here and handled by + * usb_c0_interrupt. + */ + }; + + chg_port0: isl923x@9 { + compatible = "intersil,isl923x"; + status = "okay"; + reg = <0x9>; + }; +}; + +&i2c7_0 { + label = "I2C_BATTERY"; + clock-frequency = <I2C_BITRATE_STANDARD>; +}; + +&pwm5_gpb7 { + drive-open-drain; +}; + +&pwm5 { + status = "okay"; + clock-bus = "NPCX_CLOCK_BUS_LFCLK"; + pinctrl-0 = <&pwm5_gpb7>; + pinctrl-names = "default"; +}; + +/* Tachometer for fan speed measurement */ +&tach2 { + status = "okay"; + pinctrl-0 = <&ta2_1_in_gp73>; + pinctrl-names = "default"; + port = <NPCX_TACH_PORT_A>; /* port-A is selected */ + sample-clk = <NPCX_TACH_FREQ_LFCLK>; /* Use LFCLK as sampling clock */ + pulses-per-round = <2>; /* number of pulses per round of encoder */ +}; + +/* host interface */ +&espi0 { + status = "okay"; + pinctrl-0 = <&espi_lpc_gp46_47_51_52_53_54_55_57>; + pinctrl-names = "default"; +}; + +/* + * Declare GPIOs that have leakage current caused by board issues here. NPCX ec + * will disable their input buffers before entering deep sleep and restore them + * after waking up automatically for better power consumption. + */ +&power_leakage_io { + leak-gpios = <&gpioa 4 0 + &gpiof 1 0>; +}; diff --git a/zephyr/projects/nissa/pujjo/power_signals.dtsi b/zephyr/projects/nissa/pujjo/power_signals.dtsi new file mode 100644 index 0000000000..1d2b23069d --- /dev/null +++ b/zephyr/projects/nissa/pujjo/power_signals.dtsi @@ -0,0 +1,220 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + chosen { + intel-ap-pwrseq,espi = &espi0; + }; + + common-pwrseq { + compatible = "intel,ap-pwrseq"; + + sys-pwrok-delay = <10>; + all-sys-pwrgd-timeout = <20>; + }; + + pwr-en-pp5000-s5 { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "PP5000_S5 enable output to regulator"; + enum-name = "PWR_EN_PP5000_A"; + gpios = <&gpio4 0 0>; + output; + }; + pwr-en-pp3300-s5 { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "PP3300_S5 enable output to LS"; + enum-name = "PWR_EN_PP3300_A"; + gpios = <&gpiob 6 0>; + output; + }; + pwr-pg-ec-rsmrst-od { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "RSMRST power good from regulator"; + enum-name = "PWR_RSMRST"; + gpios = <&gpio9 4 0>; + interrupt-flags = <GPIO_INT_EDGE_BOTH>; + }; + pwr-ec-pch-rsmrst-odl { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "RSMRST output to PCH"; + enum-name = "PWR_EC_PCH_RSMRST"; + gpios = <&gpioa 6 0>; + output; + }; + pwr-slp-s0-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SLP_S0_L input from PCH"; + enum-name = "PWR_SLP_S0"; + gpios = <&gpio9 7 GPIO_ACTIVE_LOW>; + interrupt-flags = <GPIO_INT_EDGE_BOTH>; + }; + pwr-slp-s3-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SLP_S3_L input from PCH"; + enum-name = "PWR_SLP_S3"; + gpios = <&gpioa 5 GPIO_ACTIVE_LOW>; + interrupt-flags = <GPIO_INT_EDGE_BOTH>; + }; + pwr-slp-sus-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SLP_SUS_L input from PCH"; + enum-name = "PWR_SLP_SUS"; + gpios = <&gpio6 2 GPIO_ACTIVE_LOW>; + interrupt-flags = <GPIO_INT_EDGE_BOTH>; + }; + pwr-ec-soc-dsw-pwrok { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "DSW_PWROK output to PCH"; + enum-name = "PWR_EC_SOC_DSW_PWROK"; + gpios = <&gpio6 1 0>; + output; + }; + pwr-vccst-pwrgd-od { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "VCCST_PWRGD output to PCH"; + enum-name = "PWR_VCCST_PWRGD"; + gpios = <&gpioa 4 GPIO_OPEN_DRAIN>; + output; + }; + pwr-imvp9-vrrdy-od { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "VRRDY input from IMVP9"; + enum-name = "PWR_IMVP9_VRRDY"; + gpios = <&gpio4 3 0>; + }; + pwr-pch-pwrok { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "PCH_PWROK output to PCH"; + enum-name = "PWR_PCH_PWROK"; + gpios = <&gpio7 2 GPIO_OPEN_DRAIN>; + output; + }; + pwr-ec-pch-sys-pwrok { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SYS_PWROK output to PCH"; + enum-name = "PWR_EC_PCH_SYS_PWROK"; + gpios = <&gpio3 7 0>; + output; + }; + pwr-sys-rst-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SYS_RESET# output to PCH"; + enum-name = "PWR_SYS_RST"; + gpios = <&gpioc 5 (GPIO_ACTIVE_LOW|GPIO_OPEN_DRAIN)>; + output; + }; + pwr-slp-s4 { + compatible = "intel,ap-pwrseq-vw"; + dbg-label = "SLP_S4 virtual wire input from PCH"; + enum-name = "PWR_SLP_S4"; + virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S4"; + vw-invert; + }; + pwr-slp-s5 { + compatible = "intel,ap-pwrseq-vw"; + dbg-label = "SLP_S5 virtual wire input from PCH"; + enum-name = "PWR_SLP_S5"; + virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S5"; + vw-invert; + }; + pwr-all-sys-pwrgd { + compatible = "intel,ap-pwrseq-external"; + dbg-label = "Combined all power good"; + enum-name = "PWR_ALL_SYS_PWRGD"; + }; + pwr-adc-pp3300 { + compatible = "intel,ap-pwrseq-adc"; + dbg-label = "PP3300 PWROK (from ADC)"; + enum-name = "PWR_DSW_PWROK"; + trigger-high = <&cmp_pp3300_s5_high>; + trigger-low = <&cmp_pp3300_s5_low>; + }; + pwr-adc-pp1p05 { + compatible = "intel,ap-pwrseq-adc"; + dbg-label = "PP1P05 PWROK (from ADC)"; + enum-name = "PWR_PG_PP1P05"; + trigger-high = <&cmp_pp1p05_high>; + trigger-low = <&cmp_pp1p05_low>; + }; + + adc-cmp { + cmp_pp3300_s5_high: pp3300_high { + compatible = "nuvoton,adc-cmp"; + io-channels = <&adc0 6>; + comparison = "ADC_CMP_NPCX_GREATER"; + /* + * This is 90% of nominal voltage considering voltage + * divider on ADC input. + */ + threshold-mv = <2448>; + }; + cmp_pp3300_s5_low: pp3300_low { + compatible = "nuvoton,adc-cmp"; + io-channels = <&adc0 6>; + comparison = "ADC_CMP_NPCX_LESS_OR_EQUAL"; + threshold-mv = <2448>; + }; + cmp_pp1p05_high: pp1p05_high { + compatible = "nuvoton,adc-cmp"; + io-channels = <&adc0 4>; + comparison = "ADC_CMP_NPCX_GREATER"; + /* Setting at 90% of nominal voltage */ + threshold-mv = <945>; + }; + cmp_pp1p05_low: pp1p05_low { + compatible = "nuvoton,adc-cmp"; + io-channels = <&adc0 4>; + comparison = "ADC_CMP_NPCX_LESS_OR_EQUAL"; + threshold-mv = <945>; + }; + }; +}; + +/* + * Because the power signals directly reference the GPIOs, + * the correspinding named-gpios need to have no-auto-init set. + */ +&gpio_ec_soc_dsw_pwrok { + no-auto-init; +}; +&gpio_ec_soc_pch_pwrok_od { + no-auto-init; +}; +&gpio_ec_soc_rsmrst_l { + no-auto-init; +}; +&gpio_ec_soc_sys_pwrok { + no-auto-init; +}; +&gpio_ec_soc_vccst_pwrgd_od { + no-auto-init; +}; +&gpio_en_pp3300_s5 { + no-auto-init; +}; +&gpio_en_pp5000_s5 { + no-auto-init; +}; +&gpio_imvp91_vrrdy_od { + no-auto-init; +}; +&gpio_rsmrst_pwrgd_l { + no-auto-init; +}; +&gpio_slp_s0_l { + no-auto-init; +}; +&gpio_slp_s3_l { + no-auto-init; +}; +&gpio_slp_s4_l { + no-auto-init; +}; +&gpio_slp_sus_l { + no-auto-init; +}; +&gpio_sys_rst_odl { + no-auto-init; +}; diff --git a/zephyr/projects/nissa/pujjo/project.conf b/zephyr/projects/nissa/pujjo/project.conf new file mode 100644 index 0000000000..b9dc28b9cd --- /dev/null +++ b/zephyr/projects/nissa/pujjo/project.conf @@ -0,0 +1,33 @@ +# Copyright 2022 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +CONFIG_BOARD_PUJJO=y + +# Sensor drivers +CONFIG_PLATFORM_EC_ACCELGYRO_LSM6DSM=y +CONFIG_PLATFORM_EC_ACCEL_BMA4XX=y +CONFIG_PLATFORM_EC_ACCELGYRO_BMI_COMM_I2C=y +CONFIG_PLATFORM_EC_ACCELGYRO_BMI3XX=y +CONFIG_PLATFORM_EC_DYNAMIC_MOTION_SENSOR_COUNT=y + +# Increase PD max power from default +CONFIG_PLATFORM_EC_PD_MAX_POWER_MW=65000 +CONFIG_PLATFORM_EC_PD_MAX_CURRENT_MA=3250 + +# LED +CONFIG_PLATFORM_EC_LED_PWM=n +CONFIG_PLATFORM_EC_LED_COMMON=y + +# CBI +CONFIG_PLATFORM_EC_BYPASS_CBI_EEPROM_WP_CHECK=y +CONFIG_PLATFORM_EC_SYSTEM_UNLOCKED=y + +# DPS +CONFIG_PLATFORM_EC_USB_PD_DPS=n + +# BTN +CONFIG_PLATFORM_EC_BUTTONS_RUNTIME_CONFIG=y + +# Charger +CONFIG_PLATFORM_EC_RAA489000_TRICKLE_CHARGE_CURRENT_256MA=y
\ No newline at end of file diff --git a/zephyr/projects/nissa/pujjo/project.overlay b/zephyr/projects/nissa/pujjo/project.overlay new file mode 100644 index 0000000000..e498775714 --- /dev/null +++ b/zephyr/projects/nissa/pujjo/project.overlay @@ -0,0 +1,13 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "../cbi.dtsi" + +#include "cbi.dtsi" +#include "generated.dtsi" +#include "keyboard.dtsi" +#include "motionsense.dtsi" +#include "overlay.dtsi" +#include "power_signals.dtsi" diff --git a/zephyr/projects/nissa/pujjo/pujjo_vif.xml b/zephyr/projects/nissa/pujjo/pujjo_vif.xml new file mode 100644 index 0000000000..b7d462584a --- /dev/null +++ b/zephyr/projects/nissa/pujjo/pujjo_vif.xml @@ -0,0 +1,350 @@ +<?xml version="1.0" encoding="utf-8"?>
+<vif:VIF xmlns:opt="http://usb.org/VendorInfoFileOptionalContent.xsd" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:vif="http://usb.org/VendorInfoFile.xsd">
+ <vif:VIF_Specification>3.19</vif:VIF_Specification>
+ <vif:VIF_App>
+ <vif:Vendor>USB-IF</vif:Vendor>
+ <vif:Name>VIF Editor</vif:Name>
+ <vif:Version>3.2.4.0</vif:Version>
+ </vif:VIF_App>
+ <vif:Vendor_Name>Google</vif:Vendor_Name>
+ <vif:Model_Part_Number>Pujjo</vif:Model_Part_Number>
+ <vif:Product_Revision>1</vif:Product_Revision>
+ <vif:TID>0</vif:TID>
+ <vif:VIF_Product_Type value="0">Port Product</vif:VIF_Product_Type>
+ <vif:Certification_Type value="0">End Product</vif:Certification_Type>
+ <vif:Product>
+ <!--Product Level Content:-->
+ </vif:Product>
+ <vif:Component>
+ <!--Component 0: Port 0-->
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <!--;Component-->
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <vif:Port_Label>0</vif:Port_Label>
+ <vif:Connector_Type value="2">Type-C®</vif:Connector_Type>
+ <vif:USB4_Supported value="false" />
+ <vif:USB_PD_Support value="true" />
+ <vif:PD_Port_Type value="4">DRP</vif:PD_Port_Type>
+ <vif:Type_C_State_Machine value="2">DRP</vif:Type_C_State_Machine>
+ <vif:Port_Battery_Powered value="true" />
+ <vif:BC_1_2_Support value="2">Charging Port</vif:BC_1_2_Support>
+ <vif:Captive_Cable value="false" />
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <!--;General PD-->
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <vif:PD_Spec_Revision_Major value="3" />
+ <vif:PD_Spec_Revision_Minor value="1" />
+ <vif:PD_Spec_Version_Major value="1" />
+ <vif:PD_Spec_Version_Minor value="3" />
+ <vif:PD_Specification_Revision value="2">Revision 3</vif:PD_Specification_Revision>
+ <vif:SOP_Capable value="true" />
+ <vif:SOP_P_Capable value="true" />
+ <vif:SOP_PP_Capable value="true" />
+ <vif:SOP_P_Debug_Capable value="false" />
+ <vif:SOP_PP_Debug_Capable value="false" />
+ <vif:Manufacturer_Info_Supported_Port value="true" />
+ <vif:Manufacturer_Info_VID_Port value="6353">18D1</vif:Manufacturer_Info_VID_Port>
+ <vif:Manufacturer_Info_PID_Port value="20570">505A</vif:Manufacturer_Info_PID_Port>
+ <vif:Chunking_Implemented_SOP value="true" />
+ <vif:Unchunked_Extended_Messages_Supported value="false" />
+ <vif:Security_Msgs_Supported_SOP value="false" />
+ <vif:Unconstrained_Power value="false" />
+ <vif:Num_Fixed_Batteries value="1" />
+ <vif:Num_Swappable_Battery_Slots value="0" />
+ <vif:ID_Header_Connector_Type_SOP value="2">USB Type-C® Receptacle</vif:ID_Header_Connector_Type_SOP>
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <!--;PD Capabilities-->
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <vif:USB_Comms_Capable value="true" />
+ <vif:DR_Swap_To_DFP_Supported value="true" />
+ <vif:DR_Swap_To_UFP_Supported value="false" />
+ <vif:VCONN_Swap_To_On_Supported value="true" />
+ <vif:VCONN_Swap_To_Off_Supported value="true" />
+ <vif:Responds_To_Discov_SOP_UFP value="false" />
+ <vif:Responds_To_Discov_SOP_DFP value="true" />
+ <vif:Attempts_Discov_SOP value="true" />
+ <vif:Power_Interruption_Available value="0">No Interruption Possible</vif:Power_Interruption_Available>
+ <vif:Data_Reset_Supported value="false" />
+ <vif:Enter_USB_Supported value="false" />
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <!--;USB Type-C®-->
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <vif:Type_C_Can_Act_As_Host value="true" />
+ <vif:Type_C_Can_Act_As_Device value="false" />
+ <vif:Type_C_Implements_Try_SRC value="true" />
+ <vif:Type_C_Implements_Try_SNK value="false" />
+ <vif:Type_C_Supports_Audio_Accessory value="false" />
+ <vif:Type_C_Is_VCONN_Powered_Accessory value="false" />
+ <vif:Type_C_Is_Debug_Target_SRC value="true" />
+ <vif:Type_C_Is_Debug_Target_SNK value="true" />
+ <vif:RP_Value value="1">1.5A</vif:RP_Value>
+ <vif:Type_C_Port_On_Hub value="false" />
+ <vif:Type_C_Power_Source value="2">Both</vif:Type_C_Power_Source>
+ <vif:Type_C_Sources_VCONN value="true" />
+ <vif:Type_C_Is_Alt_Mode_Controller value="true" />
+ <vif:Type_C_Is_Alt_Mode_Adapter value="false" />
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <!--;Product Power-->
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <vif:Product_Total_Source_Power_mW value="15000">15000 mW</vif:Product_Total_Source_Power_mW>
+ <vif:Port_Source_Power_Type value="0">Assured</vif:Port_Source_Power_Type>
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <!--;USB Host-->
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <vif:Host_Supports_USB_Data value="true" />
+ <vif:Host_Speed value="1">USB 3.2 Gen 1x1</vif:Host_Speed>
+ <vif:Host_Contains_Captive_Retimer value="false" />
+ <vif:Host_Truncates_DP_For_tDHPResponse value="false" />
+ <vif:Host_Is_Embedded value="false" />
+ <vif:Host_Suspend_Supported value="true" />
+ <vif:Is_DFP_On_Hub value="false" />
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <!--;Battery Charging 1.2-->
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <vif:BC_1_2_Charging_Port_Type value="1">CDP</vif:BC_1_2_Charging_Port_Type>
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <!--;PD Source-->
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <vif:PD_Power_As_Source value="15000">15000 mW</vif:PD_Power_As_Source>
+ <vif:EPR_Supported_As_Src value="false" />
+ <vif:USB_Suspend_May_Be_Cleared value="false" />
+ <vif:Sends_Pings value="false" />
+ <vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink value="0">FR_Swap not supported</vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink>
+ <vif:Master_Port value="false" />
+ <vif:Num_Src_PDOs value="1" />
+ <vif:PD_OC_Protection value="true" />
+ <vif:PD_OCP_Method value="0">Over-Current Response</vif:PD_OCP_Method>
+ <!--Bundle: SrcPdoList-->
+ <vif:SrcPdoList>
+ <vif:SrcPDO>
+ <!--Source PDO 1-->
+ <vif:Src_PDO_Supply_Type value="0">Fixed</vif:Src_PDO_Supply_Type>
+ <vif:Src_PDO_Peak_Current value="0">100% IOC</vif:Src_PDO_Peak_Current>
+ <vif:Src_PDO_Voltage value="100">5000 mV</vif:Src_PDO_Voltage>
+ <vif:Src_PDO_Max_Current value="300">3000 mA</vif:Src_PDO_Max_Current>
+ <vif:Src_PD_OCP_OC_Debounce value="0">0 msec</vif:Src_PD_OCP_OC_Debounce>
+ <vif:Src_PD_OCP_OC_Threshold value="300">3000 mA</vif:Src_PD_OCP_OC_Threshold>
+ </vif:SrcPDO>
+ </vif:SrcPdoList>
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <!--;PD Sink-->
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <vif:PD_Power_As_Sink value="60000">60000 mW</vif:PD_Power_As_Sink>
+ <vif:EPR_Supported_As_Snk value="false" />
+ <vif:No_USB_Suspend_May_Be_Set value="true" />
+ <vif:GiveBack_May_Be_Set value="false" />
+ <vif:Higher_Capability_Set value="false" />
+ <vif:FR_Swap_Reqd_Type_C_Current_As_Initial_Source value="0">FR_Swap not supported</vif:FR_Swap_Reqd_Type_C_Current_As_Initial_Source>
+ <vif:Num_Snk_PDOs value="3" />
+ <!--Bundle: SnkPdoList-->
+ <vif:SnkPdoList>
+ <vif:SnkPDO>
+ <!--Sink PDO 1-->
+ <vif:Snk_PDO_Supply_Type value="0">Fixed</vif:Snk_PDO_Supply_Type>
+ <vif:Snk_PDO_Voltage value="100">5000 mV</vif:Snk_PDO_Voltage>
+ <vif:Snk_PDO_Op_Current value="300">3000 mA</vif:Snk_PDO_Op_Current>
+ </vif:SnkPDO>
+ <vif:SnkPDO>
+ <!--Sink PDO 2-->
+ <vif:Snk_PDO_Supply_Type value="1">Battery</vif:Snk_PDO_Supply_Type>
+ <vif:Snk_PDO_Op_Power value="60">15000 mW</vif:Snk_PDO_Op_Power>
+ <vif:Snk_PDO_Min_Voltage value="95">4750 mV</vif:Snk_PDO_Min_Voltage>
+ <vif:Snk_PDO_Max_Voltage value="400">20000 mV</vif:Snk_PDO_Max_Voltage>
+ </vif:SnkPDO>
+ <vif:SnkPDO>
+ <!--Sink PDO 3-->
+ <vif:Snk_PDO_Supply_Type value="2">Variable</vif:Snk_PDO_Supply_Type>
+ <vif:Snk_PDO_Min_Voltage value="95">4750 mV</vif:Snk_PDO_Min_Voltage>
+ <vif:Snk_PDO_Max_Voltage value="400">20000 mV</vif:Snk_PDO_Max_Voltage>
+ <vif:Snk_PDO_Op_Current value="300">3000 mA</vif:Snk_PDO_Op_Current>
+ </vif:SnkPDO>
+ </vif:SnkPdoList>
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <!--;Dual Role-->
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <vif:Accepts_PR_Swap_As_Src value="true" />
+ <vif:Accepts_PR_Swap_As_Snk value="true" />
+ <vif:Requests_PR_Swap_As_Src value="true" />
+ <vif:Requests_PR_Swap_As_Snk value="true" />
+ <vif:FR_Swap_Supported_As_Initial_Sink value="false" />
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <!--;SOP Discover ID-->
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <vif:XID_SOP value="0" />
+ <vif:Data_Capable_As_USB_Host_SOP value="true" />
+ <vif:Data_Capable_As_USB_Device_SOP value="false" />
+ <vif:Product_Type_UFP_SOP value="0">Undefined</vif:Product_Type_UFP_SOP>
+ <vif:Product_Type_DFP_SOP value="2">PDUSB Host</vif:Product_Type_DFP_SOP>
+ <vif:DFP_VDO_Port_Number value="0" />
+ <vif:Modal_Operation_Supported_SOP value="false" />
+ <vif:USB_VID_SOP value="6353">18D1</vif:USB_VID_SOP>
+ <vif:PID_SOP value="20570">505A</vif:PID_SOP>
+ <vif:bcdDevice_SOP value="0">0000</vif:bcdDevice_SOP>
+ </vif:Component>
+ <vif:Component>
+ <!--Component 1: Port 1-->
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <!--;Component-->
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <vif:Port_Label>1</vif:Port_Label>
+ <vif:Connector_Type value="2">Type-C®</vif:Connector_Type>
+ <vif:USB4_Supported value="false" />
+ <vif:USB_PD_Support value="true" />
+ <vif:PD_Port_Type value="4">DRP</vif:PD_Port_Type>
+ <vif:Type_C_State_Machine value="2">DRP</vif:Type_C_State_Machine>
+ <vif:Port_Battery_Powered value="true" />
+ <vif:BC_1_2_Support value="2">Charging Port</vif:BC_1_2_Support>
+ <vif:Captive_Cable value="false" />
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <!--;General PD-->
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <vif:PD_Spec_Revision_Major value="3" />
+ <vif:PD_Spec_Revision_Minor value="1" />
+ <vif:PD_Spec_Version_Major value="1" />
+ <vif:PD_Spec_Version_Minor value="3" />
+ <vif:PD_Specification_Revision value="2">Revision 3</vif:PD_Specification_Revision>
+ <vif:SOP_Capable value="true" />
+ <vif:SOP_P_Capable value="true" />
+ <vif:SOP_PP_Capable value="true" />
+ <vif:SOP_P_Debug_Capable value="false" />
+ <vif:SOP_PP_Debug_Capable value="false" />
+ <vif:Manufacturer_Info_Supported_Port value="true" />
+ <vif:Manufacturer_Info_VID_Port value="6353">18D1</vif:Manufacturer_Info_VID_Port>
+ <vif:Manufacturer_Info_PID_Port value="20570">505A</vif:Manufacturer_Info_PID_Port>
+ <vif:Chunking_Implemented_SOP value="true" />
+ <vif:Unchunked_Extended_Messages_Supported value="false" />
+ <vif:Security_Msgs_Supported_SOP value="false" />
+ <vif:Unconstrained_Power value="false" />
+ <vif:Num_Fixed_Batteries value="1" />
+ <vif:Num_Swappable_Battery_Slots value="0" />
+ <vif:ID_Header_Connector_Type_SOP value="2">USB Type-C® Receptacle</vif:ID_Header_Connector_Type_SOP>
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <!--;PD Capabilities-->
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <vif:USB_Comms_Capable value="true" />
+ <vif:DR_Swap_To_DFP_Supported value="true" />
+ <vif:DR_Swap_To_UFP_Supported value="false" />
+ <vif:VCONN_Swap_To_On_Supported value="true" />
+ <vif:VCONN_Swap_To_Off_Supported value="true" />
+ <vif:Responds_To_Discov_SOP_UFP value="false" />
+ <vif:Responds_To_Discov_SOP_DFP value="true" />
+ <vif:Attempts_Discov_SOP value="true" />
+ <vif:Power_Interruption_Available value="0">No Interruption Possible</vif:Power_Interruption_Available>
+ <vif:Data_Reset_Supported value="false" />
+ <vif:Enter_USB_Supported value="false" />
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <!--;USB Type-C®-->
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <vif:Type_C_Can_Act_As_Host value="true" />
+ <vif:Type_C_Can_Act_As_Device value="false" />
+ <vif:Type_C_Implements_Try_SRC value="true" />
+ <vif:Type_C_Implements_Try_SNK value="false" />
+ <vif:Type_C_Supports_Audio_Accessory value="false" />
+ <vif:Type_C_Is_VCONN_Powered_Accessory value="false" />
+ <vif:Type_C_Is_Debug_Target_SRC value="true" />
+ <vif:Type_C_Is_Debug_Target_SNK value="true" />
+ <vif:RP_Value value="1">1.5A</vif:RP_Value>
+ <vif:Type_C_Port_On_Hub value="false" />
+ <vif:Type_C_Power_Source value="2">Both</vif:Type_C_Power_Source>
+ <vif:Type_C_Sources_VCONN value="true" />
+ <vif:Type_C_Is_Alt_Mode_Controller value="true" />
+ <vif:Type_C_Is_Alt_Mode_Adapter value="false" />
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <!--;Product Power-->
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <vif:Product_Total_Source_Power_mW value="15000">15000 mW</vif:Product_Total_Source_Power_mW>
+ <vif:Port_Source_Power_Type value="0">Assured</vif:Port_Source_Power_Type>
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <!--;USB Host-->
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <vif:Host_Supports_USB_Data value="true" />
+ <vif:Host_Speed value="1">USB 3.2 Gen 1x1</vif:Host_Speed>
+ <vif:Host_Contains_Captive_Retimer value="true" />
+ <vif:Host_Truncates_DP_For_tDHPResponse value="false" />
+ <vif:Host_Is_Embedded value="false" />
+ <vif:Host_Suspend_Supported value="true" />
+ <vif:Is_DFP_On_Hub value="false" />
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <!--;Battery Charging 1.2-->
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <vif:BC_1_2_Charging_Port_Type value="1">CDP</vif:BC_1_2_Charging_Port_Type>
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <!--;PD Source-->
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <vif:PD_Power_As_Source value="15000">15000 mW</vif:PD_Power_As_Source>
+ <vif:EPR_Supported_As_Src value="false" />
+ <vif:USB_Suspend_May_Be_Cleared value="false" />
+ <vif:Sends_Pings value="false" />
+ <vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink value="0">FR_Swap not supported</vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink>
+ <vif:Master_Port value="false" />
+ <vif:Num_Src_PDOs value="1" />
+ <vif:PD_OC_Protection value="true" />
+ <vif:PD_OCP_Method value="0">Over-Current Response</vif:PD_OCP_Method>
+ <!--Bundle: SrcPdoList-->
+ <vif:SrcPdoList>
+ <vif:SrcPDO>
+ <!--Source PDO 1-->
+ <vif:Src_PDO_Supply_Type value="0">Fixed</vif:Src_PDO_Supply_Type>
+ <vif:Src_PDO_Peak_Current value="0">100% IOC</vif:Src_PDO_Peak_Current>
+ <vif:Src_PDO_Voltage value="100">5000 mV</vif:Src_PDO_Voltage>
+ <vif:Src_PDO_Max_Current value="300">3000 mA</vif:Src_PDO_Max_Current>
+ <vif:Src_PD_OCP_OC_Debounce value="0">0 msec</vif:Src_PD_OCP_OC_Debounce>
+ <vif:Src_PD_OCP_OC_Threshold value="300">3000 mA</vif:Src_PD_OCP_OC_Threshold>
+ </vif:SrcPDO>
+ </vif:SrcPdoList>
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <!--;PD Sink-->
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <vif:PD_Power_As_Sink value="60000">60000 mW</vif:PD_Power_As_Sink>
+ <vif:EPR_Supported_As_Snk value="false" />
+ <vif:No_USB_Suspend_May_Be_Set value="true" />
+ <vif:GiveBack_May_Be_Set value="false" />
+ <vif:Higher_Capability_Set value="false" />
+ <vif:FR_Swap_Reqd_Type_C_Current_As_Initial_Source value="0">FR_Swap not supported</vif:FR_Swap_Reqd_Type_C_Current_As_Initial_Source>
+ <vif:Num_Snk_PDOs value="3" />
+ <!--Bundle: SnkPdoList-->
+ <vif:SnkPdoList>
+ <vif:SnkPDO>
+ <!--Sink PDO 1-->
+ <vif:Snk_PDO_Supply_Type value="0">Fixed</vif:Snk_PDO_Supply_Type>
+ <vif:Snk_PDO_Voltage value="100">5000 mV</vif:Snk_PDO_Voltage>
+ <vif:Snk_PDO_Op_Current value="300">3000 mA</vif:Snk_PDO_Op_Current>
+ </vif:SnkPDO>
+ <vif:SnkPDO>
+ <!--Sink PDO 2-->
+ <vif:Snk_PDO_Supply_Type value="1">Battery</vif:Snk_PDO_Supply_Type>
+ <vif:Snk_PDO_Op_Power value="60">15000 mW</vif:Snk_PDO_Op_Power>
+ <vif:Snk_PDO_Min_Voltage value="95">4750 mV</vif:Snk_PDO_Min_Voltage>
+ <vif:Snk_PDO_Max_Voltage value="400">20000 mV</vif:Snk_PDO_Max_Voltage>
+ </vif:SnkPDO>
+ <vif:SnkPDO>
+ <!--Sink PDO 3-->
+ <vif:Snk_PDO_Supply_Type value="2">Variable</vif:Snk_PDO_Supply_Type>
+ <vif:Snk_PDO_Min_Voltage value="95">4750 mV</vif:Snk_PDO_Min_Voltage>
+ <vif:Snk_PDO_Max_Voltage value="400">20000 mV</vif:Snk_PDO_Max_Voltage>
+ <vif:Snk_PDO_Op_Current value="300">3000 mA</vif:Snk_PDO_Op_Current>
+ </vif:SnkPDO>
+ </vif:SnkPdoList>
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <!--;Dual Role-->
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <vif:Accepts_PR_Swap_As_Src value="true" />
+ <vif:Accepts_PR_Swap_As_Snk value="true" />
+ <vif:Requests_PR_Swap_As_Src value="true" />
+ <vif:Requests_PR_Swap_As_Snk value="true" />
+ <vif:FR_Swap_Supported_As_Initial_Sink value="false" />
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <!--;SOP Discover ID-->
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <vif:XID_SOP value="0" />
+ <vif:Data_Capable_As_USB_Host_SOP value="true" />
+ <vif:Data_Capable_As_USB_Device_SOP value="false" />
+ <vif:Product_Type_UFP_SOP value="0">Undefined</vif:Product_Type_UFP_SOP>
+ <vif:Product_Type_DFP_SOP value="2">PDUSB Host</vif:Product_Type_DFP_SOP>
+ <vif:DFP_VDO_Port_Number value="1" />
+ <vif:Modal_Operation_Supported_SOP value="false" />
+ <vif:USB_VID_SOP value="6353">18D1</vif:USB_VID_SOP>
+ <vif:PID_SOP value="20570">505A</vif:PID_SOP>
+ <vif:bcdDevice_SOP value="0">0000</vif:bcdDevice_SOP>
+ </vif:Component>
+</vif:VIF>
\ No newline at end of file diff --git a/zephyr/projects/nissa/pujjo/src/charger.c b/zephyr/projects/nissa/pujjo/src/charger.c new file mode 100644 index 0000000000..f1f1d57790 --- /dev/null +++ b/zephyr/projects/nissa/pujjo/src/charger.c @@ -0,0 +1,64 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <zephyr/logging/log.h> + +#include "battery.h" +#include "charger.h" +#include "charger/isl923x_public.h" +#include "driver/tcpm/raa489000.h" +#include "driver/charger/isl923x.h" +#include "console.h" +#include "extpower.h" +#include "usb_pd.h" +#include "nissa_common.h" +#include "hooks.h" + +LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL); + +int extpower_is_present(void) +{ + int port; + int rv; + bool acok; + + for (port = 0; port < board_get_usb_pd_port_count(); port++) { + rv = raa489000_is_acok(port, &acok); + if ((rv == EC_SUCCESS) && acok) + return 1; + } + + return 0; +} + +/* + * Pujjo does not have a GPIO indicating whether extpower is present, + * so detect using the charger(s). + */ +__override void board_check_extpower(void) +{ + static int last_extpower_present; + int extpower_present = extpower_is_present(); + + if (last_extpower_present ^ extpower_present) + extpower_handle_update(extpower_present); + + last_extpower_present = extpower_present; +} + +__override void board_hibernate(void) +{ + /* Shut down the chargers */ + raa489000_hibernate(0, true); + LOG_INF("Charger(s) hibernated"); + cflush(); +} + +static void charger_prochot_init(void) +{ + isl923x_set_ac_prochot(CHARGER_SOLO, 3500); + isl923x_set_dc_prochot(CHARGER_SOLO, 6528); +} +DECLARE_HOOK(HOOK_INIT, charger_prochot_init, HOOK_PRIO_POST_FIRST); diff --git a/zephyr/projects/nissa/pujjo/src/fan.c b/zephyr/projects/nissa/pujjo/src/fan.c new file mode 100644 index 0000000000..97323a7edf --- /dev/null +++ b/zephyr/projects/nissa/pujjo/src/fan.c @@ -0,0 +1,43 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <zephyr/devicetree.h> +#include <zephyr/drivers/gpio.h> +#include <zephyr/logging/log.h> + +#include "cros_cbi.h" +#include "fan.h" +#include "gpio/gpio.h" +#include "hooks.h" + +#include "nissa_common.h" + +LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL); + +/* + * Pujjo fan support + */ +static void fan_init(void) +{ + int ret; + uint32_t val; + /* + * Retrieve the fan config. + */ + ret = cros_cbi_get_fw_config(FW_FAN, &val); + if (ret != 0) { + LOG_ERR("Error retrieving CBI FW_CONFIG field %d", FW_FAN); + return; + } + if (val != FW_FAN_PRESENT) { + /* Disable the fan */ + fan_set_count(0); + } else { + /* Configure the fan enable GPIO */ + gpio_pin_configure_dt(GPIO_DT_FROM_NODELABEL(gpio_fan_enable), + GPIO_OUTPUT); + } +} +DECLARE_HOOK(HOOK_INIT, fan_init, HOOK_PRIO_POST_FIRST); diff --git a/zephyr/projects/nissa/pujjo/src/form_factor.c b/zephyr/projects/nissa/pujjo/src/form_factor.c new file mode 100644 index 0000000000..6b02a258bc --- /dev/null +++ b/zephyr/projects/nissa/pujjo/src/form_factor.c @@ -0,0 +1,66 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <zephyr/devicetree.h> +#include <zephyr/logging/log.h> + +#include "accelgyro.h" +#include "button.h" +#include "cros_board_info.h" +#include "cros_cbi.h" +#include "driver/accelgyro_bmi323.h" +#include "driver/accelgyro_lsm6dsm.h" +#include "gpio/gpio_int.h" +#include "hooks.h" +#include "motionsense_sensors.h" +#include "motion_sense.h" +#include "tablet_mode.h" + +#include "nissa_common.h" + +LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL); + +static bool use_alt_sensor; + +void motion_interrupt(enum gpio_signal signal) +{ + if (use_alt_sensor) + lsm6dsm_interrupt(signal); + else + bmi3xx_interrupt(signal); +} + +static void sensor_init(void) +{ + int ret; + uint32_t val; + /* check which base sensor is used for motion_interrupt */ + use_alt_sensor = cros_cbi_ssfc_check_match( + CBI_SSFC_VALUE_ID(DT_NODELABEL(base_sensor_1))); + + motion_sensors_check_ssfc(); + + /* Check if it's tablet or not */ + ret = cros_cbi_get_fw_config(FW_TABLET, &val); + if (ret != 0) { + LOG_ERR("Error retrieving CBI FW_CONFIG field %d", FW_TABLET); + return; + } + if (val == FW_TABLET_NOT_PRESENT) { + LOG_INF("Clamshell: disable motionsense function."); + motion_sensor_count = 0; + gmr_tablet_switch_disable(); + gpio_disable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_imu)); + gpio_pin_configure_dt(GPIO_DT_FROM_NODELABEL(gpio_imu_int_l), + GPIO_DISCONNECTED); + + LOG_INF("Clamshell: disable volume button function."); + button_disable_gpio(BUTTON_VOLUME_UP); + button_disable_gpio(BUTTON_VOLUME_DOWN); + } else { + LOG_INF("Tablet: Enable motionsense function."); + } +} +DECLARE_HOOK(HOOK_INIT, sensor_init, HOOK_PRIO_POST_I2C); diff --git a/zephyr/projects/nissa/pujjo/src/hdmi.c b/zephyr/projects/nissa/pujjo/src/hdmi.c new file mode 100644 index 0000000000..9461e7c53e --- /dev/null +++ b/zephyr/projects/nissa/pujjo/src/hdmi.c @@ -0,0 +1,12 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "nissa_hdmi.h" + +__override void nissa_configure_hdmi_power_gpios(void) +{ + /* Pujjo needs to drive VCC enable but not core rails */ + nissa_configure_hdmi_vcc(); +} diff --git a/zephyr/projects/nissa/pujjo/src/keyboard.c b/zephyr/projects/nissa/pujjo/src/keyboard.c new file mode 100644 index 0000000000..1587030080 --- /dev/null +++ b/zephyr/projects/nissa/pujjo/src/keyboard.c @@ -0,0 +1,29 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "ec_commands.h" + +static const struct ec_response_keybd_config pujjo_kb = { + .num_top_row_keys = 10, + .action_keys = { + TK_BACK, /* T1 */ + TK_REFRESH, /* T2 */ + TK_FULLSCREEN, /* T3 */ + TK_OVERVIEW, /* T4 */ + TK_BRIGHTNESS_DOWN, /* T5 */ + TK_BRIGHTNESS_UP, /* T6 */ + TK_MICMUTE, /* T7 */ + TK_VOL_MUTE, /* T8 */ + TK_VOL_DOWN, /* T9 */ + TK_VOL_UP, /* T10 */ + }, + .capabilities = KEYBD_CAP_SCRNLOCK_KEY, +}; + +__override const struct ec_response_keybd_config * +board_vivaldi_keybd_config(void) +{ + return &pujjo_kb; +} diff --git a/zephyr/projects/nissa/pujjo/src/led.c b/zephyr/projects/nissa/pujjo/src/led.c new file mode 100644 index 0000000000..bd04af5a25 --- /dev/null +++ b/zephyr/projects/nissa/pujjo/src/led.c @@ -0,0 +1,134 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Pujjo specific PWM LED settings: there are 2 LEDs on each side of the board, + * each one can be controlled separately. The LED colors are white or amber, + * and the default behavior is tied to the charging process: both sides are + * amber while charging the battery and white when the battery is charged. + */ + +#include "common.h" +#include "led_onoff_states.h" +#include "led_common.h" +#include "gpio.h" + +#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args) + +#define LED_OFF_LVL 1 +#define LED_ON_LVL 0 + +__override const int led_charge_lvl_1 = 5; + +__override const int led_charge_lvl_2 = 97; + +__override struct led_descriptor + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED, + LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 2 * LED_ONE_SEC }, + { EC_LED_COLOR_GREEN, + 2 * LED_ONE_SEC } }, + }; + +__override const struct led_descriptor + led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { + [PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } }, + [PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE, + 3 * LED_ONE_SEC }, + { LED_OFF, 0.5 * LED_ONE_SEC } }, + [PWR_LED_STATE_SUSPEND_NO_AC] = { { EC_LED_COLOR_WHITE, + 3 * LED_ONE_SEC }, + { LED_OFF, + 0.5 * LED_ONE_SEC } }, + [PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } }, + }; + +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED, + EC_LED_ID_POWER_LED }; + +const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); + +__override void led_set_color_power(enum ec_led_colors color) +{ + if (color == EC_LED_COLOR_WHITE) + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_power_led), + LED_ON_LVL); + else + /* LED_OFF and unsupported colors */ + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_power_led), + LED_OFF_LVL); +} + +__override void led_set_color_battery(enum ec_led_colors color) +{ + switch (color) { + case EC_LED_COLOR_AMBER: + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_led_1_odl), + LED_ON_LVL); + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_led_2_odl), + LED_ON_LVL); + break; + case EC_LED_COLOR_RED: + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_led_1_odl), + LED_ON_LVL); + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_led_2_odl), + LED_OFF_LVL); + break; + case EC_LED_COLOR_GREEN: + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_led_1_odl), + LED_OFF_LVL); + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_led_2_odl), + LED_ON_LVL); + break; + default: /* LED_OFF and other unsupported colors */ + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_led_1_odl), + LED_OFF_LVL); + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_led_2_odl), + LED_OFF_LVL); + break; + } +} + +void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range) +{ + if (led_id == EC_LED_ID_BATTERY_LED) { + brightness_range[EC_LED_COLOR_RED] = 1; + brightness_range[EC_LED_COLOR_AMBER] = 1; + brightness_range[EC_LED_COLOR_GREEN] = 1; + } else if (led_id == EC_LED_ID_POWER_LED) { + brightness_range[EC_LED_COLOR_WHITE] = 1; + } +} + +int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness) +{ + if (led_id == EC_LED_ID_BATTERY_LED) { + if (brightness[EC_LED_COLOR_RED] != 0) + led_set_color_battery(EC_LED_COLOR_RED); + else if (brightness[EC_LED_COLOR_AMBER] != 0) + led_set_color_battery(EC_LED_COLOR_AMBER); + else if (brightness[EC_LED_COLOR_GREEN] != 0) + led_set_color_battery(EC_LED_COLOR_GREEN); + else + led_set_color_battery(LED_OFF); + } else if (led_id == EC_LED_ID_POWER_LED) { + if (brightness[EC_LED_COLOR_WHITE] != 0) + led_set_color_power(EC_LED_COLOR_WHITE); + else + led_set_color_power(LED_OFF); + } + + return EC_SUCCESS; +} diff --git a/zephyr/projects/nissa/pujjo/src/usbc.c b/zephyr/projects/nissa/pujjo/src/usbc.c new file mode 100644 index 0000000000..5d3d94c243 --- /dev/null +++ b/zephyr/projects/nissa/pujjo/src/usbc.c @@ -0,0 +1,242 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <zephyr/logging/log.h> + +#include "charge_state_v2.h" +#include "chipset.h" +#include "hooks.h" +#include "usb_mux.h" +#include "system.h" +#include "driver/charger/isl923x_public.h" +#include "driver/retimer/anx7483_public.h" +#include "driver/tcpm/tcpci.h" +#include "driver/tcpm/raa489000.h" + +#include "nissa_common.h" + +LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL); + +struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = { + { + .bus_type = EC_BUS_TYPE_I2C, + .i2c_info = { + .port = I2C_PORT_USB_C0_TCPC, + .addr_flags = RAA489000_TCPC0_I2C_FLAGS, + }, + .drv = &raa489000_tcpm_drv, + /* RAA489000 implements TCPCI 2.0 */ + .flags = TCPC_FLAGS_TCPCI_REV2_0 | + TCPC_FLAGS_VBUS_MONITOR, + }, +}; + +int board_is_sourcing_vbus(int port) +{ + int regval; + + tcpc_read(port, TCPC_REG_POWER_STATUS, ®val); + return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS); +} + +int board_set_active_charge_port(int port) +{ + int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT); + int i; + int old_port; + + if (!is_real_port && port != CHARGE_PORT_NONE) + return EC_ERROR_INVAL; + + old_port = charge_manager_get_active_charge_port(); + + LOG_INF("New chg p%d", port); + + /* Disable all ports. */ + if (port == CHARGE_PORT_NONE) { + for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) { + tcpc_write(i, TCPC_REG_COMMAND, + TCPC_REG_COMMAND_SNK_CTRL_LOW); + raa489000_enable_asgate(i, false); + } + + return EC_SUCCESS; + } + + /* Check if port is sourcing VBUS. */ + if (board_is_sourcing_vbus(port)) { + LOG_WRN("Skip enable p%d", port); + return EC_ERROR_INVAL; + } + + /* + * Turn off the other ports' sink path FETs, before enabling the + * requested charge port. + */ + for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) { + if (i == port) + continue; + + if (tcpc_write(i, TCPC_REG_COMMAND, + TCPC_REG_COMMAND_SNK_CTRL_LOW)) + LOG_WRN("p%d: sink path disable failed.", i); + raa489000_enable_asgate(i, false); + } + + /* + * Stop the charger IC from switching while changing ports. Otherwise, + * we can overcurrent the adapter we're switching to. (crbug.com/926056) + */ + if (old_port != CHARGE_PORT_NONE) + charger_discharge_on_ac(1); + + /* Enable requested charge port. */ + if (raa489000_enable_asgate(port, true) || + tcpc_write(port, TCPC_REG_COMMAND, + TCPC_REG_COMMAND_SNK_CTRL_HIGH)) { + LOG_WRN("p%d: sink path enable failed.", port); + charger_discharge_on_ac(0); + return EC_ERROR_UNKNOWN; + } + + /* Allow the charger IC to begin/continue switching. */ + charger_discharge_on_ac(0); + + return EC_SUCCESS; +} + +uint16_t tcpc_get_alert_status(void) +{ + uint16_t status = 0; + int regval; + + /* + * The interrupt line is shared between the TCPC and BC1.2 detector IC. + * Therefore, go out and actually read the alert registers to report the + * alert status. + */ + if (!gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_c0_int_odl))) { + if (!tcpc_read16(0, TCPC_REG_ALERT, ®val)) { + /* The TCPCI Rev 1.0 spec says to ignore bits 14:12. */ + if (!(tcpc_config[0].flags & TCPC_FLAGS_TCPCI_REV2_0)) + regval &= ~((1 << 14) | (1 << 13) | (1 << 12)); + + if (regval) + status |= PD_STATUS_TCPC_ALERT_0; + } + } + return status; +} + +void pd_power_supply_reset(int port) +{ + /* Disable VBUS */ + tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_LOW); + + /* Notify host of power info change. */ + pd_send_host_event(PD_EVENT_POWER_CHANGE); +} + +__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp) +{ + if (port < 0 || port >= CONFIG_USB_PD_PORT_MAX_COUNT) + return; + + raa489000_set_output_current(port, rp); +} + +int pd_set_power_supply_ready(int port) +{ + int rv; + + if (port >= CONFIG_USB_PD_PORT_MAX_COUNT) + return EC_ERROR_INVAL; + + /* Disable charging. */ + rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW); + if (rv) + return rv; + + /* Our policy is not to source VBUS when the AP is off. */ + if (chipset_in_state(CHIPSET_STATE_ANY_OFF)) + return EC_ERROR_NOT_POWERED; + + /* Provide Vbus. */ + rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_HIGH); + if (rv) + return rv; + + rv = raa489000_enable_asgate(port, true); + if (rv) + return rv; + + /* Notify host of power info change. */ + pd_send_host_event(PD_EVENT_POWER_CHANGE); + + return EC_SUCCESS; +} + +void board_reset_pd_mcu(void) +{ + /* + * TODO(b:147316511): could send a reset command to the TCPC here + * if needed. + */ +} + +/* + * Because the TCPCs and BC1.2 chips share interrupt lines, it's possible + * for an interrupt to be lost if one asserts the IRQ, the other does the same + * then the first releases it: there will only be one falling edge to trigger + * the interrupt, and the line will be held low. We handle this by running a + * deferred check after a falling edge to see whether the IRQ is still being + * asserted. If it is, we assume an interrupt may have been lost and we need + * to poll each chip for events again. + */ +#define USBC_INT_POLL_DELAY_US 5000 + +static void poll_c0_int(void); +DECLARE_DEFERRED(poll_c0_int); + +static void usbc_interrupt_trigger(int port) +{ + schedule_deferred_pd_interrupt(port); + usb_charger_task_set_event(port, USB_CHG_EVENT_BC12); +} + +static inline void poll_usb_gpio(int port, const struct gpio_dt_spec *gpio, + const struct deferred_data *ud) +{ + if (!gpio_pin_get_dt(gpio)) { + usbc_interrupt_trigger(port); + hook_call_deferred(ud, USBC_INT_POLL_DELAY_US); + } +} + +static void poll_c0_int(void) +{ + poll_usb_gpio(0, GPIO_DT_FROM_NODELABEL(gpio_usb_c0_int_odl), + &poll_c0_int_data); +} + +void usb_interrupt(enum gpio_signal signal) +{ + int port; + const struct deferred_data *ud; + + if (signal == GPIO_SIGNAL(DT_NODELABEL(gpio_usb_c0_int_odl))) { + port = 0; + ud = &poll_c0_int_data; + } + /* + * We've just been called from a falling edge, so there's definitely + * no lost IRQ right now. Cancel any pending check. + */ + hook_call_deferred(ud, -1); + /* Trigger polling of TCPC and BC1.2 in respective tasks */ + usbc_interrupt_trigger(port); + /* Check for lost interrupts in a bit */ + hook_call_deferred(ud, USBC_INT_POLL_DELAY_US); +} diff --git a/zephyr/projects/nissa/src/board_power.c b/zephyr/projects/nissa/src/board_power.c new file mode 100644 index 0000000000..d7fb4aeffe --- /dev/null +++ b/zephyr/projects/nissa/src/board_power.c @@ -0,0 +1,169 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <zephyr/sys/atomic.h> +#include <zephyr/logging/log.h> +#include <zephyr/drivers/gpio.h> + +#include <ap_power/ap_power.h> +#include <ap_power/ap_power_events.h> +#include <ap_power/ap_power_interface.h> +#include <ap_power_override_functions.h> +#include <power_signals.h> +#include <x86_power_signals.h> + +#include "gpio_signal.h" +#include "gpio/gpio.h" + +LOG_MODULE_DECLARE(ap_pwrseq, LOG_LEVEL_INF); + +#define X86_NON_DSX_ADLP_NONPWRSEQ_FORCE_SHUTDOWN_TO_MS 5 + +static bool s0_stable; + +static void generate_ec_soc_dsw_pwrok_handler(int delay) +{ + int in_sig_val = power_signal_get(PWR_DSW_PWROK); + + if (in_sig_val != power_signal_get(PWR_EC_SOC_DSW_PWROK)) { + if (in_sig_val) + k_msleep(delay); + power_signal_set(PWR_EC_SOC_DSW_PWROK, 1); + } +} + +void board_ap_power_force_shutdown(void) +{ + int timeout_ms = X86_NON_DSX_ADLP_NONPWRSEQ_FORCE_SHUTDOWN_TO_MS; + + if (s0_stable) { + /* Enable these power signals in case of sudden shutdown */ + power_signal_enable(PWR_DSW_PWROK); + power_signal_enable(PWR_PG_PP1P05); + } + + power_signal_set(PWR_EC_SOC_DSW_PWROK, 0); + power_signal_set(PWR_EC_PCH_RSMRST, 0); + + while (power_signal_get(PWR_RSMRST) == 0 && + power_signal_get(PWR_SLP_SUS) == 0 && timeout_ms > 0) { + k_msleep(1); + timeout_ms--; + } + if (power_signal_get(PWR_SLP_SUS) == 0) { + LOG_WRN("SLP_SUS is not deasserted! Assuming G3"); + } + + if (power_signal_get(PWR_RSMRST) == 1) { + LOG_WRN("RSMRST is not deasserted! Assuming G3"); + } + + power_signal_set(PWR_EN_PP3300_A, 0); + + power_signal_set(PWR_EN_PP5000_A, 0); + + timeout_ms = X86_NON_DSX_ADLP_NONPWRSEQ_FORCE_SHUTDOWN_TO_MS; + while (power_signal_get(PWR_DSW_PWROK) && timeout_ms > 0) { + k_msleep(1); + timeout_ms--; + }; + + if (power_signal_get(PWR_DSW_PWROK)) + LOG_WRN("DSW_PWROK didn't go low! Assuming G3."); + + power_signal_disable(PWR_DSW_PWROK); + power_signal_disable(PWR_PG_PP1P05); + s0_stable = false; +} + +void board_ap_power_action_g3_s5(void) +{ + power_signal_enable(PWR_DSW_PWROK); + power_signal_enable(PWR_PG_PP1P05); + + LOG_DBG("Turning on PWR_EN_PP5000_A and PWR_EN_PP3300_A"); + power_signal_set(PWR_EN_PP5000_A, 1); + power_signal_set(PWR_EN_PP3300_A, 1); + + power_wait_signals_timeout(IN_PGOOD_ALL_CORE, + AP_PWRSEQ_DT_VALUE(wait_signal_timeout)); + + generate_ec_soc_dsw_pwrok_handler(AP_PWRSEQ_DT_VALUE(dsw_pwrok_delay)); + s0_stable = false; +} + +void board_ap_power_action_s3_s0(void) +{ + s0_stable = false; +} + +void board_ap_power_action_s0_s3(void) +{ + power_signal_enable(PWR_DSW_PWROK); + power_signal_enable(PWR_PG_PP1P05); + s0_stable = false; +} + +void board_ap_power_action_s0(void) +{ + if (s0_stable) { + return; + } + LOG_INF("Reaching S0"); + power_signal_disable(PWR_DSW_PWROK); + power_signal_disable(PWR_PG_PP1P05); + s0_stable = true; +} + +int board_ap_power_assert_pch_power_ok(void) +{ + /* Pass though PCH_PWROK */ + if (power_signal_get(PWR_PCH_PWROK) == 0) { + k_msleep(AP_PWRSEQ_DT_VALUE(pch_pwrok_delay)); + power_signal_set(PWR_PCH_PWROK, 1); + } + + return 0; +} + +bool board_ap_power_check_power_rails_enabled(void) +{ + return power_signal_get(PWR_EN_PP3300_A) && + power_signal_get(PWR_EN_PP5000_A) && + power_signal_get(PWR_EC_SOC_DSW_PWROK); +} + +int board_power_signal_get(enum power_signal signal) +{ + switch (signal) { + default: + LOG_ERR("Unknown signal for board get: %d", signal); + return -EINVAL; + + case PWR_ALL_SYS_PWRGD: + /* + * All system power is good. + * Checks that PWR_SLP_S3 is off, and + * the GPIO signal for all power good is set, + * and that the 1.05 volt line is ready. + */ + if (power_signal_get(PWR_SLP_S3)) { + return 0; + } + if (!gpio_pin_get_dt( + GPIO_DT_FROM_NODELABEL(gpio_all_sys_pwrgd))) { + return 0; + } + if (!power_signal_get(PWR_PG_PP1P05)) { + return 0; + } + return 1; + } +} + +int board_power_signal_set(enum power_signal signal, int value) +{ + return -EINVAL; +} diff --git a/zephyr/projects/nissa/src/common.c b/zephyr/projects/nissa/src/common.c new file mode 100644 index 0000000000..78f703ae49 --- /dev/null +++ b/zephyr/projects/nissa/src/common.c @@ -0,0 +1,154 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <zephyr/device.h> +#include <ap_power/ap_power.h> + +#include "battery.h" +#include "charger.h" +#include "charge_state_v2.h" +#include "chipset.h" +#include "cros_cbi.h" +#include "hooks.h" +#include "usb_mux.h" +#include "system.h" + +#include "nissa_common.h" + +#include <zephyr/logging/log.h> +LOG_MODULE_REGISTER(nissa, CONFIG_NISSA_LOG_LEVEL); + +static uint8_t cached_usb_pd_port_count; + +__override uint8_t board_get_usb_pd_port_count(void) +{ + __ASSERT(cached_usb_pd_port_count != 0, + "sub-board detection did not run before a port count request"); + if (cached_usb_pd_port_count == 0) + LOG_WRN("USB PD Port count not initialized!"); + return cached_usb_pd_port_count; +} + +static void board_power_change(struct ap_power_ev_callback *cb, + struct ap_power_ev_data data) +{ + /* + * Enable power to pen garage when system is active (safe even if no + * pen is present). + */ + const struct gpio_dt_spec *const pen_power_gpio = + GPIO_DT_FROM_NODELABEL(gpio_en_pp5000_pen_x); + + switch (data.event) { + case AP_POWER_STARTUP: + gpio_pin_set_dt(pen_power_gpio, 1); + break; + case AP_POWER_SHUTDOWN: + gpio_pin_set_dt(pen_power_gpio, 0); + break; + default: + break; + } +} + +/* + * Initialise the USB PD port count, which + * depends on which sub-board is attached. + */ +static void board_setup_init(void) +{ + static struct ap_power_ev_callback cb; + + ap_power_ev_init_callback(&cb, board_power_change, + AP_POWER_STARTUP | AP_POWER_SHUTDOWN); + ap_power_ev_add_callback(&cb); + + switch (nissa_get_sb_type()) { + default: + cached_usb_pd_port_count = 1; + break; + + case NISSA_SB_C_A: + case NISSA_SB_C_LTE: + cached_usb_pd_port_count = 2; + break; + } +} +/* + * Make sure setup is done after EEPROM is readable. + */ +DECLARE_HOOK(HOOK_INIT, board_setup_init, HOOK_PRIO_INIT_I2C); + +__overridable void board_set_charge_limit(int port, int supplier, int charge_ma, + int max_ma, int charge_mv) +{ + int icl = MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT); + + /* + * Assume charger overdraws by about 4%, keeping the actual draw + * within spec. This adjustment can be changed with characterization + * of actual hardware. + */ + icl = icl * 96 / 100; + charge_set_input_current_limit(icl, charge_mv); +} + +int pd_check_vconn_swap(int port) +{ + /* Allow VCONN swaps if the AP is on. */ + return chipset_in_state(CHIPSET_STATE_ANY_SUSPEND | CHIPSET_STATE_ON); +} + +/* + * Count of chargers depends on sub board presence. + */ +__override uint8_t board_get_charger_chip_count(void) +{ + return board_get_usb_pd_port_count(); +} + +/* + * Retrieve sub-board type from FW_CONFIG. + */ +enum nissa_sub_board_type nissa_get_sb_type(void) +{ + static enum nissa_sub_board_type sb = NISSA_SB_UNKNOWN; + int ret; + uint32_t val; + + /* + * Return cached value. + */ + if (sb != NISSA_SB_UNKNOWN) + return sb; + + sb = NISSA_SB_NONE; /* Defaults to none */ + ret = cros_cbi_get_fw_config(FW_SUB_BOARD, &val); + if (ret != 0) { + LOG_WRN("Error retrieving CBI FW_CONFIG field %d", + FW_SUB_BOARD); + return sb; + } + switch (val) { + default: + LOG_WRN("No sub-board defined"); + break; + case FW_SUB_BOARD_1: + sb = NISSA_SB_C_A; + LOG_INF("SB: USB type C, USB type A"); + break; + + case FW_SUB_BOARD_2: + sb = NISSA_SB_C_LTE; + LOG_INF("SB: USB type C, WWAN LTE"); + break; + + case FW_SUB_BOARD_3: + sb = NISSA_SB_HDMI_A; + LOG_INF("SB: HDMI, USB type A"); + break; + } + return sb; +} diff --git a/zephyr/projects/nissa/src/led.c b/zephyr/projects/nissa/src/led.c new file mode 100644 index 0000000000..2617d0092d --- /dev/null +++ b/zephyr/projects/nissa/src/led.c @@ -0,0 +1,52 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + * + * Battery LED control for nissa + */ +#include "common.h" +#include "ec_commands.h" +#include "led_common.h" +#include "led_onoff_states.h" +#include "led_pwm.h" + +__override const int led_charge_lvl_1 = 5; +__override const int led_charge_lvl_2 = 97; +__override struct led_descriptor + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED, + LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 3 * LED_ONE_SEC } }, + [STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 2 * LED_ONE_SEC }, + { EC_LED_COLOR_GREEN, + 2 * LED_ONE_SEC } }, + }; + +__override void led_set_color_battery(enum ec_led_colors color) +{ + switch (color) { + case EC_LED_COLOR_RED: + set_pwm_led_color(EC_LED_ID_BATTERY_LED, EC_LED_COLOR_RED); + break; + case EC_LED_COLOR_GREEN: + set_pwm_led_color(EC_LED_ID_BATTERY_LED, EC_LED_COLOR_GREEN); + break; + case EC_LED_COLOR_AMBER: + set_pwm_led_color(EC_LED_ID_BATTERY_LED, EC_LED_COLOR_AMBER); + break; + default: /* LED_OFF and other unsupported colors */ + set_pwm_led_color(EC_LED_ID_BATTERY_LED, -1); + break; + } +} diff --git a/zephyr/projects/nissa/src/sub_board.c b/zephyr/projects/nissa/src/sub_board.c new file mode 100644 index 0000000000..3ccbcd9325 --- /dev/null +++ b/zephyr/projects/nissa/src/sub_board.c @@ -0,0 +1,298 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Nissa sub-board hardware configuration */ + +#include <ap_power/ap_power.h> +#include <zephyr/drivers/gpio.h> +#include <zephyr/drivers/pinctrl.h> +#include <zephyr/init.h> +#include <zephyr/kernel.h> +#include <zephyr/sys/printk.h> + +#include "cros_board_info.h" +#include "driver/tcpm/tcpci.h" +#include "gpio/gpio_int.h" +#include "hooks.h" +#include "usb_charge.h" +#include "usb_pd.h" +#include "usbc/usb_muxes.h" +#include "task.h" + +#include "nissa_common.h" +#include "nissa_hdmi.h" + +LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL); + +#if NISSA_BOARD_HAS_HDMI_SUPPORT +static void hdmi_power_handler(struct ap_power_ev_callback *cb, + struct ap_power_ev_data data) +{ + /* Enable VCC on the HDMI port. */ + const struct gpio_dt_spec *s3_rail = + GPIO_DT_FROM_ALIAS(gpio_hdmi_en_odl); + /* Connect AP's DDC to sub-board (default is USB-C aux) */ + const struct gpio_dt_spec *ddc_select = + GPIO_DT_FROM_NODELABEL(gpio_hdmi_sel); + + switch (data.event) { + case AP_POWER_PRE_INIT: + LOG_DBG("Connecting HDMI DDC to sub-board"); + gpio_pin_set_dt(ddc_select, 1); + break; + case AP_POWER_STARTUP: + LOG_DBG("Enabling HDMI VCC"); + gpio_pin_set_dt(s3_rail, 1); + break; + case AP_POWER_SHUTDOWN: + LOG_DBG("Disabling HDMI VCC"); + gpio_pin_set_dt(s3_rail, 0); + break; + case AP_POWER_HARD_OFF: + LOG_DBG("Disconnecting HDMI sub-board DDC"); + gpio_pin_set_dt(ddc_select, 0); + break; + default: + LOG_ERR("Unhandled HDMI power event %d", data.event); + break; + } +} + +static void hdmi_hpd_interrupt(const struct device *device, + struct gpio_callback *callback, + gpio_port_pins_t pins) +{ + int state = gpio_pin_get_dt(GPIO_DT_FROM_ALIAS(gpio_hpd_odl)); + + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_soc_hdmi_hpd), state); + LOG_DBG("HDMI HPD changed state to %d", state); +} + +void nissa_configure_hdmi_rails(void) +{ +#if DT_NODE_EXISTS(GPIO_DT_FROM_ALIAS(gpio_en_rails_odl)) + gpio_pin_configure_dt(GPIO_DT_FROM_ALIAS(gpio_en_rails_odl), + GPIO_OUTPUT_INACTIVE | GPIO_OPEN_DRAIN | + GPIO_PULL_UP | GPIO_ACTIVE_LOW); +#endif +} + +void nissa_configure_hdmi_vcc(void) +{ + gpio_pin_configure_dt(GPIO_DT_FROM_ALIAS(gpio_hdmi_en_odl), + GPIO_OUTPUT_INACTIVE | GPIO_OPEN_DRAIN | + GPIO_ACTIVE_LOW); +} + +__overridable void nissa_configure_hdmi_power_gpios(void) +{ + nissa_configure_hdmi_rails(); +} + +#ifdef CONFIG_SOC_IT8XXX2 +/* + * On it8xxx2, the below condition will break the EC to enter deep doze mode + * (b:237717730): + * Enhance i2c (GPE0/E7, GPH1/GPH2 or GPA4/GPA5) is enabled and its clock and + * data pins aren't both at high level. + * + * Since HDMI+type A SKU doesn't use i2c4, disable it for better power number. + */ +#define I2C4_NODE DT_NODELABEL(i2c4) +#if DT_NODE_EXISTS(I2C4_NODE) +PINCTRL_DT_DEFINE(I2C4_NODE); + +/* disable i2c4 alternate function */ +static void soc_it8xxx2_disable_i2c4_alt(void) +{ + const struct pinctrl_dev_config *pcfg = + PINCTRL_DT_DEV_CONFIG_GET(I2C4_NODE); + + pinctrl_apply_state(pcfg, PINCTRL_STATE_SLEEP); +} +#endif /* DT_NODE_EXISTS(I2C4_NODE) */ +#endif /* CONFIG_SOC_IT8XXX2 */ +#endif /* NISSA_BOARD_HAS_HDMI_SUPPORT */ + +static void lte_power_handler(struct ap_power_ev_callback *cb, + struct ap_power_ev_data data) +{ + /* Enable rails for S5 */ + const struct gpio_dt_spec *s5_rail = + GPIO_DT_FROM_ALIAS(gpio_en_sub_s5_rails); + switch (data.event) { + case AP_POWER_PRE_INIT: + LOG_DBG("Enabling LTE sub-board power rails"); + gpio_pin_set_dt(s5_rail, 1); + break; + case AP_POWER_HARD_OFF: + LOG_DBG("Disabling LTE sub-board power rails"); + gpio_pin_set_dt(s5_rail, 0); + break; + default: + LOG_ERR("Unhandled LTE power event %d", data.event); + break; + } +} + +/** + * Configure GPIOs (and other pin functions) that vary with present sub-board. + * + * The functions of some pins vary according to which sub-board is present + * (indicated by CBI fw_config); this function configures them according to the + * needs of the present sub-board. + */ +static void nereid_subboard_config(void) +{ + enum nissa_sub_board_type sb = nissa_get_sb_type(); + static struct ap_power_ev_callback power_cb; + + /* + * USB-A port: current limit output is configured by default and unused + * if this port is not present. VBUS enable must be configured if + * needed and is controlled by the usba-port-enable-pins driver. + */ + if (sb == NISSA_SB_C_A || sb == NISSA_SB_HDMI_A || + sb == NISSA_SB_NONE) { + /* + * Configure VBUS enable, default off. + * SB_NONE indicates missing fw_config; it's safe to enable VBUS + * control in this case since all that will happen is we turn + * off power to LTE, and it's useful to allow USB-A to work in + * such a configuration. + */ + gpio_pin_configure_dt(GPIO_DT_FROM_ALIAS(gpio_en_usb_a1_vbus), + GPIO_OUTPUT_LOW); + } else { + /* Turn off unused pins */ + gpio_pin_configure_dt( + GPIO_DT_FROM_NODELABEL(gpio_sub_usb_a1_ilimit_sdp), + GPIO_DISCONNECTED); + gpio_pin_configure_dt(GPIO_DT_FROM_ALIAS(gpio_en_usb_a1_vbus), + GPIO_DISCONNECTED); + /* Disable second USB-A port enable GPIO */ + __ASSERT(USB_PORT_ENABLE_COUNT == 2, + "USB A port count != 2 (%d)", USB_PORT_ENABLE_COUNT); + usb_port_enable[1] = -1; + } + /* + * USB-C port: the default configuration has I2C on the I2C pins, + * but the interrupt line needs to be configured. + */ +#if CONFIG_USB_PD_PORT_MAX_COUNT > 1 + if (sb == NISSA_SB_C_A || sb == NISSA_SB_C_LTE) { + /* Configure interrupt input */ + gpio_pin_configure_dt(GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl), + GPIO_INPUT | GPIO_PULL_UP); + } else { + /* Port doesn't exist, doesn't need muxing */ + USB_MUX_ENABLE_ALTERNATIVE(usb_mux_chain_1_no_mux); + } +#endif + + switch (sb) { +#if NISSA_BOARD_HAS_HDMI_SUPPORT + case NISSA_SB_HDMI_A: { + /* + * HDMI: two outputs control power which must be configured to + * non-default settings, and HPD must be forwarded to the AP + * on another output pin. + */ + const struct gpio_dt_spec *hpd_gpio = + GPIO_DT_FROM_ALIAS(gpio_hpd_odl); + static struct gpio_callback hdmi_hpd_cb; + int rv, irq_key; + + nissa_configure_hdmi_power_gpios(); + +#if CONFIG_SOC_IT8XXX2 && DT_NODE_EXISTS(I2C4_NODE) + /* disable i2c4 alternate function for better power number */ + soc_it8xxx2_disable_i2c4_alt(); +#endif + + /* + * Control HDMI power according to AP power state. Some events + * won't do anything if the corresponding pin isn't configured, + * but that's okay. + */ + ap_power_ev_init_callback( + &power_cb, hdmi_power_handler, + AP_POWER_PRE_INIT | AP_POWER_HARD_OFF | + AP_POWER_STARTUP | AP_POWER_SHUTDOWN); + ap_power_ev_add_callback(&power_cb); + + /* + * Configure HPD input from sub-board; it's inverted by a buffer + * on the sub-board. + */ + gpio_pin_configure_dt(hpd_gpio, GPIO_INPUT | GPIO_ACTIVE_LOW); + /* Register interrupt handler for HPD changes */ + gpio_init_callback(&hdmi_hpd_cb, hdmi_hpd_interrupt, + BIT(hpd_gpio->pin)); + gpio_add_callback(hpd_gpio->port, &hdmi_hpd_cb); + rv = gpio_pin_interrupt_configure_dt(hpd_gpio, + GPIO_INT_EDGE_BOTH); + __ASSERT(rv == 0, + "HPD interrupt configuration returned error %d", rv); + /* + * Run the HPD handler once to ensure output is in sync. + * Lock interrupts to ensure that we don't cause desync if an + * HPD interrupt comes in between the internal read of the input + * and write to the output. + */ + irq_key = irq_lock(); + hdmi_hpd_interrupt(hpd_gpio->port, &hdmi_hpd_cb, + BIT(hpd_gpio->pin)); + irq_unlock(irq_key); + break; + } +#endif + case NISSA_SB_C_LTE: + /* + * LTE: Set up callbacks for enabling/disabling + * sub-board power on S5 state. + */ + gpio_pin_configure_dt(GPIO_DT_FROM_ALIAS(gpio_en_sub_s5_rails), + GPIO_OUTPUT_INACTIVE); + /* Control LTE power when CPU entering or + * exiting S5 state. + */ + ap_power_ev_init_callback(&power_cb, lte_power_handler, + AP_POWER_HARD_OFF | + AP_POWER_PRE_INIT); + ap_power_ev_add_callback(&power_cb); + break; + + default: + break; + } +} +DECLARE_HOOK(HOOK_INIT, nereid_subboard_config, HOOK_PRIO_POST_FIRST); + +/* + * Enable interrupts + */ +static void board_init(void) +{ + /* + * Enable USB-C interrupts. + */ + gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0)); +#if CONFIG_USB_PD_PORT_MAX_COUNT > 1 + if (board_get_usb_pd_port_count() == 2) + gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c1)); +#endif +} +DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT); + +/* Trigger shutdown by enabling the Z-sleep circuit */ +__override void board_hibernate_late(void) +{ + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_en_slp_z), 1); + /* + * The system should hibernate, but there may be + * a small delay, so return. + */ +} diff --git a/zephyr/projects/nissa/xivu/cbi.dtsi b/zephyr/projects/nissa/xivu/cbi.dtsi new file mode 100644 index 0000000000..4149ea291c --- /dev/null +++ b/zephyr/projects/nissa/xivu/cbi.dtsi @@ -0,0 +1,77 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + /* Xivu-specific fw_config fields. */ + nissa-fw-config { + /* + * FW_CONFIG field to enable WFC or not. + */ + wfc { + enum-name = "FW_WFC"; + start = <0>; + size = <1>; + + wfc-mipi { + compatible = "cros-ec,cbi-fw-config-value"; + enum-name = "FW_WFC_MIPI"; + value = <0>; + }; + wfc-absent { + compatible = "cros-ec,cbi-fw-config-value"; + enum-name = "FW_WFC_ABSENT"; + value = <1>; + }; + }; + + /* + * FW_CONFIG field to enable stylus or not. + */ + stylus { + enum-name = "FW_STYLUS"; + start = <1>; + size = <1>; + + stylus-present { + compatible = "cros-ec,cbi-fw-config-value"; + enum-name = "FW_STYLUS_PRESENT"; + value = <0>; + }; + stylus-absent { + compatible = "cros-ec,cbi-fw-config-value"; + enum-name = "FW_STYLUS_ABSENT"; + value = <1>; + }; + }; + /* + * FW_CONFIG field to indicate which sub-board + * is attached. + */ + sub-board { + enum-name = "FW_SUB_BOARD"; + start = <2>; + size = <2>; + + sub-board-1 { + compatible = "cros-ec,cbi-fw-config-value"; + enum-name = "FW_SUB_BOARD_1"; + value = <0>; + }; + sub-board-2 { + compatible = "cros-ec,cbi-fw-config-value"; + enum-name = "FW_SUB_BOARD_2"; + value = <1>; + }; + sub-board-3 { + compatible = "cros-ec,cbi-fw-config-value"; + enum-name = "FW_SUB_BOARD_3"; + value = <2>; + }; + }; + +/delete-node/ fan; + }; + +}; diff --git a/zephyr/projects/nissa/xivu/generated.dtsi b/zephyr/projects/nissa/xivu/generated.dtsi new file mode 100644 index 0000000000..383054adf8 --- /dev/null +++ b/zephyr/projects/nissa/xivu/generated.dtsi @@ -0,0 +1,291 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + * + * This file is auto-generated - do not edit! + */ + +/ { + + named-adc-channels { + compatible = "named-adc-channels"; + + adc_ec_vsense_pp1050_proc: ec_vsense_pp1050_proc { + enum-name = "ADC_PP1050_PROC"; + io-channels = <&adc0 4>; + }; + adc_ec_vsense_pp3300_s5: ec_vsense_pp3300_s5 { + enum-name = "ADC_PP3300_S5"; + io-channels = <&adc0 6>; + }; + adc_temp_sensor_1: temp_sensor_1 { + enum-name = "ADC_TEMP_SENSOR_1"; + io-channels = <&adc0 0>; + }; + adc_temp_sensor_2: temp_sensor_2 { + enum-name = "ADC_TEMP_SENSOR_2"; + io-channels = <&adc0 1>; + }; + adc_temp_sensor_3: temp_sensor_3 { + enum-name = "ADC_TEMP_SENSOR_3"; + io-channels = <&adc0 10>; + }; + adc_temp_sensor_4: temp_sensor_4 { + enum-name = "ADC_TEMP_SENSOR_4"; + io-channels = <&adc0 11>; + }; + }; + + named-gpios { + compatible = "named-gpios"; + + gpio_acc_int_l: acc_int_l { + gpios = <&gpio5 0 GPIO_INPUT>; + }; + gpio_all_sys_pwrgd: all_sys_pwrgd { + gpios = <&gpioa 7 GPIO_INPUT>; + }; + gpio_ccd_mode_odl: ccd_mode_odl { + gpios = <&gpioe 5 GPIO_INPUT>; + enum-name = "GPIO_CCD_MODE_ODL"; + }; + gpio_cpu_c10_gate_l: cpu_c10_gate_l { + gpios = <&gpio6 7 GPIO_INPUT>; + }; + gpio_ec_battery_pres_odl: ec_battery_pres_odl { + gpios = <&gpioa 3 GPIO_INPUT>; + enum-name = "GPIO_BATT_PRES_ODL"; + }; + gpio_ec_cbi_wp: ec_cbi_wp { + gpios = <&gpio7 4 GPIO_OUTPUT>; + }; + gpio_ec_edp_bl_en_od: ec_edp_bl_en_od { + gpios = <&gpiod 3 GPIO_ODR_HIGH>; + enum-name = "GPIO_ENABLE_BACKLIGHT"; + }; + gpio_ec_entering_rw: ec_entering_rw { + gpios = <&gpio0 3 GPIO_OUTPUT>; + enum-name = "GPIO_ENTERING_RW"; + }; + gpio_ec_gsc_packet_mode: ec_gsc_packet_mode { + gpios = <&gpio7 5 GPIO_OUTPUT>; + enum-name = "GPIO_PACKET_MODE_EN"; + }; + gpio_ec_kso_02_inv: ec_kso_02_inv { + gpios = <&gpio1 7 (GPIO_OUTPUT | GPIO_ACTIVE_LOW)>; + }; + gpio_ec_pch_wake_odl: ec_pch_wake_odl { + gpios = <&gpiob 0 GPIO_ODR_LOW>; + }; + gpio_ec_prochot_odl: ec_prochot_odl { + gpios = <&gpiof 1 GPIO_ODR_HIGH>; + }; + gpio_ec_soc_dsw_pwrok: ec_soc_dsw_pwrok { + gpios = <&gpio6 1 GPIO_OUTPUT>; + }; + gpio_ec_acok_otg_c1: ec_acok_otg_c1 { + gpios = <&gpioe 4 GPIO_OUTPUT>; + }; + gpio_ec_soc_int_odl: ec_soc_int_odl { + gpios = <&gpio8 0 GPIO_ODR_HIGH>; + enum-name = "GPIO_EC_INT_L"; + }; + gpio_ec_soc_pch_pwrok_od: ec_soc_pch_pwrok_od { + gpios = <&gpio7 2 GPIO_ODR_HIGH>; + }; + gpio_ec_soc_pwr_btn_odl: ec_soc_pwr_btn_odl { + gpios = <&gpioc 1 GPIO_ODR_HIGH>; + enum-name = "GPIO_PCH_PWRBTN_L"; + }; + gpio_ec_soc_rsmrst_l: ec_soc_rsmrst_l { + gpios = <&gpioa 6 GPIO_OUTPUT>; + }; + gpio_ec_soc_rtcrst: ec_soc_rtcrst { + gpios = <&gpio7 6 GPIO_OUTPUT>; + }; + gpio_ec_soc_sys_pwrok: ec_soc_sys_pwrok { + gpios = <&gpio3 7 GPIO_OUTPUT>; + }; + gpio_ec_soc_vccst_pwrgd_od: ec_soc_vccst_pwrgd_od { + gpios = <&gpioa 4 GPIO_ODR_HIGH>; + }; + gpio_ec_wp_odl: ec_wp_odl { + gpios = <&gpioa 1 (GPIO_INPUT | GPIO_ACTIVE_LOW)>; + }; + gpio_en_pp3300_s5: en_pp3300_s5 { + gpios = <&gpiob 6 GPIO_OUTPUT>; + enum-name = "GPIO_TEMP_SENSOR_POWER"; + }; + gpio_en_pp5000_pen_x: en_pp5000_pen_x { + gpios = <&gpioe 2 GPIO_OUTPUT>; + }; + gpio_en_pp5000_s5: en_pp5000_s5 { + gpios = <&gpio4 0 GPIO_OUTPUT>; + }; + gpio_en_slp_z: en_slp_z { + gpios = <&gpioe 1 GPIO_OUTPUT>; + }; + gpio_en_usb_a0_vbus: en_usb_a0_vbus { + gpios = <&gpio9 1 GPIO_OUTPUT>; + }; + gpio_gsc_ec_pwr_btn_odl: gsc_ec_pwr_btn_odl { + gpios = <&gpio0 0 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_POWER_BUTTON_L"; + }; + gpio_ec_acok_otg_c0: ec_acok_otg_c0 { + gpios = <&gpioc 6 GPIO_OUTPUT>; + }; + gpio_imu_int_l: imu_int_l { + gpios = <&gpio5 6 GPIO_INPUT>; + }; + gpio_imvp91_vrrdy_od: imvp91_vrrdy_od { + gpios = <&gpio4 3 GPIO_INPUT>; + }; + gpio_lid_open: lid_open { + gpios = <&gpiod 2 GPIO_INPUT>; + enum-name = "GPIO_LID_OPEN"; + }; + gpio_pen_detect_odl: pen_detect_odl { + gpios = <&gpio9 6 GPIO_INPUT_PULL_UP>; + }; + gpio_pg_pp1050_mem_s3_od: pg_pp1050_mem_s3_od { + gpios = <&gpiof 0 GPIO_INPUT>; + }; + gpio_pg_pp5000_s5_od: pg_pp5000_s5_od { + gpios = <&gpio4 2 GPIO_INPUT>; + }; + gpio_rsmrst_pwrgd_l: rsmrst_pwrgd_l { + gpios = <&gpio9 4 GPIO_INPUT_PULL_UP>; + }; + gpio_slp_s0_l: slp_s0_l { + gpios = <&gpio9 7 GPIO_INPUT>; + }; + gpio_slp_s3_l: slp_s3_l { + gpios = <&gpioa 5 GPIO_INPUT>; + }; + gpio_slp_s4_l: slp_s4_l { + gpios = <&gpio7 0 GPIO_INPUT>; + }; + gpio_slp_sus_l: slp_sus_l { + gpios = <&gpio6 2 GPIO_INPUT>; + }; + gpio_sub_usb_a1_ilimit_sdp: sub_usb_a1_ilimit_sdp { + gpios = <&gpiod 5 GPIO_OUTPUT>; + enum-name = "GPIO_USB2_ILIM_SEL"; + }; + gpio_sys_rst_odl: sys_rst_odl { + gpios = <&gpioc 5 GPIO_ODR_HIGH>; + }; + gpio_tablet_mode_l: tablet_mode_l { + gpios = <&gpio9 5 GPIO_INPUT>; + enum-name = "GPIO_TABLET_MODE_L"; + }; + gpio_usb_a0_ilimit_sdp: usb_a0_ilimit_sdp { + gpios = <&gpio3 3 GPIO_OUTPUT>; + enum-name = "GPIO_USB1_ILIM_SEL"; + }; + gpio_usb_c0_int_odl: usb_c0_int_odl { + gpios = <&gpio0 1 GPIO_INPUT_PULL_UP>; + }; + gpio_vccin_aux_vid0: vccin_aux_vid0 { + gpios = <&gpio9 2 GPIO_INPUT>; + }; + gpio_vccin_aux_vid1: vccin_aux_vid1 { + gpios = <&gpioe 3 GPIO_INPUT>; + }; + gpio_voldn_btn_odl: voldn_btn_odl { + gpios = <&gpioa 2 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_VOLUME_DOWN_L"; + }; + gpio_volup_btn_odl: volup_btn_odl { + gpios = <&gpio9 3 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_VOLUME_UP_L"; + }; + }; + + named-i2c-ports { + compatible = "named-i2c-ports"; + + i2c_ec_i2c_eeprom: ec_i2c_eeprom { + i2c-port = <&i2c0_0>; + enum-names = "I2C_PORT_EEPROM"; + }; + i2c_ec_i2c_sensor: ec_i2c_sensor { + i2c-port = <&i2c1_0>; + enum-names = "I2C_PORT_SENSOR"; + }; + i2c_ec_i2c_usb_c0: ec_i2c_usb_c0 { + i2c-port = <&i2c3_0>; + enum-names = "I2C_PORT_USB_C0_TCPC"; + }; + i2c_ec_i2c_sub_usb_c1: ec_i2c_sub_usb_c1 { + i2c-port = <&i2c5_1>; + enum-names = "I2C_PORT_USB_C1_TCPC"; + }; + i2c_ec_i2c_batt: ec_i2c_batt { + i2c-port = <&i2c7_0>; + enum-names = "I2C_PORT_BATTERY"; + }; + }; +}; + +&adc0 { + status = "okay"; + pinctrl-0 = <&adc0_chan0_gp45 + &adc0_chan1_gp44 + &adc0_chan4_gp41 + &adc0_chan6_gp34 + &adc0_chan10_gpe0 + &adc0_chan11_gpc7>; + pinctrl-names = "default"; +}; + +&i2c0_0 { + status = "okay"; + pinctrl-0 = <&i2c0_0_sda_scl_gpb4_b5>; + pinctrl-names = "default"; +}; + +&i2c1_0 { + status = "okay"; + pinctrl-0 = <&i2c1_0_sda_scl_gp87_90>; + pinctrl-names = "default"; +}; + +&i2c3_0 { + status = "okay"; + pinctrl-0 = <&i2c3_0_sda_scl_gpd0_d1>; + pinctrl-names = "default"; +}; + +&i2c5_1 { + status = "okay"; + pinctrl-0 = <&i2c5_1_sda_scl_gpf4_f5>; + pinctrl-names = "default"; +}; + +&i2c7_0 { + status = "okay"; + pinctrl-0 = <&i2c7_0_sda_scl_gpb2_b3>; + pinctrl-names = "default"; +}; + +&i2c_ctrl0 { + status = "okay"; +}; + +&i2c_ctrl1 { + status = "okay"; +}; + +&i2c_ctrl3 { + status = "okay"; +}; + +&i2c_ctrl5 { + status = "okay"; +}; + +&i2c_ctrl7 { + status = "okay"; +}; diff --git a/zephyr/projects/nissa/xivu/keyboard.dtsi b/zephyr/projects/nissa/xivu/keyboard.dtsi new file mode 100644 index 0000000000..5248c4aaff --- /dev/null +++ b/zephyr/projects/nissa/xivu/keyboard.dtsi @@ -0,0 +1,34 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +&cros_kb_raw { + status = "okay"; + /* No KSO2 (it's inverted and implemented by GPIO) */ + pinctrl-0 = < + &ksi0_gp31 + &ksi1_gp30 + &ksi2_gp27 + &ksi3_gp26 + &ksi4_gp25 + &ksi5_gp24 + &ksi6_gp23 + &ksi7_gp22 + &kso00_gp21 + &kso01_gp20 + &kso03_gp16 + &kso04_gp15 + &kso05_gp14 + &kso06_gp13 + &kso07_gp12 + &kso08_gp11 + &kso09_gp10 + &kso10_gp07 + &kso11_gp06 + &kso12_gp05 + &kso13_gp04 + &kso14_gp82 + >; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/nissa/xivu/led_pins.dtsi b/zephyr/projects/nissa/xivu/led_pins.dtsi new file mode 100644 index 0000000000..d85004a0c9 --- /dev/null +++ b/zephyr/projects/nissa/xivu/led_pins.dtsi @@ -0,0 +1,94 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + pwm_pins { + compatible = "cros-ec,pwm-pin-config"; + pwm_led_y_c0: pwm_led_y_c0 { + #led-pin-cells = <1>; + pwms = <&pwm2 0 PWM_HZ(324) PWM_POLARITY_INVERTED>; + }; + + pwm_led_w_c0: pwm_led_w_c0 { + #led-pin-cells = <1>; + pwms = <&pwm0 0 PWM_HZ(324) PWM_POLARITY_INVERTED>; + }; + + pwm_led_y_c1: pwm_led_y_c1 { + #led-pin-cells = <1>; + pwms = <&pwm6 0 PWM_HZ(324) PWM_POLARITY_INVERTED>; + }; + + pwm_led_w_c1: pwm_led_w_c1 { + #led-pin-cells = <1>; + pwms = <&pwm1 0 PWM_HZ(324) PWM_POLARITY_INVERTED>; + }; + }; + + pwm-led-pins { + compatible = "cros-ec,pwm-led-pins"; + + color_off: color-off { + led-color = "LED_OFF"; + led-id = "EC_LED_ID_BATTERY_LED"; + led-pins = <&pwm_led_y_c0 0>, + <&pwm_led_y_c1 0>, + <&pwm_led_w_c0 0>, + <&pwm_led_w_c1 0>; + }; + + color_amber: color-amber { + led-color = "LED_AMBER"; + led-id = "EC_LED_ID_BATTERY_LED"; + br-color = "EC_LED_COLOR_AMBER"; + led-pins = <&pwm_led_y_c0 1>, + <&pwm_led_y_c1 1>, + <&pwm_led_w_c0 0>, + <&pwm_led_w_c1 0>; + }; + + color_white: color-white { + led-color = "LED_WHITE"; + led-id = "EC_LED_ID_BATTERY_LED"; + br-color = "EC_LED_COLOR_WHITE"; + led-pins = <&pwm_led_y_c0 0>, + <&pwm_led_y_c1 0>, + <&pwm_led_w_c0 1>, + <&pwm_led_w_c1 1>; + }; + }; +}; + +/* LED2 */ +&pwm0 { + status = "okay"; + clock-bus = "NPCX_CLOCK_BUS_LFCLK"; + pinctrl-0 = <&pwm0_gpc3>; + pinctrl-names = "default"; +}; + +/* LED3 */ +&pwm1 { + status = "okay"; + clock-bus = "NPCX_CLOCK_BUS_LFCLK"; + pinctrl-0 = <&pwm1_gpc2>; + pinctrl-names = "default"; +}; + +/* LED1 */ +&pwm2 { + status = "okay"; + clock-bus = "NPCX_CLOCK_BUS_LFCLK"; + pinctrl-0 = <&pwm2_gpc4>; + pinctrl-names = "default"; +}; + +/* LED0 */ +&pwm6 { + status = "okay"; + clock-bus = "NPCX_CLOCK_BUS_LFCLK"; + pinctrl-0 = <&pwm6_gpc0>; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/nissa/xivu/led_policy.dtsi b/zephyr/projects/nissa/xivu/led_policy.dtsi new file mode 100644 index 0000000000..562e361ec5 --- /dev/null +++ b/zephyr/projects/nissa/xivu/led_policy.dtsi @@ -0,0 +1,122 @@ +/ { + led-colors { + compatible = "cros-ec,led-policy"; + + power-state-charge { + charge-state = "PWR_STATE_CHARGE"; + /* Battery percent range (>= Empty, <= 94%) */ + batt-lvl = <0 94>; + + color-0 { + led-color = <&color_amber>; + }; + }; + + power-state-charge-lvl-2 { + charge-state = "PWR_STATE_CHARGE"; + /* Battery percent range (>= 95%, <= Near Full) */ + batt-lvl = <95 97>; + + color-0 { + led-color = <&color_white>; + }; + }; + + power-state-near-full { + charge-state = "PWR_STATE_CHARGE_NEAR_FULL"; + + color-0 { + led-color = <&color_white>; + }; + }; + + power-state-discharge-s0 { + charge-state = "PWR_STATE_DISCHARGE"; + chipset-state = "POWER_S0"; + /* Battery percent range (>= 11%, <= Full) */ + batt-lvl = <11 100>; + + color-0 { + led-color = <&color_white>; + }; + }; + + power-state-discharge-s3 { + charge-state = "PWR_STATE_DISCHARGE"; + chipset-state = "POWER_S3"; + + /* White 1 sec, off 3 sec */ + color-0 { + led-color = <&color_white>; + period-ms = <1000>; + }; + color-1 { + led-color = <&color_off>; + period-ms = <3000>; + }; + }; + + power-state-discharge-s5 { + charge-state = "PWR_STATE_DISCHARGE"; + chipset-state = "POWER_S5"; + + color-0 { + led-color = <&color_off>; + }; + }; + + power-state-discharge-s0-batt-low { + charge-state = "PWR_STATE_DISCHARGE"; + chipset-state = "POWER_S0"; + /* Battery percent range (>= Empty, <= 10%) */ + batt-lvl = <0 10>; + + /* Amber 1 sec, off 3 sec */ + color-0 { + led-color = <&color_amber>; + period-ms = <1000>; + }; + color-1 { + led-color = <&color_off>; + period-ms = <3000>; + }; + }; + + power-state-error-s0 { + charge-state = "PWR_STATE_ERROR"; + chipset-state = "POWER_S0"; + /* Amber 1 sec, off 1 sec */ + color-0 { + led-color = <&color_amber>; + period-ms = <1000>; + }; + color-1 { + led-color = <&color_off>; + period-ms = <1000>; + }; + }; + + power-state-error-s3 { + charge-state = "PWR_STATE_ERROR"; + chipset-state = "POWER_S3"; + /* White 1 sec, off 3 sec */ + color-0 { + led-color = <&color_white>; + period-ms = <1000>; + }; + color-1 { + led-color = <&color_off>; + period-ms = <3000>; + }; + }; + + power-state-error-s5 { + charge-state = "PWR_STATE_ERROR"; + chipset-state = "POWER_S5"; + + color-0 { + led-color = <&color_off>; + }; + }; + }; +}; diff --git a/zephyr/projects/nissa/xivu/motionsense.dtsi b/zephyr/projects/nissa/xivu/motionsense.dtsi new file mode 100644 index 0000000000..332252c4ef --- /dev/null +++ b/zephyr/projects/nissa/xivu/motionsense.dtsi @@ -0,0 +1,156 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <dt-bindings/motionsense/utils.h> + + +/ { + aliases { + /* + * Interrupt bindings for sensor devices. + */ + lsm6dso-int = &base_accel; + lis2dw12-int = &lid_accel; + }; + + /* + * Declare mutexes used by sensor drivers. + * A mutex node is used to create an instance of mutex_t. + * A mutex node is referenced by a sensor node if the + * corresponding sensor driver needs to use the + * instance of the mutex. + */ + motionsense-mutex { + compatible = "cros-ec,motionsense-mutex"; + lid_mutex: lid-mutex { + }; + + base_mutex: base-mutex { + }; + }; + + /* Rotation matrix used by drivers. */ + motionsense-rotation-ref { + compatible = "cros-ec,motionsense-rotation-ref"; + lid_rot_ref: lid-rotation-ref { + mat33 = <0 1 0 + 1 0 0 + 0 0 (-1)>; + }; + + base_rot_ref: base-rotation-ref { + mat33 = <0 (-1) 0 + 1 0 0 + 0 0 1>; + }; + }; + + /* + * Driver specific data. A driver-specific data can be shared with + * different motion sensors while they are using the same driver. + * + * If a node's compatible starts with "cros-ec,accelgyro-", it is for + * a common structure defined in accelgyro.h. + * e.g) compatible = "cros-ec,accelgyro-als-drv-data" is for + * "struct als_drv_data_t" in accelgyro.h + */ + motionsense-sensor-data { + lsm6dso_accel_data: lsm6dso-accel-drv-data { + compatible = "cros-ec,drvdata-lsm6dso"; + status = "okay"; + }; + + lsm6dso_gyro_data: lsm6dso-gyro-drv-data { + compatible = "cros-ec,drvdata-lsm6dso"; + status = "okay"; + }; + + lis2dw12_data: lis2dw12-drv-data { + compatible = "cros-ec,drvdata-lis2dw12"; + status = "okay"; + }; + }; + + /* + * List of motion sensors that creates motion_sensors array. + * The nodelabel "lid_accel" and "base_accel" are used to indicate + * motion sensor IDs for lid angle calculation. + * TODO(b/238139272): The first entries of the array must be + * accelerometers,then gyroscope. Fix this dependency in the DTS + * processing which makes the devicetree entries independent. + */ + motionsense-sensor { + lid_accel: lid-accel { + compatible = "cros-ec,lis2dw12"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_LID"; + mutex = <&lid_mutex>; + port = <&i2c_ec_i2c_sensor>; + rot-standard-ref = <&lid_rot_ref>; + default-range = <2>; + drv-data = <&lis2dw12_data>; + i2c-spi-addr-flags = "LIS2DWL_ADDR0_FLAGS"; + configs { + compatible = + "cros-ec,motionsense-sensor-config"; + ec-s0 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + ec-s3 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + }; + }; + + base_accel: base-accel { + compatible = "cros-ec,lsm6dso-accel"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_BASE"; + mutex = <&base_mutex>; + port = <&i2c_ec_i2c_sensor>; + rot-standard-ref = <&base_rot_ref>; + drv-data = <&lsm6dso_accel_data>; + configs { + compatible = + "cros-ec,motionsense-sensor-config"; + ec-s0 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + ec-s3 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + }; + }; + + base_gyro: base-gyro { + compatible = "cros-ec,lsm6dso-gyro"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_BASE"; + mutex = <&base_mutex>; + port = <&i2c_ec_i2c_sensor>; + rot-standard-ref = <&base_rot_ref>; + default-range = <(1000 | ROUND_UP_FLAG)>; /* dps */ + drv-data = <&lsm6dso_gyro_data>; + }; + }; + + motionsense-sensor-info { + compatible = "cros-ec,motionsense-sensor-info"; + + /* + * list of GPIO interrupts that have to + * be enabled at initial stage + */ + sensor-irqs = <&int_imu>; + /* list of sensors in force mode */ + accel-force-mode-sensors = <&lid_accel>; + }; +}; diff --git a/zephyr/projects/nissa/xivu/overlay.dtsi b/zephyr/projects/nissa/xivu/overlay.dtsi new file mode 100644 index 0000000000..de45db75e7 --- /dev/null +++ b/zephyr/projects/nissa/xivu/overlay.dtsi @@ -0,0 +1,357 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <cros/thermistor/thermistor.dtsi> + +/ { + aliases { + gpio-cbi-wp = &gpio_ec_cbi_wp; + gpio-wp = &gpio_ec_wp_odl; + int-wp = &int_wp_l; + gpio-kbd-kso2 = &gpio_ec_kso_02_inv; + }; + + ec-console { + compatible = "ec-console"; + disabled = "events", "lpc", "hostcmd"; + }; + + batteries { + default_battery: smp_c31n2005 { + compatible = "smp,c31n2005", "battery-smart"; + }; + }; + + hibernate-wake-pins { + compatible = "cros-ec,hibernate-wake-pins"; + wakeup-irqs = < + &int_power_button + &int_lid_open + >; + }; + + gpio-interrupts { + compatible = "cros-ec,gpio-interrupts"; + + int_power_button: power_button { + irq-pin = <&gpio_gsc_ec_pwr_btn_odl>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "power_button_interrupt"; + }; + int_wp_l: wp_l { + irq-pin = <&gpio_ec_wp_odl>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "switch_interrupt"; + }; + int_lid_open: lid_open { + irq-pin = <&gpio_lid_open>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "lid_interrupt"; + }; + int_tablet_mode: tablet_mode { + irq-pin = <&gpio_tablet_mode_l>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "gmr_tablet_switch_isr"; + }; + int_imu: ec_imu { + irq-pin = <&gpio_imu_int_l>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "lsm6dso_interrupt"; + }; + int_vol_down: vol_down { + irq-pin = <&gpio_voldn_btn_odl>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "button_interrupt"; + }; + int_vol_up: vol_up { + irq-pin = <&gpio_volup_btn_odl>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "button_interrupt"; + }; + int_usb_c0: usb_c0 { + irq-pin = <&gpio_usb_c0_int_odl>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "usb_interrupt"; + }; + int_usb_c1: usb_c1 { + irq-pin = <&gpio_sb_1>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "usb_interrupt"; + }; + }; + + named-gpios { + gpio_sb_1: sb-1 { + gpios = <&gpio0 2 GPIO_PULL_UP>; + no-auto-init; + }; + + gpio_sb_2: sb-2 { + gpios = <&gpiod 4 GPIO_OUTPUT>; + no-auto-init; + }; + + /* + * Set I2C pins for type C sub-board to be low voltage (I2C5_1). + * We do this for all boards, since the pins are 3.3V tolerant, + * and the only 2 types of sub-boards used on nivviks both have + * type-C ports on them. + */ + gpio_sb_3: sb-3 { + gpios = <&gpiof 4 (GPIO_OPEN_DRAIN | GPIO_VOLTAGE_1P8)>; + no-auto-init; + }; + gpio_sb_4: sb-4 { + gpios = <&gpiof 5 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; + no-auto-init; + }; + }; + + /* + * Aliases used for sub-board GPIOs. + */ + aliases { + /* + * Input GPIO when used with type-C port 1 + */ + gpio-usb-c1-int-odl = &gpio_sb_1; + gpio-en-rails-odl = &gpio_sb_1; + /* + * Sub-board with type A USB, enable. + */ + gpio-en-usb-a1-vbus = &gpio_sb_2; + /* + * Enable S5 rails for LTE sub-board + */ + gpio-en-sub-s5-rails = &gpio_sb_2; + }; + + temp_memory: memory { + compatible = "cros-ec,temp-sensor-thermistor"; + thermistor = <&thermistor_3V3_51K1_47K_4050B>; + adc = <&adc_temp_sensor_1>; + }; + temp_ambient: ambient { + compatible = "cros-ec,temp-sensor-thermistor"; + thermistor = <&thermistor_3V3_51K1_47K_4050B>; + adc = <&adc_temp_sensor_2>; + }; + temp_charger1: charger1 { + compatible = "cros-ec,temp-sensor-thermistor"; + thermistor = <&thermistor_3V3_51K1_47K_4050B>; + adc = <&adc_temp_sensor_3>; + }; + temp_charger2: charger2 { + compatible = "cros-ec,temp-sensor-thermistor"; + thermistor = <&thermistor_3V3_51K1_47K_4050B>; + adc = <&adc_temp_sensor_4>; + }; + + named-temp-sensors { + compatible = "cros-ec,temp-sensors"; + memory { + temp_host_high = <85>; + temp_host_halt = <90>; + temp_host_release_high = <80>; + temp_host_release_halt = <80>; + power-good-pin = <&gpio_ec_soc_dsw_pwrok>; + sensor = <&temp_memory>; + }; + ambient { + temp_host_high = <85>; + temp_host_halt = <90>; + temp_host_release_high = <80>; + temp_host_release_halt = <80>; + power-good-pin = <&gpio_ec_soc_dsw_pwrok>; + sensor = <&temp_ambient>; + }; + charger1 { + temp_host_high = <85>; + temp_host_halt = <90>; + temp_host_release_high = <80>; + temp_host_release_halt = <80>; + power-good-pin = <&gpio_ec_soc_dsw_pwrok>; + sensor = <&temp_charger1>; + }; + charger2 { + temp_host_high = <85>; + temp_host_halt = <90>; + temp_host_release_high = <80>; + temp_host_release_halt = <80>; + power-good-pin = <&gpio_ec_soc_dsw_pwrok>; + sensor = <&temp_charger2>; + }; + }; + + usba { + compatible = "cros-ec,usba-port-enable-pins"; + /* + * sb_2 is only configured as GPIO when USB-A1 is present, + * but it's still safe to control when disabled. + * + * ILIM_SEL pins are referred to by legacy enum name, + * GPIO_USB*_ILIM_SEL. The one for port A1 is unused on + * sub-boards that don't have USB-A so is safe to control + * regardless of system configuration. + */ + enable-pins = <&gpio_en_usb_a0_vbus &gpio_sb_2>; + status = "okay"; + }; + + usbc { + #address-cells = <1>; + #size-cells = <0>; + + port0@0 { + compatible = "named-usbc-port"; + reg = <0>; + bc12 = <&bc12_port0>; + chg = <&chg_port0>; + usb-mux-chain-0 { + compatible = "cros-ec,usb-mux-chain"; + usb-muxes = <&virtual_mux_0>; + }; + }; + port0-muxes { + virtual_mux_0: virtual-mux-0 { + compatible = "cros-ec,usbc-mux-virtual"; + }; + }; + /* + * TODO(b:211693800): port1 may not be present on some + * sub-boards. + */ + port1@1 { + compatible = "named-usbc-port"; + reg = <1>; + bc12 = <&bc12_port1>; + chg = <&chg_port1>; + usb-mux-chain-1 { + compatible = "cros-ec,usb-mux-chain"; + usb-muxes = <&virtual_mux_1 &anx7483_mux_1>; + }; + usb_mux_chain_1_no_mux: usb-mux-chain-1-no-mux { + compatible = "cros-ec,usb-mux-chain"; + alternative-chain; + usb-muxes = <&virtual_mux_1>; + }; + }; + port1-muxes { + virtual_mux_1: virtual-mux-1 { + compatible = "cros-ec,usbc-mux-virtual"; + }; + }; + }; + + unused-pins { + compatible = "unused-gpios"; + unused-gpios = + <&gpio8 5 0>, + <&gpio3 6 0>, + <&gpiod 7 0>, + <&gpio6 0 0>, + <&gpiof 2 0>, + <&gpiof 3 0>; + }; +}; + +&thermistor_3V3_51K1_47K_4050B { + status = "okay"; +}; + +&adc_ec_vsense_pp3300_s5 { + /* + * Voltage divider on input has 47k upper and 220k lower legs with + * 2714 mV full-scale reading on the ADC. Apply the largest possible + * multiplier (without overflowing int32) to get the best possible + * approximation of the actual ratio, but derate by a factor of two to + * ensure unexpectedly high values won't overflow. + */ + mul = <(791261 / 2)>; + div = <(651975 / 2)>; +}; + +/* Set bus speeds for I2C */ +&i2c0_0 { + label = "I2C_EEPROM"; + clock-frequency = <I2C_BITRATE_FAST>; + + cbi_eeprom: eeprom@50 { + compatible = "atmel,at24"; + reg = <0x50>; + size = <2048>; + pagesize = <16>; + address-width = <8>; + timeout = <5>; + }; +}; + +&i2c1_0 { + label = "I2C_SENSOR"; + clock-frequency = <I2C_BITRATE_FAST>; +}; + +&i2c3_0 { + label = "I2C_USB_C0_TCPC"; + clock-frequency = <I2C_BITRATE_FAST_PLUS>; + + bc12_port0: pi3usb9201@5f { + compatible = "pericom,pi3usb9201"; + status = "okay"; + reg = <0x5f>; + /* + * BC1.2 interrupt is shared with TCPC, so + * IRQ is not specified here and handled by + * usb_c0_interrupt. + */ + }; + + chg_port0: isl923x@9 { + compatible = "intersil,isl923x"; + status = "okay"; + reg = <0x9>; + }; +}; + +&i2c5_1 { + label = "I2C_SUB_C1_TCPC"; + clock-frequency = <I2C_BITRATE_FAST_PLUS>; + + bc12_port1: pi3usb9201@5f { + compatible = "pericom,pi3usb9201"; + status = "okay"; + reg = <0x5f>; + }; + + chg_port1: isl923x@9 { + compatible = "intersil,isl923x"; + status = "okay"; + reg = <0x9>; + }; + + anx7483_mux_1: anx7483-mux-1@3e { + compatible = "analogix,anx7483"; + reg = <0x3e>; + board-set = "anx7483_set_default_tuning"; + }; +}; + +&i2c7_0 { + label = "I2C_BATTERY"; + clock-frequency = <I2C_BITRATE_STANDARD>; +}; + +&pwm6 { + status = "okay"; + pinctrl-0 = <&pwm6_gpc0>; + pinctrl-names = "default"; +}; + +/* host interface */ +&espi0 { + status = "okay"; + pinctrl-0 = <&espi_lpc_gp46_47_51_52_53_54_55_57>; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/nissa/xivu/power_signals.dtsi b/zephyr/projects/nissa/xivu/power_signals.dtsi new file mode 100644 index 0000000000..1d2b23069d --- /dev/null +++ b/zephyr/projects/nissa/xivu/power_signals.dtsi @@ -0,0 +1,220 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + chosen { + intel-ap-pwrseq,espi = &espi0; + }; + + common-pwrseq { + compatible = "intel,ap-pwrseq"; + + sys-pwrok-delay = <10>; + all-sys-pwrgd-timeout = <20>; + }; + + pwr-en-pp5000-s5 { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "PP5000_S5 enable output to regulator"; + enum-name = "PWR_EN_PP5000_A"; + gpios = <&gpio4 0 0>; + output; + }; + pwr-en-pp3300-s5 { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "PP3300_S5 enable output to LS"; + enum-name = "PWR_EN_PP3300_A"; + gpios = <&gpiob 6 0>; + output; + }; + pwr-pg-ec-rsmrst-od { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "RSMRST power good from regulator"; + enum-name = "PWR_RSMRST"; + gpios = <&gpio9 4 0>; + interrupt-flags = <GPIO_INT_EDGE_BOTH>; + }; + pwr-ec-pch-rsmrst-odl { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "RSMRST output to PCH"; + enum-name = "PWR_EC_PCH_RSMRST"; + gpios = <&gpioa 6 0>; + output; + }; + pwr-slp-s0-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SLP_S0_L input from PCH"; + enum-name = "PWR_SLP_S0"; + gpios = <&gpio9 7 GPIO_ACTIVE_LOW>; + interrupt-flags = <GPIO_INT_EDGE_BOTH>; + }; + pwr-slp-s3-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SLP_S3_L input from PCH"; + enum-name = "PWR_SLP_S3"; + gpios = <&gpioa 5 GPIO_ACTIVE_LOW>; + interrupt-flags = <GPIO_INT_EDGE_BOTH>; + }; + pwr-slp-sus-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SLP_SUS_L input from PCH"; + enum-name = "PWR_SLP_SUS"; + gpios = <&gpio6 2 GPIO_ACTIVE_LOW>; + interrupt-flags = <GPIO_INT_EDGE_BOTH>; + }; + pwr-ec-soc-dsw-pwrok { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "DSW_PWROK output to PCH"; + enum-name = "PWR_EC_SOC_DSW_PWROK"; + gpios = <&gpio6 1 0>; + output; + }; + pwr-vccst-pwrgd-od { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "VCCST_PWRGD output to PCH"; + enum-name = "PWR_VCCST_PWRGD"; + gpios = <&gpioa 4 GPIO_OPEN_DRAIN>; + output; + }; + pwr-imvp9-vrrdy-od { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "VRRDY input from IMVP9"; + enum-name = "PWR_IMVP9_VRRDY"; + gpios = <&gpio4 3 0>; + }; + pwr-pch-pwrok { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "PCH_PWROK output to PCH"; + enum-name = "PWR_PCH_PWROK"; + gpios = <&gpio7 2 GPIO_OPEN_DRAIN>; + output; + }; + pwr-ec-pch-sys-pwrok { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SYS_PWROK output to PCH"; + enum-name = "PWR_EC_PCH_SYS_PWROK"; + gpios = <&gpio3 7 0>; + output; + }; + pwr-sys-rst-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SYS_RESET# output to PCH"; + enum-name = "PWR_SYS_RST"; + gpios = <&gpioc 5 (GPIO_ACTIVE_LOW|GPIO_OPEN_DRAIN)>; + output; + }; + pwr-slp-s4 { + compatible = "intel,ap-pwrseq-vw"; + dbg-label = "SLP_S4 virtual wire input from PCH"; + enum-name = "PWR_SLP_S4"; + virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S4"; + vw-invert; + }; + pwr-slp-s5 { + compatible = "intel,ap-pwrseq-vw"; + dbg-label = "SLP_S5 virtual wire input from PCH"; + enum-name = "PWR_SLP_S5"; + virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S5"; + vw-invert; + }; + pwr-all-sys-pwrgd { + compatible = "intel,ap-pwrseq-external"; + dbg-label = "Combined all power good"; + enum-name = "PWR_ALL_SYS_PWRGD"; + }; + pwr-adc-pp3300 { + compatible = "intel,ap-pwrseq-adc"; + dbg-label = "PP3300 PWROK (from ADC)"; + enum-name = "PWR_DSW_PWROK"; + trigger-high = <&cmp_pp3300_s5_high>; + trigger-low = <&cmp_pp3300_s5_low>; + }; + pwr-adc-pp1p05 { + compatible = "intel,ap-pwrseq-adc"; + dbg-label = "PP1P05 PWROK (from ADC)"; + enum-name = "PWR_PG_PP1P05"; + trigger-high = <&cmp_pp1p05_high>; + trigger-low = <&cmp_pp1p05_low>; + }; + + adc-cmp { + cmp_pp3300_s5_high: pp3300_high { + compatible = "nuvoton,adc-cmp"; + io-channels = <&adc0 6>; + comparison = "ADC_CMP_NPCX_GREATER"; + /* + * This is 90% of nominal voltage considering voltage + * divider on ADC input. + */ + threshold-mv = <2448>; + }; + cmp_pp3300_s5_low: pp3300_low { + compatible = "nuvoton,adc-cmp"; + io-channels = <&adc0 6>; + comparison = "ADC_CMP_NPCX_LESS_OR_EQUAL"; + threshold-mv = <2448>; + }; + cmp_pp1p05_high: pp1p05_high { + compatible = "nuvoton,adc-cmp"; + io-channels = <&adc0 4>; + comparison = "ADC_CMP_NPCX_GREATER"; + /* Setting at 90% of nominal voltage */ + threshold-mv = <945>; + }; + cmp_pp1p05_low: pp1p05_low { + compatible = "nuvoton,adc-cmp"; + io-channels = <&adc0 4>; + comparison = "ADC_CMP_NPCX_LESS_OR_EQUAL"; + threshold-mv = <945>; + }; + }; +}; + +/* + * Because the power signals directly reference the GPIOs, + * the correspinding named-gpios need to have no-auto-init set. + */ +&gpio_ec_soc_dsw_pwrok { + no-auto-init; +}; +&gpio_ec_soc_pch_pwrok_od { + no-auto-init; +}; +&gpio_ec_soc_rsmrst_l { + no-auto-init; +}; +&gpio_ec_soc_sys_pwrok { + no-auto-init; +}; +&gpio_ec_soc_vccst_pwrgd_od { + no-auto-init; +}; +&gpio_en_pp3300_s5 { + no-auto-init; +}; +&gpio_en_pp5000_s5 { + no-auto-init; +}; +&gpio_imvp91_vrrdy_od { + no-auto-init; +}; +&gpio_rsmrst_pwrgd_l { + no-auto-init; +}; +&gpio_slp_s0_l { + no-auto-init; +}; +&gpio_slp_s3_l { + no-auto-init; +}; +&gpio_slp_s4_l { + no-auto-init; +}; +&gpio_slp_sus_l { + no-auto-init; +}; +&gpio_sys_rst_odl { + no-auto-init; +}; diff --git a/zephyr/projects/nissa/xivu/project.conf b/zephyr/projects/nissa/xivu/project.conf new file mode 100644 index 0000000000..4ce9c635c3 --- /dev/null +++ b/zephyr/projects/nissa/xivu/project.conf @@ -0,0 +1,14 @@ +# Copyright 2022 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +CONFIG_BOARD_XIVU=y +CONFIG_PLATFORM_EC_OCPC=y +CONFIG_PLATFORM_EC_ACCELGYRO_LSM6DSO=y + +# LED +CONFIG_PLATFORM_EC_LED_COMMON=n +CONFIG_PLATFORM_EC_LED_DT=y + +# USBC +CONFIG_PLATFORM_EC_PD_MAX_POWER_MW=45000 diff --git a/zephyr/projects/nissa/xivu/project.overlay b/zephyr/projects/nissa/xivu/project.overlay new file mode 100644 index 0000000000..a7c5b7e9e7 --- /dev/null +++ b/zephyr/projects/nissa/xivu/project.overlay @@ -0,0 +1,15 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "../cbi.dtsi" + +#include "cbi.dtsi" +#include "generated.dtsi" +#include "keyboard.dtsi" +#include "led_pins.dtsi" +#include "led_policy.dtsi" +#include "motionsense.dtsi" +#include "overlay.dtsi" +#include "power_signals.dtsi" diff --git a/zephyr/projects/nissa/xivu/src/charger.c b/zephyr/projects/nissa/xivu/src/charger.c new file mode 100644 index 0000000000..5021a55758 --- /dev/null +++ b/zephyr/projects/nissa/xivu/src/charger.c @@ -0,0 +1,69 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <zephyr/logging/log.h> + +#include "battery.h" +#include "charger.h" +#include "charger/isl923x_public.h" +#include "console.h" +#include "extpower.h" +#include "usb_pd.h" +#include "nissa_common.h" + +LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL); + +int extpower_is_present(void) +{ + int port; + int rv; + bool acok; + + for (port = 0; port < board_get_usb_pd_port_count(); port++) { + rv = raa489000_is_acok(port, &acok); + if ((rv == EC_SUCCESS) && acok) + return 1; + } + + return 0; +} + +/* + * Xivu does not have a GPIO indicating whether extpower is present, + * so detect using the charger(s). + */ +__override void board_check_extpower(void) +{ + static int last_extpower_present; + int extpower_present_p0 = 0; + int extpower_present_p1 = 0; + + int extpower_present = extpower_is_present(); + + if (last_extpower_present ^ extpower_present) + extpower_handle_update(extpower_present); + + last_extpower_present = extpower_present; + + if (pd_is_connected(0)) + extpower_present_p0 = extpower_is_present(); + else if (pd_is_connected(1)) + extpower_present_p1 = extpower_is_present(); + + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_acok_otg_c0), + extpower_present_p0); + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_acok_otg_c1), + extpower_present_p1); +} + +__override void board_hibernate(void) +{ + /* Shut down the chargers */ + if (board_get_usb_pd_port_count() == 2) + raa489000_hibernate(CHARGER_SECONDARY, true); + raa489000_hibernate(CHARGER_PRIMARY, true); + LOG_INF("Charger(s) hibernated"); + cflush(); +} diff --git a/zephyr/projects/nissa/xivu/src/keyboard.c b/zephyr/projects/nissa/xivu/src/keyboard.c new file mode 100644 index 0000000000..ef799fb1d2 --- /dev/null +++ b/zephyr/projects/nissa/xivu/src/keyboard.c @@ -0,0 +1,29 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "ec_commands.h" + +static const struct ec_response_keybd_config xivu_kb_legacy = { + .num_top_row_keys = 10, + .action_keys = { + TK_BACK, /* T1 */ + TK_REFRESH, /* T2 */ + TK_FULLSCREEN, /* T3 */ + TK_OVERVIEW, /* T4 */ + TK_SNAPSHOT, /* T5 */ + TK_BRIGHTNESS_DOWN, /* T6 */ + TK_BRIGHTNESS_UP, /* T7 */ + TK_VOL_MUTE, /* 8 */ + TK_VOL_DOWN, /* T9 */ + TK_VOL_UP, /* T10 */ + }, + .capabilities = KEYBD_CAP_SCRNLOCK_KEY, +}; + +__override const struct ec_response_keybd_config * +board_vivaldi_keybd_config(void) +{ + return &xivu_kb_legacy; +} diff --git a/zephyr/projects/nissa/xivu/src/usbc.c b/zephyr/projects/nissa/xivu/src/usbc.c new file mode 100644 index 0000000000..1520efaa55 --- /dev/null +++ b/zephyr/projects/nissa/xivu/src/usbc.c @@ -0,0 +1,285 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <zephyr/logging/log.h> + +#include "charge_state_v2.h" +#include "chipset.h" +#include "hooks.h" +#include "usb_mux.h" +#include "system.h" +#include "driver/charger/isl923x_public.h" +#include "driver/retimer/anx7483_public.h" +#include "driver/tcpm/tcpci.h" +#include "driver/tcpm/raa489000.h" + +#include "nissa_common.h" + +LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL); + +struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = { + { + .bus_type = EC_BUS_TYPE_I2C, + .i2c_info = { + .port = I2C_PORT_USB_C0_TCPC, + .addr_flags = RAA489000_TCPC0_I2C_FLAGS, + }, + .drv = &raa489000_tcpm_drv, + /* RAA489000 implements TCPCI 2.0 */ + .flags = TCPC_FLAGS_TCPCI_REV2_0 | + TCPC_FLAGS_VBUS_MONITOR, + }, + { /* sub-board */ + .bus_type = EC_BUS_TYPE_I2C, + .i2c_info = { + .port = I2C_PORT_USB_C1_TCPC, + .addr_flags = RAA489000_TCPC0_I2C_FLAGS, + }, + .drv = &raa489000_tcpm_drv, + /* RAA489000 implements TCPCI 2.0 */ + .flags = TCPC_FLAGS_TCPCI_REV2_0 | + TCPC_FLAGS_VBUS_MONITOR, + }, +}; + +int board_is_sourcing_vbus(int port) +{ + int regval; + + tcpc_read(port, TCPC_REG_POWER_STATUS, ®val); + return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS); +} + +int board_set_active_charge_port(int port) +{ + int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT); + int i; + int old_port; + + if (!is_real_port && port != CHARGE_PORT_NONE) + return EC_ERROR_INVAL; + + old_port = charge_manager_get_active_charge_port(); + + LOG_INF("New chg p%d", port); + + /* Disable all ports. */ + if (port == CHARGE_PORT_NONE) { + for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) { + tcpc_write(i, TCPC_REG_COMMAND, + TCPC_REG_COMMAND_SNK_CTRL_LOW); + raa489000_enable_asgate(i, false); + } + + return EC_SUCCESS; + } + + /* Check if port is sourcing VBUS. */ + if (board_is_sourcing_vbus(port)) { + LOG_WRN("Skip enable p%d", port); + return EC_ERROR_INVAL; + } + + /* + * Turn off the other ports' sink path FETs, before enabling the + * requested charge port. + */ + for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) { + if (i == port) + continue; + + if (tcpc_write(i, TCPC_REG_COMMAND, + TCPC_REG_COMMAND_SNK_CTRL_LOW)) + LOG_WRN("p%d: sink path disable failed.", i); + raa489000_enable_asgate(i, false); + } + + /* + * Stop the charger IC from switching while changing ports. Otherwise, + * we can overcurrent the adapter we're switching to. (crbug.com/926056) + */ + if (old_port != CHARGE_PORT_NONE) + charger_discharge_on_ac(1); + + /* Enable requested charge port. */ + if (raa489000_enable_asgate(port, true) || + tcpc_write(port, TCPC_REG_COMMAND, + TCPC_REG_COMMAND_SNK_CTRL_HIGH)) { + LOG_WRN("p%d: sink path enable failed.", port); + charger_discharge_on_ac(0); + return EC_ERROR_UNKNOWN; + } + + /* Allow the charger IC to begin/continue switching. */ + charger_discharge_on_ac(0); + + return EC_SUCCESS; +} + +uint16_t tcpc_get_alert_status(void) +{ + uint16_t status = 0; + int regval; + + /* + * The interrupt line is shared between the TCPC and BC1.2 detector IC. + * Therefore, go out and actually read the alert registers to report the + * alert status. + */ + if (!gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_c0_int_odl))) { + if (!tcpc_read16(0, TCPC_REG_ALERT, ®val)) { + /* The TCPCI Rev 1.0 spec says to ignore bits 14:12. */ + if (!(tcpc_config[0].flags & TCPC_FLAGS_TCPCI_REV2_0)) + regval &= ~((1 << 14) | (1 << 13) | (1 << 12)); + + if (regval) + status |= PD_STATUS_TCPC_ALERT_0; + } + } + + if (board_get_usb_pd_port_count() == 2 && + !gpio_pin_get_dt(GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl))) { + if (!tcpc_read16(1, TCPC_REG_ALERT, ®val)) { + /* TCPCI spec Rev 1.0 says to ignore bits 14:12. */ + if (!(tcpc_config[1].flags & TCPC_FLAGS_TCPCI_REV2_0)) + regval &= ~((1 << 14) | (1 << 13) | (1 << 12)); + + if (regval) + status |= PD_STATUS_TCPC_ALERT_1; + } + } + + return status; +} + +void pd_power_supply_reset(int port) +{ + /* Disable VBUS */ + tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_LOW); + + /* Notify host of power info change. */ + pd_send_host_event(PD_EVENT_POWER_CHANGE); +} + +__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp) +{ + if (port < 0 || port >= CONFIG_USB_PD_PORT_MAX_COUNT) + return; + + raa489000_set_output_current(port, rp); +} + +int pd_set_power_supply_ready(int port) +{ + int rv; + + if (port >= CONFIG_USB_PD_PORT_MAX_COUNT) + return EC_ERROR_INVAL; + + /* Disable charging. */ + rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW); + if (rv) + return rv; + + /* Our policy is not to source VBUS when the AP is off. */ + if (chipset_in_state(CHIPSET_STATE_ANY_OFF)) + return EC_ERROR_NOT_POWERED; + + /* Provide Vbus. */ + rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_HIGH); + if (rv) + return rv; + + rv = raa489000_enable_asgate(port, true); + if (rv) + return rv; + + /* Notify host of power info change. */ + pd_send_host_event(PD_EVENT_POWER_CHANGE); + + return EC_SUCCESS; +} + +void board_reset_pd_mcu(void) +{ + /* + * TODO(b:147316511): could send a reset command to the TCPC here + * if needed. + */ +} + +/* + * Because the TCPCs and BC1.2 chips share interrupt lines, it's possible + * for an interrupt to be lost if one asserts the IRQ, the other does the same + * then the first releases it: there will only be one falling edge to trigger + * the interrupt, and the line will be held low. We handle this by running a + * deferred check after a falling edge to see whether the IRQ is still being + * asserted. If it is, we assume an interrupt may have been lost and we need + * to poll each chip for events again. + */ +#define USBC_INT_POLL_DELAY_US 5000 + +static void poll_c0_int(void); +DECLARE_DEFERRED(poll_c0_int); +static void poll_c1_int(void); +DECLARE_DEFERRED(poll_c1_int); + +static void usbc_interrupt_trigger(int port) +{ + schedule_deferred_pd_interrupt(port); + usb_charger_task_set_event(port, USB_CHG_EVENT_BC12); +} + +static inline void poll_usb_gpio(int port, const struct gpio_dt_spec *gpio, + const struct deferred_data *ud) +{ + if (!gpio_pin_get_dt(gpio)) { + usbc_interrupt_trigger(port); + hook_call_deferred(ud, USBC_INT_POLL_DELAY_US); + } +} + +static void poll_c0_int(void) +{ + poll_usb_gpio(0, GPIO_DT_FROM_NODELABEL(gpio_usb_c0_int_odl), + &poll_c0_int_data); +} + +static void poll_c1_int(void) +{ + poll_usb_gpio(1, GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl), + &poll_c1_int_data); +} + +void usb_interrupt(enum gpio_signal signal) +{ + int port; + const struct deferred_data *ud; + + if (signal == GPIO_SIGNAL(DT_NODELABEL(gpio_usb_c0_int_odl))) { + port = 0; + ud = &poll_c0_int_data; + } else { + port = 1; + ud = &poll_c1_int_data; + } + /* + * We've just been called from a falling edge, so there's definitely + * no lost IRQ right now. Cancel any pending check. + */ + hook_call_deferred(ud, -1); + /* Trigger polling of TCPC and BC1.2 in respective tasks */ + usbc_interrupt_trigger(port); + /* Check for lost interrupts in a bit */ + hook_call_deferred(ud, USBC_INT_POLL_DELAY_US); +} + +__override void board_set_charge_limit(int port, int supplier, int charge_ma, + int max_ma, int charge_mv) +{ + charge_ma = (charge_ma * 90) / 100; + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); +} diff --git a/zephyr/projects/nissa/yaviks/cbi.dtsi b/zephyr/projects/nissa/yaviks/cbi.dtsi new file mode 100644 index 0000000000..c5716cbd37 --- /dev/null +++ b/zephyr/projects/nissa/yaviks/cbi.dtsi @@ -0,0 +1,99 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + /* Yaviks-specific fw_config fields. */ + nissa-fw-config { + /* + * FW_CONFIG field for multiple wi-fi SAR. + * + * start = <2>; + * size = <2>; + */ + + /* + * FW_CONFIG field to enable fan or not. + */ + fan { + enum-name = "FW_FAN"; + start = <4>; + size = <1>; + + no-fan { + compatible = "cros-ec,cbi-fw-config-value"; + enum-name = "FW_FAN_NOT_PRESENT"; + value = <0>; + }; + fan-present { + compatible = "cros-ec,cbi-fw-config-value"; + enum-name = "FW_FAN_PRESENT"; + value = <1>; + /* + * Set as default so that unprovisioned + * configs will run the fan regardless. + */ + default; + }; + }; + + /* + * FW_CONFIG field to indicate which keyboard layout + * should be used. + */ + keyboard { + enum-name = "FW_KB_LAYOUT"; + start = <5>; + size = <1>; + + layout-1 { + compatible = "cros-ec,cbi-fw-config-value"; + enum-name = "FW_KB_LAYOUT_DEFAULT"; + value = <0>; + default; + }; + layout-2 { + compatible = "cros-ec,cbi-fw-config-value"; + enum-name = "FW_KB_LAYOUT_US2"; + value = <1>; + }; + }; + + /* + * FW_CONFIG field to indicate which keyboard layout + * should be used. + */ + keyboard-backlight { + enum-name = "FW_KB_BACKLIGHT"; + start = <6>; + size = <1>; + + without-keyboard-backlight { + compatible = "cros-ec,cbi-fw-config-value"; + enum-name = "FW_KB_BACKLIGHT_OFF"; + value = <1>; + }; + with-keyboard-backlight { + compatible = "cros-ec,cbi-fw-config-value"; + enum-name = "FW_KB_BACKLIGHT_ON"; + value = <0>; + default; + }; + }; + + /* + * FW_CONFIG field for multiple touch panel. + * + * start = <7>; + * size = <2>; + */ + + /* + * FW_CONFIG field for multiple storage. + * + * start = <31>; + * size = <1>; + */ + }; +}; diff --git a/zephyr/projects/nissa/yaviks/gpio.dtsi b/zephyr/projects/nissa/yaviks/gpio.dtsi new file mode 100644 index 0000000000..dae1d641cd --- /dev/null +++ b/zephyr/projects/nissa/yaviks/gpio.dtsi @@ -0,0 +1,232 @@ +/* + * Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + + named-adc-channels { + compatible = "named-adc-channels"; + + adc_ec_vsense_pp1050_proc: ec_vsense_pp1050_proc { + enum-name = "ADC_PP1050_PROC"; + io-channels = <&adc0 14>; + }; + adc_ec_vsense_pp3300_s5: ec_vsense_pp3300_s5 { + enum-name = "ADC_PP3300_S5"; + io-channels = <&adc0 0>; + }; + adc_temp_sensor_1: temp_sensor_1 { + enum-name = "ADC_TEMP_SENSOR_1"; + io-channels = <&adc0 2>; + }; + adc_temp_sensor_2: temp_sensor_2 { + enum-name = "ADC_TEMP_SENSOR_2"; + io-channels = <&adc0 3>; + }; + adc_temp_sensor_3: temp_sensor_3 { + enum-name = "ADC_TEMP_SENSOR_3"; + io-channels = <&adc0 13>; + }; + }; + + named-gpios { + compatible = "named-gpios"; + + gpio_all_sys_pwrgd: all_sys_pwrgd { + gpios = <&gpiob 7 GPIO_INPUT>; + }; + gpio_ccd_mode_odl: ccd_mode_odl { + gpios = <&gpioh 5 GPIO_INPUT>; + enum-name = "GPIO_CCD_MODE_ODL"; + }; + gpio_cpu_c10_gate_l: cpu_c10_gate_l { + gpios = <&gpiog 1 GPIO_INPUT>; + }; + gpio_ec_battery_pres_odl: ec_battery_pres_odl { + gpios = <&gpioi 4 GPIO_INPUT>; + enum-name = "GPIO_BATT_PRES_ODL"; + }; + gpio_ec_cbi_wp: ec_cbi_wp { + gpios = <&gpioj 5 GPIO_OUTPUT>; + }; + gpio_ec_edp_bl_en_od: ec_edp_bl_en_od { + gpios = <&gpiok 4 GPIO_ODR_HIGH>; + enum-name = "GPIO_ENABLE_BACKLIGHT"; + }; + gpio_ec_entering_rw: ec_entering_rw { + gpios = <&gpioc 7 GPIO_OUTPUT>; + enum-name = "GPIO_ENTERING_RW"; + }; + gpio_ec_gsc_packet_mode: ec_gsc_packet_mode { + gpios = <&gpioh 1 GPIO_OUTPUT>; + enum-name = "GPIO_PACKET_MODE_EN"; + }; + gpio_ec_pch_wake_odl: ec_pch_wake_odl { + gpios = <&gpiob 2 GPIO_ODR_LOW>; + }; + gpio_ec_prochot_odl: ec_prochot_odl { + gpios = <&gpioi 1 (GPIO_ODR_HIGH | GPIO_VOLTAGE_1P8)>; + }; + gpio_ec_soc_dsw_pwrok: ec_soc_dsw_pwrok { + gpios = <&gpiol 7 GPIO_OUTPUT>; + no-auto-init; + }; + gpio_ec_soc_int_odl: ec_soc_int_odl { + gpios = <&gpiod 5 GPIO_ODR_HIGH>; + enum-name = "GPIO_EC_INT_L"; + }; + gpio_ec_soc_pch_pwrok_od: ec_soc_pch_pwrok_od { + gpios = <&gpiod 6 GPIO_ODR_HIGH>; + no-auto-init; + }; + gpio_ec_soc_pwr_btn_odl: ec_soc_pwr_btn_odl { + gpios = <&gpiob 6 GPIO_ODR_HIGH>; + enum-name = "GPIO_PCH_PWRBTN_L"; + }; + gpio_ec_soc_rsmrst_l: ec_soc_rsmrst_l { + gpios = <&gpioh 0 GPIO_OUTPUT>; + no-auto-init; + }; + gpio_ec_soc_rtcrst: ec_soc_rtcrst { + gpios = <&gpiok 2 GPIO_OUTPUT>; + }; + gpio_ec_soc_sys_pwrok: ec_soc_sys_pwrok { + gpios = <&gpiof 2 GPIO_OUTPUT>; + no-auto-init; + }; + gpio_ec_soc_vccst_pwrgd_od: ec_soc_vccst_pwrgd_od { + gpios = <&gpioe 5 GPIO_ODR_HIGH>; + no-auto-init; + }; + gpio_ec_wp_odl: ec_wp_odl { + gpios = <&gpioa 6 (GPIO_INPUT | GPIO_ACTIVE_LOW)>; + }; + gpio_en_pp3300_s5: en_pp3300_s5 { + gpios = <&gpioc 5 GPIO_OUTPUT>; + enum-name = "GPIO_TEMP_SENSOR_POWER"; + no-auto-init; + }; + gpio_en_pp5000_pen_x: en_pp5000_pen_x { + gpios = <&gpiob 5 GPIO_OUTPUT>; + }; + gpio_en_pp5000_s5: en_pp5000_s5 { + gpios = <&gpiok 5 GPIO_OUTPUT>; + no-auto-init; + }; + gpio_en_slp_z: en_slp_z { + gpios = <&gpiok 3 GPIO_OUTPUT>; + }; + gpio_en_usb_a0_vbus: en_usb_a0_vbus { + gpios = <&gpiol 6 GPIO_OUTPUT>; + }; + gpio_en_usb_c0_cc1_vconn: en_usb_c0_cc1_vconn { + gpios = <&gpioh 4 GPIO_OUTPUT>; + }; + gpio_en_usb_c0_cc2_vconn: en_usb_c0_cc2_vconn { + gpios = <&gpioh 6 GPIO_OUTPUT>; + }; + gpio_gsc_ec_pwr_btn_odl: gsc_ec_pwr_btn_odl { + gpios = <&gpioe 2 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_POWER_BUTTON_L"; + }; + gpio_imvp91_vrrdy_od: imvp91_vrrdy_od { + gpios = <&gpioj 4 GPIO_INPUT>; + no-auto-init; + }; + gpio_lid_open: lid_open { + gpios = <&gpiof 3 GPIO_INPUT>; + enum-name = "GPIO_LID_OPEN"; + }; + gpio_pen_detect_odl: pen_detect_odl { + gpios = <&gpioj 1 GPIO_INPUT_PULL_UP>; + }; + gpio_pg_pp1050_mem_s3_od: pg_pp1050_mem_s3_od { + gpios = <&gpiod 3 GPIO_INPUT>; + }; + gpio_pg_pp5000_s5_od: pg_pp5000_s5_od { + gpios = <&gpioe 3 GPIO_INPUT>; + }; + gpio_rsmrst_pwrgd_l: rsmrst_pwrgd_l { + gpios = <&gpioe 1 GPIO_INPUT_PULL_UP>; + no-auto-init; + }; + gpio_slp_s0_l: slp_s0_l { + gpios = <&gpioe 4 GPIO_INPUT>; + no-auto-init; + }; + gpio_slp_s3_l: slp_s3_l { + gpios = <&gpioh 3 GPIO_INPUT>; + no-auto-init; + }; + gpio_slp_s4_l: slp_s4_l { + gpios = <&gpioi 5 GPIO_INPUT>; + }; + gpio_slp_sus_l: slp_sus_l { + gpios = <&gpiog 2 GPIO_INPUT>; + no-auto-init; + }; + gpio_sub_usb_a1_ilimit_sdp: sub_usb_a1_ilimit_sdp { + gpios = <&gpiof 1 GPIO_OUTPUT>; + enum-name = "GPIO_USB2_ILIM_SEL"; + }; + gpio_sys_rst_odl: sys_rst_odl { + gpios = <&gpiod 1 GPIO_ODR_HIGH>; + no-auto-init; + }; + gpio_usb_a0_ilimit_sdp: usb_a0_ilimit_sdp { + gpios = <&gpiol 5 GPIO_OUTPUT>; + enum-name = "GPIO_USB1_ILIM_SEL"; + }; + gpio_usb_c0_frs: usb_c0_frs { + gpios = <&gpioc 4 GPIO_OUTPUT>; + }; + gpio_usb_c0_int_odl: usb_c0_int_odl { + gpios = <&gpiok 0 GPIO_INPUT_PULL_UP>; + }; + gpio_vccin_aux_vid0: vccin_aux_vid0 { + gpios = <&gpiod 0 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; + }; + gpio_vccin_aux_vid1: vccin_aux_vid1 { + gpios = <&gpiok 1 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; + }; + gpio_c1_charger_led_white_l: c1_charger_led_white_l { + gpios = <&gpiol 4 GPIO_OUTPUT_HIGH>; + }; + gpio_c1_charger_led_amber_l: c1_charger_led_amber_l { + gpios = <&gpiod 4 GPIO_OUTPUT_HIGH>; + }; + gpio_c0_charger_led_white_l: c0_charger_led_white_l { + gpios = <&gpioc 3 GPIO_OUTPUT_HIGH>; + }; + gpio_c0_charger_led_amber_l: c0_charger_led_amber_l { + gpios = <&gpioj 7 GPIO_OUTPUT_HIGH>; + }; + }; + + named-i2c-ports { + compatible = "named-i2c-ports"; + + i2c_ec_i2c_eeprom: ec_i2c_eeprom { + i2c-port = <&i2c0>; + enum-names = "I2C_PORT_EEPROM"; + }; + i2c_ec_i2c_batt: ec_i2c_batt { + i2c-port = <&i2c1>; + enum-names = "I2C_PORT_BATTERY"; + }; + i2c_ec_i2c_sensor: ec_i2c_sensor { + i2c-port = <&i2c2>; + enum-names = "I2C_PORT_SENSOR"; + }; + i2c_ec_i2c_sub_usb_c1: ec_i2c_sub_usb_c1 { + i2c-port = <&i2c4>; + enum-names = "I2C_PORT_USB_C1_TCPC"; + }; + i2c_ec_i2c_usb_c0: ec_i2c_usb_c0 { + i2c-port = <&i2c5>; + enum-names = "I2C_PORT_USB_C0_TCPC"; + }; + }; +}; diff --git a/zephyr/projects/nissa/yaviks/keyboard.dtsi b/zephyr/projects/nissa/yaviks/keyboard.dtsi new file mode 100644 index 0000000000..04a620767a --- /dev/null +++ b/zephyr/projects/nissa/yaviks/keyboard.dtsi @@ -0,0 +1,22 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + kblight { + compatible = "cros-ec,kblight-pwm"; + /* + * Use 324 Hz so that 32Khz clock source is used, + * which is not gated in power saving mode. + */ + pwms = <&pwm0 0 PWM_HZ(324) PWM_POLARITY_NORMAL>; + }; +}; + +&pwm0 { + status = "okay"; + prescaler-cx = <PWM_PRESCALER_C4>; + pinctrl-0 = <&pwm0_gpa0_default>; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/nissa/yaviks/overlay.dtsi b/zephyr/projects/nissa/yaviks/overlay.dtsi new file mode 100644 index 0000000000..d768116444 --- /dev/null +++ b/zephyr/projects/nissa/yaviks/overlay.dtsi @@ -0,0 +1,402 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <cros/thermistor/thermistor.dtsi> + +/ { + aliases { + gpio-cbi-wp = &gpio_ec_cbi_wp; + gpio-wp = &gpio_ec_wp_odl; + int-wp = &int_wp_l; + /* + * USB-C: interrupt input. + * I2C pins are on i2c_ec_i2c_sub_usb_c1 + */ + gpio-usb-c1-int-odl = &gpio_sb_1; + /* + * USB-A: VBUS enable output + * LTE: power enable output + */ + gpio-en-usb-a1-vbus = &gpio_sb_2; + /* + * Enable S5 rails for LTE sub-board + */ + gpio-en-sub-s5-rails = &gpio_sb_2; + }; + + ec-console { + compatible = "ec-console"; + disabled = "events", "lpc", "hostcmd"; + }; + + batteries { + default_battery: cosmx { + compatible = "cosmx,gh02047xl", "battery-smart"; + }; + dynapack_atl_gh02047xl { + compatible = "dynapack,atl_gh02047xl", "battery-smart"; + }; + dynapack_cosmx_gh02047xl { + compatible = "dynapack,cosmx_gh02047xl", "battery-smart"; + }; + smp_coslight_gh02047xl { + compatible = "smp,coslight_gh02047xl", "battery-smart"; + }; + smp_highpower_gh02047xl { + compatible = "smp,highpower_gh02047xl", "battery-smart"; + }; + default_battery_3s:cosmx_si03058xl { + compatible = "cosmx,si03058xl", "battery-smart"; + }; + smp_highpower_si03058xl { + compatible = "smp,highpower_si03058xl", "battery-smart"; + }; + }; + + hibernate-wake-pins { + compatible = "cros-ec,hibernate-wake-pins"; + wakeup-irqs = < + &int_power_button + &int_lid_open + >; + }; + + gpio-interrupts { + compatible = "cros-ec,gpio-interrupts"; + + int_power_button: power_button { + irq-pin = <&gpio_gsc_ec_pwr_btn_odl>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "power_button_interrupt"; + }; + int_wp_l: wp_l { + irq-pin = <&gpio_ec_wp_odl>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "switch_interrupt"; + }; + int_lid_open: lid_open { + irq-pin = <&gpio_lid_open>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "lid_interrupt"; + }; + int_usb_c0: usb_c0 { + irq-pin = <&gpio_usb_c0_int_odl>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "usb_c0_interrupt"; + }; + int_usb_c1: usb_c1 { + irq-pin = <&gpio_sb_1>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "usb_c1_interrupt"; + }; + }; + + unused-pins { + compatible = "unused-gpios"; + unused-gpios = <&gpioa 7 0>, + <&gpioc 0 0>, + <&gpioc 6 0>, + <&gpiod 7 0>, + <&gpioh 2 0>, + <&gpioi 6 0>, + <&gpioi 7 0>, + <&gpioj 0 0>, + <&gpioj 3 0>, + <&gpiok 7 GPIO_OUTPUT>; + }; + + named-gpios { + /* + * EC doesn't take any specific action on CC/SBU disconnect due to + * fault, but this definition is useful for hardware testing. + */ + gpio_usb_c0_prot_fault_odl: usb_c0_prot_fault_odl { + gpios = <&gpiok 6 GPIO_INPUT_PULL_UP>; + }; + + gpio_sb_1: sb_1 { + gpios = <&gpioe 6 0>; + no-auto-init; + }; + gpio_sb_2: sb_2 { + gpios = <&gpiof 0 0>; + no-auto-init; + }; + gpio_fan_enable: fan-enable { + gpios = <&gpioa 1 GPIO_OUTPUT>; + no-auto-init; + }; + }; + + temp_cpu: cpu { + compatible = "cros-ec,temp-sensor-thermistor"; + thermistor = <&thermistor_3V3_51K1_47K_4050B>; + adc = <&adc_temp_sensor_1>; + }; + temp_5v_regulator: 5v_regulator { + compatible = "cros-ec,temp-sensor-thermistor"; + thermistor = <&thermistor_3V3_51K1_47K_4050B>; + adc = <&adc_temp_sensor_2>; + }; + temp_charger: charger { + compatible = "cros-ec,temp-sensor-thermistor"; + thermistor = <&thermistor_3V3_51K1_47K_4050B>; + adc = <&adc_temp_sensor_3>; + }; + + named-temp-sensors { + compatible = "cros-ec,temp-sensors"; + cpu { + temp_fan_off = <45>; + temp_fan_max = <60>; + temp_host_high = <75>; + temp_host_halt = <85>; + temp_host_release_high = <65>; + power-good-pin = <&gpio_ec_soc_dsw_pwrok>; + sensor = <&temp_cpu>; + }; + 5v_regulator { + temp_fan_off = <50>; + temp_fan_max = <65>; + temp_host_high = <75>; + temp_host_halt = <85>; + temp_host_release_high = <65>; + power-good-pin = <&gpio_ec_soc_dsw_pwrok>; + sensor = <&temp_5v_regulator>; + }; + charger { + temp_fan_off = <50>; + temp_fan_max = <65>; + temp_host_high = <80>; + temp_host_halt = <85>; + temp_host_release_high = <75>; + power-good-pin = <&gpio_ec_soc_dsw_pwrok>; + sensor = <&temp_charger>; + }; + }; + + usba { + compatible = "cros-ec,usba-port-enable-pins"; + /* + * sb_2 is only configured as GPIO when USB-A1 is present, + * but it's still safe to control when disabled. + * + * ILIM_SEL pins are referred to by legacy enum name, + * GPIO_USB*_ILIM_SEL. The one for port A1 is unused on + * sub-boards that don't have USB-A so is safe to control + * regardless of system configuration. + */ + enable-pins = <&gpio_en_usb_a0_vbus &gpio_sb_2>; + status = "okay"; + }; + + usbc { + #address-cells = <1>; + #size-cells = <0>; + + port0@0 { + compatible = "named-usbc-port"; + reg = <0>; + bc12 = <&bc12_port0>; + chg = <&chg_port0>; + usb-mux-chain-0 { + compatible = "cros-ec,usb-mux-chain"; + usb-muxes = <&virtual_mux_0>; + }; + }; + port0-muxes { + virtual_mux_0: virtual-mux-0 { + compatible = "cros-ec,usbc-mux-virtual"; + }; + }; + port1@1 { + compatible = "named-usbc-port"; + reg = <1>; + bc12 = <&bc12_port1>; + chg = <&chg_port1>; + usb-mux-chain-1 { + compatible = "cros-ec,usb-mux-chain"; + usb-muxes = <&virtual_mux_1 &tcpci_mux_1>; + }; + usb_mux_chain_1_no_mux: usb-mux-chain-1-no-mux { + compatible = "cros-ec,usb-mux-chain"; + alternative-chain; + usb-muxes = <&virtual_mux_1>; + }; + }; + port1-muxes { + virtual_mux_1: virtual-mux-1 { + compatible = "cros-ec,usbc-mux-virtual"; + }; + tcpci_mux_1: tcpci-mux-1 { + compatible = "parade,usbc-mux-ps8xxx"; + }; + }; + }; + + fans { + compatible = "cros-ec,fans"; + fan_0 { + pwms = <&pwm2 PWM_CHANNEL_2 PWM_KHZ(25) PWM_POLARITY_NORMAL>; + tach = <&tach1>; + rpm_min = <2600>; + rpm_start = <2600>; + rpm_max = <4100>; + enable_gpio = <&gpio_fan_enable>; + }; + }; +}; + +&thermistor_3V3_51K1_47K_4050B { + status = "okay"; +}; + +&adc_ec_vsense_pp3300_s5 { + /* + * Voltage divider on input has 47k upper and 220k lower legs with 3 V + * full-scale reading on the ADC. Apply the largest possible multiplier + * (without overflowing int32) to get the best possible approximation + * of the actual ratio, but derate by a factor of two to ensure + * unexpectedly high values won't overflow. + */ + mul = <(715828 / 2)>; + div = <(589820 / 2)>; +}; + +&adc0 { + pinctrl-0 = <&adc0_ch0_gpi0_default + &adc0_ch2_gpi2_default + &adc0_ch3_gpi3_default + &adc0_ch13_gpl0_default + &adc0_ch14_gpl1_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&pinctrl { + i2c4_clk_gpe0_sleep: i2c4_clk_gpe0_sleep { + pinmuxs = <&pinctrle 0 IT8XXX2_ALT_DEFAULT>; + }; + i2c4_data_gpe7_sleep: i2c4_data_gpe7_sleep { + pinmuxs = <&pinctrle 7 IT8XXX2_ALT_DEFAULT>; + }; + i2c2_clk_gpf6_default: i2c2_clk_gpf6_default { + gpio-voltage = "1v8"; + }; + i2c2_data_gpf7_default: i2c2_data_gpf7_default { + gpio-voltage = "1v8"; + }; +}; + +&i2c0 { + label = "I2C_EEPROM"; + clock-frequency = <I2C_BITRATE_FAST>; + + cbi_eeprom: eeprom@50 { + compatible = "atmel,at24"; + reg = <0x50>; + label = "EEPROM_CBI"; + size = <2048>; + pagesize = <16>; + address-width = <8>; + timeout = <5>; + }; + pinctrl-0 = <&i2c0_clk_gpb3_default + &i2c0_data_gpb4_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&i2c1 { + label = "I2C_BATTERY"; + clock-frequency = <50000>; + pinctrl-0 = <&i2c1_clk_gpc1_default + &i2c1_data_gpc2_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&i2c2 { + label = "I2C_SENSOR"; + clock-frequency = <I2C_BITRATE_FAST>; + pinctrl-0 = <&i2c2_clk_gpf6_default + &i2c2_data_gpf7_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&i2c4 { + label = "I2C_SUB_C1_TCPC"; + clock-frequency = <I2C_BITRATE_FAST_PLUS>; + pinctrl-0 = <&i2c4_clk_gpe0_default + &i2c4_data_gpe7_default>; + pinctrl-1 = <&i2c4_clk_gpe0_sleep + &i2c4_data_gpe7_sleep>; + pinctrl-names = "default", "sleep"; + status = "okay"; + + bc12_port1: pi3usb9201@5f { + compatible = "pericom,pi3usb9201"; + status = "okay"; + reg = <0x5f>; + }; + + chg_port1: sm5803@32 { + compatible = "siliconmitus,sm5803"; + status = "okay"; + reg = <0x32>; + }; +}; + +&i2c_ec_i2c_sub_usb_c1 { + /* + * Dynamic speed setting is used for AP-controlled firmware update + * of PS8745 TCPC/redriver: the AP lowers speed to 400 kHz in order + * to use more efficient window programming, then sets it back when + * done. + */ + dynamic-speed; +}; + +&i2c5 { + label = "I2C_USB_C0_TCPC"; + clock-frequency = <I2C_BITRATE_FAST_PLUS>; + pinctrl-0 = <&i2c5_clk_gpa4_default + &i2c5_data_gpa5_default>; + pinctrl-names = "default"; + status = "okay"; + + bc12_port0: pi3usb9201@5f { + compatible = "pericom,pi3usb9201"; + status = "okay"; + reg = <0x5f>; + }; + + chg_port0: sm5803@32 { + compatible = "siliconmitus,sm5803"; + status = "okay"; + reg = <0x32>; + }; +}; + +&usbpd0 { + status = "okay"; +}; + +/* pwm for fan */ +&pwm2 { + status = "okay"; + prescaler-cx = <PWM_PRESCALER_C6>; + pinctrl-0 = <&pwm2_gpa2_default>; + pinctrl-names = "default"; +}; +/* fan tachometer sensor */ +&tach1 { + status = "okay"; + channel = <IT8XXX2_TACH_CHANNEL_A>; + pulses-per-round = <2>; + pinctrl-0 = <&tach1a_gpd7_default>; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/nissa/yaviks/power_signals.dtsi b/zephyr/projects/nissa/yaviks/power_signals.dtsi new file mode 100644 index 0000000000..d64ac83150 --- /dev/null +++ b/zephyr/projects/nissa/yaviks/power_signals.dtsi @@ -0,0 +1,180 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + chosen { + intel-ap-pwrseq,espi = &espi0; + }; + + common-pwrseq { + compatible = "intel,ap-pwrseq"; + + sys-pwrok-delay = <10>; + all-sys-pwrgd-timeout = <20>; + }; + + pwr-en-pp5000-s5 { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "PP5000_S5 enable output to regulator"; + enum-name = "PWR_EN_PP5000_A"; + gpios = <&gpiok 5 0>; + output; + }; + pwr-en-pp3300-s5 { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "PP3300_S5 enable output to LS"; + enum-name = "PWR_EN_PP3300_A"; + gpios = <&gpioc 5 0>; + output; + }; + pwr-pg-ec-rsmrst-odl { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "RSMRST power good from regulator"; + enum-name = "PWR_RSMRST"; + gpios = <&gpioe 1 0>; + interrupt-flags = <GPIO_INT_EDGE_BOTH>; + }; + pwr-ec-pch-rsmrst-odl { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "RSMRST output to PCH"; + enum-name = "PWR_EC_PCH_RSMRST"; + gpios = <&gpioh 0 0>; + output; + }; + pwr-slp-s0-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SLP_S0_L input from PCH"; + enum-name = "PWR_SLP_S0"; + gpios = <&gpioe 4 GPIO_ACTIVE_LOW>; + interrupt-flags = <GPIO_INT_EDGE_BOTH>; + }; + pwr-slp-s3-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SLP_S3_L input from PCH"; + enum-name = "PWR_SLP_S3"; + gpios = <&gpioh 3 GPIO_ACTIVE_LOW>; + interrupt-flags = <GPIO_INT_EDGE_BOTH>; + }; + pwr-slp-sus-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SLP_SUS_L input from PCH"; + enum-name = "PWR_SLP_SUS"; + gpios = <&gpiog 2 GPIO_ACTIVE_LOW>; + interrupt-flags = <GPIO_INT_EDGE_BOTH>; + }; + pwr-ec-soc-dsw-pwrok { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "DSW_PWROK output to PCH"; + enum-name = "PWR_EC_SOC_DSW_PWROK"; + gpios = <&gpiol 7 0>; + output; + }; + pwr-vccst-pwrgd-od { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "VCCST_PWRGD output to PCH"; + enum-name = "PWR_VCCST_PWRGD"; + gpios = <&gpioe 5 (GPIO_OPEN_DRAIN | GPIO_VOLTAGE_1P8)>; + output; + }; + pwr-imvp9-vrrdy-od { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "VRRDY input from IMVP9"; + enum-name = "PWR_IMVP9_VRRDY"; + gpios = <&gpioj 4 0>; + }; + pwr-pch-pwrok { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "PCH_PWROK output to PCH"; + enum-name = "PWR_PCH_PWROK"; + gpios = <&gpiod 6 GPIO_OPEN_DRAIN>; + output; + }; + pwr-ec-pch-sys-pwrok { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SYS_PWROK output to PCH"; + enum-name = "PWR_EC_PCH_SYS_PWROK"; + gpios = <&gpiof 2 0>; + output; + }; + pwr-sys-rst-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SYS_RESET# output to PCH"; + enum-name = "PWR_SYS_RST"; + gpios = <&gpiod 1 (GPIO_ACTIVE_LOW|GPIO_OPEN_DRAIN)>; + output; + }; + pwr-slp-s4 { + compatible = "intel,ap-pwrseq-vw"; + dbg-label = "SLP_S4 virtual wire input from PCH"; + enum-name = "PWR_SLP_S4"; + virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S4"; + vw-invert; + }; + pwr-slp-s5 { + compatible = "intel,ap-pwrseq-vw"; + dbg-label = "SLP_S5 virtual wire input from PCH"; + enum-name = "PWR_SLP_S5"; + virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S5"; + vw-invert; + }; + pwr-all-sys-pwrgd { + /* + * This is a board level signal, since this + * signal needs some special processing. + */ + compatible = "intel,ap-pwrseq-external"; + dbg-label = "Combined all power good"; + enum-name = "PWR_ALL_SYS_PWRGD"; + }; + pwr-adc-pp3300 { + compatible = "intel,ap-pwrseq-adc"; + dbg-label = "PP3300_PROC"; + enum-name = "PWR_DSW_PWROK"; + trigger-high = <&vcmp0>; + trigger-low = <&vcmp1>; + }; + pwr-adc-pp1p05 { + compatible = "intel,ap-pwrseq-adc"; + dbg-label = "PP1P05_PROC"; + enum-name = "PWR_PG_PP1P05"; + trigger-high = <&vcmp2>; + trigger-low = <&vcmp3>; + }; + +}; + +&vcmp0 { + status = "okay"; + scan-period = <IT8XXX2_VCMP_SCAN_PERIOD_600US>; + comparison = <IT8XXX2_VCMP_GREATER>; + /* + * This is 90% of nominal voltage considering voltage + * divider on ADC input. + */ + threshold-mv = <2448>; + io-channels = <&adc0 0>; +}; +&vcmp1 { + status = "okay"; + scan-period = <IT8XXX2_VCMP_SCAN_PERIOD_600US>; + comparison = <IT8XXX2_VCMP_LESS_OR_EQUAL>; + threshold-mv = <2448>; + io-channels = <&adc0 0>; +}; +&vcmp2 { + status = "okay"; + scan-period = <IT8XXX2_VCMP_SCAN_PERIOD_600US>; + comparison = <IT8XXX2_VCMP_GREATER>; + /* Setting at 90% of nominal voltage */ + threshold-mv = <945>; + io-channels = <&adc0 14>; +}; +&vcmp3 { + status = "okay"; + scan-period = <IT8XXX2_VCMP_SCAN_PERIOD_600US>; + comparison = <IT8XXX2_VCMP_LESS_OR_EQUAL>; + threshold-mv = <945>; + io-channels = <&adc0 14>; +}; diff --git a/zephyr/projects/nissa/yaviks/project.conf b/zephyr/projects/nissa/yaviks/project.conf new file mode 100644 index 0000000000..0e385b843e --- /dev/null +++ b/zephyr/projects/nissa/yaviks/project.conf @@ -0,0 +1,33 @@ +# Copyright 2022 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +CONFIG_BOARD_YAVIKS=y + +# Ensure recovery key combination (esc+refresh+power) is reliable: b/236580049 +CONFIG_PLATFORM_EC_KEYBOARD_PWRBTN_ASSERTS_KSI3=y +CONFIG_PLATFORM_EC_KEYBOARD_REFRESH_ROW3=y + +# Sensors: disabled; yaviks is clamshell-only +CONFIG_PLATFORM_EC_LID_ANGLE=n +CONFIG_PLATFORM_EC_LID_ANGLE_UPDATE=n +CONFIG_PLATFORM_EC_MOTIONSENSE=n +CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCELS=n +CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCEL_INFO=n +CONFIG_PLATFORM_EC_ACCEL_FIFO=n +CONFIG_PLATFORM_EC_SENSOR_TIGHT_TIMESTAMPS=n +CONFIG_PLATFORM_EC_GMR_TABLET_MODE=n +CONFIG_PLATFORM_EC_TABLET_MODE=n +CONFIG_PLATFORM_EC_TABLET_MODE_SWITCH=n +CONFIG_PLATFORM_EC_VOLUME_BUTTONS=n +CONFIG_PLATFORM_EC_MAX_SENSOR_FREQ_MILLIHZ=100000 + +# Keyboard +CONFIG_PLATFORM_EC_KEYBOARD_KEYPAD=y +CONFIG_PLATFORM_EC_KBLIGHT_ENABLE_PIN=n + +# Fan +CONFIG_PLATFORM_EC_FAN=y + +# LED +CONFIG_PLATFORM_EC_LED_PWM=n diff --git a/zephyr/projects/nissa/yaviks/project.overlay b/zephyr/projects/nissa/yaviks/project.overlay new file mode 100644 index 0000000000..a7ce97a8b3 --- /dev/null +++ b/zephyr/projects/nissa/yaviks/project.overlay @@ -0,0 +1,12 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "../cbi.dtsi" + +#include "cbi.dtsi" +#include "gpio.dtsi" +#include "keyboard.dtsi" +#include "overlay.dtsi" +#include "power_signals.dtsi" diff --git a/zephyr/projects/nissa/yaviks/src/charger.c b/zephyr/projects/nissa/yaviks/src/charger.c new file mode 100644 index 0000000000..9be2e685b0 --- /dev/null +++ b/zephyr/projects/nissa/yaviks/src/charger.c @@ -0,0 +1,74 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <zephyr/logging/log.h> + +#include "battery.h" +#include "charger.h" +#include "console.h" +#include "driver/charger/sm5803.h" +#include "extpower.h" +#include "usb_pd.h" +#include "nissa_common.h" +#include "battery_fuel_gauge.h" + +LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL); + +int extpower_is_present(void) +{ + int port; + int rv; + bool acok; + + for (port = 0; port < board_get_usb_pd_port_count(); port++) { + rv = sm5803_is_acok(port, &acok); + if ((rv == EC_SUCCESS) && acok) + return 1; + } + + return 0; +} + +/* + * Yaviks does not have a GPIO indicating whether extpower is present, + * so detect using the charger(s). + */ +__override void board_check_extpower(void) +{ + static int last_extpower_present; + int extpower_present = extpower_is_present(); + + if (last_extpower_present ^ extpower_present) + extpower_handle_update(extpower_present); + + last_extpower_present = extpower_present; +} + +__override void board_hibernate(void) +{ + /* Shut down the chargers */ + if (board_get_usb_pd_port_count() == 2) + sm5803_hibernate(CHARGER_SECONDARY); + sm5803_hibernate(CHARGER_PRIMARY); + LOG_INF("Charger(s) hibernated"); + cflush(); +} + +__override int board_get_default_battery_type(void) +{ + int type = DEFAULT_BATTERY_TYPE; + int cells; + + if (charger_get_battery_cells(CHARGER_PRIMARY, &cells) == EC_SUCCESS) { + if (cells == 3) + type = DEFAULT_BATTERY_TYPE_3S; + if (cells != 2 && cells != 3) + LOG_ERR("Unexpected number of cells"); + } else { + LOG_ERR("Failed to get default battery type"); + } + + return type; +} diff --git a/zephyr/projects/nissa/yaviks/src/fan.c b/zephyr/projects/nissa/yaviks/src/fan.c new file mode 100644 index 0000000000..23c3ec1143 --- /dev/null +++ b/zephyr/projects/nissa/yaviks/src/fan.c @@ -0,0 +1,36 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ +#include <zephyr/devicetree.h> +#include <zephyr/drivers/gpio.h> +#include <zephyr/logging/log.h> +#include "cros_cbi.h" +#include "fan.h" +#include "gpio/gpio.h" +#include "hooks.h" +#include "nissa_common.h" +LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL); + +static void fan_init(void) +{ + int ret; + uint32_t val; + /* + * Retrieve the fan config. + */ + ret = cros_cbi_get_fw_config(FW_FAN, &val); + if (ret != 0) { + LOG_ERR("Error retrieving CBI FW_CONFIG field %d", FW_FAN); + return; + } + if (val != FW_FAN_PRESENT) { + /* Disable the fan */ + fan_set_count(0); + } else { + /* Configure the fan enable GPIO */ + gpio_pin_configure_dt(GPIO_DT_FROM_NODELABEL(gpio_fan_enable), + GPIO_OUTPUT); + } +} +DECLARE_HOOK(HOOK_INIT, fan_init, HOOK_PRIO_POST_FIRST); diff --git a/zephyr/projects/nissa/yaviks/src/keyboard.c b/zephyr/projects/nissa/yaviks/src/keyboard.c new file mode 100644 index 0000000000..46d6083dbf --- /dev/null +++ b/zephyr/projects/nissa/yaviks/src/keyboard.c @@ -0,0 +1,106 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ +#include <zephyr/logging/log.h> + +#include "cros_cbi.h" +#include "ec_commands.h" +#include "hooks.h" +#include "keyboard_8042_sharedlib.h" +#include "keyboard_scan.h" +#include "timer.h" + +LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL); + +/* Keyboard scan setting */ +__override struct keyboard_scan_config keyscan_config = { + /* Increase from 50 us, because KSO_02 passes through the H1. */ + .output_settle_us = 80, + /* Other values should be the same as the default configuration. */ + .debounce_down_us = 9 * MSEC, + .debounce_up_us = 30 * MSEC, + .scan_period_us = 3 * MSEC, + .min_post_scan_delay_us = 1000, + .poll_timeout_us = 100 * MSEC, + .actual_key_mask = { + 0x1c, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xa4, 0xff, 0xf6, 0x55, 0xfe, 0xff, 0xff, 0xff, /* full set */ + }, +}; + +static const struct ec_response_keybd_config yaviks_kb_w_kb_light = { + .num_top_row_keys = 13, + .action_keys = { + TK_BACK, /* T1 */ + TK_REFRESH, /* T2 */ + TK_FULLSCREEN, /* T3 */ + TK_OVERVIEW, /* T4 */ + TK_SNAPSHOT, /* T5 */ + TK_BRIGHTNESS_DOWN, /* T6 */ + TK_BRIGHTNESS_UP, /* T7 */ + TK_KBD_BKLIGHT_TOGGLE, /* T8 */ + TK_PLAY_PAUSE, /* T9 */ + TK_MICMUTE, /* T10 */ + TK_VOL_MUTE, /* T11 */ + TK_VOL_DOWN, /* T12 */ + TK_VOL_UP, /* T13 */ + }, + .capabilities = KEYBD_CAP_NUMERIC_KEYPAD, +}; + +static const struct ec_response_keybd_config yaviks_kb_wo_kb_light = { + .num_top_row_keys = 13, + .action_keys = { + TK_BACK, /* T1 */ + TK_REFRESH, /* T2 */ + TK_FULLSCREEN, /* T3 */ + TK_OVERVIEW, /* T4 */ + TK_SNAPSHOT, /* T5 */ + TK_BRIGHTNESS_DOWN, /* T6 */ + TK_BRIGHTNESS_UP, /* T7 */ + TK_PLAY_PAUSE, /* T8 */ + TK_MICMUTE, /* T9 */ + TK_VOL_MUTE, /* T10 */ + TK_VOL_DOWN, /* T11 */ + TK_VOL_UP, /* T12 */ + TK_MENU, /* T13 */ + }, + .capabilities = KEYBD_CAP_NUMERIC_KEYPAD, +}; + +__override const struct ec_response_keybd_config * +board_vivaldi_keybd_config(void) +{ + uint32_t val; + + cros_cbi_get_fw_config(FW_KB_BACKLIGHT, &val); + + if (val == FW_KB_BACKLIGHT_OFF) + return &yaviks_kb_wo_kb_light; + else + return &yaviks_kb_w_kb_light; +} + +/* + * Keyboard layout decided by FW config. + */ +static void kb_layout_init(void) +{ + int ret; + uint32_t val; + + ret = cros_cbi_get_fw_config(FW_KB_LAYOUT, &val); + if (ret != 0) { + LOG_ERR("Error retrieving CBI FW_CONFIG field %d", + FW_KB_LAYOUT); + return; + } + /* + * If keyboard is US2(FW_KB_LAYOUT_US2), we need translate right ctrl + * to backslash(\|) key. + */ + if (val == FW_KB_LAYOUT_US2) + set_scancode_set2(4, 0, get_scancode_set2(2, 7)); +} +DECLARE_HOOK(HOOK_INIT, kb_layout_init, HOOK_PRIO_POST_FIRST); diff --git a/zephyr/projects/nissa/yaviks/src/led.c b/zephyr/projects/nissa/yaviks/src/led.c new file mode 100644 index 0000000000..88a476f1b0 --- /dev/null +++ b/zephyr/projects/nissa/yaviks/src/led.c @@ -0,0 +1,231 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <stdint.h> + +#include "battery.h" +#include "charge_manager.h" +#include "charge_state.h" +#include "chipset.h" +#include "ec_commands.h" +#include "gpio.h" +#include "host_command.h" +#include "led_common.h" +#include "hooks.h" + +#define BAT_LED_ON 0 +#define BAT_LED_OFF 1 + +#define BATT_LOW_BCT 10 + +#define LED_TICKS_PER_CYCLE 4 +#define LED_TICKS_PER_CYCLE_S3 4 +#define LED_ON_TICKS 2 +#define POWER_LED_ON_S3_TICKS 2 + +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_LEFT_LED, + EC_LED_ID_RIGHT_LED }; + +const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); + +enum led_color { + LED_OFF = 0, + LED_AMBER, + LED_WHITE, + LED_COLOR_COUNT /* Number of colors, not a color itself */ +}; + +enum led_port { LEFT_PORT = 0, RIGHT_PORT }; + +static void led_set_color_battery(int port, enum led_color color) +{ + const struct gpio_dt_spec *amber_led, *white_led; + + if (port == LEFT_PORT) { + amber_led = GPIO_DT_FROM_NODELABEL(gpio_c0_charger_led_amber_l); + white_led = GPIO_DT_FROM_NODELABEL(gpio_c0_charger_led_white_l); + } else if (port == RIGHT_PORT) { + amber_led = GPIO_DT_FROM_NODELABEL(gpio_c1_charger_led_amber_l); + white_led = GPIO_DT_FROM_NODELABEL(gpio_c1_charger_led_white_l); + } + + switch (color) { + case LED_WHITE: + gpio_pin_set_dt(white_led, BAT_LED_ON); + gpio_pin_set_dt(amber_led, BAT_LED_OFF); + break; + case LED_AMBER: + gpio_pin_set_dt(white_led, BAT_LED_OFF); + gpio_pin_set_dt(amber_led, BAT_LED_ON); + break; + case LED_OFF: + gpio_pin_set_dt(white_led, BAT_LED_OFF); + gpio_pin_set_dt(amber_led, BAT_LED_OFF); + break; + default: + break; + } +} + +void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range) +{ + switch (led_id) { + case EC_LED_ID_LEFT_LED: + brightness_range[EC_LED_COLOR_WHITE] = 1; + brightness_range[EC_LED_COLOR_AMBER] = 1; + break; + case EC_LED_ID_RIGHT_LED: + brightness_range[EC_LED_COLOR_WHITE] = 1; + brightness_range[EC_LED_COLOR_AMBER] = 1; + break; + default: + break; + } +} + +int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness) +{ + switch (led_id) { + case EC_LED_ID_LEFT_LED: + if (brightness[EC_LED_COLOR_WHITE] != 0) + led_set_color_battery(LEFT_PORT, LED_WHITE); + else if (brightness[EC_LED_COLOR_AMBER] != 0) + led_set_color_battery(LEFT_PORT, LED_AMBER); + else + led_set_color_battery(LEFT_PORT, LED_OFF); + break; + case EC_LED_ID_RIGHT_LED: + if (brightness[EC_LED_COLOR_WHITE] != 0) + led_set_color_battery(RIGHT_PORT, LED_WHITE); + else if (brightness[EC_LED_COLOR_AMBER] != 0) + led_set_color_battery(RIGHT_PORT, LED_AMBER); + else + led_set_color_battery(RIGHT_PORT, LED_OFF); + break; + default: + return EC_ERROR_PARAM1; + } + + return EC_SUCCESS; +} + +/* + * Set active charge port color to the parameter, turn off all others. + * If no port is active (-1), turn off all LEDs. + */ +static void set_active_port_color(enum led_color color) +{ + int port = charge_manager_get_active_charge_port(); + + if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) + led_set_color_battery(RIGHT_PORT, + (port == RIGHT_PORT) ? color : LED_OFF); + if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED)) + led_set_color_battery(LEFT_PORT, + (port == LEFT_PORT) ? color : LED_OFF); +} + +static void led_set_battery(void) +{ + static unsigned int battery_ticks; + static int suspend_ticks; + + battery_ticks++; + + /* + * Override battery LEDs for Yaviks, Yaviks is non-power LED + * design, blinking both two side battery white LEDs to indicate + * system suspend with non-charging state. + */ + if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) && + charge_get_state() != PWR_STATE_CHARGE) { + suspend_ticks++; + + led_set_color_battery(RIGHT_PORT, + suspend_ticks % LED_TICKS_PER_CYCLE_S3 < + POWER_LED_ON_S3_TICKS ? + LED_WHITE : + LED_OFF); + led_set_color_battery(LEFT_PORT, + suspend_ticks % LED_TICKS_PER_CYCLE_S3 < + POWER_LED_ON_S3_TICKS ? + LED_WHITE : + LED_OFF); + return; + } + + suspend_ticks = 0; + + switch (charge_get_state()) { + case PWR_STATE_CHARGE: + /* Always indicate when charging, even in suspend. */ + set_active_port_color(LED_AMBER); + break; + case PWR_STATE_DISCHARGE: + /* + * Blinking amber LEDs slowly if battery is lower 10 + * percentage. + */ + if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) { + if (charge_get_percent() < BATT_LOW_BCT) + led_set_color_battery( + RIGHT_PORT, + (battery_ticks % LED_TICKS_PER_CYCLE < + LED_ON_TICKS) ? + LED_AMBER : + LED_OFF); + else + led_set_color_battery(RIGHT_PORT, LED_OFF); + } + + if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED)) { + if (charge_get_percent() < BATT_LOW_BCT) + led_set_color_battery( + LEFT_PORT, + (battery_ticks % LED_TICKS_PER_CYCLE < + LED_ON_TICKS) ? + LED_AMBER : + LED_OFF); + else + led_set_color_battery(LEFT_PORT, LED_OFF); + } + break; + case PWR_STATE_ERROR: + if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) { + led_set_color_battery( + RIGHT_PORT, + (battery_ticks & 0x1) ? LED_AMBER : LED_OFF); + } + + if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED)) { + led_set_color_battery(LEFT_PORT, (battery_ticks & 0x1) ? + LED_AMBER : + LED_OFF); + } + break; + case PWR_STATE_CHARGE_NEAR_FULL: + set_active_port_color(LED_WHITE); + break; + case PWR_STATE_IDLE: /* External power connected in IDLE */ + set_active_port_color(LED_WHITE); + break; + case PWR_STATE_FORCED_IDLE: + set_active_port_color( + (battery_ticks % LED_TICKS_PER_CYCLE < LED_ON_TICKS) ? + LED_AMBER : + LED_OFF); + break; + default: + /* Other states don't alter LED behavior */ + break; + } +} + +/* Called by hook task every TICK(IT83xx 500ms) */ +static void led_tick(void) +{ + led_set_battery(); +} +DECLARE_HOOK(HOOK_TICK, led_tick, HOOK_PRIO_DEFAULT); diff --git a/zephyr/projects/nissa/yaviks/src/usbc.c b/zephyr/projects/nissa/yaviks/src/usbc.c new file mode 100644 index 0000000000..48f7cfd9cb --- /dev/null +++ b/zephyr/projects/nissa/yaviks/src/usbc.c @@ -0,0 +1,393 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <zephyr/logging/log.h> +#include <ap_power/ap_power.h> + +#include "charge_state_v2.h" +#include "chipset.h" +#include "hooks.h" +#include "usb_mux.h" +#include "system.h" +#include "driver/charger/sm5803.h" +#include "driver/tcpm/it83xx_pd.h" +#include "driver/tcpm/ps8xxx_public.h" +#include "driver/tcpm/tcpci.h" + +#include "nissa_common.h" + +LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL); + +struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = { + { + .bus_type = EC_BUS_TYPE_EMBEDDED, + /* TCPC is embedded within EC so no i2c config needed */ + .drv = &it8xxx2_tcpm_drv, + /* Alert is active-low, push-pull */ + .flags = 0, + }, + { + /* + * Sub-board: optional PS8745 TCPC+redriver. Behaves the same + * as PS8815. + */ + .bus_type = EC_BUS_TYPE_I2C, + .i2c_info = { + .port = I2C_PORT_USB_C1_TCPC, + .addr_flags = PS8XXX_I2C_ADDR1_FLAGS, + }, + .drv = &ps8xxx_tcpm_drv, + /* PS8745 implements TCPCI 2.0 */ + .flags = TCPC_FLAGS_TCPCI_REV2_0, + }, +}; + +/* Vconn control for integrated ITE TCPC */ +void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled) +{ + /* Vconn control is only for port 0 */ + if (port) + return; + + if (cc_pin == USBPD_CC_PIN_1) + gpio_pin_set_dt( + GPIO_DT_FROM_NODELABEL(gpio_en_usb_c0_cc1_vconn), + !!enabled); + else + gpio_pin_set_dt( + GPIO_DT_FROM_NODELABEL(gpio_en_usb_c0_cc2_vconn), + !!enabled); +} + +__override bool pd_check_vbus_level(int port, enum vbus_level level) +{ + return sm5803_check_vbus_level(port, level); +} + +/* + * Putting chargers into LPM when in suspend reduces power draw by about 8mW + * per charger, but also seems critical to correct operation in source mode: + * if chargers are not in LPM when a sink is first connected, VBUS sourcing + * works even if the partner is later removed (causing LPM entry) and + * reconnected (causing LPM exit). If in LPM initially, sourcing VBUS + * consistently causes the charger to report (apparently spurious) overcurrent + * failures. + * + * In short, this is important to making things work correctly but we don't + * understand why. + */ +static void board_chargers_suspend(struct ap_power_ev_callback *const cb, + const struct ap_power_ev_data data) +{ + void (*fn)(int chgnum); + + switch (data.event) { + case AP_POWER_SUSPEND: + fn = sm5803_enable_low_power_mode; + break; + case AP_POWER_RESUME: + fn = sm5803_disable_low_power_mode; + break; + default: + LOG_WRN("%s: power event %d is not recognized", __func__, + data.event); + return; + } + + fn(CHARGER_PRIMARY); + if (board_get_charger_chip_count() > 1) + fn(CHARGER_SECONDARY); +} + +static int board_chargers_suspend_init(const struct device *unused) +{ + static struct ap_power_ev_callback cb = { + .handler = board_chargers_suspend, + .events = AP_POWER_SUSPEND | AP_POWER_RESUME, + }; + ap_power_ev_add_callback(&cb); + return 0; +} +SYS_INIT(board_chargers_suspend_init, APPLICATION, 0); + +int board_set_active_charge_port(int port) +{ + int is_real_port = (port >= 0 && port < board_get_usb_pd_port_count()); + int i; + int old_port; + int rv; + + if (!is_real_port && port != CHARGE_PORT_NONE) + return EC_ERROR_INVAL; + + old_port = charge_manager_get_active_charge_port(); + LOG_INF("Charge update: p%d -> p%d", old_port, port); + + /* Check if port is sourcing VBUS. */ + if (port != CHARGE_PORT_NONE && charger_is_sourcing_otg_power(port)) { + LOG_WRN("Skip enable p%d: already sourcing", port); + return EC_ERROR_INVAL; + } + + /* Disable sinking on all ports except the desired one */ + for (i = 0; i < board_get_usb_pd_port_count(); i++) { + if (i == port) + continue; + + if (sm5803_vbus_sink_enable(i, 0)) + /* + * Do not early-return because this can fail during + * power-on which would put us into a loop. + */ + LOG_WRN("p%d: sink path disable failed.", i); + } + + /* Don't enable anything (stop here) if no ports were requested */ + if ((port == CHARGE_PORT_NONE) || (old_port == port)) + return EC_SUCCESS; + + /* + * Stop the charger IC from switching while changing ports. Otherwise, + * we can overcurrent the adapter we're switching to. (crbug.com/926056) + */ + if (old_port != CHARGE_PORT_NONE) + charger_discharge_on_ac(1); + + /* Enable requested charge port. */ + rv = sm5803_vbus_sink_enable(port, 1); + if (rv) + LOG_WRN("p%d: sink path enable failed: code %d", port, rv); + + /* Allow the charger IC to begin/continue switching. */ + charger_discharge_on_ac(0); + + return rv; +} + +uint16_t tcpc_get_alert_status(void) +{ + /* + * TCPC 0 is embedded in the EC and processes interrupts in the chip + * code (it83xx/intc.c). This function only needs to poll port C1 if + * present. + */ + uint16_t status = 0; + int regval; + + /* Is the C1 port present and its IRQ line asserted? */ + if (board_get_usb_pd_port_count() == 2 && + !gpio_pin_get_dt(GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl))) { + /* + * C1 IRQ is shared between BC1.2 and TCPC; poll TCPC to see if + * it asserted the IRQ. + */ + if (!tcpc_read16(1, TCPC_REG_ALERT, ®val)) { + if (regval) + status = PD_STATUS_TCPC_ALERT_1; + } + } + + return status; +} + +void pd_power_supply_reset(int port) +{ + int prev_en; + + if (port < 0 || port >= board_get_usb_pd_port_count()) + return; + + prev_en = charger_is_sourcing_otg_power(port); + + /* Disable Vbus */ + charger_enable_otg_power(port, 0); + + /* Discharge Vbus if previously enabled */ + if (prev_en) + sm5803_set_vbus_disch(port, 1); + + /* Notify host of power info change. */ + pd_send_host_event(PD_EVENT_POWER_CHANGE); +} + +int pd_set_power_supply_ready(int port) +{ + enum ec_error_list rv; + + if (port < 0 || port > board_get_usb_pd_port_count()) { + LOG_WRN("Port C%d does not exist, cannot enable VBUS", port); + return EC_ERROR_INVAL; + } + + /* Disable sinking */ + rv = sm5803_vbus_sink_enable(port, 0); + if (rv) { + LOG_WRN("C%d failed to disable sinking: %d", port, rv); + return rv; + } + + /* Disable Vbus discharge */ + rv = sm5803_set_vbus_disch(port, 0); + if (rv) { + LOG_WRN("C%d failed to clear VBUS discharge: %d", port, rv); + return rv; + } + + /* Provide Vbus */ + rv = charger_enable_otg_power(port, 1); + if (rv) { + LOG_WRN("C%d failed to enable VBUS sourcing: %d", port, rv); + return rv; + } + + /* Notify host of power info change. */ + pd_send_host_event(PD_EVENT_POWER_CHANGE); + + return EC_SUCCESS; +} + +__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp) +{ + int rv; + const int current = rp == TYPEC_RP_3A0 ? 3000 : 1500; + + rv = charger_set_otg_current_voltage(port, current, 5000); + if (rv != EC_SUCCESS) { + LOG_WRN("Failed to set source ilimit on port %d to %d: %d", + port, current, rv); + } +} + +void board_reset_pd_mcu(void) +{ + /* + * Do nothing. The integrated TCPC for C0 lacks a dedicated reset + * command, and C1 (if present) doesn't have a reset pin connected + * to the EC. + */ +} + +#define INT_RECHECK_US 5000 + +/* C0 interrupt line shared by BC 1.2 and charger */ + +static void check_c0_line(void); +DECLARE_DEFERRED(check_c0_line); + +static void notify_c0_chips(void) +{ + usb_charger_task_set_event(0, USB_CHG_EVENT_BC12); + sm5803_interrupt(0); +} + +static void check_c0_line(void) +{ + /* + * If line is still being held low, see if there's more to process from + * one of the chips + */ + if (!gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_c0_int_odl))) { + notify_c0_chips(); + hook_call_deferred(&check_c0_line_data, INT_RECHECK_US); + } +} + +void usb_c0_interrupt(enum gpio_signal s) +{ + /* Cancel any previous calls to check the interrupt line */ + hook_call_deferred(&check_c0_line_data, -1); + + /* Notify all chips using this line that an interrupt came in */ + notify_c0_chips(); + + /* Check the line again in 5ms */ + hook_call_deferred(&check_c0_line_data, INT_RECHECK_US); +} + +/* C1 interrupt line shared by BC 1.2, TCPC, and charger */ +static void check_c1_line(void); +DECLARE_DEFERRED(check_c1_line); + +static void notify_c1_chips(void) +{ + schedule_deferred_pd_interrupt(1); + usb_charger_task_set_event(1, USB_CHG_EVENT_BC12); + /* Charger is handled in board_process_pd_alert */ +} + +static void check_c1_line(void) +{ + /* + * If line is still being held low, see if there's more to process from + * one of the chips. + */ + if (!gpio_pin_get_dt(GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl))) { + notify_c1_chips(); + hook_call_deferred(&check_c1_line_data, INT_RECHECK_US); + } +} + +void usb_c1_interrupt(enum gpio_signal s) +{ + /* Cancel any previous calls to check the interrupt line */ + hook_call_deferred(&check_c1_line_data, -1); + + /* Notify all chips using this line that an interrupt came in */ + notify_c1_chips(); + + /* Check the line again in 5ms */ + hook_call_deferred(&check_c1_line_data, INT_RECHECK_US); +} + +/* + * Check state of IRQ lines at startup, ensuring an IRQ that happened before + * the EC started up won't get lost (leaving the IRQ line asserted and blocking + * any further interrupts on the port). + * + * Although the PD task will check for pending TCPC interrupts on startup, + * the charger sharing the IRQ will not be polled automatically. + */ +void board_handle_initial_typec_irq(void) +{ + check_c0_line(); + if (board_get_usb_pd_port_count() == 2) + check_c1_line(); +} +/* + * This must run after sub-board detection (which happens in EC main()), + * but isn't depended on by anything else either. + */ +DECLARE_HOOK(HOOK_INIT, board_handle_initial_typec_irq, HOOK_PRIO_LAST); + +/* + * Handle charger interrupts in the PD task. Not doing so can lead to a priority + * inversion where we fail to respond to TCPC alerts quickly enough because we + * don't get another edge on a shared IRQ until the charger interrupt is cleared + * (or the IRQ is polled again), which happens in the low-priority charger task: + * the high-priority type-C handler is thus blocked on the lower-priority + * charger. + * + * To avoid that, we run charger interrupts at the same priority. + */ +void board_process_pd_alert(int port) +{ + /* + * Port 0 doesn't use an external TCPC, so its interrupts don't need + * this special handling. + */ + if (port == 1 && + !gpio_pin_get_dt(GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl))) { + sm5803_handle_interrupt(port); + } +} + +int pd_snk_is_vbus_provided(int port) +{ + int chg_det = 0; + + sm5803_get_chg_det(port, &chg_det); + + return chg_det; +} diff --git a/zephyr/projects/nissa/yaviks/yaviks_vif.xml b/zephyr/projects/nissa/yaviks/yaviks_vif.xml new file mode 100644 index 0000000000..edc6299c58 --- /dev/null +++ b/zephyr/projects/nissa/yaviks/yaviks_vif.xml @@ -0,0 +1,350 @@ +<?xml version="1.0" encoding="utf-8"?>
+<vif:VIF xmlns:opt="http://usb.org/VendorInfoFileOptionalContent.xsd" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:vif="http://usb.org/VendorInfoFile.xsd">
+ <vif:VIF_Specification>3.19</vif:VIF_Specification>
+ <vif:VIF_App>
+ <vif:Vendor>USB-IF</vif:Vendor>
+ <vif:Name>VIF Editor</vif:Name>
+ <vif:Version>3.2.4.0</vif:Version>
+ </vif:VIF_App>
+ <vif:Vendor_Name>Google</vif:Vendor_Name>
+ <vif:Model_Part_Number>Yaviks</vif:Model_Part_Number>
+ <vif:Product_Revision>1</vif:Product_Revision>
+ <vif:TID>0</vif:TID>
+ <vif:VIF_Product_Type value="0">Port Product</vif:VIF_Product_Type>
+ <vif:Certification_Type value="1">Reference Platform</vif:Certification_Type>
+ <vif:Product>
+ <!--Product Level Content:-->
+ </vif:Product>
+ <vif:Component>
+ <!--Component 0: Port 0-->
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <!--;Component-->
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <vif:Port_Label>0</vif:Port_Label>
+ <vif:Connector_Type value="2">Type-C®</vif:Connector_Type>
+ <vif:USB4_Supported value="false" />
+ <vif:USB_PD_Support value="true" />
+ <vif:PD_Port_Type value="4">DRP</vif:PD_Port_Type>
+ <vif:Type_C_State_Machine value="2">DRP</vif:Type_C_State_Machine>
+ <vif:Port_Battery_Powered value="true" />
+ <vif:BC_1_2_Support value="2">Charging Port</vif:BC_1_2_Support>
+ <vif:Captive_Cable value="false" />
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <!--;General PD-->
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <vif:PD_Spec_Revision_Major value="3" />
+ <vif:PD_Spec_Revision_Minor value="1" />
+ <vif:PD_Spec_Version_Major value="1" />
+ <vif:PD_Spec_Version_Minor value="3" />
+ <vif:PD_Specification_Revision value="2">Revision 3</vif:PD_Specification_Revision>
+ <vif:SOP_Capable value="true" />
+ <vif:SOP_P_Capable value="true" />
+ <vif:SOP_PP_Capable value="true" />
+ <vif:SOP_P_Debug_Capable value="false" />
+ <vif:SOP_PP_Debug_Capable value="false" />
+ <vif:Manufacturer_Info_Supported_Port value="true" />
+ <vif:Manufacturer_Info_VID_Port value="6353">18D1</vif:Manufacturer_Info_VID_Port>
+ <vif:Manufacturer_Info_PID_Port value="20570">505A</vif:Manufacturer_Info_PID_Port>
+ <vif:Chunking_Implemented_SOP value="true" />
+ <vif:Unchunked_Extended_Messages_Supported value="false" />
+ <vif:Security_Msgs_Supported_SOP value="false" />
+ <vif:Unconstrained_Power value="false" />
+ <vif:Num_Fixed_Batteries value="1" />
+ <vif:Num_Swappable_Battery_Slots value="0" />
+ <vif:ID_Header_Connector_Type_SOP value="2">USB Type-C® Receptacle</vif:ID_Header_Connector_Type_SOP>
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <!--;PD Capabilities-->
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <vif:USB_Comms_Capable value="true" />
+ <vif:DR_Swap_To_DFP_Supported value="true" />
+ <vif:DR_Swap_To_UFP_Supported value="false" />
+ <vif:VCONN_Swap_To_On_Supported value="true" />
+ <vif:VCONN_Swap_To_Off_Supported value="true" />
+ <vif:Responds_To_Discov_SOP_UFP value="false" />
+ <vif:Responds_To_Discov_SOP_DFP value="true" />
+ <vif:Attempts_Discov_SOP value="true" />
+ <vif:Power_Interruption_Available value="0">No Interruption Possible</vif:Power_Interruption_Available>
+ <vif:Data_Reset_Supported value="false" />
+ <vif:Enter_USB_Supported value="false" />
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <!--;USB Type-C®-->
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <vif:Type_C_Can_Act_As_Host value="true" />
+ <vif:Type_C_Can_Act_As_Device value="false" />
+ <vif:Type_C_Implements_Try_SRC value="true" />
+ <vif:Type_C_Implements_Try_SNK value="false" />
+ <vif:Type_C_Supports_Audio_Accessory value="false" />
+ <vif:Type_C_Is_VCONN_Powered_Accessory value="false" />
+ <vif:Type_C_Is_Debug_Target_SRC value="true" />
+ <vif:Type_C_Is_Debug_Target_SNK value="true" />
+ <vif:RP_Value value="1">1.5A</vif:RP_Value>
+ <vif:Type_C_Port_On_Hub value="false" />
+ <vif:Type_C_Power_Source value="2">Both</vif:Type_C_Power_Source>
+ <vif:Type_C_Sources_VCONN value="true" />
+ <vif:Type_C_Is_Alt_Mode_Controller value="true" />
+ <vif:Type_C_Is_Alt_Mode_Adapter value="false" />
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <!--;Product Power-->
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <vif:Product_Total_Source_Power_mW value="15000">15000 mW</vif:Product_Total_Source_Power_mW>
+ <vif:Port_Source_Power_Type value="0">Assured</vif:Port_Source_Power_Type>
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <!--;USB Host-->
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <vif:Host_Supports_USB_Data value="true" />
+ <vif:Host_Speed value="1">USB 3.2 Gen 1x1</vif:Host_Speed>
+ <vif:Host_Contains_Captive_Retimer value="false" />
+ <vif:Host_Truncates_DP_For_tDHPResponse value="false" />
+ <vif:Host_Is_Embedded value="false" />
+ <vif:Host_Suspend_Supported value="true" />
+ <vif:Is_DFP_On_Hub value="false" />
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <!--;Battery Charging 1.2-->
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <vif:BC_1_2_Charging_Port_Type value="1">CDP</vif:BC_1_2_Charging_Port_Type>
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <!--;PD Source-->
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <vif:PD_Power_As_Source value="15000">15000 mW</vif:PD_Power_As_Source>
+ <vif:EPR_Supported_As_Src value="false" />
+ <vif:USB_Suspend_May_Be_Cleared value="false" />
+ <vif:Sends_Pings value="false" />
+ <vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink value="0">FR_Swap not supported</vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink>
+ <vif:Master_Port value="false" />
+ <vif:Num_Src_PDOs value="1" />
+ <vif:PD_OC_Protection value="true" />
+ <vif:PD_OCP_Method value="0">Over-Current Response</vif:PD_OCP_Method>
+ <!--Bundle: SrcPdoList-->
+ <vif:SrcPdoList>
+ <vif:SrcPDO>
+ <!--Source PDO 1-->
+ <vif:Src_PDO_Supply_Type value="0">Fixed</vif:Src_PDO_Supply_Type>
+ <vif:Src_PDO_Peak_Current value="0">100% IOC</vif:Src_PDO_Peak_Current>
+ <vif:Src_PDO_Voltage value="100">5000 mV</vif:Src_PDO_Voltage>
+ <vif:Src_PDO_Max_Current value="300">3000 mA</vif:Src_PDO_Max_Current>
+ <vif:Src_PD_OCP_OC_Debounce value="0">0 msec</vif:Src_PD_OCP_OC_Debounce>
+ <vif:Src_PD_OCP_OC_Threshold value="300">3000 mA</vif:Src_PD_OCP_OC_Threshold>
+ </vif:SrcPDO>
+ </vif:SrcPdoList>
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <!--;PD Sink-->
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <vif:PD_Power_As_Sink value="45000">45000 mW</vif:PD_Power_As_Sink>
+ <vif:EPR_Supported_As_Snk value="false" />
+ <vif:No_USB_Suspend_May_Be_Set value="true" />
+ <vif:GiveBack_May_Be_Set value="false" />
+ <vif:Higher_Capability_Set value="false" />
+ <vif:FR_Swap_Reqd_Type_C_Current_As_Initial_Source value="0">FR_Swap not supported</vif:FR_Swap_Reqd_Type_C_Current_As_Initial_Source>
+ <vif:Num_Snk_PDOs value="3" />
+ <!--Bundle: SnkPdoList-->
+ <vif:SnkPdoList>
+ <vif:SnkPDO>
+ <!--Sink PDO 1-->
+ <vif:Snk_PDO_Supply_Type value="0">Fixed</vif:Snk_PDO_Supply_Type>
+ <vif:Snk_PDO_Voltage value="100">5000 mV</vif:Snk_PDO_Voltage>
+ <vif:Snk_PDO_Op_Current value="300">3000 mA</vif:Snk_PDO_Op_Current>
+ </vif:SnkPDO>
+ <vif:SnkPDO>
+ <!--Sink PDO 2-->
+ <vif:Snk_PDO_Supply_Type value="1">Battery</vif:Snk_PDO_Supply_Type>
+ <vif:Snk_PDO_Op_Power value="60">15000 mW</vif:Snk_PDO_Op_Power>
+ <vif:Snk_PDO_Min_Voltage value="95">4750 mV</vif:Snk_PDO_Min_Voltage>
+ <vif:Snk_PDO_Max_Voltage value="300">15000 mV</vif:Snk_PDO_Max_Voltage>
+ </vif:SnkPDO>
+ <vif:SnkPDO>
+ <!--Sink PDO 3-->
+ <vif:Snk_PDO_Supply_Type value="2">Variable</vif:Snk_PDO_Supply_Type>
+ <vif:Snk_PDO_Min_Voltage value="95">4750 mV</vif:Snk_PDO_Min_Voltage>
+ <vif:Snk_PDO_Max_Voltage value="300">15000 mV</vif:Snk_PDO_Max_Voltage>
+ <vif:Snk_PDO_Op_Current value="300">3000 mA</vif:Snk_PDO_Op_Current>
+ </vif:SnkPDO>
+ </vif:SnkPdoList>
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <!--;Dual Role-->
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <vif:Accepts_PR_Swap_As_Src value="true" />
+ <vif:Accepts_PR_Swap_As_Snk value="true" />
+ <vif:Requests_PR_Swap_As_Src value="true" />
+ <vif:Requests_PR_Swap_As_Snk value="true" />
+ <vif:FR_Swap_Supported_As_Initial_Sink value="false" />
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <!--;SOP Discover ID-->
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <vif:XID_SOP value="0" />
+ <vif:Data_Capable_As_USB_Host_SOP value="true" />
+ <vif:Data_Capable_As_USB_Device_SOP value="false" />
+ <vif:Product_Type_UFP_SOP value="0">Undefined</vif:Product_Type_UFP_SOP>
+ <vif:Product_Type_DFP_SOP value="2">PDUSB Host</vif:Product_Type_DFP_SOP>
+ <vif:DFP_VDO_Port_Number value="0" />
+ <vif:Modal_Operation_Supported_SOP value="false" />
+ <vif:USB_VID_SOP value="6353">18D1</vif:USB_VID_SOP>
+ <vif:PID_SOP value="20570">505A</vif:PID_SOP>
+ <vif:bcdDevice_SOP value="0">0000</vif:bcdDevice_SOP>
+ </vif:Component>
+ <vif:Component>
+ <!--Component 1: Port 1-->
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <!--;Component-->
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <vif:Port_Label>1</vif:Port_Label>
+ <vif:Connector_Type value="2">Type-C®</vif:Connector_Type>
+ <vif:USB4_Supported value="false" />
+ <vif:USB_PD_Support value="true" />
+ <vif:PD_Port_Type value="4">DRP</vif:PD_Port_Type>
+ <vif:Type_C_State_Machine value="2">DRP</vif:Type_C_State_Machine>
+ <vif:Port_Battery_Powered value="true" />
+ <vif:BC_1_2_Support value="2">Charging Port</vif:BC_1_2_Support>
+ <vif:Captive_Cable value="false" />
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <!--;General PD-->
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <vif:PD_Spec_Revision_Major value="3" />
+ <vif:PD_Spec_Revision_Minor value="1" />
+ <vif:PD_Spec_Version_Major value="1" />
+ <vif:PD_Spec_Version_Minor value="3" />
+ <vif:PD_Specification_Revision value="2">Revision 3</vif:PD_Specification_Revision>
+ <vif:SOP_Capable value="true" />
+ <vif:SOP_P_Capable value="true" />
+ <vif:SOP_PP_Capable value="true" />
+ <vif:SOP_P_Debug_Capable value="false" />
+ <vif:SOP_PP_Debug_Capable value="false" />
+ <vif:Manufacturer_Info_Supported_Port value="true" />
+ <vif:Manufacturer_Info_VID_Port value="6353">18D1</vif:Manufacturer_Info_VID_Port>
+ <vif:Manufacturer_Info_PID_Port value="20570">505A</vif:Manufacturer_Info_PID_Port>
+ <vif:Chunking_Implemented_SOP value="true" />
+ <vif:Unchunked_Extended_Messages_Supported value="false" />
+ <vif:Security_Msgs_Supported_SOP value="false" />
+ <vif:Unconstrained_Power value="false" />
+ <vif:Num_Fixed_Batteries value="1" />
+ <vif:Num_Swappable_Battery_Slots value="0" />
+ <vif:ID_Header_Connector_Type_SOP value="2">USB Type-C® Receptacle</vif:ID_Header_Connector_Type_SOP>
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <!--;PD Capabilities-->
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <vif:USB_Comms_Capable value="true" />
+ <vif:DR_Swap_To_DFP_Supported value="true" />
+ <vif:DR_Swap_To_UFP_Supported value="false" />
+ <vif:VCONN_Swap_To_On_Supported value="true" />
+ <vif:VCONN_Swap_To_Off_Supported value="true" />
+ <vif:Responds_To_Discov_SOP_UFP value="false" />
+ <vif:Responds_To_Discov_SOP_DFP value="true" />
+ <vif:Attempts_Discov_SOP value="true" />
+ <vif:Power_Interruption_Available value="0">No Interruption Possible</vif:Power_Interruption_Available>
+ <vif:Data_Reset_Supported value="false" />
+ <vif:Enter_USB_Supported value="false" />
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <!--;USB Type-C®-->
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <vif:Type_C_Can_Act_As_Host value="true" />
+ <vif:Type_C_Can_Act_As_Device value="false" />
+ <vif:Type_C_Implements_Try_SRC value="true" />
+ <vif:Type_C_Implements_Try_SNK value="false" />
+ <vif:Type_C_Supports_Audio_Accessory value="false" />
+ <vif:Type_C_Is_VCONN_Powered_Accessory value="false" />
+ <vif:Type_C_Is_Debug_Target_SRC value="true" />
+ <vif:Type_C_Is_Debug_Target_SNK value="true" />
+ <vif:RP_Value value="1">1.5A</vif:RP_Value>
+ <vif:Type_C_Port_On_Hub value="false" />
+ <vif:Type_C_Power_Source value="2">Both</vif:Type_C_Power_Source>
+ <vif:Type_C_Sources_VCONN value="true" />
+ <vif:Type_C_Is_Alt_Mode_Controller value="true" />
+ <vif:Type_C_Is_Alt_Mode_Adapter value="false" />
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <!--;Product Power-->
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <vif:Product_Total_Source_Power_mW value="15000">15000 mW</vif:Product_Total_Source_Power_mW>
+ <vif:Port_Source_Power_Type value="0">Assured</vif:Port_Source_Power_Type>
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <!--;USB Host-->
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <vif:Host_Supports_USB_Data value="true" />
+ <vif:Host_Speed value="1">USB 3.2 Gen 1x1</vif:Host_Speed>
+ <vif:Host_Contains_Captive_Retimer value="true" />
+ <vif:Host_Truncates_DP_For_tDHPResponse value="false" />
+ <vif:Host_Is_Embedded value="false" />
+ <vif:Host_Suspend_Supported value="true" />
+ <vif:Is_DFP_On_Hub value="false" />
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <!--;Battery Charging 1.2-->
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <vif:BC_1_2_Charging_Port_Type value="1">CDP</vif:BC_1_2_Charging_Port_Type>
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <!--;PD Source-->
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <vif:PD_Power_As_Source value="15000">15000 mW</vif:PD_Power_As_Source>
+ <vif:EPR_Supported_As_Src value="false" />
+ <vif:USB_Suspend_May_Be_Cleared value="false" />
+ <vif:Sends_Pings value="false" />
+ <vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink value="0">FR_Swap not supported</vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink>
+ <vif:Master_Port value="false" />
+ <vif:Num_Src_PDOs value="1" />
+ <vif:PD_OC_Protection value="true" />
+ <vif:PD_OCP_Method value="0">Over-Current Response</vif:PD_OCP_Method>
+ <!--Bundle: SrcPdoList-->
+ <vif:SrcPdoList>
+ <vif:SrcPDO>
+ <!--Source PDO 1-->
+ <vif:Src_PDO_Supply_Type value="0">Fixed</vif:Src_PDO_Supply_Type>
+ <vif:Src_PDO_Peak_Current value="0">100% IOC</vif:Src_PDO_Peak_Current>
+ <vif:Src_PDO_Voltage value="100">5000 mV</vif:Src_PDO_Voltage>
+ <vif:Src_PDO_Max_Current value="300">3000 mA</vif:Src_PDO_Max_Current>
+ <vif:Src_PD_OCP_OC_Debounce value="0">0 msec</vif:Src_PD_OCP_OC_Debounce>
+ <vif:Src_PD_OCP_OC_Threshold value="300">3000 mA</vif:Src_PD_OCP_OC_Threshold>
+ </vif:SrcPDO>
+ </vif:SrcPdoList>
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <!--;PD Sink-->
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <vif:PD_Power_As_Sink value="45000">45000 mW</vif:PD_Power_As_Sink>
+ <vif:EPR_Supported_As_Snk value="false" />
+ <vif:No_USB_Suspend_May_Be_Set value="true" />
+ <vif:GiveBack_May_Be_Set value="false" />
+ <vif:Higher_Capability_Set value="false" />
+ <vif:FR_Swap_Reqd_Type_C_Current_As_Initial_Source value="0">FR_Swap not supported</vif:FR_Swap_Reqd_Type_C_Current_As_Initial_Source>
+ <vif:Num_Snk_PDOs value="3" />
+ <!--Bundle: SnkPdoList-->
+ <vif:SnkPdoList>
+ <vif:SnkPDO>
+ <!--Sink PDO 1-->
+ <vif:Snk_PDO_Supply_Type value="0">Fixed</vif:Snk_PDO_Supply_Type>
+ <vif:Snk_PDO_Voltage value="100">5000 mV</vif:Snk_PDO_Voltage>
+ <vif:Snk_PDO_Op_Current value="300">3000 mA</vif:Snk_PDO_Op_Current>
+ </vif:SnkPDO>
+ <vif:SnkPDO>
+ <!--Sink PDO 2-->
+ <vif:Snk_PDO_Supply_Type value="1">Battery</vif:Snk_PDO_Supply_Type>
+ <vif:Snk_PDO_Op_Power value="60">15000 mW</vif:Snk_PDO_Op_Power>
+ <vif:Snk_PDO_Min_Voltage value="95">4750 mV</vif:Snk_PDO_Min_Voltage>
+ <vif:Snk_PDO_Max_Voltage value="300">15000 mV</vif:Snk_PDO_Max_Voltage>
+ </vif:SnkPDO>
+ <vif:SnkPDO>
+ <!--Sink PDO 3-->
+ <vif:Snk_PDO_Supply_Type value="2">Variable</vif:Snk_PDO_Supply_Type>
+ <vif:Snk_PDO_Min_Voltage value="95">4750 mV</vif:Snk_PDO_Min_Voltage>
+ <vif:Snk_PDO_Max_Voltage value="300">15000 mV</vif:Snk_PDO_Max_Voltage>
+ <vif:Snk_PDO_Op_Current value="300">3000 mA</vif:Snk_PDO_Op_Current>
+ </vif:SnkPDO>
+ </vif:SnkPdoList>
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <!--;Dual Role-->
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <vif:Accepts_PR_Swap_As_Src value="true" />
+ <vif:Accepts_PR_Swap_As_Snk value="true" />
+ <vif:Requests_PR_Swap_As_Src value="true" />
+ <vif:Requests_PR_Swap_As_Snk value="true" />
+ <vif:FR_Swap_Supported_As_Initial_Sink value="false" />
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <!--;SOP Discover ID-->
+ <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+ <vif:XID_SOP value="0" />
+ <vif:Data_Capable_As_USB_Host_SOP value="true" />
+ <vif:Data_Capable_As_USB_Device_SOP value="false" />
+ <vif:Product_Type_UFP_SOP value="0">Undefined</vif:Product_Type_UFP_SOP>
+ <vif:Product_Type_DFP_SOP value="2">PDUSB Host</vif:Product_Type_DFP_SOP>
+ <vif:DFP_VDO_Port_Number value="1" />
+ <vif:Modal_Operation_Supported_SOP value="false" />
+ <vif:USB_VID_SOP value="6353">18D1</vif:USB_VID_SOP>
+ <vif:PID_SOP value="20570">505A</vif:PID_SOP>
+ <vif:bcdDevice_SOP value="0">0000</vif:bcdDevice_SOP>
+ </vif:Component>
+</vif:VIF>
\ No newline at end of file diff --git a/zephyr/projects/npcx_evb/npcx7/BUILD.py b/zephyr/projects/npcx_evb/npcx7/BUILD.py new file mode 100644 index 0000000000..baa6774595 --- /dev/null +++ b/zephyr/projects/npcx_evb/npcx7/BUILD.py @@ -0,0 +1,11 @@ +# Copyright 2021 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +"""Define zmake projects for npcx7_evb.""" + +register_npcx_project( + project_name="npcx7", + zephyr_board="npcx7_evb", + dts_overlays=["gpio.dts", "interrupts.dts", "fan.dts", "keyboard.dts"], +) diff --git a/zephyr/projects/npcx_evb/npcx7/CMakeLists.txt b/zephyr/projects/npcx_evb/npcx7/CMakeLists.txt new file mode 100644 index 0000000000..64429d586e --- /dev/null +++ b/zephyr/projects/npcx_evb/npcx7/CMakeLists.txt @@ -0,0 +1,10 @@ +# Copyright 2021 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +cmake_minimum_required(VERSION 3.13.1) + +find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}") +project(npcx7) + +zephyr_include_directories(include) diff --git a/zephyr/projects/npcx_evb/npcx7/fan.dts b/zephyr/projects/npcx_evb/npcx7/fan.dts new file mode 100644 index 0000000000..dc4debdcb9 --- /dev/null +++ b/zephyr/projects/npcx_evb/npcx7/fan.dts @@ -0,0 +1,39 @@ +/* Copyright 2021 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + fans { + compatible = "cros-ec,fans"; + + fan_0 { + pwms = <&pwm0 0 PWM_KHZ(25) PWM_POLARITY_NORMAL>; + rpm_min = <1000>; + rpm_start = <1000>; + rpm_max = <5200>; + tach = <&tach1>; + pgood_gpio = <&gpio_pgood_fan>; + }; + }; +}; + +/* Tachometer for fan speed measurement */ +&tach1 { + status = "okay"; + pinctrl-0 = <&ta1_1_in_gp40>; + pinctrl-names = "default"; + port = <NPCX_TACH_PORT_A>; /* port-A is selected */ + sample-clk = <NPCX_TACH_FREQ_LFCLK>; /* Use LFCLK as sampling clock */ + pulses-per-round = <2>; /* number of pulses per round of encoder */ +}; + +&pwm0_gpc3 { + drive-open-drain; +}; + +&pwm0 { + status = "okay"; + pinctrl-0 = <&pwm0_gpc3>; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/npcx_evb/npcx7/gpio.dts b/zephyr/projects/npcx_evb/npcx7/gpio.dts new file mode 100644 index 0000000000..d44927609d --- /dev/null +++ b/zephyr/projects/npcx_evb/npcx7/gpio.dts @@ -0,0 +1,68 @@ +/* Copyright 2021 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + aliases { + gpio-wp = &gpio_wp; + }; + + named-gpios { + compatible = "named-gpios"; + + recovery_l { + gpios = <&gpio0 3 GPIO_INPUT_PULL_UP>; + }; + gpio_wp: wp_l { + gpios = <&gpio9 3 (GPIO_INPUT_PULL_UP | + GPIO_ACTIVE_LOW)>; + }; + gpio_ac_present: ac_present { + gpios = <&gpiod 2 GPIO_INPUT>; + enum-name = "GPIO_AC_PRESENT"; + }; + gpio_power_button_l: power_button_l { + gpios = <&gpio0 0 GPIO_INPUT>; + enum-name = "GPIO_POWER_BUTTON_L"; + }; + gpio_lid_open: lid_open { + gpios = <&gpio0 1 GPIO_INPUT>; + enum-name = "GPIO_LID_OPEN"; + }; + entering_rw { + gpios = <&gpio3 6 GPIO_OUTPUT_LOW>; + enum-name = "GPIO_ENTERING_RW"; + }; + gpio_ec_pch_wake_odl: pch_wake_l { + gpios = <&gpio5 0 GPIO_OUTPUT_HIGH>; + }; + gpio_pgood_fan: pgood_fan { + gpios = <&gpioc 7 GPIO_INPUT_PULL_UP>; + }; + spi_cs_l { + gpios = <&gpioa 5 GPIO_OUTPUT_HIGH>; + }; + board_version1 { + gpios = <&gpio6 4 GPIO_INPUT>; + enum-name = "GPIO_BOARD_VERSION1"; + }; + board_version2 { + gpios = <&gpio6 5 GPIO_INPUT>; + enum-name = "GPIO_BOARD_VERSION2"; + }; + board_version3 { + gpios = <&gpio6 6 GPIO_INPUT>; + enum-name = "GPIO_BOARD_VERSION3"; + }; + }; + + hibernate-wake-pins { + compatible = "cros-ec,hibernate-wake-pins"; + wakeup-irqs = < + &int_ac_present + &int_power_button + &int_lid_open + >; + }; +}; diff --git a/zephyr/projects/npcx_evb/npcx7/interrupts.dts b/zephyr/projects/npcx_evb/npcx7/interrupts.dts new file mode 100644 index 0000000000..3e92428ef4 --- /dev/null +++ b/zephyr/projects/npcx_evb/npcx7/interrupts.dts @@ -0,0 +1,26 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + gpio-interrupts { + compatible = "cros-ec,gpio-interrupts"; + + int_ac_present: ac_present { + irq-pin = <&gpio_ac_present>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "extpower_interrupt"; + }; + int_lid_open: lid_open { + irq-pin = <&gpio_lid_open>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "lid_interrupt"; + }; + int_power_button: power_button { + irq-pin = <&gpio_power_button_l>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "power_button_interrupt"; + }; + }; +}; diff --git a/zephyr/projects/npcx_evb/npcx7/keyboard.dts b/zephyr/projects/npcx_evb/npcx7/keyboard.dts new file mode 100644 index 0000000000..3fb6986f1a --- /dev/null +++ b/zephyr/projects/npcx_evb/npcx7/keyboard.dts @@ -0,0 +1,42 @@ +/* Copyright 2021 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + cros-keyscan { + compatible = "cros-keyscan"; + + output-settle = <40>; + debounce-down = <6000>; + scan-period = <1500>; + poll-timeout = <1000000>; + + actual-key-mask = < + 0x14 /* C0 */ + 0xff /* C1 */ + 0xff /* C2 */ + 0xff /* C3 */ + 0xff /* C4 */ + 0xf5 /* C5 */ + 0xff /* C6 */ + 0xa4 /* C7 */ + 0xff /* C8 */ + 0xf6 /* C9 */ + 0x55 /* C10 */ + 0xfa /* C11 */ + 0xc8 /* C12 */ + >; + }; + + kblight { + compatible = "cros-ec,kblight-pwm"; + pwms = <&pwm2 0 PWM_KHZ(10) PWM_POLARITY_NORMAL>; + }; +}; + +&pwm2 { + status = "okay"; + pinctrl-0 = <&pwm2_gpc4>; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/npcx_evb/npcx7/prj.conf b/zephyr/projects/npcx_evb/npcx7/prj.conf new file mode 100644 index 0000000000..5f1fc03f88 --- /dev/null +++ b/zephyr/projects/npcx_evb/npcx7/prj.conf @@ -0,0 +1,60 @@ +# Copyright 2021 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +CONFIG_CROS_EC=y +CONFIG_PLATFORM_EC=y +CONFIG_PLATFORM_EC_BRINGUP=y +CONFIG_PLATFORM_EC_EXTPOWER_GPIO=y +CONFIG_PLATFORM_EC_LID_SWITCH=y +CONFIG_PLATFORM_EC_POWER_BUTTON=y +CONFIG_SHIMMED_TASKS=y + +CONFIG_PLATFORM_EC_BACKLIGHT_LID=n +CONFIG_PLATFORM_EC_SWITCH=n +CONFIG_PLATFORM_EC_VBOOT_EFS2=n +CONFIG_PLATFORM_EC_VSTORE=n + +# Board version is selected over GPIO board ID pins. +CONFIG_PLATFORM_EC_BOARD_VERSION_GPIO=y + +# PWM +CONFIG_PWM=y + +# Sensors +CONFIG_SENSOR=y +CONFIG_SENSOR_SHELL=n + +# Console command +CONFIG_PLATFORM_EC_CONSOLE_CMD_SCRATCHPAD=y + +CONFIG_TRACING=y +CONFIG_TRACING_ISR=y +CONFIG_TRACING_USER=y +CONFIG_PLATFORM_EC_CONSOLE_CMD_IRQ=y + +# eSPI +CONFIG_ESPI=y +CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S3=y +CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S4=y + +# Keyboard +CONFIG_CROS_KB_RAW_NPCX_KSO_HIGH_DRIVE=y + +# RTC +CONFIG_PLATFORM_EC_RTC=y +CONFIG_PLATFORM_EC_CONSOLE_CMD_RTC=y + +# USB-C +CONFIG_PLATFORM_EC_USB_PD_TBT_COMPAT_MODE=n +CONFIG_PLATFORM_EC_USB_PD_USB4=n + +# Zephyr feature +CONFIG_ASSERT=y +CONFIG_SHELL_MINIMAL=n +CONFIG_LOG=y + +# Avoid underflow info from tachometer +CONFIG_SENSOR_LOG_LEVEL_ERR=y + +CONFIG_SYSCON=y diff --git a/zephyr/projects/npcx_evb/npcx9/BUILD.py b/zephyr/projects/npcx_evb/npcx9/BUILD.py new file mode 100644 index 0000000000..335f410d9b --- /dev/null +++ b/zephyr/projects/npcx_evb/npcx9/BUILD.py @@ -0,0 +1,16 @@ +# Copyright 2021 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +"""Define zmake projects for npcx9_evb.""" + +register_npcx_project( + project_name="npcx9", + zephyr_board="npcx9_evb", + dts_overlays=[ + "gpio.dts", + "interrupts.dts", + "fan.dts", + "keyboard.dts", + ], +) diff --git a/zephyr/projects/npcx_evb/npcx9/CMakeLists.txt b/zephyr/projects/npcx_evb/npcx9/CMakeLists.txt new file mode 100644 index 0000000000..ef734c06f6 --- /dev/null +++ b/zephyr/projects/npcx_evb/npcx9/CMakeLists.txt @@ -0,0 +1,10 @@ +# Copyright 2021 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +cmake_minimum_required(VERSION 3.13.1) + +find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}") +project(npcx9) + +zephyr_include_directories(include) diff --git a/zephyr/projects/npcx_evb/npcx9/fan.dts b/zephyr/projects/npcx_evb/npcx9/fan.dts new file mode 100644 index 0000000000..dc4debdcb9 --- /dev/null +++ b/zephyr/projects/npcx_evb/npcx9/fan.dts @@ -0,0 +1,39 @@ +/* Copyright 2021 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + fans { + compatible = "cros-ec,fans"; + + fan_0 { + pwms = <&pwm0 0 PWM_KHZ(25) PWM_POLARITY_NORMAL>; + rpm_min = <1000>; + rpm_start = <1000>; + rpm_max = <5200>; + tach = <&tach1>; + pgood_gpio = <&gpio_pgood_fan>; + }; + }; +}; + +/* Tachometer for fan speed measurement */ +&tach1 { + status = "okay"; + pinctrl-0 = <&ta1_1_in_gp40>; + pinctrl-names = "default"; + port = <NPCX_TACH_PORT_A>; /* port-A is selected */ + sample-clk = <NPCX_TACH_FREQ_LFCLK>; /* Use LFCLK as sampling clock */ + pulses-per-round = <2>; /* number of pulses per round of encoder */ +}; + +&pwm0_gpc3 { + drive-open-drain; +}; + +&pwm0 { + status = "okay"; + pinctrl-0 = <&pwm0_gpc3>; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/npcx_evb/npcx9/gpio.dts b/zephyr/projects/npcx_evb/npcx9/gpio.dts new file mode 100644 index 0000000000..9a32112471 --- /dev/null +++ b/zephyr/projects/npcx_evb/npcx9/gpio.dts @@ -0,0 +1,72 @@ +/* Copyright 2021 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + aliases { + gpio-wp = &gpio_wp; + }; + + named-gpios { + compatible = "named-gpios"; + + recovery_l { + gpios = <&gpio0 3 GPIO_INPUT_PULL_UP>; + }; + gpio_wp: wp_l { + gpios = <&gpio9 3 (GPIO_INPUT_PULL_UP | + GPIO_ACTIVE_LOW)>; + }; + gpio_ac_present: ac_present { + gpios = <&gpiod 2 GPIO_INPUT>; + enum-name = "GPIO_AC_PRESENT"; + }; + gpio_power_button_l: power_button_l { + gpios = <&gpio0 0 GPIO_INPUT>; + enum-name = "GPIO_POWER_BUTTON_L"; + }; + gpio_lid_open: lid_open { + gpios = <&gpio0 1 GPIO_INPUT>; + enum-name = "GPIO_LID_OPEN"; + }; + entering_rw { + gpios = <&gpio3 6 GPIO_OUTPUT_LOW>; + enum-name = "GPIO_ENTERING_RW"; + }; + gpio_ec_pch_wake_odl: pch_wake_l { + gpios = <&gpio5 0 GPIO_OUTPUT_HIGH>; + }; + gpio_pgood_fan: pgood_fan { + gpios = <&gpioc 7 GPIO_INPUT_PULL_UP>; + }; + spi_cs_l { + gpios = <&gpioa 5 GPIO_OUTPUT_HIGH>; + }; + board_version1 { + gpios = <&gpio6 4 GPIO_INPUT>; + enum-name = "GPIO_BOARD_VERSION1"; + }; + board_version2 { + gpios = <&gpio6 5 GPIO_INPUT>; + enum-name = "GPIO_BOARD_VERSION2"; + }; + board_version3 { + gpios = <&gpio6 6 GPIO_INPUT>; + enum-name = "GPIO_BOARD_VERSION3"; + }; + }; +}; + +/* A falling edge detection type for PSL_IN2 */ +&psl_in2_gp00 { + psl-in-mode = "edge"; + psl-in-pol = "low-falling"; +}; + +/* Power domain device controlled by PSL (Power Switch Logic) IO pads */ +&power_ctrl_psl { + status = "okay"; + pinctrl-names = "sleep"; + pinctrl-0 = <&psl_in2_gp00>; +}; diff --git a/zephyr/projects/npcx_evb/npcx9/interrupts.dts b/zephyr/projects/npcx_evb/npcx9/interrupts.dts new file mode 100644 index 0000000000..3e92428ef4 --- /dev/null +++ b/zephyr/projects/npcx_evb/npcx9/interrupts.dts @@ -0,0 +1,26 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + gpio-interrupts { + compatible = "cros-ec,gpio-interrupts"; + + int_ac_present: ac_present { + irq-pin = <&gpio_ac_present>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "extpower_interrupt"; + }; + int_lid_open: lid_open { + irq-pin = <&gpio_lid_open>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "lid_interrupt"; + }; + int_power_button: power_button { + irq-pin = <&gpio_power_button_l>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "power_button_interrupt"; + }; + }; +}; diff --git a/zephyr/projects/npcx_evb/npcx9/keyboard.dts b/zephyr/projects/npcx_evb/npcx9/keyboard.dts new file mode 100644 index 0000000000..3fb6986f1a --- /dev/null +++ b/zephyr/projects/npcx_evb/npcx9/keyboard.dts @@ -0,0 +1,42 @@ +/* Copyright 2021 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + cros-keyscan { + compatible = "cros-keyscan"; + + output-settle = <40>; + debounce-down = <6000>; + scan-period = <1500>; + poll-timeout = <1000000>; + + actual-key-mask = < + 0x14 /* C0 */ + 0xff /* C1 */ + 0xff /* C2 */ + 0xff /* C3 */ + 0xff /* C4 */ + 0xf5 /* C5 */ + 0xff /* C6 */ + 0xa4 /* C7 */ + 0xff /* C8 */ + 0xf6 /* C9 */ + 0x55 /* C10 */ + 0xfa /* C11 */ + 0xc8 /* C12 */ + >; + }; + + kblight { + compatible = "cros-ec,kblight-pwm"; + pwms = <&pwm2 0 PWM_KHZ(10) PWM_POLARITY_NORMAL>; + }; +}; + +&pwm2 { + status = "okay"; + pinctrl-0 = <&pwm2_gpc4>; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/npcx_evb/npcx9/prj.conf b/zephyr/projects/npcx_evb/npcx9/prj.conf new file mode 100644 index 0000000000..827b6366c6 --- /dev/null +++ b/zephyr/projects/npcx_evb/npcx9/prj.conf @@ -0,0 +1,64 @@ +# Copyright 2021 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +CONFIG_CROS_EC=y +CONFIG_PLATFORM_EC=y +CONFIG_PLATFORM_EC_BRINGUP=y +CONFIG_PLATFORM_EC_EXTPOWER_GPIO=y +CONFIG_PLATFORM_EC_LID_SWITCH=y +CONFIG_PLATFORM_EC_POWER_BUTTON=y +CONFIG_SHIMMED_TASKS=y + +CONFIG_PLATFORM_EC_BACKLIGHT_LID=n +CONFIG_PLATFORM_EC_SWITCH=n +CONFIG_PLATFORM_EC_VBOOT_EFS2=n +CONFIG_PLATFORM_EC_VSTORE=n + +# Workaround npcx9 A1 chip's bug for download_from_flash API in th booter. +# This can be removed when A2 chip is available. +CONFIG_PLATFORM_EC_WORKAROUND_FLASH_DOWNLOAD_API=y + +# Board version is selected over GPIO board ID pins. +CONFIG_PLATFORM_EC_BOARD_VERSION_GPIO=y + +# PWM +CONFIG_PWM=y + +# Sensors +CONFIG_SENSOR=y +CONFIG_SENSOR_SHELL=n + +# Console command +CONFIG_PLATFORM_EC_CONSOLE_CMD_SCRATCHPAD=y + +CONFIG_TRACING=y +CONFIG_TRACING_ISR=y +CONFIG_TRACING_USER=y +CONFIG_PLATFORM_EC_CONSOLE_CMD_IRQ=y + +# eSPI +CONFIG_ESPI=y +CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S3=y +CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S4=y + +# Keyboard +CONFIG_CROS_KB_RAW_NPCX_KSO_HIGH_DRIVE=y + +# RTC +CONFIG_PLATFORM_EC_RTC=y +CONFIG_PLATFORM_EC_CONSOLE_CMD_RTC=y + +# USB-C +CONFIG_PLATFORM_EC_USB_PD_TBT_COMPAT_MODE=n +CONFIG_PLATFORM_EC_USB_PD_USB4=n + +# Zephyr feature +CONFIG_ASSERT=y +CONFIG_SHELL_MINIMAL=n +CONFIG_LOG=y + +# Avoid underflow info from tachometer +CONFIG_SENSOR_LOG_LEVEL_ERR=y + +CONFIG_SYSCON=y diff --git a/zephyr/projects/rex/BUILD.py b/zephyr/projects/rex/BUILD.py new file mode 100644 index 0000000000..2537f61226 --- /dev/null +++ b/zephyr/projects/rex/BUILD.py @@ -0,0 +1,45 @@ +# Copyright 2022 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +"""Rex Projects.""" + + +def register_variant( + project_name, extra_dts_overlays=(), extra_kconfig_files=() +): + """Register a variant of rex.""" + register_npcx_project( + project_name=project_name, + zephyr_board="npcx9m7f", + dts_overlays=[ + # Common to all projects. + here / "rex.dts", + # Project-specific DTS customization. + *extra_dts_overlays, + ], + kconfig_files=[ + # Common to all projects. + here / "prj.conf", + # Project-specific KConfig customization. + *extra_kconfig_files, + ], + ) + + +register_variant( + project_name="rex", + extra_dts_overlays=[ + here / "generated.dts", + here / "interrupts.dts", + here / "power_signals.dts", + here / "battery.dts", + here / "usbc.dts", + here / "keyboard.dts", + here / "led.dts", + here / "fan.dts", + here / "temp_sensors.dts", + here / "motionsense.dts", + ], + extra_kconfig_files=[here / "prj_rex.conf"], +) diff --git a/zephyr/projects/rex/CMakeLists.txt b/zephyr/projects/rex/CMakeLists.txt new file mode 100644 index 0000000000..27d7dff068 --- /dev/null +++ b/zephyr/projects/rex/CMakeLists.txt @@ -0,0 +1,12 @@ +# Copyright 2022 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +cmake_minimum_required(VERSION 3.20.5) +find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}") +project(rex) + +zephyr_include_directories("${CMAKE_CURRENT_SOURCE_DIR}/include") +zephyr_library_sources_ifdef(CONFIG_AP_PWRSEQ "src/board_power.c") +zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "src/usbc_config.c") +zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "src/usb_pd_policy.c") diff --git a/zephyr/projects/rex/Kconfig b/zephyr/projects/rex/Kconfig new file mode 100644 index 0000000000..7d17c27815 --- /dev/null +++ b/zephyr/projects/rex/Kconfig @@ -0,0 +1,11 @@ +# Copyright 2022 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +config BOARD_REX + bool "Google Rex Baseboard" + help + Build Google Rex reference board. The board uses Nuvoton + NPCX9 chip as the EC. + +source "Kconfig.zephyr" diff --git a/zephyr/projects/rex/battery.dts b/zephyr/projects/rex/battery.dts new file mode 100644 index 0000000000..e11346f48d --- /dev/null +++ b/zephyr/projects/rex/battery.dts @@ -0,0 +1,12 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + batteries { + default_battery: batgqa05l22 { + compatible = "powertech,batgqa05l22", "battery-smart"; + }; + }; +}; diff --git a/zephyr/projects/rex/fan.dts b/zephyr/projects/rex/fan.dts new file mode 100644 index 0000000000..aa6dcfde7d --- /dev/null +++ b/zephyr/projects/rex/fan.dts @@ -0,0 +1,39 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + fans { + compatible = "cros-ec,fans"; + + fan_0 { + pwms = <&pwm5 0 PWM_KHZ(1) PWM_POLARITY_NORMAL>; + rpm_min = <2200>; + rpm_start = <2200>; + rpm_max = <4200>; + tach = <&tach1>; + enable_gpio = <&gpio_en_pp5000_fan>; + }; + }; +}; + +/* Tachemeter for fan speed measurement */ +&tach1 { + status = "okay"; + pinctrl-0 = <&ta1_1_in_gp40>; + pinctrl-names = "default"; + port = <NPCX_TACH_PORT_A>; /* port-A is selected */ + sample-clk = <NPCX_TACH_FREQ_LFCLK>; /* Use LFCLK as sampling clock */ + pulses-per-round = <2>; /* number of pulses per round of encoder */ +}; + +&pwm5_gpb7 { + drive-open-drain; +}; + +&pwm5 { + status = "okay"; + pinctrl-0 = <&pwm5_gpb7>; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/rex/generated.dts b/zephyr/projects/rex/generated.dts new file mode 100644 index 0000000000..5b6f9cd708 --- /dev/null +++ b/zephyr/projects/rex/generated.dts @@ -0,0 +1,363 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + * + * This file is auto-generated - do not edit! + * + * TODO(b:/244441996): There are some errors in the main Rex EC GPIO spreadsheet + * which is used as input to create this device tree file. Until that issue is + * resolved, there are some edits required to this file to support EC + * functionality. + */ + +/ { + + named-adc-channels { + compatible = "named-adc-channels"; + + adc_ddr_soc: ddr_soc { + enum-name = "ADC_TEMP_SENSOR_1_DDR_SOC"; + io-channels = <&adc0 0>; + }; + adc_ambient: ambient { + enum-name = "ADC_TEMP_SENSOR_2"; + io-channels = <&adc0 1>; + }; + adc_charger: charger { + enum-name = "ADC_TEMP_SENSOR_3"; + io-channels = <&adc0 8>; + }; + adc_wwan: wwan { + enum-name = "ADC_TEMP_SENSOR_4"; + io-channels = <&adc0 7>; + }; + }; + + named-gpios { + compatible = "named-gpios"; + + gpio_acok_od: acok_od { + gpios = <&gpio0 0 GPIO_INPUT>; + enum-name = "GPIO_AC_PRESENT"; + }; + gpio_ccd_mode_odl: ccd_mode_odl { + gpios = <&gpioe 5 GPIO_ODR_HIGH>; + enum-name = "GPIO_CCD_MODE_ODL"; + }; + gpio_cpu_c10_gate_l: cpu_c10_gate_l { + gpios = <&gpioa 7 GPIO_INPUT>; + }; + gpio_ec_accel_int_r_l: ec_accel_int_r_l { + gpios = <&gpio8 1 GPIO_INPUT>; + }; + gpio_ec_als_rgb_int_r_l: ec_als_rgb_int_r_l { + gpios = <&gpiod 4 GPIO_INPUT_PULL_UP>; + }; + gpio_ec_batt_pres_odl: ec_batt_pres_odl { + gpios = <&gpioa 3 GPIO_INPUT>; + enum-name = "GPIO_BATT_PRES_ODL"; + }; + gpio_ec_cbi_wp: ec_cbi_wp { + gpios = <&gpio7 3 GPIO_OUTPUT>; + }; + gpio_ec_edp_bl_en: ec_edp_bl_en { + gpios = <&gpiod 3 GPIO_OUTPUT_LOW>; + enum-name = "GPIO_ENABLE_BACKLIGHT"; + }; + gpio_ec_gsc_packet_mode: ec_gsc_packet_mode { + gpios = <&gpio7 5 GPIO_OUTPUT>; + enum-name = "GPIO_PACKET_MODE_EN"; + }; + gpio_ec_imu_int_r_l: ec_imu_int_r_l { + gpios = <&gpio5 6 GPIO_INPUT_PULL_UP>; + }; + gpio_ec_imvp92_en_smb: ec_imvp92_en_smb { + gpios = <&gpiob 1 GPIO_OUTPUT>; + }; + gpio_ec_kb_bl_en_l: ec_kb_bl_en_l { + gpios = <&gpio8 6 GPIO_OUTPUT>; + }; + gpio_ec_kso_02_inv: ec_kso_02_inv { + gpios = <&gpio1 7 (GPIO_OUTPUT | GPIO_ACTIVE_LOW)>; + }; + gpio_ec_prochot_in_l: ec_prochot_in_l { + gpios = <&gpiof 0 GPIO_INPUT>; + }; + gpio_ec_prochot_odl: ec_prochot_odl { + gpios = <&gpio6 3 GPIO_ODR_HIGH>; + }; + gpio_ec_rst_r_odl: ec_rst_r_odl { + gpios = <&gpio7 7 GPIO_INPUT>; + }; + gpio_ec_soc_int_odl: ec_soc_int_odl { + gpios = <&gpio7 0 GPIO_ODR_LOW>; + enum-name = "GPIO_EC_INT_L"; + }; + gpio_ec_soc_pwr_btn_odl: ec_soc_pwr_btn_odl { + gpios = <&gpioc 1 GPIO_ODR_LOW>; + enum-name = "GPIO_PCH_PWRBTN_L"; + }; + gpio_ec_soc_rsmrst_l: ec_soc_rsmrst_l { + gpios = <&gpioa 6 GPIO_OUTPUT>; + }; + gpio_ec_soc_rtcrst: ec_soc_rtcrst { + gpios = <&gpio7 6 GPIO_ODR_HIGH>; + }; + gpio_ec_soc_wake_r_odl: ec_soc_wake_r_odl { + gpios = <&gpioc 0 GPIO_ODR_LOW>; + }; + gpio_ec_spare_gpio42: ec_spare_gpio42 { + gpios = <&gpio4 2 GPIO_OUTPUT>; + }; + gpio_ec_spare_gpio66: ec_spare_gpio66 { + gpios = <&gpio6 6 GPIO_OUTPUT>; + }; + gpio_ec_spare_gpio94: ec_spare_gpio94 { + gpios = <&gpio9 4 GPIO_OUTPUT>; + }; + gpio_ec_spare_gpioa2: ec_spare_gpioa2 { + gpios = <&gpioa 2 GPIO_OUTPUT>; + }; + gpio_ec_spare_gpioa4: ec_spare_gpioa4 { + gpios = <&gpioa 4 GPIO_OUTPUT>; + }; + gpio_ec_spare_gpioc7: ec_spare_gpioc7 { + gpios = <&gpioc 7 GPIO_OUTPUT>; + }; + gpio_ec_spare_gpo32: ec_spare_gpo32 { + gpios = <&gpio3 2 GPIO_OUTPUT>; + }; + gpio_ec_spare_gpo35: ec_spare_gpo35 { + gpios = <&gpio3 5 GPIO_OUTPUT>; + }; + gpio_ec_voldn_btn_odl: ec_voldn_btn_odl { + gpios = <&gpio9 3 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_VOLUME_DOWN_L"; + }; + gpio_ec_volup_btn_odl: ec_volup_btn_odl { + gpios = <&gpio9 7 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_VOLUME_UP_L"; + }; + gpio_ec_wp_l: ec_wp_l { + gpios = <&gpioa 1 GPIO_INPUT>; + }; + gpio_en_pp5000_fan: en_pp5000_fan { + gpios = <&gpio6 1 GPIO_OUTPUT_LOW>; + }; + gpio_en_pp5000_usba_r: en_pp5000_usba_r { + gpios = <&gpiod 7 GPIO_OUTPUT>; + }; + gpio_en_s5_rails: en_s5_rails { + gpios = <&gpiob 6 GPIO_ODR_HIGH>; + enum-name = "GPIO_TEMP_SENSOR_POWER"; + }; + gpio_en_z1_rails: en_z1_rails { + gpios = <&gpio8 5 GPIO_OUTPUT>; + }; + gpio_gsc_ec_pwr_btn_odl: gsc_ec_pwr_btn_odl { + gpios = <&gpio0 1 GPIO_INPUT_PULL_UP>; + }; + gpio_imvp92_vrrdy_od: imvp92_vrrdy_od { + gpios = <&gpio4 3 GPIO_INPUT>; + }; + gpio_led_1_l: led_1_l { + gpios = <&gpioc 4 GPIO_OUTPUT>; + }; + gpio_led_2_l: led_2_l { + gpios = <&gpioc 3 GPIO_OUTPUT>; + }; + gpio_led_3_l: led_3_l { + gpios = <&gpioc 2 GPIO_OUTPUT>; + }; + gpio_led_4_l: led_4_l { + gpios = <&gpio6 0 GPIO_OUTPUT>; + }; + gpio_lid_open: lid_open { + gpios = <&gpiod 2 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_LID_OPEN"; + }; + gpio_mech_pwr_btn_odl: mech_pwr_btn_odl { + gpios = <&gpio0 2 GPIO_INPUT>; + enum-name = "GPIO_POWER_BUTTON_L"; + }; + gpio_seq_ec_all_sys_pg: seq_ec_all_sys_pg { + gpios = <&gpiof 4 GPIO_INPUT>; + }; + gpio_seq_ec_rsmrst_odl: seq_ec_rsmrst_odl { + gpios = <&gpioe 2 GPIO_INPUT>; + }; + gpio_slp_s3_ls_l: slp_s3_ls_l { + gpios = <&gpio4 1 GPIO_INPUT>; + }; + gpio_sochot_odl: sochot_odl { + gpios = <&gpio9 6 GPIO_INPUT>; + }; + gpio_soc_pwrok: soc_pwrok { + gpios = <&gpioa 5 GPIO_OUTPUT>; + }; + gpio_sys_pwrok: sys_pwrok { + gpios = <&gpiob 0 GPIO_OUTPUT>; + }; + gpio_sys_rst_odl: sys_rst_odl { + gpios = <&gpioc 5 GPIO_INPUT>; + }; + gpio_sys_slp_s0ix_3v3_l: sys_slp_s0ix_3v3_l { + gpios = <&gpiod 5 GPIO_INPUT>; + }; + gpio_tablet_mode_l: tablet_mode_l { + gpios = <&gpio9 5 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_TABLET_MODE_L"; + }; + gpio_usb_c0_bc12_int_odl: usb_c0_bc12_int_odl { + gpios = <&gpioc 6 GPIO_INPUT>; + enum-name = "GPIO_USB_C0_BC12_INT_ODL"; + }; + gpio_usb_c0_ppc_int_odl: usb_c0_ppc_int_odl { + gpios = <&gpio6 2 GPIO_INPUT>; + enum-name = "GPIO_USB_C0_PPC_INT_ODL"; + }; + gpio_usb_c0_rt_3p3_sx_en: usb_c0_rt_3p3_sx_en { + gpios = <&gpio0 3 GPIO_OUTPUT_LOW>; + }; + gpio_usb_c0_rt_int_odl: usb_c0_rt_int_odl { + gpios = <&gpioa 0 GPIO_INPUT>; + }; + gpio_usb_c0_tcpc_int_odl: usb_c0_tcpc_int_odl { + gpios = <&gpioe 0 GPIO_INPUT>; + enum-name = "GPIO_USB_C0_TCPC_INT_ODL"; + }; + gpio_usb_c0_tcpc_rst_odl: usb_c0_tcpc_rst_odl { + gpios = <&gpio6 7 GPIO_ODR_HIGH>; + }; + gpio_usb_c1_bc12_int_odl: usb_c1_bc12_int_odl { + gpios = <&gpio5 0 GPIO_INPUT>; + enum-name = "GPIO_USB_C1_BC12_INT_ODL"; + }; + gpio_usb_c1_frs_en: usb_c1_frs_en { + gpios = <&gpio8 3 GPIO_ODR_HIGH>; + }; + gpio_usb_c1_ppc_int_odl: usb_c1_ppc_int_odl { + gpios = <&gpiof 5 GPIO_INPUT>; + enum-name = "GPIO_USB_C1_PPC_INT_ODL"; + }; + gpio_usb_c1_rst_odl: usb_c1_rst_odl { + gpios = <&gpio3 7 GPIO_ODR_LOW>; + }; + gpio_usb_c1_rt_int_odl: usb_c1_rt_int_odl { + gpios = <&gpio7 2 GPIO_INPUT_PULL_UP>; + }; + gpio_usb_c1_rt_rst_r_odl: usb_c1_rt_rst_r_odl { + gpios = <&gpio7 4 GPIO_ODR_HIGH>; + }; + gpio_usb_c1_tcpc_int_odl: usb_c1_tcpc_int_odl { + gpios = <&gpio3 4 GPIO_INPUT>; + enum-name = "GPIO_USB_C1_TCPC_INT_ODL"; + }; + }; + + named-i2c-ports { + compatible = "named-i2c-ports"; + + i2c_ec_i2c_sensor: ec_i2c_sensor { + i2c-port = <&i2c0_0>; + enum-names = "I2C_PORT_SENSOR"; + }; + i2c_ec_i2c_usb_c0_tcp: ec_i2c_usb_c0_tcp { + i2c-port = <&i2c1_0>; + enum-names = "I2C_PORT_USB_C0_TCPC"; + }; + i2c_ec_i2c_usb_c0_ppc_b: ec_i2c_usb_c0_ppc_b { + i2c-port = <&i2c2_0>; + enum-names = "I2C_PORT_PPC0"; + }; + i2c_ec_i2c_usb_c0_rt: ec_i2c_usb_c0_rt { + i2c-port = <&i2c3_0>; + enum-names = "I2C_PORT_USB_C0_RT"; + }; + i2c_ec_i2c_usb_c1_tcp: ec_i2c_usb_c1_tcp { + i2c-port = <&i2c4_1>; + enum-names = "I2C_PORT_USB_C1_TCPC"; + dynamic-speed; + }; + i2c_ec_i2c_bat: ec_i2c_bat { + i2c-port = <&i2c5_0>; + enum-names = "I2C_PORT_BATTERY"; + }; + i2c_ec_i2c_usb_c1_mix: ec_i2c_usb_c1_mix { + i2c-port = <&i2c6_1>; + enum-names = "I2C_PORT_USB_1_MIX"; + }; + i2c_ec_i2c_mi: ec_i2c_mi { + i2c-port = <&i2c7_0>; + enum-names = "I2C_PORT_EEPROM"; + }; + }; +}; + +&adc0 { + status = "okay"; +}; + +&i2c0_0 { + status = "okay"; +}; + +&i2c1_0 { + status = "okay"; +}; + +&i2c2_0 { + status = "okay"; +}; + +&i2c3_0 { + status = "okay"; +}; + +&i2c4_1 { + status = "okay"; +}; + +&i2c5_0 { + status = "okay"; +}; + +&i2c6_1 { + status = "okay"; +}; + +&i2c7_0 { + status = "okay"; +}; + +&i2c_ctrl0 { + status = "okay"; +}; + +&i2c_ctrl1 { + status = "okay"; +}; + +&i2c_ctrl2 { + status = "okay"; +}; + +&i2c_ctrl3 { + status = "okay"; +}; + +&i2c_ctrl4 { + status = "okay"; +}; + +&i2c_ctrl5 { + status = "okay"; +}; + +&i2c_ctrl6 { + status = "okay"; +}; + +&i2c_ctrl7 { + status = "okay"; +}; diff --git a/zephyr/projects/rex/include/gpio_map.h b/zephyr/projects/rex/include/gpio_map.h new file mode 100644 index 0000000000..01cbc44396 --- /dev/null +++ b/zephyr/projects/rex/include/gpio_map.h @@ -0,0 +1,9 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#ifndef __ZEPHYR_GPIO_MAP_H +#define __ZEPHYR_GPIO_MAP_H + +#endif /* __ZEPHYR_GPIO_MAP_H */ diff --git a/zephyr/projects/rex/interrupts.dts b/zephyr/projects/rex/interrupts.dts new file mode 100644 index 0000000000..7de9141caf --- /dev/null +++ b/zephyr/projects/rex/interrupts.dts @@ -0,0 +1,80 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + gpio-interrupts { + compatible = "cros-ec,gpio-interrupts"; + + int_ac_present: ac_present { + irq-pin = <&gpio_acok_od>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "extpower_interrupt"; + }; + int_power_button: power_button { + irq-pin = <&gpio_mech_pwr_btn_odl>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "power_button_interrupt"; + }; + int_lid_open: lid_open { + irq-pin = <&gpio_lid_open>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "lid_interrupt"; + }; + int_usb_c0_sbu_fault: c0_sbu_fault { + irq-pin = <&ioex_usb_c0_sbu_fault_odl>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "sbu_fault_interrupt"; + }; + int_usb_c0_tcpc: usb_c0_tcpc { + irq-pin = <&gpio_usb_c0_tcpc_int_odl>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "tcpc_alert_event"; + }; + int_usb_c0_ppc: usb_c0_ppc { + irq-pin = <&gpio_usb_c0_ppc_int_odl>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "ppc_interrupt"; + }; + int_usb_c0_bc12: usb_c0_bc12 { + irq-pin = <&gpio_usb_c0_bc12_int_odl>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "bc12_interrupt"; + }; + int_usb_c1_tcpc: usb_c1_tcpc { + irq-pin = <&gpio_usb_c1_tcpc_int_odl>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "tcpc_alert_event"; + }; + int_usb_c1_ppc: usb_c1_ppc { + irq-pin = <&gpio_usb_c1_ppc_int_odl>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "ppc_interrupt"; + }; + int_usb_c1_bc12: usb_c1_bc12 { + irq-pin = <&gpio_usb_c1_bc12_int_odl>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "bc12_interrupt"; + }; + int_imu: ec_imu { + irq-pin = <&gpio_ec_imu_int_r_l>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "lsm6dso_interrupt"; + }; + int_als_rgb: ec_als_rgb { + irq-pin = <&gpio_ec_als_rgb_int_r_l>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "tcs3400_interrupt"; + }; + int_accel: ec_accel { + irq-pin = <&gpio_ec_accel_int_r_l>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "lis2dw12_interrupt"; + }; + }; +}; + +/* Required node label that doesn't is named differently on Rex */ +gpio_ec_pch_wake_odl: &gpio_ec_soc_wake_r_odl {}; + diff --git a/zephyr/projects/rex/keyboard.dts b/zephyr/projects/rex/keyboard.dts new file mode 100644 index 0000000000..91fad2db92 --- /dev/null +++ b/zephyr/projects/rex/keyboard.dts @@ -0,0 +1,47 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + kblight { + compatible = "cros-ec,kblight-pwm"; + pwms = <&pwm3 0 PWM_HZ(2400) PWM_POLARITY_NORMAL>; + }; +}; + +&pwm3 { + status = "okay"; + pinctrl-0 = <&pwm3_gp80>; + pinctrl-names = "default"; +}; + +&cros_kb_raw { + status = "okay"; + /* No KSO2 (it's inverted and implemented by GPIO) */ + pinctrl-0 = < + &ksi0_gp31 + &ksi1_gp30 + &ksi2_gp27 + &ksi3_gp26 + &ksi4_gp25 + &ksi5_gp24 + &ksi6_gp23 + &ksi7_gp22 + &kso00_gp21 + &kso01_gp20 + &kso03_gp16 + &kso04_gp15 + &kso05_gp14 + &kso06_gp13 + &kso07_gp12 + &kso08_gp11 + &kso09_gp10 + &kso10_gp07 + &kso11_gp06 + &kso12_gp05 + &kso13_gp04 + &kso14_gp82 + >; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/rex/led.dts b/zephyr/projects/rex/led.dts new file mode 100644 index 0000000000..94acb6da5c --- /dev/null +++ b/zephyr/projects/rex/led.dts @@ -0,0 +1,138 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + gpio-led-pins { + compatible = "cros-ec,gpio-led-pins"; + + color_off: color-off { + led-color = "LED_OFF"; + led-id = "EC_LED_ID_BATTERY_LED"; + led-pins = <&gpio_led_1_l 1>, + <&gpio_led_2_l 1>; + }; + + color_white: color-white { + led-color = "LED_WHITE"; + led-id = "EC_LED_ID_BATTERY_LED"; + br-color = "EC_LED_COLOR_WHITE"; + led-pins = <&gpio_led_1_l 1>, + <&gpio_led_2_l 0>; + }; + + color_amber: color-amber { + led-color = "LED_AMBER"; + led-id = "EC_LED_ID_BATTERY_LED"; + br-color = "EC_LED_COLOR_AMBER"; + led-pins = <&gpio_led_1_l 0>, + <&gpio_led_2_l 1>; + }; + }; + + led-colors { + compatible = "cros-ec,led-policy"; + + power-state-charge { + charge-state = "PWR_STATE_CHARGE"; + + color-0 { + led-color = <&color_amber>; + }; + }; + + power-state-discharge-s0 { + charge-state = "PWR_STATE_DISCHARGE"; + chipset-state = "POWER_S0"; + + color-0 { + led-color = <&color_off>; + }; + }; + + power-state-discharge-s3 { + charge-state = "PWR_STATE_DISCHARGE"; + chipset-state = "POWER_S3"; + + /* Blue 1 sec, off 3 sec */ + color-0 { + led-color = <&color_white>; + period-ms = <1000>; + }; + color-1 { + led-color = <&color_off>; + period-ms = <3000>; + }; + }; + + power-state-discharge-s5 { + charge-state = "PWR_STATE_DISCHARGE"; + chipset-state = "POWER_S5"; + + color-0 { + led-color = <&color_off>; + }; + }; + + power-state-error { + charge-state = "PWR_STATE_ERROR"; + + /* Red 1 sec, off 1 sec */ + color-0 { + led-color = <&color_white>; + period-ms = <1000>; + }; + color-1 { + led-color = <&color_off>; + period-ms = <1000>; + }; + }; + + power-state-near-full { + charge-state = "PWR_STATE_CHARGE_NEAR_FULL"; + + color-0 { + led-color = <&color_amber>; + }; + }; + + power-state-forced-idle { + charge-state = "PWR_STATE_FORCED_IDLE"; + + /* White 2 sec, Amber 2 sec */ + color-0 { + led-color = <&color_white>; + period-ms = <2000>; + }; + color-1 { + led-color = <&color_amber>; + period-ms = <2000>; + }; + }; + + power-state-idle-default { + charge-state = "PWR_STATE_IDLE"; + + color-0 { + led-color = <&color_white>; + }; + }; + }; +}; + +&gpio_led_1_l { + #led-pin-cells = <1>; +}; + +&gpio_led_2_l { + #led-pin-cells = <1>; +}; + +&gpio_led_3_l { + #led-pin-cells = <1>; +}; + +&gpio_led_4_l { + #led-pin-cells = <1>; +}; diff --git a/zephyr/projects/rex/motionsense.dts b/zephyr/projects/rex/motionsense.dts new file mode 100644 index 0000000000..6af7cd2b12 --- /dev/null +++ b/zephyr/projects/rex/motionsense.dts @@ -0,0 +1,257 @@ +/* + * Copyright 2022 The ChromiumOS Authors + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include <dt-bindings/motionsense/utils.h> + + +/ { + aliases { + /* + * motion sense's <>_INT_EVENT is handled + * by alias. Using the alias, each driver creates + * its own <>_INT_EVENT. + */ + lsm6dso-int = &base_accel; + lis2dw12-int = &lid_accel; + tcs3400-int = &als_clear; + }; + + /* + * Declare mutexes used by sensor drivers. + * A mutex node is used to create an instance of mutex_t. + * A mutex node is referenced by a sensor node if the + * corresponding sensor driver needs to use the + * instance of the mutex. + */ + motionsense-mutex { + compatible = "cros-ec,motionsense-mutex"; + mutex_lis2dw12: lis2dw12-mutex { + }; + + mutex_lsm6dso: lsm6dso-mutex { + }; + }; + + /* Rotation matrix used by drivers. */ + motionsense-rotation-ref { + compatible = "cros-ec,motionsense-rotation-ref"; + lid_rot_ref: lid-rotation-ref { + mat33 = <0 1 0 + 1 0 0 + 0 0 (-1)>; + }; + base_rot_ref: base-rotation-ref { + mat33 = <1 0 0 + 0 (-1) 0 + 0 0 (-1)>; + }; + }; + + /* + * Driver specific data. A driver-specific data can be shared with + * different motion sensors while they are using the same driver. + * + * If a node's compatible starts with "cros-ec,accelgyro-", it is for + * a common structure defined in accelgyro.h. + * e.g) compatible = "cros-ec,accelgyro-als-drv-data" is for + * "struct als_drv_data_t" in accelgyro.h + */ + motionsense-sensor-data { + lis2dw12_data: lis2dw12-drv-data { + compatible = "cros-ec,drvdata-lis2dw12"; + status = "okay"; + }; + + lsm6dso_accel_data: lsm6dso-accel-drv-data { + compatible = "cros-ec,drvdata-lsm6dso"; + status = "okay"; + }; + + lsm6dso_gyro_data: lsm6dso-gyro-drv-data { + compatible = "cros-ec,drvdata-lsm6dso"; + status = "okay"; + }; + + tcs_clear_data: tcs3400-clear-drv-data { + compatible = "cros-ec,drvdata-tcs3400-clear"; + status = "okay"; + + als-drv-data { + compatible = "cros-ec,accelgyro-als-drv-data"; + als-cal { + scale = <1>; + uscale = <0>; + offset = <0>; + als-channel-scale { + compatible = + "cros-ec,accelgyro-als-channel-scale"; + k-channel-scale = <1>; + cover-scale = <1>; + }; + }; + }; + }; + + tcs_rgb_data: tcs3400-rgb-drv-data { + compatible = "cros-ec,drvdata-tcs3400-rgb"; + status = "okay"; + + /* node for rgb_calibration_t defined in accelgyro.h */ + rgb_calibration { + compatible = + "cros-ec,accelgyro-rgb-calibration"; + + irt = <1>; + + rgb-cal-x { + offset = <0>; + coeff = <0 0 0 1>; + als-channel-scale { + compatible = + "cros-ec,accelgyro-als-channel-scale"; + k-channel-scale = <1>; + cover-scale = <1>; + }; + }; + rgb-cal-y { + offset = <0>; + coeff = <0 0 0 1>; + als-channel-scale { + compatible = + "cros-ec,accelgyro-als-channel-scale"; + k-channel-scale = <1>; + cover-scale = <1>; + }; + }; + rgb-cal-z { + offset = <0>; + coeff = <0 0 0 1>; + als-channel-scale { + compatible = + "cros-ec,accelgyro-als-channel-scale"; + k-channel-scale = <1>; + cover-scale = <1>; + }; + }; + }; + }; + }; + + /* + * List of motion sensors that creates motion_sensors array. + * The nodelabel "lid_accel" and "base_accel" are used to indicate + * motion sensor IDs for lid angle calculation. + */ + motionsense-sensor { + lid_accel: lid-accel { + compatible = "cros-ec,lis2dw12"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_LID"; + mutex = <&mutex_lis2dw12>; + port = <&i2c_ec_i2c_sensor>; + rot-standard-ref = <&lid_rot_ref>; + default-range = <2>; + drv-data = <&lis2dw12_data>; + i2c-spi-addr-flags = "LIS2DWL_ADDR0_FLAGS"; + configs { + compatible = + "cros-ec,motionsense-sensor-config"; + ec-s0 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + ec-s3 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + }; + }; + + base_accel: base-accel { + compatible = "cros-ec,lsm6dso-accel"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_BASE"; + mutex = <&mutex_lsm6dso>; + port = <&i2c_ec_i2c_sensor>; + rot-standard-ref = <&base_rot_ref>; + default-range = <4>; + drv-data = <&lsm6dso_accel_data>; + i2c-spi-addr-flags = "LSM6DSO_ADDR0_FLAGS"; + configs { + compatible = + "cros-ec,motionsense-sensor-config"; + ec-s0 { + odr = <(10000 | ROUND_UP_FLAG)>; + ec-rate = <(100 * USEC_PER_MSEC)>; + }; + ec-s3 { + odr = <(10000 | ROUND_UP_FLAG)>; + ec-rate = <(100 * USEC_PER_MSEC)>; + }; + }; + }; + + base-gyro { + compatible = "cros-ec,lsm6dso-gyro"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_BASE"; + mutex = <&mutex_lsm6dso>; + port = <&i2c_ec_i2c_sensor>; + rot-standard-ref = <&base_rot_ref>; + default-range = <(1000 | ROUND_UP_FLAG)>; /* dps */ + drv-data = <&lsm6dso_gyro_data>; + i2c-spi-addr-flags = "LSM6DSO_ADDR0_FLAGS"; + }; + + als_clear: base-als-clear { + compatible = "cros-ec,tcs3400-clear"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_CAMERA"; + port = <&i2c_ec_i2c_sensor>; + default-range = <0x10000>; + drv-data = <&tcs_clear_data>; + i2c-spi-addr-flags = "TCS3400_I2C_ADDR_FLAGS"; + configs { + compatible = + "cros-ec,motionsense-sensor-config"; + ec-s0 { + /* Run ALS sensor in S0 */ + odr = <1000>; + }; + }; + }; + + base-als-rgb { + compatible = "cros-ec,tcs3400-rgb"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_CAMERA"; + default-range = <0x10000>; /* scale = 1x, uscale = 0 */ + drv-data = <&tcs_rgb_data>; + }; + }; + + motionsense-sensor-info { + compatible = "cros-ec,motionsense-sensor-info"; + + /* list of entries for motion_als_sensors */ + als-sensors = <&als_clear>; + /* + * list of GPIO interrupts that have to + * be enabled at initial stage + */ + sensor-irqs = <&int_imu &int_als_rgb &int_accel>; + /* list of sensors in force mode */ + accel-force-mode-sensors = <&lid_accel &als_clear>; + }; +}; diff --git a/zephyr/projects/rex/power_signals.dts b/zephyr/projects/rex/power_signals.dts new file mode 100644 index 0000000000..860c316795 --- /dev/null +++ b/zephyr/projects/rex/power_signals.dts @@ -0,0 +1,152 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + chosen { + intel-ap-pwrseq,espi = &espi0; + }; + + common-pwrseq { + compatible = "intel,ap-pwrseq"; + + sys-pwrok-delay = <3>; + all-sys-pwrgd-timeout = <20>; + }; + + pwr-en-pp3300-s5 { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "PP1800_S5/PP3300_S5 enable output to LS"; + enum-name = "PWR_EN_PP3300_A"; + gpios = <&gpiob 6 GPIO_ACTIVE_HIGH>; + output; + }; + pwr-pg-ec-rsmrst-od { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "RSMRST power good from regulator"; + enum-name = "PWR_RSMRST"; + gpios = <&gpioe 2 GPIO_ACTIVE_HIGH>; + interrupt-flags = <GPIO_INT_EDGE_BOTH>; + }; + pwr-ec-pch-rsmrst-odl { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "RSMRST output to PCH"; + enum-name = "PWR_EC_PCH_RSMRST"; + gpios = <&gpioa 6 GPIO_ACTIVE_HIGH>; + output; + }; + pwr-pch-pwrok { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "PCH_PWROK output to PCH"; + enum-name = "PWR_PCH_PWROK"; + gpios = <&gpioa 5 GPIO_ACTIVE_HIGH>; + output; + }; + pwr-ec-pch-sys-pwrok { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SYS_PWROK output to PCH"; + enum-name = "PWR_EC_PCH_SYS_PWROK"; + gpios = <&gpiob 0 GPIO_ACTIVE_HIGH>; + output; + }; + pwr-sys-rst-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SYS_RESET# output to PCH"; + enum-name = "PWR_SYS_RST"; + gpios = <&gpioc 5 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; + output; + }; + pwr-slp-s0-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SLP_S0_L input from PCH"; + enum-name = "PWR_SLP_S0"; + gpios = <&gpiod 5 GPIO_ACTIVE_LOW>; + interrupt-flags = <GPIO_INT_EDGE_BOTH>; + }; + pwr-slp-s3-l { + compatible = "intel,ap-pwrseq-vw"; + dbg-label = "SLP_S3_L input from PCH"; + enum-name = "PWR_SLP_S3"; + virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S4"; + vw-invert; +/* + * TODO: Initially, use virtual wire for sleep S3 signal instead of + * of the GPIO signal which also exists. + * compatible = "intel,ap-pwrseq-gpio"; + * gpios = <&gpio4 1 GPIO_ACTIVE_LOW>; + * interrupt-flags = <GPIO_INT_EDGE_BOTH>; + */ + }; + pwr-slp-s4 { + compatible = "intel,ap-pwrseq-vw"; + dbg-label = "SLP_S4 virtual wire input from PCH"; + enum-name = "PWR_SLP_S4"; + virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S4"; + vw-invert; + }; + pwr-slp-s5 { + compatible = "intel,ap-pwrseq-vw"; + dbg-label = "SLP_S5 virtual wire input from PCH"; + enum-name = "PWR_SLP_S5"; + virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S5"; + vw-invert; + }; + pwr-all-sys-pwrgd { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "all power good"; + enum-name = "PWR_ALL_SYS_PWRGD"; + gpios = <&gpiof 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; + interrupt-flags = <GPIO_INT_EDGE_BOTH>; + }; +}; + +/* + * Because the power signals directly reference the GPIOs, + * the corresponding named-gpios need to have no-auto-init set. + */ + /* pwr-en-pp3300-s5 */ +&gpio_en_s5_rails { + no-auto-init; +}; + +/* pwr-pg-ec-rsmrst-od */ +&gpio_seq_ec_rsmrst_odl{ + no-auto-init; +}; + +/* pwr-ec-pch-rsmrst-odl */ +&gpio_ec_soc_rsmrst_l{ + no-auto-init; +}; + +/* pwr-pch-pwrok */ +&gpio_soc_pwrok{ + no-auto-init; +}; + +/* pwr-ec-pch-sys-pwrok */ +&gpio_sys_pwrok{ + no-auto-init; +}; + +/* pwr-sys-rst-l */ +&gpio_sys_rst_odl{ + no-auto-init; +}; + +/* pwr-slp-s0-l */ +&gpio_sys_slp_s0ix_3v3_l{ + no-auto-init; +}; + +/* pwr-slp-s3-l */ +&gpio_slp_s3_ls_l{ + no-auto-init; +}; + +/* pwr-all-sys-pwrgd */ +&gpio_seq_ec_all_sys_pg{ + no-auto-init; +}; + diff --git a/zephyr/projects/rex/prj.conf b/zephyr/projects/rex/prj.conf new file mode 100644 index 0000000000..7dcb2894da --- /dev/null +++ b/zephyr/projects/rex/prj.conf @@ -0,0 +1,180 @@ +# Copyright 2022 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +CONFIG_PLATFORM_EC=y +CONFIG_CROS_EC=y +CONFIG_SHIMMED_TASKS=y +CONFIG_SYSCON=y +# Enable during development +CONFIG_LTO=n +CONFIG_PLATFORM_EC_SYSTEM_UNLOCKED=y +CONFIG_PLATFORM_EC_BOARD_RESET_AFTER_POWER_ON=y + +# Shell Commands +CONFIG_SHELL_HELP=y +CONFIG_SHELL_HISTORY=y +CONFIG_SHELL_TAB=y +CONFIG_SHELL_TAB_AUTOCOMPLETION=y +CONFIG_KERNEL_SHELL=y + +# Logging +CONFIG_LOG=y +CONFIG_LOG_MODE_MINIMAL=y + +# Disable default features we don't want in a minimal example. +CONFIG_PLATFORM_EC_BACKLIGHT_LID=y +CONFIG_PLATFORM_EC_SWITCH=y +CONFIG_PLATFORM_EC_VBOOT_EFS2=y + +# Application processor; communicates with EC via eSPI +CONFIG_AP=y +CONFIG_ESPI=y +CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S3=y +CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S4=y +CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S5=y +CONFIG_PLATFORM_EC_HOSTCMD=y +# Disabling this until temp sensor support is in +CONFIG_PLATFORM_EC_THROTTLE_AP=n +CONFIG_PLATFORM_EC_PORT80=y + +# Power Sequecing +CONFIG_AP_X86_INTEL_MTL=y +CONFIG_X86_NON_DSX_PWRSEQ_MTL=y +CONFIG_X86_NON_DSX_PWRSEQ_HOST_CMD=y +# TODO (b/240434243): This may be needed, but using eSPI VW for now +CONFIG_PLATFORM_EC_POWERSEQ_SLP_S3_L_OVERRIDE=n +CONFIG_PLATFORM_EC_POWERSEQ_PP5000_CONTROL=n + +# Zephyr Inbuilt AP Power Sequencing Config +CONFIG_AP_PWRSEQ=y +CONFIG_X86_NON_DSX_PWRSEQ_CONSOLE=y +CONFIG_AP_PWRSEQ_S0IX=y + +# ADC +CONFIG_ADC=y + +# I2C +CONFIG_I2C=y +CONFIG_PLATFORM_EC_HOSTCMD_I2C_CONTROL=y + +# PWM +CONFIG_PWM=y + +# Fan +CONFIG_TACH_NPCX=y + +# Temperature sensors +CONFIG_SENSOR=y +CONFIG_PLATFORM_EC_TEMP_SENSOR=y +CONFIG_PLATFORM_EC_THERMISTOR=y +CONFIG_PLATFORM_EC_TEMP_SENSOR_POWER=y + +# CBI EEPROM support +CONFIG_EEPROM=y +CONFIG_EEPROM_AT24=y +CONFIG_EEPROM_SHELL=n +CONFIG_PLATFORM_EC_CBI_EEPROM=y +CONFIG_PLATFORM_EC_BOARD_VERSION_CBI=y +CONFIG_PLATFORM_EC_BYPASS_CBI_EEPROM_WP_CHECK=y + +# LED +CONFIG_PLATFORM_EC_LED_DT=y + +# Battery +CONFIG_PLATFORM_EC_BATTERY=y +CONFIG_PLATFORM_EC_BATTERY_SMART=y +CONFIG_PLATFORM_EC_BATTERY_FUEL_GAUGE=y +CONFIG_PLATFORM_EC_BATTERY_CUT_OFF=y +CONFIG_PLATFORM_EC_BATTERY_PRESENT_GPIO=y +CONFIG_PLATFORM_EC_BATTERY_REVIVE_DISCONNECT=y + +# Charger +CONFIG_PLATFORM_EC_CHARGER_DISCHARGE_ON_AC=y +CONFIG_PLATFORM_EC_CHARGER_INPUT_CURRENT=512 +CONFIG_PLATFORM_EC_CHARGER_ISL9241=y +CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR=5 +CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR_AC=10 +CONFIG_PLATFORM_EC_CHARGER_MIN_POWER_MW_FOR_POWER_ON=30000 +CONFIG_PLATFORM_EC_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT=15000 + +# USB-A +CONFIG_PLATFORM_EC_USBA=y + +# USBC +CONFIG_PLATFORM_EC_USBC_PPC=y +CONFIG_PLATFORM_EC_USBC_PPC_NX20P3483=y +CONFIG_PLATFORM_EC_USBC_PPC_SYV682X=y +CONFIG_PLATFORM_EC_USBC_PPC_SYV682C=y +CONFIG_PLATFORM_EC_USBC_PPC_SYV682X_SMART_DISCHARGE=y +CONFIG_PLATFORM_EC_USBC_RETIMER_INTEL_HB=y +CONFIG_PLATFORM_EC_USBC_VCONN=y + +CONFIG_PLATFORM_EC_USB_DRP_ACC_TRYSRC=y +CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_TCPC=y +CONFIG_PLATFORM_EC_USB_PD_DISCHARGE_PPC=y +CONFIG_PLATFORM_EC_USB_PD_FRS=y +CONFIG_PLATFORM_EC_USB_PD_FRS_PPC=y +CONFIG_PLATFORM_EC_USB_PD_REV30=y +CONFIG_PLATFORM_EC_USB_PD_TCPC_LOW_POWER=y +CONFIG_PLATFORM_EC_USB_PD_TCPM_TCPCI=y +CONFIG_PLATFORM_EC_USB_PD_TCPM_NCT38XX=y +CONFIG_PLATFORM_EC_USB_PD_TCPM_PS8815=y +CONFIG_PLATFORM_EC_USB_PD_TRY_SRC=y +CONFIG_PLATFORM_EC_USB_PD_DUAL_ROLE_AUTO_TOGGLE=y +CONFIG_PLATFORM_EC_USB_PD_TBT_COMPAT_MODE=y +CONFIG_PLATFORM_EC_USB_PD_USB32_DRD=y +CONFIG_PLATFORM_EC_USB_PD_USB4=y +CONFIG_PLATFORM_EC_USB_PD_VBUS_MEASURE_CHARGER=y +CONFIG_PLATFORM_EC_USB_PID=0x504D + +# IOEX +CONFIG_GPIO_NCT38XX=y + +# BC 1.2 +CONFIG_PLATFORM_EC_BC12_DETECT_PI3USB9201=y + +#USB Mux +CONFIG_PLATFORM_EC_USB_MUX_VIRTUAL=y +CONFIG_PLATFORM_EC_USB_MUX_TASK=y + +# External power +CONFIG_PLATFORM_EC_EXTPOWER_GPIO=y + +# Standard shimmed features +CONFIG_PLATFORM_EC_POWER_BUTTON=y +CONFIG_PLATFORM_EC_LID_SWITCH=y + +# Keyboard support +CONFIG_PLATFORM_EC_KEYBOARD=y +CONFIG_PLATFORM_EC_KEYBOARD_PROTOCOL_8042=y +# Column 2 is driven through the GSC, which inverts the signal going through it +CONFIG_PLATFORM_EC_KEYBOARD_COL2_INVERTED=y + +# MKBP event +CONFIG_PLATFORM_EC_MKBP_EVENT=y +CONFIG_PLATFORM_EC_MKBP_INPUT_DEVICES=y +CONFIG_PLATFORM_EC_MKBP_USE_GPIO_AND_HOST_EVENT=y + +# Sensors console command +CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCELS=y +CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCEL_INFO=y +CONFIG_PLATFORM_EC_CONSOLE_CMD_I2C_SPEED=y + +# Sensors +CONFIG_SENSOR=y +CONFIG_SENSOR_SHELL=n +CONFIG_PLATFORM_EC_MOTIONSENSE=y +CONFIG_PLATFORM_EC_ACCEL_FIFO=y +CONFIG_PLATFORM_EC_DYNAMIC_MOTION_SENSOR_COUNT=y +CONFIG_PLATFORM_EC_GMR_TABLET_MODE=y +CONFIG_PLATFORM_EC_LID_ANGLE=y +CONFIG_PLATFORM_EC_LID_ANGLE_UPDATE=y +CONFIG_PLATFORM_EC_SENSOR_TIGHT_TIMESTAMPS=y +CONFIG_PLATFORM_EC_TABLET_MODE=y +CONFIG_PLATFORM_EC_TABLET_MODE_SWITCH=y + +# Sensor Drivers +CONFIG_PLATFORM_EC_ACCELGYRO_LSM6DSO=y +CONFIG_PLATFORM_EC_ACCEL_LIS2DW12=y +CONFIG_PLATFORM_EC_ALS_TCS3400=y diff --git a/zephyr/projects/rex/prj_rex.conf b/zephyr/projects/rex/prj_rex.conf new file mode 100644 index 0000000000..0f204b9669 --- /dev/null +++ b/zephyr/projects/rex/prj_rex.conf @@ -0,0 +1,9 @@ +# Copyright 2022 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +# Rex reference-board-specific Kconfig settings. +CONFIG_BOARD_REX=y + +# Keyboard +CONFIG_CROS_KB_RAW_NPCX=y diff --git a/zephyr/projects/rex/rex.dts b/zephyr/projects/rex/rex.dts new file mode 100644 index 0000000000..0db4b96aa7 --- /dev/null +++ b/zephyr/projects/rex/rex.dts @@ -0,0 +1,262 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + + #include <dt-bindings/usb_pd_tcpm.h> + +/ { + aliases { + gpio-wp = &ec_wp_l; + gpio-kbd-kso2 = &gpio_ec_kso_02_inv; + }; + + named-gpios { + compatible = "named-gpios"; + + ec_wp_l: write-protect { + gpios = <&gpioa 0 GPIO_INPUT>; + }; + gpio_ec_entering_rw: ec_entering_rw { + enum-name = "GPIO_ENTERING_RW"; + }; + + ioex_usb_c0_sbu_fault_odl: usb_c0_sbu_fault_odl { + gpios = <&ioex_c0_port1 2 GPIO_INPUT>; + }; + ioex_usb_c0_rt_rst_ls_l: usb_c0_rt_rst_ls_l { + gpios = <&ioex_c0_port0 7 GPIO_OUTPUT>; + }; + + ioex_usb_c0_frs_en: usb_c0_frs_en { + gpios = <&ioex_c0_port0 6 GPIO_OUTPUT_LOW>; + }; + + /* Need to designate 1.8V for I2C buses on the 1800mV rail */ + ec-i2c-sensor-scl { + gpios = <&gpiob 5 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; + }; + ec-i2c-sensor-sda { + gpios = <&gpiob 4 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; + }; + ec-i2c-c0-rt-scl { + gpios = <&gpiod 1 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; + }; + ec-i2c-c0-rt-sda { + gpios = <&gpiod 0 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; + }; + }; + + usba-port-enable-list { + compatible = "cros-ec,usba-port-enable-pins"; + enable-pins = <&gpio_en_pp5000_usba_r>; + }; +}; + +/* host interface */ +&espi0 { + status = "okay"; + pinctrl-0 = <&espi_lpc_gp46_47_51_52_53_54_55_57>; + pinctrl-names = "default"; +}; + +/* Power switch logic input pads */ +&psl_in1_gpd2 { + /* LID_OPEN */ + psl-in-mode = "edge"; + psl-in-pol = "high-rising"; +}; + +&psl_in2_gp00 { + /* ACOK_OD */ + psl-in-mode = "edge"; + psl-in-pol = "high-rising"; +}; + +&psl_in4_gp02 { + /* MECH_PWR_BTN_ODL */ + psl-in-mode = "edge"; + psl-in-pol = "low-falling"; +}; + +/* Power domain device controlled by PSL (Power Switch Logic) IO pads */ +&power_ctrl_psl { + status = "okay"; + pinctrl-names = "sleep"; + pinctrl-0 = <&psl_in1_gpd2 &psl_in2_gp00 &psl_in3_gp01 &psl_in4_gp02>; +}; + +/* ADC and GPIO alt-function specifications */ +&adc0 { + pinctrl-0 = <&adc0_chan0_gp45 + &adc0_chan1_gp44 + &adc0_chan8_gpf1 + &adc0_chan7_gpe1>; + pinctrl-names = "default"; +}; + +&i2c0_0 { + label = "I2C_SENSOR"; + clock-frequency = <I2C_BITRATE_FAST>; + + pinctrl-0 = <&i2c0_0_sda_scl_gpb4_b5>; + pinctrl-names = "default"; +}; + +&i2c1_0 { + label = "I2C_USB_C0_TCPC"; + clock-frequency = <I2C_BITRATE_FAST>; + + pinctrl-0 = <&i2c1_0_sda_scl_gp87_90>; + pinctrl-names = "default"; + + tcpc_port0: nct38xx@70 { + compatible = "nuvoton,nct38xx"; + gpio-dev = <&nct3807_C0>; + reg = <0x70>; + tcpc-flags = <(TCPC_FLAGS_TCPCI_REV2_0)>; + }; + + nct3807_C0:nct3807_C0@70 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nuvoton,nct38xx-gpio"; + reg = <0x70>; + label = "NCT3807_C0"; + + ioex_c0_port0:gpio@0 { + compatible = "nuvoton,nct38xx-gpio-port"; + reg = <0x0>; + label = "NCT3807_C0_GPIO0"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + pin_mask = <0xff>; + pinmux_mask = <0xf7>; + }; + ioex_c0_port1:gpio@1 { + compatible = "nuvoton,nct38xx-gpio-port"; + reg = <0x1>; + label = "NCT3807_C0_GPIO1"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + pin_mask = <0xff>; + }; + }; + + nct3808_alert_0 { + compatible = "nuvoton,nct38xx-gpio-alert"; + irq-gpios = <&gpioe 0 GPIO_ACTIVE_LOW>; + nct38xx-dev = <&nct3807_C0>; + label = "NCT3807_ALERT_0"; + }; +}; + +&i2c2_0 { + label = "I2C_PPC0"; + clock-frequency = <I2C_BITRATE_FAST>; + + pinctrl-0 = <&i2c2_0_sda_scl_gp91_92>; + pinctrl-names = "default"; + + bc12_port0: pi3usb9201@5f { + compatible = "pericom,pi3usb9201"; + status = "okay"; + reg = <0x5f>; + irq = <&int_usb_c0_bc12>; + }; + + ppc_port0_syv: ppc_syv@40 { + compatible = "silergy,syv682x"; + status = "okay"; + reg = <0x40>; + frs_en_gpio = <&ioex_usb_c0_frs_en>; + }; +}; + +&i2c3_0 { + label = "I2C_USB_C0_RT"; + clock-frequency = <I2C_BITRATE_FAST>; + + pinctrl-0 = <&i2c3_0_sda_scl_gpd0_d1>; + pinctrl-names = "default"; + + usb_c0_hb_retimer: jhl8040r-c0@56 { + compatible = "intel,jhl8040r"; + reg = <0x56>; + ls-en-pin = <&gpio_usb_c0_rt_3p3_sx_en>; + int-pin = <&gpio_usb_c0_rt_int_odl>; + reset-pin = <&ioex_usb_c0_rt_rst_ls_l>; + }; +}; + +&i2c4_1 { + label = "I2_USB_C1_TCPC"; + clock-frequency = <I2C_BITRATE_FAST>; + + pinctrl-0 = <&i2c4_1_sda_scl_gpf2_f3>; + pinctrl-names = "default"; + + tcpc_port1: ps8xxx@b { + compatible = "parade,ps8xxx"; + reg = <0xb>; + tcpc-flags = <( + TCPC_FLAGS_TCPCI_REV2_0 | + TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V | + TCPC_FLAGS_CONTROL_VCONN | + TCPC_FLAGS_CONTROL_FRS)>; + }; +}; + +&i2c5_0 { + label = "I2C__BATTERY"; + clock-frequency = <I2C_BITRATE_STANDARD>; + + pinctrl-0 = <&i2c5_0_sda_scl_gp33_36>; + pinctrl-names = "default"; +}; + +&i2c6_1 { + label = "I2C_USB_1_MIX"; + clock-frequency = <I2C_BITRATE_FAST>; + + pinctrl-0 = <&i2c6_1_sda_scl_gpe3_e4>; + pinctrl-names = "default"; + + bc12_port1: pi3usb9201@5f { + compatible = "pericom,pi3usb9201"; + status = "okay"; + reg = <0x5f>; + irq = <&int_usb_c1_bc12>; + }; + + ppc_port1_nxp: nx20p348x@72 { + compatible = "nxp,nx20p348x"; + status = "okay"; + reg = <0x72>; + }; +}; + +&i2c7_0 { + label = "I2C_CHARGER"; + clock-frequency = <I2C_BITRATE_FAST>; + + pinctrl-0 = <&i2c7_0_sda_scl_gpb2_b3>; + pinctrl-names = "default"; + + cbi_eeprom: eeprom@50 { + compatible = "atmel,at24"; + reg = <0x50>; + size = <2048>; + pagesize = <16>; + address-width = <8>; + timeout = <5>; + }; + + charger: isl9241@9 { + compatible = "intersil,isl9241"; + status = "okay"; + reg = <0x09>; + }; +}; diff --git a/zephyr/projects/rex/rex0_gpio.csv b/zephyr/projects/rex/rex0_gpio.csv new file mode 100644 index 0000000000..5c20f6fb00 --- /dev/null +++ b/zephyr/projects/rex/rex0_gpio.csv @@ -0,0 +1,122 @@ +Signal Name,Pin Number,Type,Enum +USB_C1_BC12_INT_ODL,G10,INPUT,GPIO_USB_C1_BC12_INT_ODL +ESPI_SOC_CS0_L,L2,OTHER, +ESPI_SOC_RESET_L,K3,OTHER, +ESPI_SOC_CLK,M1,OTHER, +EC_IMU_INT_R_L,M2,INPUT_PU, +ESPI_SOC_IO0,H1,OTHER, +ESPI_SOC_IO1,J1,OTHER, +ESPI_SOC_IO2,K1,OTHER, +ESPI_SOC_IO3,L1,OTHER, +ESPI_SOC_ALERT_L_R,L3,OTHER, +EC_VOLDN_BTN_ODL,E11,INPUT_PU,GPIO_VOLUME_DOWN_L +TABLET_MODE_L,M12,INPUT_PU,GPIO_TABLET_MODE_L +SOCHOT_ODL,G12,INPUT, +EC_VOLUP_BTN_ODL,L10,INPUT_PU,GPIO_VOLUME_UP_L +USB_C0_RT_INT_ODL,G11,INPUT, +EC_WP_L,L12,INPUT, +EC_BATT_PRES_ODL,K12,INPUT,GPIO_BATT_PRES_ODL +CPU_C10_GATE_L,J11,INPUT, +SOC_PWROK,K11,OUTPUT, +EC_SOC_RSMRST_L,F11,OUTPUT, +SYS_PWROK,L11,OUTPUT, +EC_SPARE_GPIO94,M11,OUTPUT, +EC_SPARE_GPIOA2,F12,OUTPUT, +EC_SPARE_GPIOA4,H11,OUTPUT, +EC_ACCEL_INT_R_L,M7,INPUT, +SLP_S3_LS_L,C2,INPUT, +IMVP92_VRRDY_OD,E2,INPUT, +EC_PROCHOT_IN_L,D2,INPUT, +EC_SPARE_GPIO42,D3,OUTPUT, +TEMP_SENSOR_2,E3,ADC,ADC_TEMP_SENSOR_2 +TEMP_SENSOR_1,F2,ADC,ADC_TEMP_SENSOR_1 +TEMP_SENSOR_4,F3,ADC,ADC_TEMP_SENSOR_4 +TEMP_SENSOR_3,G3,ADC,ADC_TEMP_SENSOR_3 +SYS_RST_ODL,H7,INPUT, +EC_SOC_WAKE_R_ODL,H8,OUTPUT_ODL, +EC_PROCHOT_ODL,J2,OUTPUT_ODR, +EC_SOC_INT_ODL,J4,OUTPUT_ODL,GPIO_EC_INT_L +EC_SOC_RTCRST,J5,OUTPUT_ODR, +EC_SOC_PWR_BTN_ODL,H9,OUTPUT_ODL,GPIO_PCH_PWRBTN_L +USB_C0_RT_3P3_SX_EN,D9,OUTPUT_ODR, +KSO_13,D11,OTHER, +KSO_12,C11,OTHER, +KSO_11,B10,OTHER, +KSO_10,B11,OTHER, +KSO_09,C10,OTHER, +KSO_08,C9,OTHER, +KSO_05,C6,OTHER, +KSO_04,C7,OTHER, +KSO_03,B8,OTHER, +EC_KSO_02_INV,B7,OUTPUT_L, +KSO_01,B6,OTHER, +KSO_00,B5,OTHER, +KSI_07,C5,OTHER, +KSI_06,C4,OTHER, +KSI_05,C3,OTHER, +KSI_04,B4,OTHER, +EC_KSI_03,B3,OTHER, +EC_KSI_02,A4,OTHER, +KSI_01,A3,OTHER, +EC_KSI_00,A2,OTHER, +EC_I2C_BAT_SCL,D5,I2C_CLOCK,I2C_PORT_BATTERY +USB_C1_TCPC_INT_ODL,B2,INPUT,GPIO_USB_C1_TCPC_INT_ODL +EC_I2C_BAT_SDA,D4,I2C_DATA, +USB_C1_RST_ODL,C1,OUTPUT_ODL, +EC_FAN_TACH,E5,TACH, +LED_4_L,G6,OUTPUT, +EN_PP5000_FAN,K4,OUTPUT_ODR, +USB_C0_PPC_INT_ODL,H2,INPUT,GPIO_USB_C0_PPC_INT_ODL +UART_GSC_DBG_TX_EC_RX_R,G4,OTHER, +EC_SPARE_GPIO66,G2,OUTPUT, +USB_C0_TCPC_RST_ODL,J3,OUTPUT_ODL, +USB_C1_RT_INT_ODL,M4,INPUT_PU, +EC_CBI_WP,G5,OUTPUT, +USB_C1_RT_RST_R_ODL,H5,OUTPUT_ODL, +EC_GSC_PACKET_MODE,J6,OUTPUT_ODR,GPIO_PACKET_MODE_EN +EC_KB_BL_PWM,K5,PWM,GPIO_EN_KEYBOARD_BACKLIGHT +KSO_14,D6,OTHER, +USB_C1_FRS_EN,D7,OUTPUT_ODR, +EC_I2C_USB_C0_TCPC_SDA,K7,I2C_DATA, +EC_I2C_USB_C0_TCPC_SCL,K8,I2C_CLOCK,I2C_PORT_USB_C0_TCPC +EC_I2C_USB_C0_PPC_BC_SDA,K9,I2C_DATA, +EC_I2C_USB_C0_PPC_BC_SCL,L8,I2C_CLOCK,I2C_PORT_PPC0 +EC_IMVP92_EN_SMB,D8,OUTPUT, +EC_I2C_MISC_SDA,K10,I2C_DATA, +EC_I2C_MISC_SCL,J10,I2C_CLOCK,I2C_PORT_EEPROM +EC_I2C_SENSOR_SDA,B12,I2C_DATA, +EC_I2C_SENSOR_SCL,C12,I2C_CLOCK,I2C_PORT_SENSOR +EN_S5_RAILS,L9,OUTPUT_ODR, +FAN_PWM,J7,PWM, +LED_3_L,H10,OUTPUT, +LED_2_L,G9,OUTPUT, +LED_1_L,G8,OUTPUT, +USB_C0_BC12_INT_ODL,D10,INPUT,GPIO_USB_C0_BC12_INT_ODL +EC_SPARE_GPIOC7,F10,OUTPUT, +EC_I2C_USB_C0_RT_SDA,F9,I2C_DATA, +EC_I2C_USB_C0_RT_SCL,F8,I2C_CLOCK,I2C_PORT_USB_C0_RT +EC_EDP_BL_EN,E10,OUTPUT_ODR,GPIO_ENABLE_BACKLIGHT +EC_ALS_RGB_INT_R_L,A9,INPUT_PU, +SYS_SLP_S0IX_3V3_L,A10,INPUT, +USB_C0_TCPC_INT_ODL,F4,INPUT,GPIO_USB_C0_TCPC_INT_ODL +SEQ_EC_RSMRST_ODL,A11,INPUT, +EC_I2C_USB_C1_MIX_SDA,L7,I2C_DATA, +EC_I2C_USB_C1_MIX_SCL,L6,I2C_CLOCK,I2C_PORT_USB_1_MIX +CCD_MODE_ODL,A12,OUTPUT_ODL,GPIO_CCD_MODE_ODL +EC_I2C_USB_C1_TCPC_SDA,F6,I2C_DATA, +EC_I2C_USB_C1_TCPC_SCL,F5,I2C_CLOCK,I2C_PORT_USB_C1_TCPC +SEQ_EC_ALL_SYS_PG,E9,INPUT, +USB_C1_PPC_INT_ODL,E8,INPUT,GPIO_USB_C1_PPC_INT_ODL +EC_KSO_07_JEN_L,B9,OTHER, +EC_KSO_06_GP_SEL_L,C8,OTHER, +EC_SPARE_GPO32,E4,OUTPUT, +EC_SPARE_GPO35,K2,OUTPUT, +UART_GSC_DBG_RX_EC_TX_R,H4,OTHER, +EC_RST_R_ODL,K6,INPUT, +EC_KB_BL_EN_L,J9,OUTPUT, +ACOK_OD,E7,INPUT,GPIO_AC_PRESENT +GSC_EC_PWR_BTN_ODL,E6,INPUT_PU,GPIO_POWER_BUTTON_L +MECH_PWR_BTN_ODL,F7,INPUT, +LID_OPEN,G7,INPUT_PU,GPIO_LID_OPEN +EN_Z1_RAILS,J8,OUTPUT, +EN_PP5000_USBA_R,H6,OUTPUT, diff --git a/zephyr/projects/rex/src/board_power.c b/zephyr/projects/rex/src/board_power.c new file mode 100644 index 0000000000..c7f12d024e --- /dev/null +++ b/zephyr/projects/rex/src/board_power.c @@ -0,0 +1,61 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <zephyr/logging/log.h> +#include <zephyr/drivers/gpio.h> + +#include <ap_power/ap_power.h> +#include <ap_power/ap_power_events.h> +#include <ap_power/ap_power_interface.h> +#include <ap_power_override_functions.h> +#include <power_signals.h> +#include <x86_power_signals.h> + +#include "gpio_signal.h" +#include "gpio/gpio.h" + +LOG_MODULE_DECLARE(ap_pwrseq, LOG_LEVEL_INF); + +#if CONFIG_X86_NON_DSX_PWRSEQ_MTL +#define X86_NON_DSX_MTL_FORCE_SHUTDOWN_TO_MS 50 + +void board_ap_power_force_shutdown(void) +{ + int timeout_ms = X86_NON_DSX_MTL_FORCE_SHUTDOWN_TO_MS; + + /* Turn off PCH_RMSRST to meet tPCH12 */ + power_signal_set(PWR_EC_PCH_RSMRST, 0); + + /* Turn off PRIM load switch. */ + power_signal_set(PWR_EN_PP3300_A, 0); + + /* Wait RSMRST to be off. */ + while (power_signal_get(PWR_RSMRST) && (timeout_ms > 0)) { + k_msleep(1); + timeout_ms--; + }; + + if (power_signal_get(PWR_RSMRST)) { + LOG_WRN("RSMRST_ODL didn't go low! Assuming G3."); + } +} + +void board_ap_power_action_g3_s5(void) +{ + /* Turn on the PP3300_PRIM rail. */ + power_signal_set(PWR_EN_PP3300_A, 1); + + if (!power_wait_signals_timeout( + IN_PGOOD_ALL_CORE, + AP_PWRSEQ_DT_VALUE(wait_signal_timeout))) { + ap_power_ev_send_callbacks(AP_POWER_PRE_INIT); + } +} + +bool board_ap_power_check_power_rails_enabled(void) +{ + return power_signal_get(PWR_EN_PP3300_A); +} +#endif /* CONFIG_X86_NON_DSX_PWRSEQ_MTL */ diff --git a/zephyr/projects/rex/src/usb_pd_policy.c b/zephyr/projects/rex/src/usb_pd_policy.c new file mode 100644 index 0000000000..7e9876f9c1 --- /dev/null +++ b/zephyr/projects/rex/src/usb_pd_policy.c @@ -0,0 +1,77 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Shared USB-C policy for Rex boards */ + +#include <zephyr/drivers/gpio.h> + +#include "charge_manager.h" +#include "chipset.h" +#include "common.h" +#include "compile_time_macros.h" +#include "console.h" +#include "ec_commands.h" +#include "ioexpander.h" +#include "system.h" +#include "usb_mux.h" +#include "usb_pd.h" +#include "usbc_ppc.h" +#include "util.h" + +int pd_check_vconn_swap(int port) +{ + /* Allow VCONN swaps if the AP is on. */ + return chipset_in_state(CHIPSET_STATE_ANY_SUSPEND | CHIPSET_STATE_ON); +} + +void pd_power_supply_reset(int port) +{ + /* Disable VBUS. */ + ppc_vbus_source_enable(port, 0); + + /* Enable discharge if we were previously sourcing 5V */ + if (IS_ENABLED(CONFIG_USB_PD_DISCHARGE)) + pd_set_vbus_discharge(port, 1); + + /* Notify host of power info change. */ + pd_send_host_event(PD_EVENT_POWER_CHANGE); +} + +int pd_set_power_supply_ready(int port) +{ + int rv; + + /* Disable charging. */ + rv = ppc_vbus_sink_enable(port, 0); + if (rv) + return rv; + + if (IS_ENABLED(CONFIG_USB_PD_DISCHARGE)) { + pd_set_vbus_discharge(port, 0); + } + + /* Provide Vbus. */ + rv = ppc_vbus_source_enable(port, 1); + if (rv) { + return rv; + } + + /* Notify host of power info change. */ + pd_send_host_event(PD_EVENT_POWER_CHANGE); + + return EC_SUCCESS; +} + +/* Used by Vbus discharge common code with CONFIG_USB_PD_DISCHARGE */ +int board_vbus_source_enabled(int port) +{ + return tcpm_get_src_ctrl(port); +} + +/* Used by USB charger task with CONFIG_USB_PD_5V_EN_CUSTOM */ +int board_is_sourcing_vbus(int port) +{ + return board_vbus_source_enabled(port); +} diff --git a/zephyr/projects/rex/src/usbc_config.c b/zephyr/projects/rex/src/usbc_config.c new file mode 100644 index 0000000000..66f3a1f45d --- /dev/null +++ b/zephyr/projects/rex/src/usbc_config.c @@ -0,0 +1,300 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <zephyr/drivers/gpio.h> + +#include "battery_fuel_gauge.h" +#include "charger.h" +#include "charge_manager.h" +#include "charge_ramp.h" +#include "charge_state_v2.h" +#include "charge_state.h" +#include "charger.h" +#include "driver/charger/isl9241.h" +#include "driver/retimer/bb_retimer_public.h" +#include "driver/tcpm/nct38xx.h" +#include "driver/tcpm/ps8xxx_public.h" +#include "driver/tcpm/tcpci.h" +#include "gpio/gpio_int.h" +#include "hooks.h" +#include "i2c.h" +#include "ioexpander.h" +#include "driver/ppc/nx20p348x.h" +#include "ppc/syv682x_public.h" +#include "system.h" +#include "task.h" +#include "usb_mux.h" +#include "usbc_ppc.h" + +#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args) + +/*******************************************************************/ +/* USB-C Configuration Start */ + +/* USB-C ports */ +enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT }; +BUILD_ASSERT(USBC_PORT_COUNT == CONFIG_USB_PD_PORT_MAX_COUNT); + +static void usbc_interrupt_init(void) +{ + /* Only reset TCPC if not sysjump */ + if (!system_jumped_late()) { + board_reset_pd_mcu(); + } + + /* Enable PPC interrupts. */ + gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0_ppc)); + gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c1_ppc)); + + /* Enable TCPC interrupts. */ + gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0_tcpc)); + gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c1_tcpc)); + + /* Enable BC 1.2 interrupts */ + gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0_bc12)); + gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c1_bc12)); + + /* Enable SBU fault interrupts */ + gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0_sbu_fault)); +} +DECLARE_HOOK(HOOK_INIT, usbc_interrupt_init, HOOK_PRIO_POST_I2C); + +void board_overcurrent_event(int port, int is_overcurrented) +{ + /* + * TODO: Meteorlake PCH does not use Physical GPIO for over current + * error, hence Send 'Over Current Virtual Wire' eSPI signal. + */ +} + +void sbu_fault_interrupt(enum gpio_signal signal) +{ + int port = USBC_PORT_C0; + + CPRINTSUSB("C%d: SBU fault", port); + pd_handle_overcurrent(port); +} + +void tcpc_alert_event(enum gpio_signal signal) +{ + int port; + + switch (signal) { + case GPIO_USB_C0_TCPC_INT_ODL: + port = 0; + break; + case GPIO_USB_C1_TCPC_INT_ODL: + port = 1; + break; + default: + return; + } + + schedule_deferred_pd_interrupt(port); +} + +static void reset_nct38xx_port(int port) +{ + const struct gpio_dt_spec *reset_gpio_l; + const struct device *ioex_port0, *ioex_port1; + + /* TODO(b/225189538): Save and restore ioex signals */ + if (port == USBC_PORT_C0) { + reset_gpio_l = GPIO_DT_FROM_NODELABEL(gpio_usb_c0_tcpc_rst_odl); + ioex_port0 = DEVICE_DT_GET(DT_NODELABEL(ioex_c0_port0)); + ioex_port1 = DEVICE_DT_GET(DT_NODELABEL(ioex_c0_port1)); + } else { + /* Invalid port: do nothing */ + return; + } + + gpio_pin_set_dt(reset_gpio_l, 0); + msleep(NCT38XX_RESET_HOLD_DELAY_MS); + gpio_pin_set_dt(reset_gpio_l, 1); + nct38xx_reset_notify(port); + if (NCT3807_RESET_POST_DELAY_MS != 0) { + msleep(NCT3807_RESET_POST_DELAY_MS); + } + + /* Re-enable the IO expander pins */ + gpio_reset_port(ioex_port0); + gpio_reset_port(ioex_port1); +} + +void board_reset_pd_mcu(void) +{ + /* Reset TCPC0 */ + reset_nct38xx_port(USBC_PORT_C0); + + /* Reset TCPC1 */ + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_c1_rt_rst_r_odl), 0); + msleep(PS8XXX_RESET_DELAY_MS); + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_c1_rt_rst_r_odl), 1); + msleep(PS8815_FW_INIT_DELAY_MS); +} + +uint16_t tcpc_get_alert_status(void) +{ + uint16_t status = 0; + const struct gpio_dt_spec *tcpc_c0_rst_l; + const struct gpio_dt_spec *tcpc_c0_int_l; + const struct gpio_dt_spec *tcpc_c1_rst_l; + const struct gpio_dt_spec *tcpc_c1_int_l; + + tcpc_c0_rst_l = GPIO_DT_FROM_NODELABEL(gpio_usb_c0_tcpc_rst_odl); + tcpc_c0_int_l = GPIO_DT_FROM_NODELABEL(gpio_usb_c0_tcpc_int_odl); + + tcpc_c1_rst_l = GPIO_DT_FROM_NODELABEL(gpio_usb_c1_rt_rst_r_odl); + tcpc_c1_int_l = GPIO_DT_FROM_NODELABEL(gpio_usb_c1_tcpc_int_odl); + + /* + * Check which port has the ALERT line set and ignore if that TCPC has + * its reset line active. + */ + if (!gpio_pin_get_dt(tcpc_c0_int_l) && gpio_pin_get_dt(tcpc_c0_rst_l)) { + status |= PD_STATUS_TCPC_ALERT_0; + } + + if (!gpio_pin_get_dt(tcpc_c1_int_l) && gpio_pin_get_dt(tcpc_c1_rst_l)) { + status |= PD_STATUS_TCPC_ALERT_1; + } + + return status; +} + +void ppc_interrupt(enum gpio_signal signal) +{ + switch (signal) { + case GPIO_USB_C0_PPC_INT_ODL: + syv682x_interrupt(USBC_PORT_C0); + break; + case GPIO_USB_C1_PPC_INT_ODL: + nx20p348x_interrupt(USBC_PORT_C1); + break; + default: + break; + } +} + +void bc12_interrupt(enum gpio_signal signal) +{ + switch (signal) { + case GPIO_USB_C0_BC12_INT_ODL: + usb_charger_task_set_event(0, USB_CHG_EVENT_BC12); + break; + case GPIO_USB_C1_BC12_INT_ODL: + usb_charger_task_set_event(1, USB_CHG_EVENT_BC12); + break; + default: + break; + } +} + +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) +{ + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); +} + +static void board_disable_charger_ports(void) +{ + int i; + + CPRINTSUSB("Disabling all charger ports"); + + /* Disable all ports. */ + for (i = 0; i < ppc_cnt; i++) { + /* + * If this port had booted in dead battery mode, go + * ahead and reset it so EN_SNK responds properly. + */ + if (nct38xx_get_boot_type(i) == NCT38XX_BOOT_DEAD_BATTERY) { + reset_nct38xx_port(i); + pd_set_error_recovery(i); + } + + /* + * Do not return early if one fails otherwise we can + * get into a boot loop assertion failure. + */ + if (ppc_vbus_sink_enable(i, 0)) { + CPRINTSUSB("Disabling C%d as sink failed.", i); + } + } +} + +int board_set_active_charge_port(int port) +{ + int is_valid_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT); + int i; + int rv; + + if (port == CHARGE_PORT_NONE) { + board_disable_charger_ports(); + return EC_SUCCESS; + } else if (!is_valid_port) { + return EC_ERROR_INVAL; + } + + /* + * Check if we can reset any ports in dead battery mode + * + * The NCT3807 may continue to keep EN_SNK low on the dead battery port + * and allow a dangerous level of voltage to pass through to the initial + * charge port (see b/183660105). We must reset the ports if we have + * sufficient battery to do so, which will bring EN_SNK back under + * normal control. + */ + rv = EC_SUCCESS; + if (port == USBC_PORT_C0 && + nct38xx_get_boot_type(port) == NCT38XX_BOOT_DEAD_BATTERY) { + /* Handle dead battery boot case */ + CPRINTSUSB("Found dead battery on C0"); + /* + * If we have battery, get this port reset ASAP. + * This means temporarily rejecting charge manager + * sets to it. + */ + if (pd_is_battery_capable()) { + reset_nct38xx_port(port); + pd_set_error_recovery(port); + } + } + + if (rv != EC_SUCCESS) { + return rv; + } + + /* Check if the port is sourcing VBUS. */ + if (tcpm_get_src_ctrl(port)) { + CPRINTSUSB("Skip enable C%d", port); + return EC_ERROR_INVAL; + } + + CPRINTSUSB("New charge port: C%d", port); + + /* + * Turn off the other ports' sink path FETs, before enabling the + * requested charge port. + */ + for (i = 0; i < ppc_cnt; i++) { + if (i == port) { + continue; + } + if (ppc_vbus_sink_enable(i, 0)) { + CPRINTSUSB("C%d: sink path disable failed.", i); + } + } + + /* Enable requested charge port. */ + if (ppc_vbus_sink_enable(port, 1)) { + CPRINTSUSB("C%d: sink path enable failed.", port); + return EC_ERROR_UNKNOWN; + } + + return EC_SUCCESS; +} diff --git a/zephyr/projects/rex/temp_sensors.dts b/zephyr/projects/rex/temp_sensors.dts new file mode 100644 index 0000000000..680ebc8954 --- /dev/null +++ b/zephyr/projects/rex/temp_sensors.dts @@ -0,0 +1,69 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <cros/thermistor/thermistor.dtsi> + +/ { + temp_ddr_soc: ddr_soc { + compatible = "cros-ec,temp-sensor-thermistor"; + thermistor = <&thermistor_3V3_30K9_47K_4050B>; + adc = <&adc_ddr_soc>; + }; + temp_ambient: ambient { + compatible = "cros-ec,temp-sensor-thermistor"; + thermistor = <&thermistor_3V3_30K9_47K_4050B>; + adc = <&adc_ambient>; + }; + temp_charger: charger { + compatible = "cros-ec,temp-sensor-thermistor"; + thermistor = <&thermistor_3V3_30K9_47K_4050B>; + adc = <&adc_charger>; + }; + temp_wwan: wwan { + compatible = "cros-ec,temp-sensor-thermistor"; + thermistor = <&thermistor_3V3_30K9_47K_4050B>; + adc = <&adc_wwan>; + }; + + named-temp-sensors { + compatible = "cros-ec,temp-sensors"; + ddr_soc { + temp_fan_off = <35>; + temp_fan_max = <60>; + temp_host_high = <85>; + temp_host_halt = <90>; + temp_host_release_high = <80>; + sensor = <&temp_ddr_soc>; + }; + ambient { + temp_fan_off = <35>; + temp_fan_max = <60>; + temp_host_high = <85>; + temp_host_halt = <90>; + temp_host_release_high = <80>; + sensor = <&temp_ambient>; + }; + charger { + temp_fan_off = <35>; + temp_fan_max = <65>; + temp_host_high = <105>; + temp_host_halt = <120>; + temp_host_release_high = <90>; + sensor = <&temp_charger>; + }; + wwan { + temp_fan_off = <35>; + temp_fan_max = <60>; + temp_host_high = <130>; + temp_host_halt = <130>; + temp_host_release_high = <100>; + sensor = <&temp_wwan>; + }; + }; +}; + +&thermistor_3V3_30K9_47K_4050B { + status = "okay"; +}; diff --git a/zephyr/projects/rex/usbc.dts b/zephyr/projects/rex/usbc.dts new file mode 100644 index 0000000000..84ae79fae6 --- /dev/null +++ b/zephyr/projects/rex/usbc.dts @@ -0,0 +1,51 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + usbc { + #address-cells = <1>; + #size-cells = <0>; + + usbc_port0: port0@0 { + compatible = "named-usbc-port"; + reg = <0>; + bc12 = <&bc12_port0>; + ppc = <&ppc_port0_syv>; + tcpc = <&tcpc_port0>; + chg = <&charger>; + usb-mux-chain-0 { + compatible = "cros-ec,usb-mux-chain"; + usb-muxes = <&usb_c0_hb_retimer + &virtual_mux_c0>; + }; + }; + port0-muxes { + virtual_mux_c0: virtual-mux-c0 { + compatible = "cros-ec,usbc-mux-virtual"; + }; + }; + + usbc_port1: port1@1 { + compatible = "named-usbc-port"; + reg = <1>; + bc12 = <&bc12_port1>; + ppc = <&ppc_port1_nxp>; + tcpc = <&tcpc_port1>; + usb-mux-chain-1 { + compatible = "cros-ec,usb-mux-chain"; + usb-muxes = <&virtual_mux_c1 &tcpci_mux_c1>; + }; + }; + port1-muxes { + tcpci_mux_c1: tcpci-mux-c1 { + compatible = "cros-ec,usbc-mux-tcpci"; + hpd-update = "ps8xxx_tcpc_update_hpd_status"; + }; + virtual_mux_c1: virtual-mux-c1 { + compatible = "cros-ec,usbc-mux-virtual"; + }; + }; + }; +}; diff --git a/zephyr/projects/skyrim/BUILD.py b/zephyr/projects/skyrim/BUILD.py new file mode 100644 index 0000000000..3807150af9 --- /dev/null +++ b/zephyr/projects/skyrim/BUILD.py @@ -0,0 +1,86 @@ +# Copyright 2021 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +"""Define zmake projects for skyrim.""" + + +def register_skyrim_project( + project_name, + extra_dts_overlays=(), + extra_kconfig_files=(), +): + """Register a variant of skyrim.""" + register_npcx_project( + project_name=project_name, + zephyr_board="npcx9m3f", + dts_overlays=[ + # Common to all projects. + here / "adc.dts", + here / "fan.dts", + here / "gpio.dts", + here / "interrupts.dts", + here / "keyboard.dts", + here / "motionsense.dts", + here / "usbc.dts", + # Project-specific DTS customizations. + *extra_dts_overlays, + ], + kconfig_files=[here / "prj.conf", *extra_kconfig_files], + ) + + +register_skyrim_project( + project_name="morthal", + extra_dts_overlays=[ + here / "morthal.dts", + here / "battery_morthal.dts", + here / "led_pins_morthal.dts", + here / "led_policy_morthal.dts", + ], + extra_kconfig_files=[ + here / "prj_morthal.conf", + ], +) + + +register_skyrim_project( + project_name="skyrim", + extra_dts_overlays=[ + here / "skyrim.dts", + here / "battery_skyrim.dts", + here / "led_pins_skyrim.dts", + here / "led_policy_skyrim.dts", + ], + extra_kconfig_files=[ + here / "prj_skyrim.conf", + ], +) + + +register_skyrim_project( + project_name="winterhold", + extra_dts_overlays=[ + here / "winterhold.dts", + here / "battery_winterhold.dts", + here / "led_pins_winterhold.dts", + here / "led_policy_winterhold.dts", + ], + extra_kconfig_files=[ + here / "prj_winterhold.conf", + ], +) + + +register_skyrim_project( + project_name="frostflow", + extra_dts_overlays=[ + here / "frostflow.dts", + here / "battery_frostflow.dts", + here / "led_pins_frostflow.dts", + here / "led_policy_frostflow.dts", + ], + extra_kconfig_files=[ + here / "prj_frostflow.conf", + ], +) diff --git a/zephyr/projects/skyrim/CMakeLists.txt b/zephyr/projects/skyrim/CMakeLists.txt new file mode 100644 index 0000000000..71b8427aa1 --- /dev/null +++ b/zephyr/projects/skyrim/CMakeLists.txt @@ -0,0 +1,62 @@ +# Copyright 2021 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +cmake_minimum_required(VERSION 3.13.1) + +find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}") + +zephyr_library_sources("src/common.c") +zephyr_library_sources("src/power_signals.c") + +zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC + "src/usb_pd_policy.c" + "src/usbc_config.c") +zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_LED_COMMON + "src/led.c") +zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_AMD_STT + "src/stt.c") + +if(DEFINED CONFIG_BOARD_MORTHAL) + project(morthal) + zephyr_library_sources( + "src/morthal/ppc_config.c" + "src/morthal/usb_mux_config.c" +) +endif() + +if(DEFINED CONFIG_BOARD_SKYRIM) + project(skyrim) + cros_ec_library_include_directories_ifdef(CONFIG_BOARD_SKYRIM include) + zephyr_library_sources( + "src/skyrim/usb_mux_config.c" + "src/skyrim/ppc_config.c" + "src/skyrim/form_factor.c" + "src/skyrim/alt_charger.c" + "src/skyrim/keyboard.c" + ) + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_FAN "src/skyrim/fan.c") +endif() + +if(DEFINED CONFIG_BOARD_WINTERHOLD) + project(winterhold) + zephyr_library_sources( + "src/winterhold/usb_mux_config.c" + "src/winterhold/ppc_config.c" + "src/winterhold/kb_backlight.c" + "src/winterhold/keyboard.c" + ) +endif() + +if(DEFINED CONFIG_BOARD_FROSTFLOW) + project(frostflow) + cros_ec_library_include_directories_ifdef(CONFIG_BOARD_FROSTFLOW include) + zephyr_include_directories("include/frostflow") + zephyr_library_sources( + "src/frostflow/usb_mux_config.c" + "src/frostflow/ppc_config.c" + ) + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_KEYBOARD_CUSTOMIZATION + "src/frostflow/keyboard.c" + "src/frostflow/keyboard_customization.c") +endif() diff --git a/zephyr/projects/skyrim/Kconfig b/zephyr/projects/skyrim/Kconfig new file mode 100644 index 0000000000..fbb797f6fc --- /dev/null +++ b/zephyr/projects/skyrim/Kconfig @@ -0,0 +1,46 @@ +# Copyright 2021 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +config BOARD_MORTHAL + bool "Google Morthal Board" + help + Build Google Morthal reference board. This board uses an AMD SoC + and NPCX9 EC + +config BOARD_SKYRIM + bool "Google Skyrim Board" + help + Build Google Skyrim reference board. This board uses an AMD SoC + and NPCX9 EC + +config BOARD_WINTERHOLD + bool "Google Winterhold Board" + help + Build Google Winterhold reference board. This board uses an AMD SoC + and NPCX9 EC + +config BOARD_FROSTFLOW + bool "Google Frostflow Board" + help + Build Google Frostflow reference board. This board uses an AMD SoC + and NPCX9 EC + +config BOARD_INPUT_CURRENT_SCALE_FACTOR + int "Input current scale factor" + default 100 + help + Limit input current to fraction of negotiated limit. + +config BOARD_USB_HUB_RESET + bool "Support USB hub reset or not" + default y + help + Enable this if your board has a USB hub reset GPIO connect to EC to + reset the USB hub. + +module = SKYRIM +module-str = Skyrim board-specific code +source "subsys/logging/Kconfig.template.log_config" + +source "Kconfig.zephyr" diff --git a/zephyr/projects/skyrim/adc.dts b/zephyr/projects/skyrim/adc.dts new file mode 100644 index 0000000000..0f2ffd6436 --- /dev/null +++ b/zephyr/projects/skyrim/adc.dts @@ -0,0 +1,82 @@ +/* Copyright 2021 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <cros/thermistor/thermistor.dtsi> + +/ { + named-adc-channels { + compatible = "named-adc-channels"; + + adc_temp_charger: temp-charger { + enum-name = "ADC_TEMP_SENSOR_CHARGER"; + io-channels = <&adc0 1>; + }; + adc_temp_memory: temp-memory { + enum-name = "ADC_TEMP_SENSOR_MEMORY"; + io-channels = <&adc0 2>; + }; + adc_core_imon1: core-imon1 { + enum-name = "ADC_CORE_IMON1"; + io-channels = <&adc0 3>; + }; + adc_core_imon2: core-imon2 { + enum-name = "ADC_SOC_IMON2"; + io-channels = <&adc0 4>; + }; + }; + + temp_charger_thermistor: charger-thermistor { + compatible = "cros-ec,temp-sensor-thermistor"; + thermistor = <&thermistor_3V3_30K9_47K_4050B>; + adc = <&adc_temp_charger>; + }; + + temp_memory_thermistor: memory-thermistor { + compatible = "cros-ec,temp-sensor-thermistor"; + thermistor = <&thermistor_3V3_30K9_47K_4050B>; + adc = <&adc_temp_memory>; + }; + + named-temp-sensors { + compatible = "cros-ec,temp-sensors"; + charger-thermistor { + temp_host_high = <100>; + temp_host_halt = <105>; + temp_host_release_high = <80>; + sensor = <&temp_charger_thermistor>; + }; + + memory-thermistor { + temp_host_high = <100>; + temp_host_halt = <105>; + temp_host_release_high = <80>; + power-good-pin = <&gpio_pg_pwr_s5>; + sensor = <&temp_memory_thermistor>; + }; + + cpu { + temp_host_high = <100>; + temp_host_halt = <105>; + temp_host_release_high = <80>; + temp_fan_off = <60>; + temp_fan_max = <90>; + power-good-pin = <&gpio_s0_pgood>; + sensor = <&temp_cpu>; + }; + }; +}; + +&adc0 { + status = "okay"; + pinctrl-0 = <&adc0_chan1_gp44 + &adc0_chan2_gp43 + &adc0_chan3_gp42 + &adc0_chan4_gp41>; + pinctrl-names = "default"; +}; + +&thermistor_3V3_30K9_47K_4050B { + status = "okay"; +}; diff --git a/zephyr/projects/skyrim/battery_frostflow.dts b/zephyr/projects/skyrim/battery_frostflow.dts new file mode 100644 index 0000000000..2d6b28de70 --- /dev/null +++ b/zephyr/projects/skyrim/battery_frostflow.dts @@ -0,0 +1,12 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + batteries { + default_battery: cdt_c340152 { + compatible = "cdt,c340152", "battery-smart"; + }; + }; +}; diff --git a/zephyr/projects/skyrim/battery_morthal.dts b/zephyr/projects/skyrim/battery_morthal.dts new file mode 100644 index 0000000000..8c87cef7f9 --- /dev/null +++ b/zephyr/projects/skyrim/battery_morthal.dts @@ -0,0 +1,15 @@ +/* Copyright 2021 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + batteries { + default_battery: aec_5477109 { + compatible = "aec,5477109", "battery-smart"; + }; + smp_l20m3pg1 { + compatible = "smp,l20m3pg1", "battery-smart"; + }; + }; +}; diff --git a/zephyr/projects/skyrim/battery_skyrim.dts b/zephyr/projects/skyrim/battery_skyrim.dts new file mode 100644 index 0000000000..8c87cef7f9 --- /dev/null +++ b/zephyr/projects/skyrim/battery_skyrim.dts @@ -0,0 +1,15 @@ +/* Copyright 2021 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + batteries { + default_battery: aec_5477109 { + compatible = "aec,5477109", "battery-smart"; + }; + smp_l20m3pg1 { + compatible = "smp,l20m3pg1", "battery-smart"; + }; + }; +}; diff --git a/zephyr/projects/skyrim/battery_winterhold.dts b/zephyr/projects/skyrim/battery_winterhold.dts new file mode 100644 index 0000000000..d923243d45 --- /dev/null +++ b/zephyr/projects/skyrim/battery_winterhold.dts @@ -0,0 +1,33 @@ +/* Copyright 2021 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + batteries { + default_battery: lgc_xphx8 { + compatible = "lgc,xphx8", "battery-smart"; + }; + smp_atlxdy9k { + compatible = "smp,atlxdy9k", "battery-smart"; + }; + smp_cosxdy9k{ + compatible = "smp,cosxdy9k", "battery-smart"; + }; + byd_wv3k8{ + compatible = "byd,wv3k8", "battery-smart"; + }; + cosmx_mvk11{ + compatible = "cosmx,mvk11", "battery-smart"; + }; + sunwoda_atlvkyjx{ + compatible = "sunwoda,atlvkyjx", "battery-smart"; + }; + sunwoda_cosvkyjx{ + compatible = "sunwoda,cosvkyjx", "battery-smart"; + }; + atl_cfd72{ + compatible = "atl,cfd72", "battery-smart"; + }; + }; +}; diff --git a/zephyr/projects/skyrim/fan.dts b/zephyr/projects/skyrim/fan.dts new file mode 100644 index 0000000000..f0bc28cb7e --- /dev/null +++ b/zephyr/projects/skyrim/fan.dts @@ -0,0 +1,39 @@ +/* Copyright 2021 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + fans { + compatible = "cros-ec,fans"; + + fan_0 { + pwms = <&pwm0 0 PWM_KHZ(25) PWM_POLARITY_NORMAL>; + rpm_min = <3100>; + rpm_start = <3100>; + rpm_max = <8000>; + tach = <&tach1>; + pgood_gpio = <&gpio_s0_pgood>; + }; + }; +}; + +/* Tachemeter for fan speed measurement */ +&tach1 { + status = "okay"; + pinctrl-0 = <&ta1_1_in_gp40>; + pinctrl-names = "default"; + port = <NPCX_TACH_PORT_A>; /* port-A is selected */ + sample-clk = <NPCX_TACH_FREQ_LFCLK>; /* Use LFCLK as sampling clock */ + pulses-per-round = <2>; /* number of pulses per round of encoder */ +}; + +&pwm0_gpc3 { + drive-open-drain; +}; + +&pwm0 { + status = "okay"; + pinctrl-0 = <&pwm0_gpc3>; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/skyrim/frostflow.dts b/zephyr/projects/skyrim/frostflow.dts new file mode 100644 index 0000000000..1ed0b4cb2b --- /dev/null +++ b/zephyr/projects/skyrim/frostflow.dts @@ -0,0 +1,136 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <dt-bindings/usbc_mux.h> + +#include "i2c_common.dtsi" + +/ { + named-gpios { + /* Frostflow-specific GPIO customizations */ + }; + + named-temp-sensors { + compatible = "cros-ec,temp-sensors"; + soc-pct2075 { + temp_host_high = <100>; + temp_host_halt = <105>; + temp_host_release_high = <80>; + temp_host_release_halt = <80>; + temp_fan_off = <35>; + temp_fan_max = <70>; + power-good-pin = <&gpio_pg_pwr_s5>; + sensor = <&soc_pct2075>; + }; + amb-pct2075 { + power-good-pin = <&gpio_pg_pwr_s5>; + sensor = <&amb_pct2075>; + }; + }; + + /* Rotation matrices for motion sensors. */ + motionsense-rotation-ref { + compatible = "cros-ec,motionsense-rotation-ref"; + lid_rot_ref: lid-rotation-ref { + mat33 = <1 0 0 + 0 1 0 + 0 0 1>; + }; + + base_rot_ref: base-rotation-ref { + mat33 = <0 1 0 + 1 0 0 + 0 0 (-1)>; + }; + }; + + ppc_port0: aoz1380 { + compatible = "aoz,aoz1380"; + status = "okay"; + }; +}; + +&i2c0_0 { + anx7483_port0: anx7483@3e { + compatible = "analogix,anx7483"; + reg = <0x3e>; + board-set = "board_anx7483_c0_mux_set"; + }; +}; + +&i2c1_0 { + anx7483_port1: anx7483@3e { + compatible = "analogix,anx7483"; + reg = <0x3e>; + board-set = "board_anx7483_c1_mux_set"; + }; + ppc_port1: nx20p348x@71 { + compatible = "nxp,nx20p348x"; + status = "okay"; + reg = <0x71>; + }; + ps8818_port1: ps8818@28 { + compatible = "parade,ps8818"; + reg = <0x28>; + flags = <(USB_MUX_FLAG_RESETS_IN_G3)>; + board-set = "board_c1_ps8818_mux_set"; + }; +}; + +&i2c4_1 { + charger: isl9241@9 { + compatible = "intersil,isl9241"; + status = "okay"; + reg = <0x9>; + }; +}; + +&usbc_port0 { + ppc = <&ppc_port0>; + usb-mux-chain-0 { + compatible = "cros-ec,usb-mux-chain"; + usb-muxes = <&amd_fp6_port0 &anx7483_port0>; + }; +}; + +&usbc_port1 { + ppc = <&ppc_port1>; + usb-mux-chain-1-anx { + compatible = "cros-ec,usb-mux-chain"; + usb-muxes = <&amd_fp6_port1 &anx7483_port1>; + }; + usb_mux_chain_ps8818_port1: usb-mux-chain-1-ps { + compatible = "cros-ec,usb-mux-chain"; + usb-muxes = <&amd_fp6_port1 &ps8818_port1>; + alternative-chain; + }; +}; + +&cros_kb_raw { + pinctrl-0 = < + &ksi0_gp31 + &ksi1_gp30 + &ksi2_gp27 + &ksi3_gp26 + &ksi4_gp25 + &ksi5_gp24 + &ksi6_gp23 + &ksi7_gp22 + &kso00_gp21 + &kso01_gp20 + &kso03_gp16 + &kso04_gp15 + &kso05_gp14 + &kso06_gp13 + &kso07_gp12 + &kso08_gp11 + &kso09_gp10 + &kso10_gp07 + &kso11_gp06 + &kso12_gp05 + &kso13_gp04 + &kso14_gp82 + >; +}; diff --git a/zephyr/projects/skyrim/gpio.dts b/zephyr/projects/skyrim/gpio.dts new file mode 100644 index 0000000000..57abcc846d --- /dev/null +++ b/zephyr/projects/skyrim/gpio.dts @@ -0,0 +1,370 @@ +/* Copyright 2021 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + aliases { + gpio-wp = &gpio_wp; + gpio-cbi-wp = &gpio_cbi_wp; + gpio-kbd-kso2 = &gpio_ec_kso_02_inv; + }; + + /* GPIOs shared by all boards */ + named-gpios { + compatible = "named-gpios"; + + ccd_mode_odl { + gpios = <&gpioc 6 GPIO_ODR_HIGH>; + }; + ec_gsc_packet_mode { + gpios = <&gpiob 1 GPIO_OUTPUT_LOW>; + enum-name = "GPIO_PACKET_MODE_EN"; + }; + gpio_mech_pwr_btn_odl: mech_pwr_btn_odl { + gpios = <&gpiod 2 GPIO_INPUT>; + enum-name = "GPIO_POWER_BUTTON_L"; + }; + gpio_slp_s3_l: slp_s3_l { + gpios = <&gpio6 1 GPIO_INPUT>; + enum-name = "GPIO_PCH_SLP_S3_L"; + alias = "GPIO_PCH_SLP_S0_L"; + }; + gpio_slp_s5_l: slp_s5_l { + gpios = <&gpio7 2 GPIO_INPUT>; + enum-name = "GPIO_PCH_SLP_S5_L"; + }; + gpio_pg_pwr_s5: pg_pwr_s5 { + gpios = <&gpioc 0 GPIO_INPUT>; + enum-name = "GPIO_S5_PGOOD"; + }; + gpio_s0_pgood: pg_pcore_s0_r_od { + gpios = <&gpiob 6 GPIO_INPUT>; + enum-name = "GPIO_S0_PGOOD"; + }; + gpio_acok_od: acok_od { + gpios = <&gpio0 0 GPIO_INPUT>; + enum-name = "GPIO_AC_PRESENT"; + }; + gpio_en_pwr_s5: en_pwr_s5 { + gpios = <&gpiob 7 GPIO_OUTPUT_LOW>; + enum-name = "GPIO_EN_PWR_A"; + }; + gpio_en_pwr_s0_r: en_pwr_s0_r { + gpios = <&gpiof 1 GPIO_OUTPUT_LOW>; + }; + gpio_en_pwr_pcore_s0_r: en_pwr_pcore_s0_r { + gpios = <&gpioe 1 GPIO_OUTPUT_LOW>; + }; + ec_sys_rst_l { + gpios = <&gpio7 6 GPIO_ODR_HIGH>; + enum-name = "GPIO_SYS_RESET_L"; + }; + gpio_ec_soc_rsmrst_l: ec_soc_rsmrst_l { + gpios = <&gpioc 5 GPIO_OUTPUT_LOW>; + enum-name = "GPIO_PCH_RSMRST_L"; + }; + gpio_ec_pch_wake_odl: ec_soc_wake_l { + gpios = <&gpio0 3 GPIO_OUTPUT_HIGH>; + }; + prochot_odl { + gpios = <&gpiod 5 GPIO_ODR_HIGH>; + enum-name = "GPIO_CPU_PROCHOT"; + }; + soc_alert_ec_l { + gpios = <&gpioe 2 GPIO_INPUT>; + }; + gpio_usb_c0_tcpc_int_odl: usb_c0_tcpc_int_odl { + gpios = <&gpioe 0 GPIO_INPUT>; + enum-name = "GPIO_USB_C0_TCPC_INT_ODL"; + }; + gpio_usb_c1_tcpc_int_odl: usb_c1_tcpc_int_odl { + gpios = <&gpioc 7 GPIO_INPUT>; + enum-name = "GPIO_USB_C1_TCPC_INT_ODL"; + }; + gpio_usb_c0_ppc_int_odl: usb_c0_ppc_int_odl { + gpios = <&gpio7 5 GPIO_INPUT>; + enum-name = "GPIO_USB_C0_PPC_INT_ODL"; + }; + gpio_usb_c1_ppc_int_odl: usb_c1_ppc_int_odl { + gpios = <&gpiod 4 GPIO_INPUT>; + enum-name = "GPIO_USB_C1_PPC_INT_ODL"; + }; + gpio_usb_c0_bc12_int_odl: usb_c0_bc12_int_odl { + gpios = <&gpioa 4 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_USB_C0_BC12_INT_ODL"; + }; + gpio_usb_c1_bc12_int_odl: usb_c1_bc12_int_odl { + gpios = <&gpio9 6 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_USB_C1_BC12_INT_ODL"; + }; + gpio_usb_c0_tcpc_rst_l: usb_c0_tcpc_rst_l { + gpios = <&gpio3 4 GPIO_OUTPUT_HIGH>; + enum-name = "GPIO_USB_C0_TCPC_RST_L"; + }; + gpio_usb_c1_tcpc_rst_l: usb_c1_tcpc_rst_l { + gpios = <&gpio3 7 GPIO_OUTPUT_HIGH>; + enum-name = "GPIO_USB_C1_TCPC_RST_L"; + }; + usb_c0_hpd { + gpios = <&gpiof 5 GPIO_OUTPUT_LOW>; + enum-name = "GPIO_USB_C0_DP_HPD"; + }; + usb_c1_hpd { + gpios = <&gpiof 4 GPIO_OUTPUT_LOW>; + enum-name = "GPIO_USB_C1_DP_HPD"; + }; + gpio_lid_open: lid_open { + gpios = <&gpio0 2 GPIO_INPUT>; + enum-name = "GPIO_LID_OPEN"; + }; + ec_batt_pres_odl { + gpios = <&gpio9 4 GPIO_INPUT>; + enum-name = "GPIO_BATT_PRES_ODL"; + }; + gpio_ec_disable_disp_bl: ec_disable_disp_bl { + gpios = <&gpioa 6 GPIO_OUTPUT_HIGH>; + enum-name = "GPIO_ENABLE_BACKLIGHT_L"; + }; + gpio_usb_fault_odl: usb_fault_odl { + gpios = <&gpio5 0 (GPIO_ODR_HIGH | GPIO_VOLTAGE_1P8)>; + }; + gpio_en_pwr_s3: en_pwr_s3 { + gpios = <&gpio7 4 GPIO_OUTPUT_LOW>; + }; + gpio_pg_groupc_s0_od: pg_groupc_s0_od { + gpios = <&gpiof 0 GPIO_INPUT>; + }; + gpio_ec_i2c_usbc_pd_int: ec_i2c_usbc_pd_int { + gpios = <&gpioa 3 GPIO_INPUT>; + }; + gpio_soc_thermtrip_odl: soc_thermtrip_odl { + gpios = <&gpio9 5 GPIO_INPUT>; + }; + gpio_hub_rst: hub_rst { + gpios = <&gpio6 6 GPIO_OUTPUT_HIGH>; + }; + ec_soc_int_l { + gpios = <&gpioa 1 GPIO_OUTPUT_HIGH>; + enum-name = "GPIO_EC_INT_L"; + }; + gpio_ec_soc_pwr_good: ec_soc_pwr_good { + gpios = <&gpiod 3 GPIO_OUTPUT_LOW>; + }; + gpio_pcore_ocp_r_l: pcore_ocp_r_l { + gpios = <&gpioa 5 GPIO_INPUT>; + }; + gpio_usb_hub_fault_q_odl: usb_hub_fault_q_odl { + gpios = <&gpioe 5 GPIO_INPUT_PULL_UP>; + }; + gpio_pg_lpddr5_s3_od: pg_lpddr5_s3_od { + gpios = <&gpio7 3 GPIO_INPUT>; + }; + 3axis_int_l { + gpios = <&gpioa 2 GPIO_INPUT_PULL_UP>; + }; + gpio_ec_soc_pwr_btn_l: ec_soc_pwr_btn_l { + gpios = <&gpioa 7 GPIO_OUTPUT_HIGH>; + enum-name = "GPIO_PCH_PWRBTN_L"; + }; + gpio_volup_btn_odl: volup_btn_odl { + gpios = <&gpio6 7 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_VOLUME_UP_L"; + }; + gpio_voldn_btn_odl: voldn_btn_odl { + gpios = <&gpio7 0 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_VOLUME_DOWN_L"; + }; + ec_sc_rst { + gpios = <&gpiob 0 GPIO_OUTPUT_LOW>; + }; + gpio_cbi_wp: ec_cbi_wp { + gpios = <&gpio8 1 GPIO_OUTPUT_LOW>; + }; + gpio_wp: ec_wp_l { + gpios = <&gpiod 7 (GPIO_INPUT | GPIO_ACTIVE_LOW)>; + }; + gpio_pg_lpddr5_s0_od: pg_lpddr5_s0_od { + gpios = <&gpio6 0 GPIO_INPUT>; + }; + ec_espi_rst_l { + gpios = <&gpio5 4 GPIO_PULL_DOWN>; + }; + gpio_accel_gyro_int_l: accel_gyro_int_l { + gpios = <&gpioa 0 GPIO_INPUT>; + }; + /* unimplemented GPIOs */ + entering-rw { + enum-name = "GPIO_ENTERING_RW"; + }; + pch-sys-prwok { + enum-name = "GPIO_PCH_SYS_PWROK"; + }; + ec_i2c_usb_a0_c0_scl { + gpios = <&gpiob 5 GPIO_INPUT>; + }; + ec_i2c_usb_a0_c0_sda { + gpios = <&gpiob 4 GPIO_INPUT>; + }; + ec_i2c_usb_a1_c1_scl { + gpios = <&gpio9 0 GPIO_INPUT>; + }; + ec_i2c_usb_a1_c1_sda { + gpios = <&gpio8 7 GPIO_INPUT>; + }; + ec_i2c_batt_scl { + gpios = <&gpio9 2 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; + }; + ec_i2c_batt_sda { + gpios = <&gpio9 1 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; + }; + ec_i2c_usbc_mux_scl { + gpios = <&gpiod 1 GPIO_INPUT>; + }; + ec_i2c_usbc_mux_sda { + gpios = <&gpiod 0 GPIO_INPUT>; + }; + ec_i2c_power_scl { + gpios = <&gpiof 3 GPIO_INPUT>; + }; + ec_i2c_power_sda { + gpios = <&gpiof 2 GPIO_INPUT>; + }; + ec_i2c_cbi_scl { + gpios = <&gpio3 3 GPIO_INPUT>; + }; + ec_i2c_cbi_sda { + gpios = <&gpio3 6 GPIO_INPUT>; + }; + ec_i2c_sensor_scl { + gpios = <&gpioe 4 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; + }; + ec_i2c_sensor_sda { + gpios = <&gpioe 3 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; + }; + ec_i2c_soc_sic { + gpios = <&gpiob 3 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; + }; + ec_i2c_soc_sid { + gpios = <&gpiob 2 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; + }; + en_kb_bl { + gpios = <&gpio9 7 GPIO_OUTPUT_HIGH>; + enum-name = "GPIO_EN_KEYBOARD_BACKLIGHT"; + }; + gpio_ec_kso_02_inv: ec_kso_02_inv { + gpios = <&gpio1 7 (GPIO_OUTPUT_LOW | GPIO_ACTIVE_LOW)>; + }; + tablet_mode_l { + gpios = <&gpioc 1 GPIO_INPUT>; + enum-name = "GPIO_TABLET_MODE_L"; + }; + ec_gpio56 { + gpios = <&gpio5 6 GPIO_INPUT_PULL_UP>; + }; + ec_flprg2 { + gpios = <&gpio8 6 GPIO_INPUT_PULL_UP>; + }; + + usb_c0_tcpc_fastsw_ctl_en { + gpios = <&ioex_c0_port0 4 GPIO_OUTPUT_LOW>; + enum-name = "IOEX_USB_C0_TCPC_FASTSW_CTL_EN"; + }; + usb_c0_ppc_en_l { + gpios = <&ioex_c0_port1 0 GPIO_OUTPUT_LOW>; + }; + ioex_usb_c0_ilim_3a_en: usb_c0_ppc_ilim_3a_en { + gpios = <&ioex_c0_port1 1 GPIO_OUTPUT_LOW>; + enum-name = "IOEX_USB_C0_PPC_ILIM_3A_EN"; + }; + ioex_usb_c0_sbu_fault_odl: usb_c0_sbu_fault_odl { + gpios = <&ioex_c0_port1 2 GPIO_INPUT>; + }; + ioex_en_pp5000_usb_a0_vbus: en_pp5000_usb_a0_vbus { + gpios = <&ioex_c0_port1 5 GPIO_OUTPUT_LOW>; + }; + ioex_usb_a0_fault_odl: usb_a0_fault_odl { + gpios = <&ioex_c0_port1 6 GPIO_INPUT>; + }; + ioex_usb_c0_sbu_flip: usb_c0_sbu_flip { + gpios = <&ioex_c0_port1 7 GPIO_OUTPUT_LOW>; + enum-name = "IOEX_USB_C0_SBU_FLIP"; + }; + + usb_a1_retimer_en { + gpios = <&ioex_c1_port0 0 GPIO_OUTPUT_LOW>; + enum-name = "IOEX_USB_A1_RETIMER_EN"; + }; + usb_a1_retimer_rst { + gpios = <&ioex_c1_port0 1 GPIO_OUTPUT_LOW>; + }; + usb_c1_in_hpd { + gpios = <&ioex_c1_port0 3 GPIO_OUTPUT_LOW>; + enum-name = "IOEX_USB_C1_HPD_IN_DB"; + }; + usb_c1_tcpc_fastsw_ctl_en { + gpios = <&ioex_c1_port0 4 GPIO_OUTPUT_LOW>; + enum-name = "IOEX_USB_C1_TCPC_FASTSW_CTL_EN"; + }; + usb_c1_ppc_en_l { + gpios = <&ioex_c1_port1 0 GPIO_OUTPUT_LOW>; + }; + usb_c1_ppc_ilim_3a_en { + gpios = <&ioex_c1_port1 1 GPIO_OUTPUT_LOW>; + enum-name = "IOEX_USB_C1_PPC_ILIM_3A_EN"; + }; + ioex_usb_c1_sbu_fault_odl: usb_c1_sbu_fault_odl { + gpios = <&ioex_c1_port1 2 GPIO_INPUT>; + enum-name = "IOEX_USB_C1_FAULT_ODL"; + }; + ioex_en_pp5000_usb_a1_vbus: en_pp5000_usb_a1_vbus { + gpios = <&ioex_c1_port1 5 GPIO_OUTPUT_LOW>; + }; + ioex_usb_a1_fault_db_odl: usb_a1_fault_db_odl { + gpios = <&ioex_c1_port1 6 GPIO_INPUT>; + }; + ioex_usb_c1_sbu_flip: usb_c1_sbu_flip { + gpios = <&ioex_c1_port1 7 GPIO_OUTPUT_LOW>; + enum-name = "IOEX_USB_C1_SBU_FLIP"; + }; + }; + + usba-port-enable-list { + compatible = "cros-ec,usba-port-enable-pins"; + enable-pins = <&ioex_en_pp5000_usb_a0_vbus + &ioex_en_pp5000_usb_a1_vbus>; + }; +}; + +/* PSL input pads*/ +&psl_in1_gpd2 { + /* MECH_PWR_BTN_ODL */ + psl-in-mode = "edge"; + psl-in-pol = "low-falling"; +}; + +&psl_in2_gp00 { + /* ACOK_OD */ + psl-in-mode = "edge"; + psl-in-pol = "high-rising"; +}; + +&psl_in4_gp02 { + /* LID_OPEN */ + psl-in-mode = "edge"; + psl-in-pol = "high-rising"; +}; + +/* Power domain device controlled by PSL (Power Switch Logic) IO pads */ +&power_ctrl_psl { + status = "okay"; + pinctrl-names = "sleep"; + pinctrl-0 = <&psl_in1_gpd2 &psl_in2_gp00 &psl_in4_gp02>; +}; + +/* host interface */ +&espi0 { + status = "okay"; + pinctrl-0 = <&espi_lpc_gp46_47_51_52_53_54_55_57>; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/skyrim/i2c_common.dtsi b/zephyr/projects/skyrim/i2c_common.dtsi new file mode 100644 index 0000000000..aaf54a161b --- /dev/null +++ b/zephyr/projects/skyrim/i2c_common.dtsi @@ -0,0 +1,294 @@ +/* Copyright 2021 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + + #include <dt-bindings/usb_pd_tcpm.h> + +/ { + aliases { + i2c-0 = &i2c0_0; + i2c-1 = &i2c1_0; + i2c-2 = &i2c2_0; + i2c-3 = &i2c3_0; + i2c-4 = &i2c4_1; + i2c-5 = &i2c5_0; + i2c-7 = &i2c7_0; + }; + + named-i2c-ports { + compatible = "named-i2c-ports"; + + i2c_tcpc0: tcpc0 { + i2c-port = <&i2c0_0>; + enum-names = "I2C_PORT_TCPC0"; + }; + + i2c_tcpc1: tcpc1 { + i2c-port = <&i2c1_0>; + enum-names = "I2C_PORT_TCPC1"; + }; + + battery { + i2c-port = <&i2c2_0>; + remote-port = <0>; + enum-names = "I2C_PORT_BATTERY"; + }; + + usb-mux { + i2c-port = <&i2c3_0>; + enum-names = "I2C_PORT_USB_MUX"; + }; + + i2c_charger: charger { + i2c-port = <&i2c4_1>; + enum-names = "I2C_PORT_CHARGER"; + }; + + eeprom { + i2c-port = <&i2c5_0>; + enum-names = "I2C_PORT_EEPROM"; + }; + + i2c_sensor: sensor { + i2c-port = <&i2c6_1>; + enum-names = "I2C_PORT_SENSOR"; + }; + + i2c_soc_thermal: soc-thermal { + i2c-port = <&i2c7_0>; + enum-names = "I2C_PORT_THERMAL_AP"; + }; + }; + + +}; + +&i2c0_0 { + status = "okay"; + label = "I2C_TCPC0"; + clock-frequency = <I2C_BITRATE_FAST>; + pinctrl-0 = <&i2c0_0_sda_scl_gpb4_b5>; + pinctrl-names = "default"; + + bc12_port0: pi3usb9201@5f { + compatible = "pericom,pi3usb9201"; + status = "okay"; + reg = <0x5f>; + irq = <&int_usb_c0_bc12>; + }; + + tcpc_port0: nct38xx@70 { + compatible = "nuvoton,nct38xx"; + reg = <0x70>; + gpio-dev = <&nct3807_C0>; + tcpc-flags = <(TCPC_FLAGS_TCPCI_REV2_0)>; + }; + + nct3807_C0:nct3807_C0@70 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nuvoton,nct38xx-gpio"; + reg = <0x70>; + label = "NCT3807_C0"; + + ioex_c0_port0:gpio@0 { + compatible = "nuvoton,nct38xx-gpio-port"; + reg = <0x0>; + label = "NCT3807_C0_GPIO0"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + pin_mask = <0xff>; + pinmux_mask = <0xf7>; + }; + ioex_c0_port1:gpio@1 { + compatible = "nuvoton,nct38xx-gpio-port"; + reg = <0x1>; + label = "NCT3807_C0_GPIO1"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + pin_mask = <0xff>; + }; + }; + + nct3808_alert_0 { + compatible = "nuvoton,nct38xx-gpio-alert"; + irq-gpios = <&gpioe 0 GPIO_ACTIVE_LOW>; + nct38xx-dev = <&nct3807_C0>; + label = "NCT3807_ALERT_0"; + }; +}; + +&i2c_ctrl0 { + status = "okay"; +}; + +&i2c1_0 { + status = "okay"; + label = "I2C_TCPC1"; + clock-frequency = <I2C_BITRATE_FAST>; + pinctrl-0 = <&i2c1_0_sda_scl_gp87_90>; + pinctrl-names = "default"; + + bc12_port1: pi3usb9201@5f { + compatible = "pericom,pi3usb9201"; + status = "okay"; + reg = <0x5f>; + irq = <&int_usb_c1_bc12>; + }; + + tcpc_port1: nct38xx@70 { + compatible = "nuvoton,nct38xx"; + reg = <0x70>; + gpio-dev = <&nct3807_C1>; + tcpc-flags = <(TCPC_FLAGS_TCPCI_REV2_0)>; + }; + + nct3807_C1:nct3807_C1@70 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nuvoton,nct38xx-gpio"; + reg = <0x70>; + label = "NCT3807_C1"; + + ioex_c1_port0:gpio@0 { + compatible = "nuvoton,nct38xx-gpio-port"; + reg = <0x0>; + label = "NCT3807_C1_GPIO0"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + pin_mask = <0xff>; + pinmux_mask = <0xf7>; + }; + ioex_c1_port1:gpio@1 { + compatible = "nuvoton,nct38xx-gpio-port"; + reg = <0x1>; + label = "NCT3807_C1_GPIO1"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + pin_mask = <0xff>; + }; + }; + + nct3808_alert_1 { + compatible = "nuvoton,nct38xx-gpio-alert"; + irq-gpios = <&gpioc 7 GPIO_ACTIVE_LOW>; + nct38xx-dev = <&nct3807_C1>; + label = "NCT3807_ALERT_1"; + }; +}; + +&i2c_ctrl1 { + status = "okay"; +}; + +&i2c2_0 { + status = "okay"; + label = "I2C_BATTERY"; + clock-frequency = <I2C_BITRATE_STANDARD>; + pinctrl-0 = <&i2c2_0_sda_scl_gp91_92>; + pinctrl-names = "default"; +}; + +&i2c_ctrl2 { + status = "okay"; +}; + +&i2c3_0 { + status = "okay"; + label = "I2C_USB_MUX"; + clock-frequency = <I2C_BITRATE_FAST>; + pinctrl-0 = <&i2c3_0_sda_scl_gpd0_d1>; + pinctrl-names = "default"; + + amd_fp6_port0: amd_fp6@5c { + compatible = "amd,usbc-mux-amd-fp6"; + status = "okay"; + reg = <0x5c>; + }; + amd_fp6_port1: amd_fp6@52 { + compatible = "amd,usbc-mux-amd-fp6"; + status = "okay"; + reg = <0x52>; + }; +}; + +&i2c_ctrl3 { + status = "okay"; +}; + +&i2c4_1 { + status = "okay"; + label = "I2C_CHARGER"; + clock-frequency = <I2C_BITRATE_FAST>; + pinctrl-0 = <&i2c4_1_sda_scl_gpf2_f3>; + pinctrl-names = "default"; +}; + +&i2c_ctrl4 { + status = "okay"; +}; + +&i2c5_0 { + status = "okay"; + label = "I2C_EEPROM"; + clock-frequency = <I2C_BITRATE_FAST>; + pinctrl-0 = <&i2c5_0_sda_scl_gp33_36>; + pinctrl-names = "default"; + + cbi_eeprom: eeprom@50 { + compatible = "atmel,at24"; + reg = <0x50>; + size = <2048>; + pagesize = <16>; + address-width = <8>; + timeout = <5>; + }; +}; + +&i2c_ctrl5 { + status = "okay"; +}; + +&i2c6_1 { + status = "okay"; + label = "I2C_SENSOR"; + clock-frequency = <I2C_BITRATE_FAST>; + pinctrl-0 = <&i2c6_1_sda_scl_gpe3_e4>; + pinctrl-names = "default"; + + soc_pct2075: soc-pct2075@48 { + compatible = "nxp,pct2075"; + reg = <0x48>; + }; + + amb_pct2075: amb-pct2075@4f { + compatible = "nxp,pct2075"; + reg = <0x4f>; + }; +}; + +&i2c_ctrl6 { + status = "okay"; +}; + +&i2c7_0 { + status = "okay"; + label = "I2C_THERMAL_AP"; + clock-frequency = <I2C_BITRATE_FAST>; + pinctrl-0 = <&i2c7_0_sda_scl_gpb2_b3>; + pinctrl-names = "default"; + + temp_cpu: cpu@4c { + compatible = "amd,sb-tsi"; + reg = <0x4c>; + }; +}; + +&i2c_ctrl7 { + status = "okay"; +}; diff --git a/zephyr/projects/skyrim/include/frostflow/keyboard_customization.h b/zephyr/projects/skyrim/include/frostflow/keyboard_customization.h new file mode 100644 index 0000000000..2d2a997f91 --- /dev/null +++ b/zephyr/projects/skyrim/include/frostflow/keyboard_customization.h @@ -0,0 +1,78 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Keyboard configuration */ + +#ifndef __KEYBOARD_CUSTOMIZATION_H +#define __KEYBOARD_CUSTOMIZATION_H + +/* + * KEYBOARD_COLS_MAX has the build time column size. It's used to allocate + * exact spaces for arrays. Actual keyboard scanning is done using + * keyboard_cols, which holds a runtime column size. + */ +#ifdef CONFIG_KEYBOARD_CUSTOMIZATION +#undef KEYBOARD_COLS_MAX +#undef KEYBOARD_ROWS + +#define KEYBOARD_COLS_MAX 15 +#define KEYBOARD_ROWS 8 +#endif + +/* + * WARNING: Do not directly modify it. You should call keyboard_raw_set_cols, + * instead. It checks whether you're eligible or not. + */ +extern uint8_t keyboard_cols; + +#define KEYBOARD_ROW_TO_MASK(r) (1 << (r)) + +/* Columns and masks for keys we particularly care about */ +#define KEYBOARD_COL_DOWN 11 +#define KEYBOARD_ROW_DOWN 5 +#define KEYBOARD_MASK_DOWN KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_DOWN) +#define KEYBOARD_COL_ESC 1 +#define KEYBOARD_ROW_ESC 1 +#define KEYBOARD_MASK_ESC KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_ESC) +#define KEYBOARD_COL_KEY_H 6 +#define KEYBOARD_ROW_KEY_H 1 +#define KEYBOARD_MASK_KEY_H KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_H) +#define KEYBOARD_COL_KEY_R 3 +#define KEYBOARD_ROW_KEY_R 7 +#define KEYBOARD_MASK_KEY_R KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_R) +#define KEYBOARD_COL_LEFT_ALT 10 +#define KEYBOARD_ROW_LEFT_ALT 6 +#define KEYBOARD_MASK_LEFT_ALT KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_ALT) +#define KEYBOARD_COL_REFRESH 2 +#define KEYBOARD_ROW_REFRESH 3 +#define KEYBOARD_MASK_REFRESH KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_REFRESH) +#define KEYBOARD_COL_RIGHT_ALT 10 +#define KEYBOARD_ROW_RIGHT_ALT 0 +#define KEYBOARD_MASK_RIGHT_ALT KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_RIGHT_ALT) +#define KEYBOARD_DEFAULT_COL_VOL_UP 4 +#define KEYBOARD_DEFAULT_ROW_VOL_UP 1 +#define KEYBOARD_COL_LEFT_CTRL 0 +#define KEYBOARD_ROW_LEFT_CTRL 2 +#define KEYBOARD_MASK_LEFT_CTRL KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_CTRL) +#define KEYBOARD_COL_RIGHT_CTRL 0 +#define KEYBOARD_ROW_RIGHT_CTRL 4 +#define KEYBOARD_MASK_RIGHT_CTRL KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_RIGHT_CTRL) +#define KEYBOARD_COL_SEARCH 0 +#define KEYBOARD_ROW_SEARCH 3 +#define KEYBOARD_MASK_SEARCH KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_SEARCH) +#define KEYBOARD_COL_KEY_0 9 +#define KEYBOARD_ROW_KEY_0 0 +#define KEYBOARD_MASK_KEY_0 KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_0) +#define KEYBOARD_COL_KEY_1 1 +#define KEYBOARD_ROW_KEY_1 7 +#define KEYBOARD_MASK_KEY_1 KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_1) +#define KEYBOARD_COL_KEY_2 4 +#define KEYBOARD_ROW_KEY_2 6 +#define KEYBOARD_MASK_KEY_2 KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_2) +#define KEYBOARD_COL_LEFT_SHIFT 7 +#define KEYBOARD_ROW_LEFT_SHIFT 1 +#define KEYBOARD_MASK_LEFT_SHIFT KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_SHIFT) + +#endif /* __KEYBOARD_CUSTOMIZATION_H */ diff --git a/zephyr/projects/skyrim/interrupts.dts b/zephyr/projects/skyrim/interrupts.dts new file mode 100644 index 0000000000..de4e87986a --- /dev/null +++ b/zephyr/projects/skyrim/interrupts.dts @@ -0,0 +1,146 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + gpio-interrupts { + compatible = "cros-ec,gpio-interrupts"; + + int_lid_open: lid_open { + irq-pin = <&gpio_lid_open>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "lid_interrupt"; + }; + int_ac_present: ac_present { + irq-pin = <&gpio_acok_od>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "extpower_interrupt"; + }; + int_power_button: power_button { + irq-pin = <&gpio_mech_pwr_btn_odl>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "power_button_interrupt"; + }; + int_slp_s3: slp_s3 { + irq-pin = <&gpio_slp_s3_l>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "baseboard_en_pwr_s0"; + }; + int_slp_s5: slp_s5 { + irq-pin = <&gpio_slp_s5_l>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "baseboard_set_en_pwr_s3"; + }; + int_s5_pgood: s5_pgood { + irq-pin = <&gpio_pg_pwr_s5>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "baseboard_s5_pgood"; + }; + int_pg_groupc_s0: pg_groupc_s0 { + irq-pin = <&gpio_pg_groupc_s0_od>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "baseboard_set_en_pwr_pcore"; + }; + int_pg_lpddr_s3: pg_lpddr_s3 { + irq-pin = <&gpio_pg_lpddr5_s3_od>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "baseboard_set_en_pwr_pcore"; + }; + int_pg_lpddr_s0: pg_lpddr_s0 { + irq-pin = <&gpio_pg_lpddr5_s0_od>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "baseboard_set_soc_pwr_pgood"; + }; + int_s0_pgood: s0_pgood { + irq-pin = <&gpio_s0_pgood>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "baseboard_s0_pgood"; + }; + int_soc_thermtrip: soc_thermtrip { + irq-pin = <&gpio_soc_thermtrip_odl>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "baseboard_soc_thermtrip"; + }; + int_soc_pcore_ocp: soc_pcore_ocp { + irq-pin = <&gpio_pcore_ocp_r_l>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "baseboard_soc_pcore_ocp"; + }; + int_volume_up: volume_up { + irq-pin = <&gpio_volup_btn_odl>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "button_interrupt"; + }; + int_volume_down: volume_down { + irq-pin = <&gpio_voldn_btn_odl>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "button_interrupt"; + }; + int_usb_a0_fault: a0_fault { + irq-pin = <&ioex_usb_a0_fault_odl>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "usb_fault_interrupt"; + }; + int_usb_a1_fault: a1_fault { + irq-pin = <&ioex_usb_a1_fault_db_odl>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "usb_fault_interrupt"; + }; + int_usb_c0_sbu_fault: c0_sbu_fault { + irq-pin = <&ioex_usb_c0_sbu_fault_odl>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "sbu_fault_interrupt"; + }; + int_usb_c1_sbu_fault: c1_sbu_fault { + irq-pin = <&ioex_usb_c1_sbu_fault_odl>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "sbu_fault_interrupt"; + }; + int_usb_c0_tcpc: usb_c0_tcpc { + irq-pin = <&gpio_usb_c0_tcpc_int_odl>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "tcpc_alert_event"; + }; + int_usb_c1_tcpc: usb_c1_tcpc { + irq-pin = <&gpio_usb_c1_tcpc_int_odl>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "tcpc_alert_event"; + }; + int_usb_c0_ppc: usb_c0_ppc { + irq-pin = <&gpio_usb_c0_ppc_int_odl>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "ppc_interrupt"; + }; + int_usb_c1_ppc: usb_c1_ppc { + irq-pin = <&gpio_usb_c1_ppc_int_odl>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "ppc_interrupt"; + }; + int_usb_c0_bc12: usb_c0_bc12 { + irq-pin = <&gpio_usb_c0_bc12_int_odl>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "bc12_interrupt"; + }; + int_usb_c1_bc12: usb_c1_bc12 { + irq-pin = <&gpio_usb_c1_bc12_int_odl>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "bc12_interrupt"; + }; + int_usb_hub_fault: hub_fault { + irq-pin = <&gpio_usb_hub_fault_q_odl>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "usb_fault_interrupt"; + }; + int_usb_pd_soc: usb_pd_soc { + irq-pin = <&gpio_ec_i2c_usbc_pd_int>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "usb_pd_soc_interrupt"; + }; + int_accel_gyro: accel_gyro { + irq-pin = <&gpio_accel_gyro_int_l>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "bmi3xx_interrupt"; + }; + }; +}; diff --git a/zephyr/projects/skyrim/keyboard.dts b/zephyr/projects/skyrim/keyboard.dts new file mode 100644 index 0000000000..df334ba54c --- /dev/null +++ b/zephyr/projects/skyrim/keyboard.dts @@ -0,0 +1,46 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + kblight { + compatible = "cros-ec,kblight-pwm"; + pwms = <&pwm1 0 PWM_HZ(100) PWM_POLARITY_NORMAL>; + }; +}; + +&pwm1 { + status = "okay"; + clock-bus = "NPCX_CLOCK_BUS_LFCLK"; + pinctrl-0 = <&pwm1_gpc2>; + pinctrl-names = "default"; +}; + +&cros_kb_raw { + status = "okay"; + /* No KSO2 (it's inverted and implemented by GPIO) */ + pinctrl-0 = < + &ksi0_gp31 + &ksi1_gp30 + &ksi2_gp27 + &ksi3_gp26 + &ksi4_gp25 + &ksi5_gp24 + &ksi6_gp23 + &ksi7_gp22 + &kso00_gp21 + &kso01_gp20 + &kso03_gp16 + &kso04_gp15 + &kso05_gp14 + &kso06_gp13 + &kso07_gp12 + &kso08_gp11 + &kso09_gp10 + &kso10_gp07 + &kso11_gp06 + &kso12_gp05 + >; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/skyrim/led_pins_frostflow.dts b/zephyr/projects/skyrim/led_pins_frostflow.dts new file mode 100644 index 0000000000..d294490208 --- /dev/null +++ b/zephyr/projects/skyrim/led_pins_frostflow.dts @@ -0,0 +1,63 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + pwm_pins { + compatible = "cros-ec,pwm-pin-config"; + + pwm_y: pwm_y { + #led-pin-cells = <1>; + pwms = <&pwm2 0 PWM_HZ(100) PWM_POLARITY_INVERTED>; + }; + + pwm_w: pwm_w { + #led-pin-cells = <1>; + pwms = <&pwm3 0 PWM_HZ(100) PWM_POLARITY_INVERTED>; + }; + }; + + pwm-led-pins { + compatible = "cros-ec,pwm-led-pins"; + + color_off: color-off { + led-color = "LED_OFF"; + led-id = "EC_LED_ID_BATTERY_LED"; + led-pins = <&pwm_y 0>, + <&pwm_w 0>; + }; + + color_amber: color-amber { + led-color = "LED_AMBER"; + led-id = "EC_LED_ID_BATTERY_LED"; + br-color = "EC_LED_COLOR_AMBER"; + led-pins = <&pwm_y 100>, + <&pwm_w 0>; + }; + + color_white: color-white { + led-color = "LED_WHITE"; + led-id = "EC_LED_ID_BATTERY_LED"; + br-color = "EC_LED_COLOR_WHITE"; + led-pins = <&pwm_y 0>, + <&pwm_w 100>; + }; + }; +}; + +/* Amber "battery charging" LED */ +&pwm2 { + status = "okay"; + clock-bus = "NPCX_CLOCK_BUS_LFCLK"; + pinctrl-0 = <&pwm2_gpc4>; + pinctrl-names = "default"; +}; + +/* White "battery full" LED */ +&pwm3 { + status = "okay"; + clock-bus = "NPCX_CLOCK_BUS_LFCLK"; + pinctrl-0 = <&pwm3_gp80>; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/skyrim/led_pins_morthal.dts b/zephyr/projects/skyrim/led_pins_morthal.dts new file mode 100644 index 0000000000..d294490208 --- /dev/null +++ b/zephyr/projects/skyrim/led_pins_morthal.dts @@ -0,0 +1,63 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + pwm_pins { + compatible = "cros-ec,pwm-pin-config"; + + pwm_y: pwm_y { + #led-pin-cells = <1>; + pwms = <&pwm2 0 PWM_HZ(100) PWM_POLARITY_INVERTED>; + }; + + pwm_w: pwm_w { + #led-pin-cells = <1>; + pwms = <&pwm3 0 PWM_HZ(100) PWM_POLARITY_INVERTED>; + }; + }; + + pwm-led-pins { + compatible = "cros-ec,pwm-led-pins"; + + color_off: color-off { + led-color = "LED_OFF"; + led-id = "EC_LED_ID_BATTERY_LED"; + led-pins = <&pwm_y 0>, + <&pwm_w 0>; + }; + + color_amber: color-amber { + led-color = "LED_AMBER"; + led-id = "EC_LED_ID_BATTERY_LED"; + br-color = "EC_LED_COLOR_AMBER"; + led-pins = <&pwm_y 100>, + <&pwm_w 0>; + }; + + color_white: color-white { + led-color = "LED_WHITE"; + led-id = "EC_LED_ID_BATTERY_LED"; + br-color = "EC_LED_COLOR_WHITE"; + led-pins = <&pwm_y 0>, + <&pwm_w 100>; + }; + }; +}; + +/* Amber "battery charging" LED */ +&pwm2 { + status = "okay"; + clock-bus = "NPCX_CLOCK_BUS_LFCLK"; + pinctrl-0 = <&pwm2_gpc4>; + pinctrl-names = "default"; +}; + +/* White "battery full" LED */ +&pwm3 { + status = "okay"; + clock-bus = "NPCX_CLOCK_BUS_LFCLK"; + pinctrl-0 = <&pwm3_gp80>; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/skyrim/led_pins_skyrim.dts b/zephyr/projects/skyrim/led_pins_skyrim.dts new file mode 100644 index 0000000000..d294490208 --- /dev/null +++ b/zephyr/projects/skyrim/led_pins_skyrim.dts @@ -0,0 +1,63 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + pwm_pins { + compatible = "cros-ec,pwm-pin-config"; + + pwm_y: pwm_y { + #led-pin-cells = <1>; + pwms = <&pwm2 0 PWM_HZ(100) PWM_POLARITY_INVERTED>; + }; + + pwm_w: pwm_w { + #led-pin-cells = <1>; + pwms = <&pwm3 0 PWM_HZ(100) PWM_POLARITY_INVERTED>; + }; + }; + + pwm-led-pins { + compatible = "cros-ec,pwm-led-pins"; + + color_off: color-off { + led-color = "LED_OFF"; + led-id = "EC_LED_ID_BATTERY_LED"; + led-pins = <&pwm_y 0>, + <&pwm_w 0>; + }; + + color_amber: color-amber { + led-color = "LED_AMBER"; + led-id = "EC_LED_ID_BATTERY_LED"; + br-color = "EC_LED_COLOR_AMBER"; + led-pins = <&pwm_y 100>, + <&pwm_w 0>; + }; + + color_white: color-white { + led-color = "LED_WHITE"; + led-id = "EC_LED_ID_BATTERY_LED"; + br-color = "EC_LED_COLOR_WHITE"; + led-pins = <&pwm_y 0>, + <&pwm_w 100>; + }; + }; +}; + +/* Amber "battery charging" LED */ +&pwm2 { + status = "okay"; + clock-bus = "NPCX_CLOCK_BUS_LFCLK"; + pinctrl-0 = <&pwm2_gpc4>; + pinctrl-names = "default"; +}; + +/* White "battery full" LED */ +&pwm3 { + status = "okay"; + clock-bus = "NPCX_CLOCK_BUS_LFCLK"; + pinctrl-0 = <&pwm3_gp80>; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/skyrim/led_pins_winterhold.dts b/zephyr/projects/skyrim/led_pins_winterhold.dts new file mode 100644 index 0000000000..d294490208 --- /dev/null +++ b/zephyr/projects/skyrim/led_pins_winterhold.dts @@ -0,0 +1,63 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + pwm_pins { + compatible = "cros-ec,pwm-pin-config"; + + pwm_y: pwm_y { + #led-pin-cells = <1>; + pwms = <&pwm2 0 PWM_HZ(100) PWM_POLARITY_INVERTED>; + }; + + pwm_w: pwm_w { + #led-pin-cells = <1>; + pwms = <&pwm3 0 PWM_HZ(100) PWM_POLARITY_INVERTED>; + }; + }; + + pwm-led-pins { + compatible = "cros-ec,pwm-led-pins"; + + color_off: color-off { + led-color = "LED_OFF"; + led-id = "EC_LED_ID_BATTERY_LED"; + led-pins = <&pwm_y 0>, + <&pwm_w 0>; + }; + + color_amber: color-amber { + led-color = "LED_AMBER"; + led-id = "EC_LED_ID_BATTERY_LED"; + br-color = "EC_LED_COLOR_AMBER"; + led-pins = <&pwm_y 100>, + <&pwm_w 0>; + }; + + color_white: color-white { + led-color = "LED_WHITE"; + led-id = "EC_LED_ID_BATTERY_LED"; + br-color = "EC_LED_COLOR_WHITE"; + led-pins = <&pwm_y 0>, + <&pwm_w 100>; + }; + }; +}; + +/* Amber "battery charging" LED */ +&pwm2 { + status = "okay"; + clock-bus = "NPCX_CLOCK_BUS_LFCLK"; + pinctrl-0 = <&pwm2_gpc4>; + pinctrl-names = "default"; +}; + +/* White "battery full" LED */ +&pwm3 { + status = "okay"; + clock-bus = "NPCX_CLOCK_BUS_LFCLK"; + pinctrl-0 = <&pwm3_gp80>; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/skyrim/led_policy_frostflow.dts b/zephyr/projects/skyrim/led_policy_frostflow.dts new file mode 100644 index 0000000000..e5875640fb --- /dev/null +++ b/zephyr/projects/skyrim/led_policy_frostflow.dts @@ -0,0 +1,122 @@ +/ { + led-colors { + compatible = "cros-ec,led-policy"; + + power-state-charge { + charge-state = "PWR_STATE_CHARGE"; + /* Battery percent range (>= Empty, <= 94%) */ + batt-lvl = <0 94>; + + color-0 { + led-color = <&color_amber>; + }; + }; + + power-state-charge-lvl-2 { + charge-state = "PWR_STATE_CHARGE"; + /* Battery percent range (>= 95%, <= Near Full) */ + batt-lvl = <95 97>; + + color-0 { + led-color = <&color_white>; + }; + }; + + power-state-near-full { + charge-state = "PWR_STATE_CHARGE_NEAR_FULL"; + + color-0 { + led-color = <&color_white>; + }; + }; + + power-state-discharge-s0 { + charge-state = "PWR_STATE_DISCHARGE"; + chipset-state = "POWER_S0"; + /* Battery percent range (>= 11%, <= Full) */ + batt-lvl = <11 100>; + + color-0 { + led-color = <&color_white>; + }; + }; + + power-state-discharge-s0-batt-low { + charge-state = "PWR_STATE_DISCHARGE"; + chipset-state = "POWER_S0"; + /* Battery percent range (>= Empty, <= 10%) */ + batt-lvl = <0 10>; + + /* Amber 1 sec, off 3 sec */ + color-0 { + led-color = <&color_amber>; + period-ms = <1000>; + }; + color-1 { + led-color = <&color_off>; + period-ms = <3000>; + }; + }; + + power-state-discharge-s3 { + charge-state = "PWR_STATE_DISCHARGE"; + chipset-state = "POWER_S3"; + + /* White 1 sec, off 3 sec */ + color-0 { + led-color = <&color_white>; + period-ms = <1000>; + }; + color-1 { + led-color = <&color_off>; + period-ms = <3000>; + }; + }; + + power-state-discharge-s5 { + charge-state = "PWR_STATE_DISCHARGE"; + chipset-state = "POWER_S5"; + + color-0 { + led-color = <&color_off>; + }; + }; + + power-state-error-s0 { + charge-state = "PWR_STATE_ERROR"; + chipset-state = "POWER_S0"; + /* Amber 1 sec, off 1 sec */ + color-0 { + led-color = <&color_amber>; + period-ms = <1000>; + }; + color-1 { + led-color = <&color_off>; + period-ms = <1000>; + }; + }; + + power-state-error-s3 { + charge-state = "PWR_STATE_ERROR"; + chipset-state = "POWER_S3"; + /* White 1 sec, off 3 sec */ + color-0 { + led-color = <&color_white>; + period-ms = <1000>; + }; + color-1 { + led-color = <&color_off>; + period-ms = <3000>; + }; + }; + + power-state-error-s5 { + charge-state = "PWR_STATE_ERROR"; + chipset-state = "POWER_S5"; + + color-0 { + led-color = <&color_off>; + }; + }; + }; +}; diff --git a/zephyr/projects/skyrim/led_policy_morthal.dts b/zephyr/projects/skyrim/led_policy_morthal.dts new file mode 100644 index 0000000000..a075c6b0d2 --- /dev/null +++ b/zephyr/projects/skyrim/led_policy_morthal.dts @@ -0,0 +1,103 @@ +#include <dt-bindings/battery.h> + +/ { + led-colors { + compatible = "cros-ec,led-policy"; + + power-state-charge { + charge-state = "PWR_STATE_CHARGE"; + + color-0 { + led-color = <&color_amber>; + }; + }; + + power-state-discharge-s0 { + charge-state = "PWR_STATE_DISCHARGE"; + chipset-state = "POWER_S0"; + /* Battery percent range (> Low, <= Full) */ + batt-lvl = <(BATTERY_LEVEL_LOW + 1) BATTERY_LEVEL_FULL>; + + color-0 { + led-color = <&color_white>; + }; + }; + + power-state-discharge-s0-batt-low { + charge-state = "PWR_STATE_DISCHARGE"; + chipset-state = "POWER_S0"; + /* Battery percent range (>= Empty, <= Low) */ + batt-lvl = <BATTERY_LEVEL_EMPTY BATTERY_LEVEL_LOW>; + + /* White 2 sec, off 1 sec */ + color-0 { + led-color = <&color_white>; + period-ms = <2000>; + }; + color-1 { + led-color = <&color_off>; + period-ms = <1000>; + }; + }; + + power-state-discharge-s3 { + charge-state = "PWR_STATE_DISCHARGE"; + chipset-state = "POWER_S3"; + + /* White 1 sec, off 1 sec */ + color-0 { + led-color = <&color_white>; + period-ms = <1000>; + }; + color-1 { + led-color = <&color_off>; + period-ms = <1000>; + }; + }; + + power-state-discharge-s5 { + charge-state = "PWR_STATE_DISCHARGE"; + chipset-state = "POWER_S5"; + + color-0 { + led-color = <&color_off>; + }; + }; + + power-state-error { + charge-state = "PWR_STATE_ERROR"; + + /* Amber 1 sec, off 1 sec */ + color-0 { + led-color = <&color_amber>; + period-ms = <1000>; + }; + color-1 { + led-color = <&color_off>; + period-ms = <1000>; + }; + }; + + power-state-near-full { + charge-state = "PWR_STATE_CHARGE_NEAR_FULL"; + + color-0 { + led-color = <&color_white>; + }; + }; + + power-state-forced-idle { + charge-state = "PWR_STATE_FORCED_IDLE"; + + /* Amber 2 sec, White 2 sec */ + color-0 { + led-color = <&color_amber>; + period-ms = <2000>; + }; + color-1 { + led-color = <&color_white>; + period-ms = <2000>; + }; + }; + }; +}; diff --git a/zephyr/projects/skyrim/led_policy_skyrim.dts b/zephyr/projects/skyrim/led_policy_skyrim.dts new file mode 100644 index 0000000000..a075c6b0d2 --- /dev/null +++ b/zephyr/projects/skyrim/led_policy_skyrim.dts @@ -0,0 +1,103 @@ +#include <dt-bindings/battery.h> + +/ { + led-colors { + compatible = "cros-ec,led-policy"; + + power-state-charge { + charge-state = "PWR_STATE_CHARGE"; + + color-0 { + led-color = <&color_amber>; + }; + }; + + power-state-discharge-s0 { + charge-state = "PWR_STATE_DISCHARGE"; + chipset-state = "POWER_S0"; + /* Battery percent range (> Low, <= Full) */ + batt-lvl = <(BATTERY_LEVEL_LOW + 1) BATTERY_LEVEL_FULL>; + + color-0 { + led-color = <&color_white>; + }; + }; + + power-state-discharge-s0-batt-low { + charge-state = "PWR_STATE_DISCHARGE"; + chipset-state = "POWER_S0"; + /* Battery percent range (>= Empty, <= Low) */ + batt-lvl = <BATTERY_LEVEL_EMPTY BATTERY_LEVEL_LOW>; + + /* White 2 sec, off 1 sec */ + color-0 { + led-color = <&color_white>; + period-ms = <2000>; + }; + color-1 { + led-color = <&color_off>; + period-ms = <1000>; + }; + }; + + power-state-discharge-s3 { + charge-state = "PWR_STATE_DISCHARGE"; + chipset-state = "POWER_S3"; + + /* White 1 sec, off 1 sec */ + color-0 { + led-color = <&color_white>; + period-ms = <1000>; + }; + color-1 { + led-color = <&color_off>; + period-ms = <1000>; + }; + }; + + power-state-discharge-s5 { + charge-state = "PWR_STATE_DISCHARGE"; + chipset-state = "POWER_S5"; + + color-0 { + led-color = <&color_off>; + }; + }; + + power-state-error { + charge-state = "PWR_STATE_ERROR"; + + /* Amber 1 sec, off 1 sec */ + color-0 { + led-color = <&color_amber>; + period-ms = <1000>; + }; + color-1 { + led-color = <&color_off>; + period-ms = <1000>; + }; + }; + + power-state-near-full { + charge-state = "PWR_STATE_CHARGE_NEAR_FULL"; + + color-0 { + led-color = <&color_white>; + }; + }; + + power-state-forced-idle { + charge-state = "PWR_STATE_FORCED_IDLE"; + + /* Amber 2 sec, White 2 sec */ + color-0 { + led-color = <&color_amber>; + period-ms = <2000>; + }; + color-1 { + led-color = <&color_white>; + period-ms = <2000>; + }; + }; + }; +}; diff --git a/zephyr/projects/skyrim/led_policy_winterhold.dts b/zephyr/projects/skyrim/led_policy_winterhold.dts new file mode 100644 index 0000000000..f1f8aa31ed --- /dev/null +++ b/zephyr/projects/skyrim/led_policy_winterhold.dts @@ -0,0 +1,103 @@ +#include <dt-bindings/battery.h> + +/ { + led-colors { + compatible = "cros-ec,led-policy"; + + power-state-charge { + charge-state = "PWR_STATE_CHARGE"; + color-0 { + led-color = <&color_white>; + }; + }; + + power-state-discharge-s0 { + charge-state = "PWR_STATE_DISCHARGE"; + chipset-state = "POWER_S0"; + /* Battery percent range (> Low, <= Full) */ + batt-lvl = <(BATTERY_LEVEL_LOW + 1) BATTERY_LEVEL_FULL>; + + color-0 { + led-color = <&color_off>; + }; + }; + + power-state-discharge-s0-batt-low { + charge-state = "PWR_STATE_DISCHARGE"; + chipset-state = "POWER_S0"; + /* Battery percent range (>= Empty, <= Low) */ + batt-lvl = <BATTERY_LEVEL_EMPTY BATTERY_LEVEL_LOW>; + + color-0 { + led-color = <&color_amber>; + }; + }; + + power-state-discharge-s3 { + charge-state = "PWR_STATE_DISCHARGE"; + chipset-state = "POWER_S3"; + /* Battery percent range (> Low, <= Full) */ + batt-lvl = <(BATTERY_LEVEL_LOW + 1) BATTERY_LEVEL_FULL>; + + color-0 { + led-color = <&color_off>; + }; + }; + + power-state-discharge-s3-batt-low { + charge-state = "PWR_STATE_DISCHARGE"; + chipset-state = "POWER_S3"; + /* Battery percent range (>= Empty, <= Low) */ + batt-lvl = <BATTERY_LEVEL_EMPTY BATTERY_LEVEL_LOW>; + + color-0 { + led-color = <&color_amber>; + }; + }; + + power-state-discharge-s5 { + charge-state = "PWR_STATE_DISCHARGE"; + chipset-state = "POWER_S5"; + + color-0 { + led-color = <&color_off>; + }; + }; + + power-state-error { + charge-state = "PWR_STATE_ERROR"; + + /* Amber 1 sec, off 1 sec */ + color-0 { + led-color = <&color_amber>; + period-ms = <1000>; + }; + color-1 { + led-color = <&color_off>; + period-ms = <1000>; + }; + }; + + power-state-near-full { + charge-state = "PWR_STATE_CHARGE_NEAR_FULL"; + + color-0 { + led-color = <&color_off>; + }; + }; + + power-state-forced-idle { + charge-state = "PWR_STATE_FORCED_IDLE"; + + /* Amber 2 sec, White 2 sec */ + color-0 { + led-color = <&color_amber>; + period-ms = <2000>; + }; + color-1 { + led-color = <&color_white>; + period-ms = <2000>; + }; + }; + }; +}; diff --git a/zephyr/projects/skyrim/morthal.dts b/zephyr/projects/skyrim/morthal.dts new file mode 100644 index 0000000000..508ce23bce --- /dev/null +++ b/zephyr/projects/skyrim/morthal.dts @@ -0,0 +1,183 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <dt-bindings/usbc_mux.h> + +#include "i2c_common.dtsi" + +/ { + named-gpios { + /* Morthal-specific GPIO customizations */ + }; + + named-temp-sensors { + compatible = "cros-ec,temp-sensors"; + soc-pct2075 { + temp_host_high = <100>; + temp_host_halt = <105>; + temp_host_release_high = <80>; + temp_host_release_halt = <80>; + temp_fan_off = <0>; + temp_fan_max = <70>; + power-good-pin = <&gpio_pg_pwr_s5>; + sensor = <&soc_pct2075>; + }; + amb-pct2075 { + power-good-pin = <&gpio_pg_pwr_s5>; + sensor = <&amb_pct2075>; + }; + }; + + /* + * Note this is expected to vary per-board, so we keep it in the board + * dts files. + */ + morthal-fw-config { + compatible = "cros-ec,cbi-fw-config"; + + form-factor { + enum-name = "FW_FORM_FACTOR"; + start = <0>; + size = <1>; + + ff-clamshell { + compatible = "cros-ec,cbi-fw-config-value"; + enum-name = "FW_FF_CLAMSHELL"; + value = <0>; + }; + ff-convertible { + compatible = "cros-ec,cbi-fw-config-value"; + enum-name = "FW_FF_CONVERTIBLE"; + value = <1>; + default; + }; + }; + io-db { + enum-name = "FW_IO_DB"; + start = <6>; + size = <2>; + + io-db-ps8811-ps8818 { + compatible = "cros-ec,cbi-fw-config-value"; + enum-name = "FW_IO_DB_PS8811_PS8818"; + value = <0>; + }; + io-db-none-anx7483 { + compatible = "cros-ec,cbi-fw-config-value"; + enum-name = "FW_IO_DB_NONE_ANX7483"; + value = <1>; + default; + }; + }; + + /* + * FW_CONFIG field to enable fan or not. + */ + fan { + enum-name = "FW_FAN"; + start = <10>; + size = <1>; + + no-fan { + compatible = "cros-ec,cbi-fw-config-value"; + enum-name = "FW_FAN_NOT_PRESENT"; + value = <0>; + }; + fan-present { + compatible = "cros-ec,cbi-fw-config-value"; + enum-name = "FW_FAN_PRESENT"; + value = <1>; + /* + * Set as default so that unprovisioned + * configs will run the fan regardless. + */ + default; + }; + }; + }; + + /* Rotation matrices for motion sensors. */ + motionsense-rotation-ref { + compatible = "cros-ec,motionsense-rotation-ref"; + lid_rot_ref: lid-rotation-ref { + mat33 = <0 (-1) 0 + 1 0 0 + 0 0 1>; + }; + + lid_rot_ref1: lid-rotation-ref1 { + mat33 = <0 1 0 + (-1) 0 0 + 0 0 1>; + }; + + base_rot_ref: base-rotation-ref { + mat33 = <0 1 0 + (-1) 0 0 + 0 0 1>; + }; + }; + + ppc_port0: aoz1380 { + compatible = "aoz,aoz1380"; + status = "okay"; + }; +}; + +&i2c0_0 { + anx7483_port0: anx7483@3e { + compatible = "analogix,anx7483"; + reg = <0x3e>; + board-set = "board_anx7483_c0_mux_set"; + }; +}; + +&i2c1_0 { + anx7483_port1: anx7483@3e { + compatible = "analogix,anx7483"; + reg = <0x3e>; + board-set = "board_anx7483_c1_mux_set"; + }; + ppc_port1: nx20p348x@71 { + compatible = "nxp,nx20p348x"; + status = "okay"; + reg = <0x71>; + }; + ps8818_port1: ps8818@28 { + compatible = "parade,ps8818"; + reg = <0x28>; + flags = <(USB_MUX_FLAG_RESETS_IN_G3)>; + board-set = "board_c1_ps8818_mux_set"; + }; +}; + +&i2c4_1 { + charger: isl9241@9 { + compatible = "intersil,isl9241"; + status = "okay"; + reg = <0x9>; + }; +}; + +&usbc_port0 { + ppc = <&ppc_port0>; + usb-mux-chain-0 { + compatible = "cros-ec,usb-mux-chain"; + usb-muxes = <&amd_fp6_port0 &anx7483_port0>; + }; +}; + +&usbc_port1 { + ppc = <&ppc_port1>; + usb-mux-chain-1-anx { + compatible = "cros-ec,usb-mux-chain"; + usb-muxes = <&amd_fp6_port1 &anx7483_port1>; + }; + usb_mux_chain_ps8818_port1: usb-mux-chain-1-ps { + compatible = "cros-ec,usb-mux-chain"; + usb-muxes = <&amd_fp6_port1 &ps8818_port1>; + alternative-chain; + }; +}; diff --git a/zephyr/projects/skyrim/motionsense.dts b/zephyr/projects/skyrim/motionsense.dts new file mode 100644 index 0000000000..f943bea4c8 --- /dev/null +++ b/zephyr/projects/skyrim/motionsense.dts @@ -0,0 +1,135 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <dt-bindings/motionsense/utils.h> + + +/ { + aliases { + /* + * motion sense's <>_INT_EVENT is handled + * by alias. Using the alias, each driver creates + * its own <>_INT_EVENT. + */ + bmi3xx-int = &base_accel; + }; + + /* + * Declare mutexes used by sensor drivers. + * A mutex node is used to create an instance of mutex_t. + * A mutex node is referenced by a sensor node if the + * corresponding sensor driver needs to use the + * instance of the mutex. + */ + motionsense-mutex { + compatible = "cros-ec,motionsense-mutex"; + lid_mutex: lid-mutex { + }; + + mutex_bmi3xx: bmi3xx-mutex { + }; + }; + + /* + * Driver specific data. A driver-specific data can be shared with + * different motion sensors while they are using the same driver. + * + * If a node's compatible starts with "cros-ec,accelgyro-", it is for + * a common structure defined in accelgyro.h. + * e.g) compatible = "cros-ec,accelgyro-als-drv-data" is for + * "struct als_drv_data_t" in accelgyro.h + */ + motionsense-sensor-data { + bma4xx_data: bma4xx-drv-data { + compatible = "cros-ec,drvdata-bma4xx"; + status = "okay"; + }; + + bmi3xx_data: bmi3xx-drv-data { + compatible = "cros-ec,drvdata-bmi3xx"; + status = "okay"; + }; + }; + + /* + * List of motion sensors that creates motion_sensors array. + * The nodelabel "lid_accel" and "base_accel" are used to indicate + * motion sensor IDs for lid angle calculation. + */ + motionsense-sensor { + lid_accel: lid-accel { + compatible = "cros-ec,bma4xx"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_LID"; + mutex = <&lid_mutex>; + port = <&i2c_sensor>; + drv-data = <&bma4xx_data>; + rot-standard-ref = <&lid_rot_ref>; + default-range = <2>; + configs { + compatible = + "cros-ec,motionsense-sensor-config"; + ec-s0 { + odr = <(12500 | ROUND_UP_FLAG)>; + ec-rate = <100>; + }; + ec-s3 { + odr = <(12500 | ROUND_UP_FLAG)>; + }; + }; + }; + + base_accel: base-accel { + compatible = "cros-ec,bmi3xx-accel"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_BASE"; + mutex = <&mutex_bmi3xx>; + port = <&i2c_sensor>; + rot-standard-ref = <&base_rot_ref>; + drv-data = <&bmi3xx_data>; + + configs { + compatible = + "cros-ec,motionsense-sensor-config"; + ec-s0 { + odr = <(12500 | ROUND_UP_FLAG)>; + ec-rate = <100>; + }; + ec-s3 { + odr = <(12500 | ROUND_UP_FLAG)>; + }; + }; + }; + + base-gyro { + compatible = "cros-ec,bmi3xx-gyro"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_BASE"; + mutex = <&mutex_bmi3xx>; + port = <&i2c_sensor>; + rot-standard-ref = <&base_rot_ref>; + drv-data = <&bmi3xx_data>; + }; + }; + + motionsense-sensor-info { + compatible = "cros-ec,motionsense-sensor-info"; + + /* + * list of GPIO interrupts that have to + * be enabled at initial stage + */ + sensor-irqs = <&int_accel_gyro>; + + /* list of sensors in force mode */ + accel-force-mode-sensors = <&lid_accel>; + }; +}; diff --git a/zephyr/projects/skyrim/prj.conf b/zephyr/projects/skyrim/prj.conf new file mode 100644 index 0000000000..a0085258e4 --- /dev/null +++ b/zephyr/projects/skyrim/prj.conf @@ -0,0 +1,167 @@ +# Copyright 2021 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +CONFIG_CROS_EC=y +CONFIG_PLATFORM_EC=y +CONFIG_SHIMMED_TASKS=y +CONFIG_ESPI=y + +# Shell features +CONFIG_SHELL_HELP=y +CONFIG_SHELL_HISTORY=y +CONFIG_SHELL_TAB=y +CONFIG_SHELL_TAB_AUTOCOMPLETION=y +CONFIG_KERNEL_SHELL=y + +# Power sequencing +CONFIG_AP=y +CONFIG_AP_X86_AMD=y +CONFIG_PLATFORM_EC_POWERSEQ=y +CONFIG_PLATFORM_EC_POWER_BUTTON_TO_PCH_CUSTOM=y +CONFIG_PLATFORM_EC_POWER_SLEEP_FAILURE_DETECTION=y +CONFIG_PLATFORM_EC_POWERSEQ_RSMRST_DELAY=y +CONFIG_PLATFORM_EC_POWERSEQ_S0IX=y +CONFIG_PLATFORM_EC_PORT80=y + +# Power button +CONFIG_PLATFORM_EC_POWER_BUTTON=y + +# ADC +CONFIG_ADC=y + +# I2C +CONFIG_I2C=y + +# CBI +CONFIG_EEPROM=y +CONFIG_EEPROM_AT24=y +CONFIG_EEPROM_SHELL=n +CONFIG_PLATFORM_EC_BOARD_VERSION_CBI=y +CONFIG_PLATFORM_EC_CBI_EEPROM=y + +# Temperature Sensors +CONFIG_PLATFORM_EC_AMD_SB_RMI=y +CONFIG_PLATFORM_EC_AMD_STT=y +CONFIG_PLATFORM_EC_TEMP_SENSOR=y +CONFIG_PLATFORM_EC_TEMP_SENSOR_SB_TSI=y +CONFIG_PLATFORM_EC_THERMISTOR=y +CONFIG_PLATFORM_EC_THROTTLE_AP=y + +# External power +CONFIG_PLATFORM_EC_HOSTCMD=y +CONFIG_PLATFORM_EC_EXTPOWER_GPIO=y +CONFIG_PLATFORM_EC_BACKLIGHT_LID=y +CONFIG_PLATFORM_EC_BACKLIGHT_LID_ACTIVE_LOW=y + +# Sensors +CONFIG_SENSOR=y +CONFIG_SENSOR_SHELL=n + +# Fan +CONFIG_TACH_NPCX=y + +# Lid switch +CONFIG_PLATFORM_EC_LID_ANGLE=y +CONFIG_PLATFORM_EC_LID_ANGLE_UPDATE=y +CONFIG_PLATFORM_EC_LID_SWITCH=y + +# Keyboard +CONFIG_PLATFORM_EC_KBLIGHT_ENABLE_PIN=y +CONFIG_PLATFORM_EC_KEYBOARD=y +CONFIG_PLATFORM_EC_KEYBOARD_COL2_INVERTED=y +CONFIG_PLATFORM_EC_VOLUME_BUTTONS=y +CONFIG_PLATFORM_EC_KEYBOARD_PWRBTN_ASSERTS_KSI3=y +CONFIG_PLATFORM_EC_KEYBOARD_REFRESH_ROW3=y + +# PWM +CONFIG_PWM=y +CONFIG_PWM_SHELL=n + +CONFIG_SYSCON=y + +# Battery +CONFIG_PLATFORM_EC_BATTERY=y +CONFIG_PLATFORM_EC_BATTERY_SMART=y +CONFIG_PLATFORM_EC_BATTERY_FUEL_GAUGE=y +CONFIG_PLATFORM_EC_BATTERY_CUT_OFF=y +CONFIG_PLATFORM_EC_BATTERY_PRESENT_GPIO=y +CONFIG_PLATFORM_EC_BATTERY_REVIVE_DISCONNECT=y + +# Charger +CONFIG_PLATFORM_EC_CHARGER_DISCHARGE_ON_AC=y +CONFIG_PLATFORM_EC_CHARGER_INPUT_CURRENT=512 +CONFIG_PLATFORM_EC_CHARGER_ISL9241=y +CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR=10 +CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR_AC=20 +CONFIG_PLATFORM_EC_CHARGER_MIN_POWER_MW_FOR_POWER_ON=50000 + +# USB-A +CONFIG_PLATFORM_EC_USBA=y + +# USB-C +CONFIG_PLATFORM_EC_BC12_DETECT_PI3USB9201=y +CONFIG_PLATFORM_EC_USBC_PPC_NX20P3483=y +CONFIG_PLATFORM_EC_USBC_PPC_AOZ1380=y +CONFIG_PLATFORM_EC_USBC_RETIMER_ANX7451=y +CONFIG_PLATFORM_EC_USBC_RETIMER_PS8811=y +CONFIG_PLATFORM_EC_USBC_RETIMER_PS8818=y +CONFIG_PLATFORM_EC_USBC_SS_MUX_DFP_ONLY=y +CONFIG_PLATFORM_EC_USB_MUX_AMD_FP6=y +CONFIG_PLATFORM_EC_USB_MUX_RUNTIME_CONFIG=y +CONFIG_PLATFORM_EC_USB_DRP_ACC_TRYSRC=y +CONFIG_PLATFORM_EC_USB_PID=0x505F +CONFIG_PLATFORM_EC_USB_PD_5V_EN_CUSTOM=y +CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_TCPC=y +CONFIG_PLATFORM_EC_USB_PD_DISCHARGE_TCPC=y +CONFIG_PLATFORM_EC_USB_PD_DP_HPD_GPIO=y +CONFIG_PLATFORM_EC_USB_PD_FRS=y +CONFIG_PLATFORM_EC_USB_PD_FRS_TCPC=y +CONFIG_PLATFORM_EC_USB_PD_LOGGING=y +CONFIG_PLATFORM_EC_USB_PD_REV30=y +CONFIG_PLATFORM_EC_USB_PD_TBT_COMPAT_MODE=n +CONFIG_PLATFORM_EC_USB_PD_TCPC_LOW_POWER=y +CONFIG_PLATFORM_EC_USB_PD_TCPM_NCT38XX=y +CONFIG_PLATFORM_EC_USB_PD_TCPC_RUNTIME_CONFIG=n +CONFIG_PLATFORM_EC_USB_PD_USB4=n +CONFIG_PLATFORM_EC_USB_PD_VBUS_MEASURE_CHARGER=y +# Give ourselves enough task space to use i2ctrace +CONFIG_TASK_PD_STACK_SIZE=1280 + +# IOEX +CONFIG_GPIO_NCT38XX=y + +# Motion sense +CONFIG_PLATFORM_EC_MOTIONSENSE=y +CONFIG_PLATFORM_EC_ACCEL_FIFO=y +CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCELS=y +CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCEL_INFO=y +CONFIG_PLATFORM_EC_LID_ANGLE=y +CONFIG_PLATFORM_EC_LID_ANGLE_UPDATE=y +CONFIG_PLATFORM_EC_SENSOR_TIGHT_TIMESTAMPS=y + +CONFIG_PLATFORM_EC_MKBP_EVENT=y +CONFIG_PLATFORM_EC_MKBP_INPUT_DEVICES=y +CONFIG_PLATFORM_EC_MKBP_USE_GPIO=y + +CONFIG_PLATFORM_EC_TABLET_MODE=y +CONFIG_PLATFORM_EC_TABLET_MODE_SWITCH=y +CONFIG_PLATFORM_EC_GMR_TABLET_MODE=y + +CONFIG_PLATFORM_EC_ACCEL_BMA4XX=y +CONFIG_PLATFORM_EC_ACCELGYRO_BMI3XX=y +CONFIG_PLATFORM_EC_ACCELGYRO_BMI_COMM_I2C=y + +# Misc. +CONFIG_PLATFORM_EC_I2C_DEBUG=y +CONFIG_PLATFORM_EC_PORT80_4_BYTE=y + +# These are debug options that happen to be expensive in terms of flash space. +# Turn on as needed based on demand. +CONFIG_FLASH_PAGE_LAYOUT=n # 1876 bytes +CONFIG_FLASH_SHELL=n # 1852 bytes +CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCEL_INFO=n # 656 bytes +CONFIG_PLATFORM_EC_CONSOLE_CMD_MEM=n # 896 bytes +# CONFIG_PLATFORM_EC_CONSOLE_CMD_TCPC_DUMP=n # 1180 bytes +CONFIG_PLATFORM_EC_CONSOLE_CMD_USB_PD_CABLE=n # 1104 bytes +CONFIG_THREAD_MONITOR=n # 1548 bytes diff --git a/zephyr/projects/skyrim/prj_frostflow.conf b/zephyr/projects/skyrim/prj_frostflow.conf new file mode 100644 index 0000000000..29931de4d4 --- /dev/null +++ b/zephyr/projects/skyrim/prj_frostflow.conf @@ -0,0 +1,30 @@ +# Copyright 2022 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +# Frostflow reference-board-specific Kconfig settings. +CONFIG_BOARD_FROSTFLOW=y +CONFIG_BOARD_INPUT_CURRENT_SCALE_FACTOR=90 + +# TODO(b/215404321): Remove later in board development +CONFIG_PLATFORM_EC_EEPROM_CBI_WP=y +CONFIG_PLATFORM_EC_SYSTEM_UNLOCKED=y + +# LED +CONFIG_PLATFORM_EC_LED_DT=y + +# Frostflow is capable of sinking 45W +CONFIG_PLATFORM_EC_PD_MAX_POWER_MW=45000 +CONFIG_PLATFORM_EC_PD_MAX_CURRENT_MA=3000 +CONFIG_PLATFORM_EC_PD_MAX_VOLTAGE_MV=20000 +CONFIG_PLATFORM_EC_CHARGER_MIN_POWER_MW_FOR_POWER_ON=15000 +# Only Frostflow has the PCT2075 +CONFIG_PLATFORM_EC_TEMP_SENSOR_PCT2075=y + +CONFIG_PLATFORM_EC_USBC_RETIMER_ANX7483=y + +# Keyboard +CONFIG_PLATFORM_EC_KEYBOARD_CUSTOMIZATION=y + +# Frostflow not have the USB HUB +CONFIG_BOARD_USB_HUB_RESET=n diff --git a/zephyr/projects/skyrim/prj_morthal.conf b/zephyr/projects/skyrim/prj_morthal.conf new file mode 100644 index 0000000000..3d2b3fddb7 --- /dev/null +++ b/zephyr/projects/skyrim/prj_morthal.conf @@ -0,0 +1,23 @@ +# Copyright 2022 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +# Morthal reference-board-specific Kconfig settings. +CONFIG_BOARD_MORTHAL=y + +# TODO(b/215404321): Remove later in board development +CONFIG_PLATFORM_EC_EEPROM_CBI_WP=y +CONFIG_PLATFORM_EC_SYSTEM_UNLOCKED=y + +# LED +CONFIG_PLATFORM_EC_LED_DT=y + +# Morthal is capable of sinking 100W +CONFIG_PLATFORM_EC_PD_MAX_POWER_MW=100000 +CONFIG_PLATFORM_EC_PD_MAX_CURRENT_MA=5000 +CONFIG_PLATFORM_EC_PD_MAX_VOLTAGE_MV=20000 + +# Only Morthal has the PCT2075 +CONFIG_PLATFORM_EC_TEMP_SENSOR_PCT2075=y + +CONFIG_PLATFORM_EC_USBC_RETIMER_ANX7483=y diff --git a/zephyr/projects/skyrim/prj_skyrim.conf b/zephyr/projects/skyrim/prj_skyrim.conf new file mode 100644 index 0000000000..2752854c8b --- /dev/null +++ b/zephyr/projects/skyrim/prj_skyrim.conf @@ -0,0 +1,26 @@ +# Copyright 2021 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +# Skyrim reference-board-specific Kconfig settings. +CONFIG_BOARD_SKYRIM=y + +# CBI WP pin present +CONFIG_PLATFORM_EC_EEPROM_CBI_WP=y + +# LED +CONFIG_PLATFORM_EC_LED_DT=y + +# Skyrim is capable of sinking 100W +CONFIG_PLATFORM_EC_PD_MAX_POWER_MW=100000 +CONFIG_PLATFORM_EC_PD_MAX_CURRENT_MA=5000 +CONFIG_PLATFORM_EC_PD_MAX_VOLTAGE_MV=20000 + +# Only Skyrim has the PCT2075 +CONFIG_PLATFORM_EC_TEMP_SENSOR_PCT2075=y + +CONFIG_PLATFORM_EC_USBC_RETIMER_ANX7483=y + +# Enable alternative charger chip +CONFIG_PLATFORM_EC_CHARGER_RUNTIME_CONFIG=y +CONFIG_PLATFORM_EC_CHARGER_ISL9238C=y diff --git a/zephyr/projects/skyrim/prj_winterhold.conf b/zephyr/projects/skyrim/prj_winterhold.conf new file mode 100644 index 0000000000..2ccd195a72 --- /dev/null +++ b/zephyr/projects/skyrim/prj_winterhold.conf @@ -0,0 +1,26 @@ +# Copyright 2022 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +# Winterhold reference-board-specific Kconfig settings. +CONFIG_BOARD_WINTERHOLD=y + +# TODO(b/215404321): Remove later in board development +CONFIG_PLATFORM_EC_EEPROM_CBI_WP=y +CONFIG_PLATFORM_EC_SYSTEM_UNLOCKED=y + +# LED +CONFIG_PLATFORM_EC_LED_DT=y + +# Only Winterhold has the PCT2075 +CONFIG_PLATFORM_EC_TEMP_SENSOR_PCT2075=y + +CONFIG_PLATFORM_EC_USBC_RETIMER_ANX7483=y + +# Enable charger chip +CONFIG_PLATFORM_EC_CHARGER_ISL9238=y +CONFIG_PLATFORM_EC_CHARGER_ISL9241=n + +# Get the vbus voltage from TCPC +CONFIG_PLATFORM_EC_USB_PD_VBUS_MEASURE_CHARGER=n +CONFIG_PLATFORM_EC_USB_PD_VBUS_MEASURE_TCPC=y
\ No newline at end of file diff --git a/zephyr/projects/skyrim/skyrim.dts b/zephyr/projects/skyrim/skyrim.dts new file mode 100644 index 0000000000..6a812a55f3 --- /dev/null +++ b/zephyr/projects/skyrim/skyrim.dts @@ -0,0 +1,207 @@ +/* Copyright 2021 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <dt-bindings/usbc_mux.h> + +#include "i2c_common.dtsi" + +/ { + named-gpios { + /* Skyrim-specific GPIO customizations */ + }; + + named-temp-sensors { + compatible = "cros-ec,temp-sensors"; + soc-pct2075 { + temp_host_high = <100>; + temp_host_halt = <105>; + temp_host_release_high = <80>; + temp_host_release_halt = <80>; + temp_fan_off = <35>; + temp_fan_max = <70>; + power-good-pin = <&gpio_pg_pwr_s5>; + sensor = <&soc_pct2075>; + }; + amb-pct2075 { + power-good-pin = <&gpio_pg_pwr_s5>; + sensor = <&amb_pct2075>; + }; + }; + + /* + * Note this is expected to vary per-board, so we keep it in the board + * dts files. + */ + skyrim-fw-config { + compatible = "cros-ec,cbi-fw-config"; + + form-factor { + enum-name = "FW_FORM_FACTOR"; + start = <0>; + size = <1>; + + ff-clamshell { + compatible = "cros-ec,cbi-fw-config-value"; + enum-name = "FW_FF_CLAMSHELL"; + value = <0>; + }; + ff-convertible { + compatible = "cros-ec,cbi-fw-config-value"; + enum-name = "FW_FF_CONVERTIBLE"; + value = <1>; + default; + }; + }; + io-db { + enum-name = "FW_IO_DB"; + start = <6>; + size = <2>; + + io-db-ps8811-ps8818 { + compatible = "cros-ec,cbi-fw-config-value"; + enum-name = "FW_IO_DB_PS8811_PS8818"; + value = <0>; + }; + io-db-none-anx7483 { + compatible = "cros-ec,cbi-fw-config-value"; + enum-name = "FW_IO_DB_NONE_ANX7483"; + value = <1>; + default; + }; + }; + + /* + * FW_CONFIG field to enable fan or not. + */ + fan { + enum-name = "FW_FAN"; + start = <10>; + size = <1>; + + no-fan { + compatible = "cros-ec,cbi-fw-config-value"; + enum-name = "FW_FAN_NOT_PRESENT"; + value = <0>; + }; + fan-present { + compatible = "cros-ec,cbi-fw-config-value"; + enum-name = "FW_FAN_PRESENT"; + value = <1>; + /* + * Set as default so that unprovisioned + * configs will run the fan regardless. + */ + default; + }; + }; + + charger-option { + enum-name = "FW_CHARGER"; + start = <11>; + size = <2>; + + charger-option-isl9241 { + compatible = "cros-ec,cbi-fw-config-value"; + enum-name = "FW_CHARGER_ISL9241"; + value = <0>; + default; + }; + charger-option-isl9538 { + compatible = "cros-ec,cbi-fw-config-value"; + enum-name = "FW_CHARGER_ISL9538"; + value = <1>; + }; + }; + }; + + /* Rotation matrices for motion sensors. */ + motionsense-rotation-ref { + compatible = "cros-ec,motionsense-rotation-ref"; + lid_rot_ref: lid-rotation-ref { + mat33 = <0 (-1) 0 + 1 0 0 + 0 0 1>; + }; + + lid_rot_ref1: lid-rotation-ref1 { + mat33 = <0 1 0 + (-1) 0 0 + 0 0 1>; + }; + + base_rot_ref: base-rotation-ref { + mat33 = <0 1 0 + (-1) 0 0 + 0 0 1>; + }; + }; + + ppc_port0: aoz1380 { + compatible = "aoz,aoz1380"; + status = "okay"; + }; +}; + +&i2c0_0 { + anx7483_port0: anx7483@3e { + compatible = "analogix,anx7483"; + reg = <0x3e>; + board-set = "board_anx7483_c0_mux_set"; + }; +}; + +&i2c1_0 { + anx7483_port1: anx7483@3e { + compatible = "analogix,anx7483"; + reg = <0x3e>; + board-set = "board_anx7483_c1_mux_set"; + }; + ppc_port1: nx20p348x@71 { + compatible = "nxp,nx20p348x"; + status = "okay"; + reg = <0x71>; + }; + ps8818_port1: ps8818@28 { + compatible = "parade,ps8818"; + reg = <0x28>; + flags = <(USB_MUX_FLAG_RESETS_IN_G3)>; + board-set = "board_c1_ps8818_mux_set"; + }; +}; + +&i2c4_1 { + charger: isl9241@9 { + compatible = "intersil,isl9241"; + status = "okay"; + reg = <0x9>; + }; + alt_charger: isl9538@9 { + compatible = "intersil,isl923x"; + status = "okay"; + reg = <0x9>; + }; +}; + +&usbc_port0 { + chg_alt = <&alt_charger>; + ppc = <&ppc_port0>; + usb-mux-chain-0 { + compatible = "cros-ec,usb-mux-chain"; + usb-muxes = <&amd_fp6_port0 &anx7483_port0>; + }; +}; + +&usbc_port1 { + ppc = <&ppc_port1>; + usb-mux-chain-1-anx { + compatible = "cros-ec,usb-mux-chain"; + usb-muxes = <&amd_fp6_port1 &anx7483_port1>; + }; + usb_mux_chain_ps8818_port1: usb-mux-chain-1-ps { + compatible = "cros-ec,usb-mux-chain"; + usb-muxes = <&amd_fp6_port1 &ps8818_port1>; + alternative-chain; + }; +}; diff --git a/zephyr/projects/skyrim/src/common.c b/zephyr/projects/skyrim/src/common.c new file mode 100644 index 0000000000..af82139c1b --- /dev/null +++ b/zephyr/projects/skyrim/src/common.c @@ -0,0 +1,8 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <zephyr/logging/log.h> + +LOG_MODULE_REGISTER(skyrim, CONFIG_SKYRIM_LOG_LEVEL); diff --git a/zephyr/projects/skyrim/src/frostflow/keyboard.c b/zephyr/projects/skyrim/src/frostflow/keyboard.c new file mode 100644 index 0000000000..2905f17941 --- /dev/null +++ b/zephyr/projects/skyrim/src/frostflow/keyboard.c @@ -0,0 +1,74 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "ec_commands.h" +#include "keyboard_scan.h" +#include "timer.h" + +/* Keyboard scan setting */ +__override struct keyboard_scan_config keyscan_config = { + /* Increase from 50 us, because KSO_02 passes through the H1. */ + .output_settle_us = 80, + /* Other values should be the same as the default configuration. */ + .debounce_down_us = 9 * MSEC, + .debounce_up_us = 30 * MSEC, + .scan_period_us = 3 * MSEC, + .min_post_scan_delay_us = 1000, + .poll_timeout_us = 100 * MSEC, + .actual_key_mask = { + 0x1c, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x86, 0xff, 0xff, 0x55, 0xff, 0xff, 0xff, 0xff, /* full set */ + }, +}; + +static const struct ec_response_keybd_config frostflow_kb = { + .num_top_row_keys = 10, + .action_keys = { + TK_BACK, /* T1 */ + TK_REFRESH, /* T2 */ + TK_FULLSCREEN, /* T3 */ + TK_OVERVIEW, /* T4 */ + TK_SNAPSHOT, /* T5 */ + TK_BRIGHTNESS_DOWN, /* T6 */ + TK_BRIGHTNESS_UP, /* T7 */ + TK_VOL_MUTE, /* T8 */ + TK_VOL_DOWN, /* T9 */ + TK_VOL_UP, /* T10 */ + }, + .capabilities = KEYBD_CAP_SCRNLOCK_KEY, +}; + +__override const struct ec_response_keybd_config * +board_vivaldi_keybd_config(void) +{ + return &frostflow_kb; +} + +/* + * Row Column info for Top row keys T1 - T15. + * on frostflow_kb keyboard Row Column is customization + * need define row col to mapping matrix layout. + */ +__override const struct key { + uint8_t row; + uint8_t col; +} vivaldi_keys[] = { + { .row = 4, .col = 2 }, /* T1 */ + { .row = 3, .col = 2 }, /* T2 */ + { .row = 2, .col = 2 }, /* T3 */ + { .row = 1, .col = 2 }, /* T4 */ + { .row = 4, .col = 4 }, /* T5 */ + { .row = 3, .col = 4 }, /* T6 */ + { .row = 2, .col = 4 }, /* T7 */ + { .row = 2, .col = 9 }, /* T8 */ + { .row = 1, .col = 9 }, /* T9 */ + { .row = 1, .col = 4 }, /* T10 */ + { .row = 0, .col = 4 }, /* T11 */ + { .row = 1, .col = 5 }, /* T12 */ + { .row = 3, .col = 5 }, /* T13 */ + { .row = 2, .col = 1 }, /* T14 */ + { .row = 0, .col = 1 }, /* T15 */ +}; +BUILD_ASSERT(ARRAY_SIZE(vivaldi_keys) == MAX_TOP_ROW_KEYS); diff --git a/zephyr/projects/skyrim/src/frostflow/keyboard_customization.c b/zephyr/projects/skyrim/src/frostflow/keyboard_customization.c new file mode 100644 index 0000000000..d176323d80 --- /dev/null +++ b/zephyr/projects/skyrim/src/frostflow/keyboard_customization.c @@ -0,0 +1,85 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <zephyr/drivers/gpio.h> + +#include "common.h" +#include "gpio.h" +#include "keyboard_customization.h" +#include "keyboard_protocol.h" +#include "keyboard_raw.h" + +static uint16_t scancode_set2[KEYBOARD_COLS_MAX][KEYBOARD_ROWS] = { + { 0x0000, 0x0000, 0x0014, 0xe01f, 0xe014, 0x0000, 0x0000, 0x0000 }, + { 0x001f, 0x0076, 0x0017, 0x000e, 0x001c, 0x003a, 0x000d, 0x0016 }, + { 0x006c, 0xe024, 0xe01d, 0xe020, 0xe038, 0xe071, 0x0026, 0x002a }, + { 0x0032, 0x0034, 0x002c, 0x002e, 0x002b, 0x0029, 0x0025, 0x002d }, + { 0x0078, 0xe032, 0xe035, 0xe02c, 0xe02d, 0x0041, 0x001e, 0x001d }, + { 0x0051, 0x0007, 0x005b, 0x000f, 0x0042, 0x0022, 0x003e, 0x0043 }, + { 0x0031, 0x0033, 0x0035, 0x0036, 0x003b, 0x001b, 0x003d, 0x003c }, + { 0x0000, 0x0012, 0x0061, 0x0000, 0x0000, 0x0000, 0x0000, 0x0059 }, + { 0x0055, 0x0052, 0x0054, 0x004e, 0x004c, 0x0024, 0x0044, 0x004d }, + { 0x0045, 0xe021, 0xe023, 0x002f, 0x004b, 0x0049, 0x0046, 0x001a }, + { 0xe011, 0x0000, 0x006a, 0x0000, 0x005d, 0x0000, 0x0011, 0x0000 }, + { 0xe07a, 0x005d, 0xe075, 0x006b, 0x005a, 0xe072, 0x004a, 0x0066 }, + { 0xe06b, 0xe074, 0xe069, 0x0067, 0xe06c, 0x0064, 0x0015, 0xe07d }, + { 0x0073, 0x007c, 0x007b, 0x0074, 0x0071, 0xe04a, 0x0070, 0x0021 }, + { 0x0023, 0xe05a, 0x0075, 0x0079, 0x007a, 0x0072, 0x007d, 0x0069 }, +}; + +uint16_t get_scancode_set2(uint8_t row, uint8_t col) +{ + if (col < KEYBOARD_COLS_MAX && row < KEYBOARD_ROWS) + return scancode_set2[col][row]; + return 0; +} + +void set_scancode_set2(uint8_t row, uint8_t col, uint16_t val) +{ + if (col < KEYBOARD_COLS_MAX && row < KEYBOARD_ROWS) + scancode_set2[col][row] = val; +} + +#ifdef CONFIG_KEYBOARD_DEBUG +static char keycap_label[KEYBOARD_COLS_MAX][KEYBOARD_ROWS] = { + { 'c', KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, + KLLI_UNKNO, KLLI_UNKNO }, + { KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, + KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO }, + { 'q', KLLI_UNKNO, KLLI_UNKNO, KLLI_TAB, '`', '1', KLLI_UNKNO, 'a' }, + { KLLI_R_ALT, KLLI_L_ALT, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, + KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO }, + { KLLI_UNKNO, KLLI_SPACE, 'e', KLLI_F4, KLLI_SEARC, '3', KLLI_F3, + KLLI_UNKNO }, + { 'x', 'z', KLLI_F2, KLLI_F1, 's', '2', 'w', KLLI_ESC }, + { 'v', 'b', 'g', 't', '5', '4', 'r', 'f' }, + { 'm', 'n', 'h', 'y', '6', '7', 'u', 'j' }, + { '.', KLLI_DOWN, '\\', 'o', KLLI_F10, '9', KLLI_UNKNO, 'l' }, + { KLLI_R_SHT, KLLI_L_SHT, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, + KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO }, + { ',', KLLI_UNKNO, KLLI_F7, KLLI_F6, KLLI_F5, '8', 'i', 'k' }, + { KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_F9, KLLI_UNKNO, KLLI_UNKNO, + KLLI_LEFT, KLLI_UNKNO }, + { KLLI_R_CTR, KLLI_L_CTR, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, + KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO }, + { '/', KLLI_UP, '-', KLLI_UNKNO, '0', 'p', '[', ';' }, + { '\'', KLLI_ENTER, KLLI_UNKNO, KLLI_UNKNO, '=', KLLI_B_SPC, ']', 'd' }, + { KLLI_UNKNO, KLLI_F8, KLLI_RIGHT, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, + KLLI_UNKNO, KLLI_UNKNO }, +}; + +char get_keycap_label(uint8_t row, uint8_t col) +{ + if (col < KEYBOARD_COLS_MAX && row < KEYBOARD_ROWS) + return keycap_label[col][row]; + return KLLI_UNKNO; +} + +void set_keycap_label(uint8_t row, uint8_t col, char val) +{ + if (col < KEYBOARD_COLS_MAX && row < KEYBOARD_ROWS) + keycap_label[col][row] = val; +} +#endif diff --git a/zephyr/projects/skyrim/src/frostflow/ppc_config.c b/zephyr/projects/skyrim/src/frostflow/ppc_config.c new file mode 100644 index 0000000000..6072a788eb --- /dev/null +++ b/zephyr/projects/skyrim/src/frostflow/ppc_config.c @@ -0,0 +1,46 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Frostflow board-specific PPC code */ + +#include <zephyr/drivers/gpio.h> + +#include "driver/ppc/nx20p348x.h" +#include "driver/ppc/aoz1380_public.h" +#include "usbc_ppc.h" + +#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args) + +/* + * In the AOZ1380 PPC, there are no programmable features. We use + * the attached NCT3807 to control a GPIO to indicate 1A5 or 3A0 + * current limits. + */ +int board_aoz1380_set_vbus_source_current_limit(int port, enum tcpc_rp_value rp) +{ + int rv = EC_SUCCESS; + + rv = gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(ioex_usb_c0_ilim_3a_en), + (rp == TYPEC_RP_3A0) ? 1 : 0); + + return rv; +} + +void ppc_interrupt(enum gpio_signal signal) +{ + switch (signal) { + case GPIO_USB_C0_PPC_INT_ODL: + aoz1380_interrupt(0); + break; + + case GPIO_USB_C1_PPC_INT_ODL: + nx20p348x_interrupt(1); + break; + + default: + break; + } +} diff --git a/zephyr/projects/skyrim/src/frostflow/usb_mux_config.c b/zephyr/projects/skyrim/src/frostflow/usb_mux_config.c new file mode 100644 index 0000000000..e641e0d649 --- /dev/null +++ b/zephyr/projects/skyrim/src/frostflow/usb_mux_config.c @@ -0,0 +1,123 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Frostflow board-specific USB-C mux configuration */ + +#include <zephyr/drivers/gpio.h> + +#include "console.h" +#include "cros_board_info.h" +#include "cros_cbi.h" +#include "driver/retimer/anx7483_public.h" +#include "hooks.h" +#include "ioexpander.h" +#include "usb_mux.h" +#include "usbc/usb_muxes.h" + +#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args) + +/* + * USB C0 (general) and C1 (just ANX DB) use IOEX pins to + * indicate flipped polarity to a protection switch. + */ +static int ioex_set_flip(int port, mux_state_t mux_state) +{ + if (port == 0) { + if (mux_state & USB_PD_MUX_POLARITY_INVERTED) + gpio_pin_set_dt( + GPIO_DT_FROM_NODELABEL(ioex_usb_c0_sbu_flip), + 1); + else + gpio_pin_set_dt( + GPIO_DT_FROM_NODELABEL(ioex_usb_c0_sbu_flip), + 0); + } else { + if (mux_state & USB_PD_MUX_POLARITY_INVERTED) + gpio_pin_set_dt( + GPIO_DT_FROM_NODELABEL(ioex_usb_c1_sbu_flip), + 1); + else + gpio_pin_set_dt( + GPIO_DT_FROM_NODELABEL(ioex_usb_c1_sbu_flip), + 0); + } + + return EC_SUCCESS; +} + +int board_anx7483_c0_mux_set(const struct usb_mux *me, mux_state_t mux_state) +{ + /* Set the SBU polarity mux */ + RETURN_ERROR(ioex_set_flip(me->usb_port, mux_state)); + + return anx7483_set_default_tuning(me, mux_state); +} + +int board_anx7483_c1_mux_set(const struct usb_mux *me, mux_state_t mux_state) +{ + bool flipped = mux_state & USB_PD_MUX_POLARITY_INVERTED; + + /* Set the SBU polarity mux */ + RETURN_ERROR(ioex_set_flip(me->usb_port, mux_state)); + + /* Remove flipped from the state for easier compraisons */ + mux_state = mux_state & ~USB_PD_MUX_POLARITY_INVERTED; + + RETURN_ERROR(anx7483_set_default_tuning(me, mux_state)); + + if (mux_state == USB_PD_MUX_USB_ENABLED) { + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX1, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX2, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_DRX1, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_DRX2, + ANX7483_EQ_SETTING_12_5DB)); + } else if (mux_state == USB_PD_MUX_DP_ENABLED) { + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX1, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX2, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_UTX1, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_UTX2, + ANX7483_EQ_SETTING_12_5DB)); + } else if (mux_state == USB_PD_MUX_DOCK && !flipped) { + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX1, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX2, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_DRX1, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_UTX2, + ANX7483_EQ_SETTING_12_5DB)); + } else if (mux_state == USB_PD_MUX_DOCK && flipped) { + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX1, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX2, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_UTX1, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_DRX2, + ANX7483_EQ_SETTING_12_5DB)); + } + + return EC_SUCCESS; +} + +int board_c1_ps8818_mux_set(const struct usb_mux *me, mux_state_t mux_state) +{ + CPRINTSUSB("C1: PS8818 mux using default tuning"); + + /* Once a DP connection is established, we need to set IN_HPD */ + if (mux_state & USB_PD_MUX_DP_ENABLED) + ioex_set_level(IOEX_USB_C1_HPD_IN_DB, 1); + else + ioex_set_level(IOEX_USB_C1_HPD_IN_DB, 0); + + return 0; +} diff --git a/zephyr/projects/skyrim/src/morthal/ppc_config.c b/zephyr/projects/skyrim/src/morthal/ppc_config.c new file mode 100644 index 0000000000..f3ec1d312e --- /dev/null +++ b/zephyr/projects/skyrim/src/morthal/ppc_config.c @@ -0,0 +1,46 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Morthal board-specific PPC code */ + +#include <zephyr/drivers/gpio.h> + +#include "driver/ppc/nx20p348x.h" +#include "driver/ppc/aoz1380_public.h" +#include "usbc_ppc.h" + +#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args) + +/* + * In the AOZ1380 PPC, there are no programmable features. We use + * the attached NCT3807 to control a GPIO to indicate 1A5 or 3A0 + * current limits. + */ +int board_aoz1380_set_vbus_source_current_limit(int port, enum tcpc_rp_value rp) +{ + int rv = EC_SUCCESS; + + rv = gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(ioex_usb_c0_ilim_3a_en), + (rp == TYPEC_RP_3A0) ? 1 : 0); + + return rv; +} + +void ppc_interrupt(enum gpio_signal signal) +{ + switch (signal) { + case GPIO_USB_C0_PPC_INT_ODL: + aoz1380_interrupt(0); + break; + + case GPIO_USB_C1_PPC_INT_ODL: + nx20p348x_interrupt(1); + break; + + default: + break; + } +} diff --git a/zephyr/projects/skyrim/src/morthal/usb_mux_config.c b/zephyr/projects/skyrim/src/morthal/usb_mux_config.c new file mode 100644 index 0000000000..8fe76233e2 --- /dev/null +++ b/zephyr/projects/skyrim/src/morthal/usb_mux_config.c @@ -0,0 +1,142 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Morthal board-specific USB-C mux configuration */ + +#include <zephyr/drivers/gpio.h> + +#include "console.h" +#include "cros_board_info.h" +#include "cros_cbi.h" +#include "driver/retimer/anx7483_public.h" +#include "hooks.h" +#include "ioexpander.h" +#include "usb_mux.h" +#include "usbc/usb_muxes.h" + +#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args) + +/* + * USB C0 (general) and C1 (just ANX DB) use IOEX pins to + * indicate flipped polarity to a protection switch. + */ +static int ioex_set_flip(int port, mux_state_t mux_state) +{ + if (port == 0) { + if (mux_state & USB_PD_MUX_POLARITY_INVERTED) + gpio_pin_set_dt( + GPIO_DT_FROM_NODELABEL(ioex_usb_c0_sbu_flip), + 1); + else + gpio_pin_set_dt( + GPIO_DT_FROM_NODELABEL(ioex_usb_c0_sbu_flip), + 0); + } else { + if (mux_state & USB_PD_MUX_POLARITY_INVERTED) + gpio_pin_set_dt( + GPIO_DT_FROM_NODELABEL(ioex_usb_c1_sbu_flip), + 1); + else + gpio_pin_set_dt( + GPIO_DT_FROM_NODELABEL(ioex_usb_c1_sbu_flip), + 0); + } + + return EC_SUCCESS; +} + +int board_anx7483_c0_mux_set(const struct usb_mux *me, mux_state_t mux_state) +{ + /* Set the SBU polarity mux */ + RETURN_ERROR(ioex_set_flip(me->usb_port, mux_state)); + + return anx7483_set_default_tuning(me, mux_state); +} + +int board_anx7483_c1_mux_set(const struct usb_mux *me, mux_state_t mux_state) +{ + bool flipped = mux_state & USB_PD_MUX_POLARITY_INVERTED; + + /* Set the SBU polarity mux */ + RETURN_ERROR(ioex_set_flip(me->usb_port, mux_state)); + + /* Remove flipped from the state for easier compraisons */ + mux_state = mux_state & ~USB_PD_MUX_POLARITY_INVERTED; + + RETURN_ERROR(anx7483_set_default_tuning(me, mux_state)); + + if (mux_state == USB_PD_MUX_USB_ENABLED) { + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX1, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX2, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_DRX1, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_DRX2, + ANX7483_EQ_SETTING_12_5DB)); + } else if (mux_state == USB_PD_MUX_DP_ENABLED) { + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX1, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX2, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_UTX1, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_UTX2, + ANX7483_EQ_SETTING_12_5DB)); + } else if (mux_state == USB_PD_MUX_DOCK && !flipped) { + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX1, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX2, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_DRX1, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_UTX2, + ANX7483_EQ_SETTING_12_5DB)); + } else if (mux_state == USB_PD_MUX_DOCK && flipped) { + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX1, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX2, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_UTX1, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_DRX2, + ANX7483_EQ_SETTING_12_5DB)); + } + + return EC_SUCCESS; +} + +int board_c1_ps8818_mux_set(const struct usb_mux *me, mux_state_t mux_state) +{ + CPRINTSUSB("C1: PS8818 mux using default tuning"); + + /* Once a DP connection is established, we need to set IN_HPD */ + if (mux_state & USB_PD_MUX_DP_ENABLED) + ioex_set_level(IOEX_USB_C1_HPD_IN_DB, 1); + else + ioex_set_level(IOEX_USB_C1_HPD_IN_DB, 0); + + return 0; +} + +static void setup_mux(void) +{ + uint32_t val; + + if (cros_cbi_get_fw_config(FW_IO_DB, &val) != 0) + CPRINTSUSB("Error finding FW_DB_IO in CBI FW_CONFIG"); + /* Val will have our dts default on error, so continue setup */ + + if (val == FW_IO_DB_PS8811_PS8818) { + CPRINTSUSB("C1: Setting PS8818 mux"); + USB_MUX_ENABLE_ALTERNATIVE(usb_mux_chain_ps8818_port1); + } else if (val == FW_IO_DB_NONE_ANX7483) { + CPRINTSUSB("C1: Setting ANX7483 mux"); + } else { + CPRINTSUSB("Unexpected DB_IO board: %d", val); + } +} +DECLARE_HOOK(HOOK_INIT, setup_mux, HOOK_PRIO_INIT_I2C); diff --git a/zephyr/projects/skyrim/src/power_signals.c b/zephyr/projects/skyrim/src/power_signals.c new file mode 100644 index 0000000000..5d372d35ae --- /dev/null +++ b/zephyr/projects/skyrim/src/power_signals.c @@ -0,0 +1,245 @@ +/* Copyright 2021 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "ap_power/ap_power.h" +#include "charger.h" +#include "chipset.h" +#include "config.h" +#include "gpio_signal.h" +#include "gpio/gpio_int.h" +#include "hooks.h" +#include "i2c.h" +#include "ioexpander.h" +#include "power.h" +#include "power/amd_x86.h" +#include "timer.h" + +/* Power Signal Input List */ +/* TODO: b/218904113: Convert to using Zephyr GPIOs */ +const struct power_signal_info power_signal_list[] = { + [X86_SLP_S3_N] = { + .gpio = GPIO_PCH_SLP_S3_L, + .flags = POWER_SIGNAL_ACTIVE_HIGH, + .name = "SLP_S3_DEASSERTED", + }, + [X86_SLP_S5_N] = { + .gpio = GPIO_PCH_SLP_S5_L, + .flags = POWER_SIGNAL_ACTIVE_HIGH, + .name = "SLP_S5_DEASSERTED", + }, + [X86_S0_PGOOD] = { + .gpio = GPIO_S0_PGOOD, + .flags = POWER_SIGNAL_ACTIVE_HIGH, + .name = "S0_PGOOD", + }, + [X86_S5_PGOOD] = { + .gpio = GPIO_S5_PGOOD, + .flags = POWER_SIGNAL_ACTIVE_HIGH, + .name = "S5_PGOOD", + }, +}; +BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT); + +/* Chipset hooks */ +static void baseboard_suspend_change(struct ap_power_ev_callback *cb, + struct ap_power_ev_data data) +{ + switch (data.event) { + default: + return; + + case AP_POWER_SUSPEND: + /* Disable display backlight and retimer */ + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_disable_disp_bl), + 1); + ioex_set_level(IOEX_USB_A1_RETIMER_EN, 0); + break; + + case AP_POWER_RESUME: + /* Enable retimer and display backlight */ + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_disable_disp_bl), + 0); + ioex_set_level(IOEX_USB_A1_RETIMER_EN, 1); + /* Any retimer tuning can be done after the retimer turns on */ + break; + } +} + +static void baseboard_init(void) +{ + static struct ap_power_ev_callback cb; + + /* Setup a suspend/resume callback */ + ap_power_ev_init_callback(&cb, baseboard_suspend_change, + AP_POWER_RESUME | AP_POWER_SUSPEND); + ap_power_ev_add_callback(&cb); + /* Enable Power Group interrupts. */ + gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_pg_groupc_s0)); + gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_pg_lpddr_s0)); + gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_pg_lpddr_s3)); + + /* Enable thermtrip interrupt */ + gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_soc_thermtrip)); +} +DECLARE_HOOK(HOOK_INIT, baseboard_init, HOOK_PRIO_POST_I2C); + +/** + * b/227296844: On G3->S5, wait for RSMRST_L to be deasserted before asserting + * PCH_PWRBTN_L. This can be as long as ~65ms after cold boot. Then wait an + * additional delay of T1a defined in the EDS before changing the power button. + */ +#define RSMRST_WAIT_DELAY 70 +#define EDS_PWR_BTN_RSMRST_T1A_DELAY 16 +void board_pwrbtn_to_pch(int level) +{ + timestamp_t start; + + /* Add delay for G3 exit if asserting PWRBTN_L and RSMRST_L is low. */ + if (!level && + !gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_soc_rsmrst_l))) { + start = get_time(); + do { + usleep(500); + if (gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL( + gpio_ec_soc_rsmrst_l))) + break; + } while (time_since32(start) < (RSMRST_WAIT_DELAY * MSEC)); + + if (!gpio_pin_get_dt( + GPIO_DT_FROM_NODELABEL(gpio_ec_soc_rsmrst_l))) + ccprints("Error pwrbtn: RSMRST_L still low"); + + msleep(EDS_PWR_BTN_RSMRST_T1A_DELAY); + } + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_soc_pwr_btn_l), level); +} + +/* Note: signal parameter unused */ +void baseboard_set_soc_pwr_pgood(enum gpio_signal unused) +{ + gpio_pin_set_dt( + GPIO_DT_FROM_NODELABEL(gpio_ec_soc_pwr_good), + gpio_pin_get_dt( + GPIO_DT_FROM_NODELABEL(gpio_en_pwr_pcore_s0_r)) && + gpio_pin_get_dt( + GPIO_DT_FROM_NODELABEL(gpio_pg_lpddr5_s0_od)) && + gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_s0_pgood))); +} + +/* TODO(b/248284045): Remove when boards switch to new chip */ +#define MP2845A_I2C_ADDR_FLAGS 0x20 +#define MP2854A_MFR_VOUT_CMPS_MAX_REG 0x69 +#define MP2854A_MFR_LOW_PWR_SEL BIT(12) + +__overridable bool board_supports_pcore_ocp(void) +{ + return true; +} + +static void setup_mp2845(void) +{ + if (i2c_update16(chg_chips[CHARGER_SOLO].i2c_port, + MP2845A_I2C_ADDR_FLAGS, MP2854A_MFR_VOUT_CMPS_MAX_REG, + MP2854A_MFR_LOW_PWR_SEL, MASK_CLR)) + ccprints("Failed to send mp2845 workaround"); + + if (board_supports_pcore_ocp()) + gpio_enable_dt_interrupt( + GPIO_INT_FROM_NODELABEL(int_soc_pcore_ocp)); +} +DECLARE_DEFERRED(setup_mp2845); + +void baseboard_s0_pgood(enum gpio_signal signal) +{ + baseboard_set_soc_pwr_pgood(signal); + + /* Chain off power signal interrupt handler for PG_PCORE_S0_R_OD */ + power_signal_interrupt(signal); + + /* Set up the MP2845, which is powered in S0 */ + if (gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_s0_pgood))) + hook_call_deferred(&setup_mp2845_data, 50 * MSEC); + else + gpio_disable_dt_interrupt( + GPIO_INT_FROM_NODELABEL(int_soc_pcore_ocp)); +} + +/* Note: signal parameter unused */ +void baseboard_set_en_pwr_pcore(enum gpio_signal unused) +{ + /* + * EC must AND signals PG_LPDDR5_S3_OD, PG_GROUPC_S0_OD, and + * EN_PWR_S0_R + */ + gpio_pin_set_dt( + GPIO_DT_FROM_NODELABEL(gpio_en_pwr_pcore_s0_r), + gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_pg_lpddr5_s3_od)) && + gpio_pin_get_dt( + GPIO_DT_FROM_NODELABEL(gpio_pg_groupc_s0_od)) && + gpio_pin_get_dt( + GPIO_DT_FROM_NODELABEL(gpio_en_pwr_s0_r))); + + /* Update EC_SOC_PWR_GOOD based on our results */ + baseboard_set_soc_pwr_pgood(unused); +} + +void baseboard_en_pwr_s0(enum gpio_signal signal) +{ + /* EC must AND signals SLP_S3_L and PG_PWR_S5 */ + gpio_pin_set_dt( + GPIO_DT_FROM_NODELABEL(gpio_en_pwr_s0_r), + gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_slp_s3_l)) && + gpio_pin_get_dt( + GPIO_DT_FROM_NODELABEL(gpio_pg_pwr_s5))); + + /* Change EN_PWR_PCORE_S0_R if needed*/ + baseboard_set_en_pwr_pcore(signal); + + /* Now chain off to the normal power signal interrupt handler. */ + power_signal_interrupt(signal); +} +#ifdef CONFIG_BOARD_USB_HUB_RESET +void baseboard_enable_hub(void) +{ + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_hub_rst), 0); +} +DECLARE_DEFERRED(baseboard_enable_hub); +#endif /* CONFIG_BOARD_USB_HUB_RESET */ + +void baseboard_s5_pgood(enum gpio_signal signal) +{ +#ifdef CONFIG_BOARD_USB_HUB_RESET + /* We must enable the USB hub at least 30ms after S5 PGOOD */ + if (gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_pg_pwr_s5))) + hook_call_deferred(&baseboard_enable_hub_data, 30 * MSEC); + else + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_hub_rst), 1); +#endif /* CONFIG_BOARD_USB_HUB_RESET */ + + /* Continue to our signal AND-ing and power interrupt */ + baseboard_en_pwr_s0(signal); +} + +void baseboard_set_en_pwr_s3(enum gpio_signal signal) +{ + /* EC must enable PWR_S3 when SLP_S5_L goes high, disable on low */ + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_en_pwr_s3), + gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_slp_s5_l))); + + /* Chain off the normal power signal interrupt handler */ + power_signal_interrupt(signal); +} + +void baseboard_soc_thermtrip(enum gpio_signal signal) +{ + ccprints("SoC thermtrip reported, shutting down"); + chipset_force_shutdown(CHIPSET_SHUTDOWN_THERMAL); +} + +void baseboard_soc_pcore_ocp(enum gpio_signal signal) +{ + ccprints("SoC Pcore OCP reported, shutting down"); + chipset_force_shutdown(CHIPSET_SHUTDOWN_BOARD_CUSTOM); +} diff --git a/zephyr/projects/skyrim/src/skyrim/alt_charger.c b/zephyr/projects/skyrim/src/skyrim/alt_charger.c new file mode 100644 index 0000000000..4b717901cd --- /dev/null +++ b/zephyr/projects/skyrim/src/skyrim/alt_charger.c @@ -0,0 +1,31 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <zephyr/devicetree.h> +#include <zephyr/logging/log.h> + +#include "charger_chips.h" +#include "common.h" +#include "cros_board_info.h" +#include "cros_cbi.h" +#include "hooks.h" + +LOG_MODULE_DECLARE(skyrim, CONFIG_SKYRIM_LOG_LEVEL); + +static void alt_charger_init(void) +{ + int ret; + uint32_t val; + + ret = cros_cbi_get_fw_config(FW_CHARGER, &val); + if (ret != 0) { + LOG_ERR("Error retrieving CBI FW_CONFIG field %d", FW_CHARGER); + return; + } + + if (val == FW_CHARGER_ISL9538) + CHG_ENABLE_ALTERNATE(0); +} +DECLARE_HOOK(HOOK_INIT, alt_charger_init, HOOK_PRIO_POST_FIRST); diff --git a/zephyr/projects/skyrim/src/skyrim/fan.c b/zephyr/projects/skyrim/src/skyrim/fan.c new file mode 100644 index 0000000000..0a368ee6f0 --- /dev/null +++ b/zephyr/projects/skyrim/src/skyrim/fan.c @@ -0,0 +1,62 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <zephyr/devicetree.h> +#include <zephyr/drivers/gpio.h> +#include <zephyr/logging/log.h> + +#include "cros_board_info.h" +#include "cros_cbi.h" +#include "fan.h" +#include "gpio/gpio.h" +#include "hooks.h" + +LOG_MODULE_DECLARE(skyrim, CONFIG_SKYRIM_LOG_LEVEL); + +/* + * Skyrim fan support + */ +static void fan_init(void) +{ + int ret; + uint32_t val; + uint32_t board_version; + /* + * Retrieve the fan config. + */ + ret = cros_cbi_get_fw_config(FW_FAN, &val); + if (ret != 0) { + LOG_ERR("Error retrieving CBI FW_CONFIG field %d", FW_FAN); + return; + } + + ret = cbi_get_board_version(&board_version); + if (ret != EC_SUCCESS) { + LOG_ERR("Error retrieving CBI board version"); + return; + } + + if ((board_version >= 3) && (val != FW_FAN_PRESENT)) { + /* Disable the fan */ + fan_set_count(0); + } +} +DECLARE_HOOK(HOOK_INIT, fan_init, HOOK_PRIO_POST_FIRST); + +/* + * Pcore OCP support + * Note: early boards should note enable this interrupt as they are not + * correctly configured for it. + */ +__override bool board_supports_pcore_ocp(void) +{ + uint32_t board_version; + + if (cbi_get_board_version(&board_version) == EC_SUCCESS && + board_version > 3) + return true; + + return false; +} diff --git a/zephyr/projects/skyrim/src/skyrim/form_factor.c b/zephyr/projects/skyrim/src/skyrim/form_factor.c new file mode 100644 index 0000000000..f137c6db31 --- /dev/null +++ b/zephyr/projects/skyrim/src/skyrim/form_factor.c @@ -0,0 +1,37 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <zephyr/devicetree.h> +#include <zephyr/logging/log.h> +#include "common.h" +#include "accelgyro.h" +#include "cros_board_info.h" +#include "hooks.h" +#include "motionsense_sensors.h" + +LOG_MODULE_DECLARE(skyrim, CONFIG_SKYRIM_LOG_LEVEL); + +/* + * Mainboard orientation support. + */ + +#define ALT_MAT SENSOR_ROT_STD_REF_NAME(DT_NODELABEL(lid_rot_ref1)) +#define LID_ACCEL SENSOR_ID(DT_NODELABEL(lid_accel)) + +static void form_factor_init(void) +{ + int ret; + uint32_t val; + /* + * If the board version >=4 + * use ver1 rotation matrix. + */ + ret = cbi_get_board_version(&val); + if (ret == EC_SUCCESS && val >= 4) { + LOG_INF("Switching to ver1 lid"); + motion_sensors[LID_ACCEL].rot_standard_ref = &ALT_MAT; + } +} +DECLARE_HOOK(HOOK_INIT, form_factor_init, HOOK_PRIO_POST_I2C); diff --git a/zephyr/projects/skyrim/src/skyrim/keyboard.c b/zephyr/projects/skyrim/src/skyrim/keyboard.c new file mode 100644 index 0000000000..e261321e86 --- /dev/null +++ b/zephyr/projects/skyrim/src/skyrim/keyboard.c @@ -0,0 +1,29 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "ec_commands.h" + +static const struct ec_response_keybd_config skyrim_kb = { + .num_top_row_keys = 10, + .action_keys = { + TK_BACK, /* T1 */ + TK_REFRESH, /* T2 */ + TK_FULLSCREEN, /* T3 */ + TK_OVERVIEW, /* T4 */ + TK_SNAPSHOT, /* T5 */ + TK_BRIGHTNESS_DOWN, /* T6 */ + TK_BRIGHTNESS_UP, /* T7 */ + TK_VOL_MUTE, /* T8 */ + TK_VOL_DOWN, /* T9 */ + TK_VOL_UP, /* T10 */ + }, + .capabilities = KEYBD_CAP_SCRNLOCK_KEY, +}; + +__override const struct ec_response_keybd_config * +board_vivaldi_keybd_config(void) +{ + return &skyrim_kb; +} diff --git a/zephyr/projects/skyrim/src/skyrim/ppc_config.c b/zephyr/projects/skyrim/src/skyrim/ppc_config.c new file mode 100644 index 0000000000..bebc8adcc7 --- /dev/null +++ b/zephyr/projects/skyrim/src/skyrim/ppc_config.c @@ -0,0 +1,46 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Skyrim board-specific PPC code */ + +#include <zephyr/drivers/gpio.h> + +#include "driver/ppc/nx20p348x.h" +#include "driver/ppc/aoz1380_public.h" +#include "usbc_ppc.h" + +#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args) + +/* + * In the AOZ1380 PPC, there are no programmable features. We use + * the attached NCT3807 to control a GPIO to indicate 1A5 or 3A0 + * current limits. + */ +int board_aoz1380_set_vbus_source_current_limit(int port, enum tcpc_rp_value rp) +{ + int rv = EC_SUCCESS; + + rv = gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(ioex_usb_c0_ilim_3a_en), + (rp == TYPEC_RP_3A0) ? 1 : 0); + + return rv; +} + +void ppc_interrupt(enum gpio_signal signal) +{ + switch (signal) { + case GPIO_USB_C0_PPC_INT_ODL: + aoz1380_interrupt(0); + break; + + case GPIO_USB_C1_PPC_INT_ODL: + nx20p348x_interrupt(1); + break; + + default: + break; + } +} diff --git a/zephyr/projects/skyrim/src/skyrim/usb_mux_config.c b/zephyr/projects/skyrim/src/skyrim/usb_mux_config.c new file mode 100644 index 0000000000..6c65e56d9e --- /dev/null +++ b/zephyr/projects/skyrim/src/skyrim/usb_mux_config.c @@ -0,0 +1,142 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Skyrim board-specific USB-C mux configuration */ + +#include <zephyr/drivers/gpio.h> + +#include "console.h" +#include "cros_board_info.h" +#include "cros_cbi.h" +#include "driver/retimer/anx7483_public.h" +#include "hooks.h" +#include "ioexpander.h" +#include "usb_mux.h" +#include "usbc/usb_muxes.h" + +#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args) + +/* + * USB C0 (general) and C1 (just ANX DB) use IOEX pins to + * indicate flipped polarity to a protection switch. + */ +static int ioex_set_flip(int port, mux_state_t mux_state) +{ + if (port == 0) { + if (mux_state & USB_PD_MUX_POLARITY_INVERTED) + gpio_pin_set_dt( + GPIO_DT_FROM_NODELABEL(ioex_usb_c0_sbu_flip), + 1); + else + gpio_pin_set_dt( + GPIO_DT_FROM_NODELABEL(ioex_usb_c0_sbu_flip), + 0); + } else { + if (mux_state & USB_PD_MUX_POLARITY_INVERTED) + gpio_pin_set_dt( + GPIO_DT_FROM_NODELABEL(ioex_usb_c1_sbu_flip), + 1); + else + gpio_pin_set_dt( + GPIO_DT_FROM_NODELABEL(ioex_usb_c1_sbu_flip), + 0); + } + + return EC_SUCCESS; +} + +int board_anx7483_c0_mux_set(const struct usb_mux *me, mux_state_t mux_state) +{ + /* Set the SBU polarity mux */ + RETURN_ERROR(ioex_set_flip(me->usb_port, mux_state)); + + return anx7483_set_default_tuning(me, mux_state); +} + +int board_anx7483_c1_mux_set(const struct usb_mux *me, mux_state_t mux_state) +{ + bool flipped = mux_state & USB_PD_MUX_POLARITY_INVERTED; + + /* Set the SBU polarity mux */ + RETURN_ERROR(ioex_set_flip(me->usb_port, mux_state)); + + /* Remove flipped from the state for easier compraisons */ + mux_state = mux_state & ~USB_PD_MUX_POLARITY_INVERTED; + + RETURN_ERROR(anx7483_set_default_tuning(me, mux_state)); + + if (mux_state == USB_PD_MUX_USB_ENABLED) { + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX1, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX2, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_DRX1, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_DRX2, + ANX7483_EQ_SETTING_12_5DB)); + } else if (mux_state == USB_PD_MUX_DP_ENABLED) { + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX1, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX2, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_UTX1, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_UTX2, + ANX7483_EQ_SETTING_12_5DB)); + } else if (mux_state == USB_PD_MUX_DOCK && !flipped) { + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX1, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX2, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_DRX1, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_UTX2, + ANX7483_EQ_SETTING_12_5DB)); + } else if (mux_state == USB_PD_MUX_DOCK && flipped) { + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX1, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX2, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_UTX1, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_DRX2, + ANX7483_EQ_SETTING_12_5DB)); + } + + return EC_SUCCESS; +} + +int board_c1_ps8818_mux_set(const struct usb_mux *me, mux_state_t mux_state) +{ + CPRINTSUSB("C1: PS8818 mux using default tuning"); + + /* Once a DP connection is established, we need to set IN_HPD */ + if (mux_state & USB_PD_MUX_DP_ENABLED) + ioex_set_level(IOEX_USB_C1_HPD_IN_DB, 1); + else + ioex_set_level(IOEX_USB_C1_HPD_IN_DB, 0); + + return 0; +} + +static void setup_mux(void) +{ + uint32_t val; + + if (cros_cbi_get_fw_config(FW_IO_DB, &val) != 0) + CPRINTSUSB("Error finding FW_DB_IO in CBI FW_CONFIG"); + /* Val will have our dts default on error, so continue setup */ + + if (val == FW_IO_DB_PS8811_PS8818) { + CPRINTSUSB("C1: Setting PS8818 mux"); + USB_MUX_ENABLE_ALTERNATIVE(usb_mux_chain_ps8818_port1); + } else if (val == FW_IO_DB_NONE_ANX7483) { + CPRINTSUSB("C1: Setting ANX7483 mux"); + } else { + CPRINTSUSB("Unexpected DB_IO board: %d", val); + } +} +DECLARE_HOOK(HOOK_INIT, setup_mux, HOOK_PRIO_INIT_I2C); diff --git a/zephyr/projects/skyrim/src/stt.c b/zephyr/projects/skyrim/src/stt.c new file mode 100644 index 0000000000..40743fbc68 --- /dev/null +++ b/zephyr/projects/skyrim/src/stt.c @@ -0,0 +1,28 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Support code for STT temperature reporting */ + +#include "chipset.h" +#include "temp_sensor/pct2075.h" +#include "temp_sensor/temp_sensor.h" + +int board_get_soc_temp_mk(int *temp_mk) +{ + if (chipset_in_state(CHIPSET_STATE_HARD_OFF)) + return EC_ERROR_NOT_POWERED; + + return pct2075_get_val_mk(PCT2075_SENSOR_ID(DT_NODELABEL(soc_pct2075)), + temp_mk); +} + +int board_get_ambient_temp_mk(int *temp_mk) +{ + if (chipset_in_state(CHIPSET_STATE_HARD_OFF)) + return EC_ERROR_NOT_POWERED; + + return pct2075_get_val_mk(PCT2075_SENSOR_ID(DT_NODELABEL(amb_pct2075)), + temp_mk); +} diff --git a/zephyr/projects/skyrim/src/usb_pd_policy.c b/zephyr/projects/skyrim/src/usb_pd_policy.c new file mode 100644 index 0000000000..ec9f873863 --- /dev/null +++ b/zephyr/projects/skyrim/src/usb_pd_policy.c @@ -0,0 +1,93 @@ +/* Copyright 2021 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Shared USB-C policy for Zork boards */ + +#include <zephyr/drivers/gpio.h> + +#include "charge_manager.h" +#include "chipset.h" +#include "common.h" +#include "compile_time_macros.h" +#include "console.h" +#include "ec_commands.h" +#include "ioexpander.h" +#include "system.h" +#include "usb_mux.h" +#include "usb_pd.h" +#include "usbc_ppc.h" +#include "util.h" + +int pd_check_vconn_swap(int port) +{ + /* + * Do not allow vconn swap 5V rail is off + * S5_PGOOD depends on PG_PP5000_S5 being asserted, + * so GPIO_S5_PGOOD is a reasonable proxy for PP5000_S5 + */ + return gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_pg_pwr_s5)); +} + +void pd_power_supply_reset(int port) +{ + /* Disable VBUS. */ + ppc_vbus_source_enable(port, 0); + + /* Enable discharge if we were previously sourcing 5V */ + if (IS_ENABLED(CONFIG_USB_PD_DISCHARGE)) + pd_set_vbus_discharge(port, 1); + + /* Notify host of power info change. */ + pd_send_host_event(PD_EVENT_POWER_CHANGE); +} + +int pd_set_power_supply_ready(int port) +{ + int rv; + + /* Disable charging. */ + rv = ppc_vbus_sink_enable(port, 0); + if (rv) + return rv; + + if (IS_ENABLED(CONFIG_USB_PD_DISCHARGE)) + pd_set_vbus_discharge(port, 0); + + /* Provide Vbus. */ + rv = ppc_vbus_source_enable(port, 1); + if (rv) + return rv; + + /* Notify host of power info change. */ + pd_send_host_event(PD_EVENT_POWER_CHANGE); + + return EC_SUCCESS; +} + +__override int board_pd_set_frs_enable(int port, int enable) +{ + /* + * Both PPCs require the FRS GPIO to be set as soon as FRS capability + * is established. + */ + if (port == 0) + ioex_set_level(IOEX_USB_C0_TCPC_FASTSW_CTL_EN, enable); + else + ioex_set_level(IOEX_USB_C1_TCPC_FASTSW_CTL_EN, enable); + + return EC_SUCCESS; +} + +/* Used by Vbus discharge common code with CONFIG_USB_PD_DISCHARGE */ +int board_vbus_source_enabled(int port) +{ + return tcpm_get_src_ctrl(port); +} + +/* Used by USB charger task with CONFIG_USB_PD_5V_EN_CUSTOM */ +int board_is_sourcing_vbus(int port) +{ + return board_vbus_source_enabled(port); +} diff --git a/zephyr/projects/skyrim/src/usbc_config.c b/zephyr/projects/skyrim/src/usbc_config.c new file mode 100644 index 0000000000..dec9f928b5 --- /dev/null +++ b/zephyr/projects/skyrim/src/usbc_config.c @@ -0,0 +1,403 @@ +/* Copyright 2021 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Skyrim family-specific USB-C configuration */ + +#include <zephyr/drivers/gpio.h> + +#include "cros_board_info.h" +#include "cros_cbi.h" +#include "battery_fuel_gauge.h" +#include "charge_manager.h" +#include "charge_ramp.h" +#include "charge_state_v2.h" +#include "charge_state.h" +#include "charger.h" +#include "driver/bc12/pi3usb9201.h" +#include "driver/charger/isl9241.h" +#include "driver/ppc/nx20p348x.h" +#include "driver/retimer/anx7483_public.h" +#include "driver/retimer/ps8811.h" +#include "driver/retimer/ps8818_public.h" +#include "driver/tcpm/nct38xx.h" +#include "driver/usb_mux/amd_fp6.h" +#include "gpio/gpio_int.h" +#include "hooks.h" +#include "ioexpander.h" +#include "power.h" +#include "usb_mux.h" +#include "usb_pd_tcpm.h" +#include "usbc_ppc.h" +#include "usbc/usb_muxes.h" + +#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args) + +/* USB-A ports */ +enum usba_port { USBA_PORT_A0 = 0, USBA_PORT_A1, USBA_PORT_COUNT }; + +/* USB-C ports */ +enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT }; +BUILD_ASSERT(USBC_PORT_COUNT == CONFIG_USB_PD_PORT_MAX_COUNT); + +static void reset_nct38xx_port(int port); + +static void usbc_interrupt_init(void) +{ + /* Enable PPC interrupts. */ + gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0_ppc)); + gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c1_ppc)); + + /* Enable TCPC interrupts. */ + gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0_tcpc)); + gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c1_tcpc)); + + /* Enable BC 1.2 interrupts */ + gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0_bc12)); + gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c1_bc12)); + + /* Enable SBU fault interrupts */ + gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0_sbu_fault)); + gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c1_sbu_fault)); +} +DECLARE_HOOK(HOOK_INIT, usbc_interrupt_init, HOOK_PRIO_POST_I2C); + +static void usb_fault_interrupt_init(void) +{ + /* Enable USB fault interrupts when we hit S5 */ + gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_hub_fault)); + gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_a0_fault)); + gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_a1_fault)); +} +DECLARE_HOOK(HOOK_CHIPSET_STARTUP, usb_fault_interrupt_init, HOOK_PRIO_DEFAULT); + +static void usb_fault_interrupt_disable(void) +{ + /* Disable USB fault interrupts leaving S5 */ + gpio_disable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_hub_fault)); + gpio_disable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_a0_fault)); + gpio_disable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_a1_fault)); +} +DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, usb_fault_interrupt_disable, + HOOK_PRIO_DEFAULT); + +int board_set_active_charge_port(int port) +{ + int is_valid_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT); + int i; + int rv; + + if (port == CHARGE_PORT_NONE) { + CPRINTSUSB("Disabling all charger ports"); + + /* Disable all ports. */ + for (i = 0; i < ppc_cnt; i++) { + /* + * If this port had booted in dead battery mode, go + * ahead and reset it so EN_SNK responds properly. + */ + if (nct38xx_get_boot_type(i) == + NCT38XX_BOOT_DEAD_BATTERY) { + reset_nct38xx_port(i); + pd_set_error_recovery(i); + } + + /* + * Do not return early if one fails otherwise we can + * get into a boot loop assertion failure. + */ + if (ppc_vbus_sink_enable(i, 0)) + CPRINTSUSB("Disabling C%d as sink failed.", i); + } + + return EC_SUCCESS; + } else if (!is_valid_port) { + return EC_ERROR_INVAL; + } + + /* + * Check if we can reset any ports in dead battery mode + * + * The NCT3807 may continue to keep EN_SNK low on the dead battery port + * and allow a dangerous level of voltage to pass through to the initial + * charge port (see b/183660105). We must reset the ports if we have + * sufficient battery to do so, which will bring EN_SNK back under + * normal control. + */ + rv = EC_SUCCESS; + for (i = 0; i < board_get_usb_pd_port_count(); i++) { + if (nct38xx_get_boot_type(i) == NCT38XX_BOOT_DEAD_BATTERY) { + CPRINTSUSB("Found dead battery on %d", i); + /* + * If we have battery, get this port reset ASAP. + * This means temporarily rejecting charge manager + * sets to it. + */ + if (pd_is_battery_capable()) { + reset_nct38xx_port(i); + pd_set_error_recovery(i); + + if (port == i) + rv = EC_ERROR_INVAL; + } else if (port != i) { + /* + * If other port is selected and in dead battery + * mode, reset this port. Otherwise, reject + * change because we'll brown out. + */ + if (nct38xx_get_boot_type(port) == + NCT38XX_BOOT_DEAD_BATTERY) { + reset_nct38xx_port(i); + pd_set_error_recovery(i); + } else { + rv = EC_ERROR_INVAL; + } + } + } + } + + if (rv != EC_SUCCESS) + return rv; + + /* Check if the port is sourcing VBUS. */ + if (tcpm_get_src_ctrl(port)) { + CPRINTSUSB("Skip enable C%d", port); + return EC_ERROR_INVAL; + } + + CPRINTSUSB("New charge port: C%d", port); + + /* + * Turn off the other ports' sink path FETs, before enabling the + * requested charge port. + */ + for (i = 0; i < ppc_cnt; i++) { + if (i == port) + continue; + + if (ppc_vbus_sink_enable(i, 0)) + CPRINTSUSB("C%d: sink path disable failed.", i); + } + + /* Enable requested charge port. */ + if (ppc_vbus_sink_enable(port, 1)) { + CPRINTSUSB("C%d: sink path enable failed.", port); + return EC_ERROR_UNKNOWN; + } + + return EC_SUCCESS; +} + +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) +{ + charge_ma = (charge_ma * CONFIG_BOARD_INPUT_CURRENT_SCALE_FACTOR) / 100; + + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); +} + +void sbu_fault_interrupt(enum gpio_signal signal) +{ + int port = signal == IOEX_USB_C1_FAULT_ODL ? 1 : 0; + + CPRINTSUSB("C%d: SBU fault", port); + pd_handle_overcurrent(port); +} + +void usb_fault_interrupt(enum gpio_signal signal) +{ + int out; + + CPRINTSUSB("USB fault(%d), alerting the SoC", signal); + out = gpio_pin_get_dt( + GPIO_DT_FROM_NODELABEL(gpio_usb_hub_fault_q_odl)) && + gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(ioex_usb_a0_fault_odl)) && + gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(ioex_usb_a1_fault_db_odl)); + + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_fault_odl), out); +} + +void usb_pd_soc_interrupt(enum gpio_signal signal) +{ + /* + * This interrupt is unexpected with our use of the SoC mux, so just log + * it as a point of interest. + */ + CPRINTSUSB("SOC PD Interrupt"); +} + +#ifdef CONFIG_CHARGER_ISL9241 +/* Round up 3250 max current to multiple of 128mA for ISL9241 AC prochot. */ +#define SKYRIM_AC_PROCHOT_CURRENT_MA 3328 +static void set_ac_prochot(void) +{ + isl9241_set_ac_prochot(CHARGER_SOLO, SKYRIM_AC_PROCHOT_CURRENT_MA); +} +DECLARE_HOOK(HOOK_INIT, set_ac_prochot, HOOK_PRIO_DEFAULT); +#endif /* CONFIG_CHARGER_ISL9241 */ + +void tcpc_alert_event(enum gpio_signal signal) +{ + int port; + + switch (signal) { + case GPIO_USB_C0_TCPC_INT_ODL: + port = 0; + break; + case GPIO_USB_C1_TCPC_INT_ODL: + port = 1; + break; + default: + return; + } + + schedule_deferred_pd_interrupt(port); +} + +static void reset_nct38xx_port(int port) +{ + const struct gpio_dt_spec *reset_gpio_l; + const struct device *ioex_port0, *ioex_port1; + + /* TODO(b/225189538): Save and restore ioex signals */ + if (port == USBC_PORT_C0) { + reset_gpio_l = GPIO_DT_FROM_NODELABEL(gpio_usb_c0_tcpc_rst_l); + ioex_port0 = DEVICE_DT_GET(DT_NODELABEL(ioex_c0_port0)); + ioex_port1 = DEVICE_DT_GET(DT_NODELABEL(ioex_c0_port1)); + } else if (port == USBC_PORT_C1) { + reset_gpio_l = GPIO_DT_FROM_NODELABEL(gpio_usb_c1_tcpc_rst_l); + ioex_port0 = DEVICE_DT_GET(DT_NODELABEL(ioex_c1_port0)); + ioex_port1 = DEVICE_DT_GET(DT_NODELABEL(ioex_c1_port1)); + } else { + /* Invalid port: do nothing */ + return; + } + + gpio_pin_set_dt(reset_gpio_l, 0); + msleep(NCT38XX_RESET_HOLD_DELAY_MS); + gpio_pin_set_dt(reset_gpio_l, 1); + nct38xx_reset_notify(port); + if (NCT3807_RESET_POST_DELAY_MS != 0) + msleep(NCT3807_RESET_POST_DELAY_MS); + + /* Re-enable the IO expander pins */ + gpio_reset_port(ioex_port0); + gpio_reset_port(ioex_port1); +} + +void board_reset_pd_mcu(void) +{ + /* Reset TCPC0 */ + reset_nct38xx_port(USBC_PORT_C0); + + /* Reset TCPC1 */ + reset_nct38xx_port(USBC_PORT_C1); +} + +uint16_t tcpc_get_alert_status(void) +{ + uint16_t status = 0; + + /* + * Check which port has the ALERT line set and ignore if that TCPC has + * its reset line active. + */ + if (!gpio_pin_get_dt( + GPIO_DT_FROM_NODELABEL(gpio_usb_c0_tcpc_int_odl))) { + if (gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL( + gpio_usb_c0_tcpc_rst_l)) != 0) + status |= PD_STATUS_TCPC_ALERT_0; + } + + if (!gpio_pin_get_dt( + GPIO_DT_FROM_NODELABEL(gpio_usb_c1_tcpc_int_odl))) { + if (gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL( + gpio_usb_c1_tcpc_rst_l)) != 0) + status |= PD_STATUS_TCPC_ALERT_1; + } + + return status; +} + +void bc12_interrupt(enum gpio_signal signal) +{ + switch (signal) { + case GPIO_USB_C0_BC12_INT_ODL: + usb_charger_task_set_event(0, USB_CHG_EVENT_BC12); + break; + + case GPIO_USB_C1_BC12_INT_ODL: + usb_charger_task_set_event(1, USB_CHG_EVENT_BC12); + break; + + default: + break; + } +} + +/** + * Return if VBUS is sagging too low + * + * For legacy BC1.2 charging with CONFIG_CHARGE_RAMP_SW, ramp up input current + * until voltage drops to 4.5V. Don't go lower than this to be kind to the + * charger (see b/67964166). + */ +#define BC12_MIN_VOLTAGE 4500 +int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state) +{ + int voltage = 0; + int rv; + + rv = charger_get_vbus_voltage(port, &voltage); + + if (rv) { + CPRINTSUSB("%s rv=%d", __func__, rv); + return 0; + } + + /* + * b/168569046: The ISL9241 sometimes incorrectly reports 0 for unknown + * reason, causing ramp to stop at 0.5A. Workaround this by ignoring 0. + * This partly defeats the point of ramping, but will still catch + * VBUS below 4.5V and above 0V. + */ + if (voltage == 0) { + CPRINTSUSB("%s vbus=0", __func__); + return 0; + } + + if (voltage < BC12_MIN_VOLTAGE) + CPRINTSUSB("%s vbus=%d", __func__, voltage); + + return voltage < BC12_MIN_VOLTAGE; +} + +#define SAFE_RESET_VBUS_DELAY_MS 900 +#define SAFE_RESET_VBUS_MV 5000 +void board_hibernate(void) +{ + int port; + enum ec_error_list ret; + + /* + * If we are charging, then drop the Vbus level down to 5V to ensure + * that we don't get locked out of the 6.8V OVLO for our PPCs in + * dead-battery mode. This is needed when the TCPC/PPC rails go away. + * (b/79218851, b/143778351, b/147007265) + */ + port = charge_manager_get_active_charge_port(); + if (port != CHARGE_PORT_NONE) { + pd_request_source_voltage(port, SAFE_RESET_VBUS_MV); + + /* Give PD task and PPC chip time to get to 5V */ + msleep(SAFE_RESET_VBUS_DELAY_MS); + } + + /* Try to put our battery fuel gauge into sleep mode */ + ret = battery_sleep_fuel_gauge(); + if ((ret != EC_SUCCESS) && (ret != EC_ERROR_UNIMPLEMENTED)) + cprints(CC_SYSTEM, "Failed to send battery sleep command"); +} diff --git a/zephyr/projects/skyrim/src/winterhold/kb_backlight.c b/zephyr/projects/skyrim/src/winterhold/kb_backlight.c new file mode 100644 index 0000000000..049b99e3a1 --- /dev/null +++ b/zephyr/projects/skyrim/src/winterhold/kb_backlight.c @@ -0,0 +1,34 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <zephyr/devicetree.h> +#include <zephyr/logging/log.h> + +#include "board_config.h" +#include "common.h" +#include "cros_board_info.h" +#include "cros_cbi.h" + +LOG_MODULE_DECLARE(skyrim, CONFIG_SKYRIM_LOG_LEVEL); + +__override uint32_t board_override_feature_flags0(uint32_t flags0) +{ + int ret; + uint32_t val; + + /* + * Remove keyboard backlight feature for devices that don't support it. + */ + ret = cros_cbi_get_fw_config(FW_KB_BL, &val); + if (ret != 0) { + LOG_ERR("Error retrieving CBI FW_CONFIG field %d", FW_KB_BL); + return flags0; + } + + if (val == FW_KB_BL_NOT_PRESENT) + return (flags0 & ~EC_FEATURE_MASK_0(EC_FEATURE_PWM_KEYB)); + else + return flags0; +} diff --git a/zephyr/projects/skyrim/src/winterhold/keyboard.c b/zephyr/projects/skyrim/src/winterhold/keyboard.c new file mode 100644 index 0000000000..d3aebe0f2e --- /dev/null +++ b/zephyr/projects/skyrim/src/winterhold/keyboard.c @@ -0,0 +1,29 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "ec_commands.h" + +static const struct ec_response_keybd_config winterhold_kb = { + .num_top_row_keys = 10, + .action_keys = { + TK_BACK, /* T1 */ + TK_REFRESH, /* T2 */ + TK_FULLSCREEN, /* T3 */ + TK_OVERVIEW, /* T4 */ + TK_SNAPSHOT, /* T5 */ + TK_BRIGHTNESS_DOWN, /* T6 */ + TK_BRIGHTNESS_UP, /* T7 */ + TK_VOL_MUTE, /* T8 */ + TK_VOL_DOWN, /* T9 */ + TK_VOL_UP, /* T10 */ + }, + .capabilities = KEYBD_CAP_SCRNLOCK_KEY, +}; + +__override const struct ec_response_keybd_config * +board_vivaldi_keybd_config(void) +{ + return &winterhold_kb; +} diff --git a/zephyr/projects/skyrim/src/winterhold/ppc_config.c b/zephyr/projects/skyrim/src/winterhold/ppc_config.c new file mode 100644 index 0000000000..72ddb6ce6c --- /dev/null +++ b/zephyr/projects/skyrim/src/winterhold/ppc_config.c @@ -0,0 +1,27 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Winterhold board-specific PPC code */ + +#include <zephyr/drivers/gpio.h> + +#include "driver/ppc/nx20p348x.h" +#include "usbc_ppc.h" + +void ppc_interrupt(enum gpio_signal signal) +{ + switch (signal) { + case GPIO_USB_C0_PPC_INT_ODL: + nx20p348x_interrupt(0); + break; + + case GPIO_USB_C1_PPC_INT_ODL: + nx20p348x_interrupt(1); + break; + + default: + break; + } +} diff --git a/zephyr/projects/skyrim/src/winterhold/usb_mux_config.c b/zephyr/projects/skyrim/src/winterhold/usb_mux_config.c new file mode 100644 index 0000000000..d2ee4a6606 --- /dev/null +++ b/zephyr/projects/skyrim/src/winterhold/usb_mux_config.c @@ -0,0 +1,110 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Winterhold board-specific USB-C mux configuration */ + +#include <zephyr/drivers/gpio.h> + +#include "console.h" +#include "cros_board_info.h" +#include "cros_cbi.h" +#include "driver/retimer/anx7483_public.h" +#include "hooks.h" +#include "ioexpander.h" +#include "usb_mux.h" +#include "usbc/usb_muxes.h" + +#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args) + +/* + * USB C0 (general) and C1 (just ANX DB) use IOEX pins to + * indicate flipped polarity to a protection switch. + */ +static int ioex_set_flip(int port, mux_state_t mux_state) +{ + if (port == 0) { + if (mux_state & USB_PD_MUX_POLARITY_INVERTED) + gpio_pin_set_dt( + GPIO_DT_FROM_NODELABEL(ioex_usb_c0_sbu_flip), + 1); + else + gpio_pin_set_dt( + GPIO_DT_FROM_NODELABEL(ioex_usb_c0_sbu_flip), + 0); + } else { + if (mux_state & USB_PD_MUX_POLARITY_INVERTED) + gpio_pin_set_dt( + GPIO_DT_FROM_NODELABEL(ioex_usb_c1_sbu_flip), + 1); + else + gpio_pin_set_dt( + GPIO_DT_FROM_NODELABEL(ioex_usb_c1_sbu_flip), + 0); + } + + return EC_SUCCESS; +} + +int board_anx7483_c0_mux_set(const struct usb_mux *me, mux_state_t mux_state) +{ + /* Set the SBU polarity mux */ + RETURN_ERROR(ioex_set_flip(me->usb_port, mux_state)); + + return anx7483_set_default_tuning(me, mux_state); +} + +int board_anx7483_c1_mux_set(const struct usb_mux *me, mux_state_t mux_state) +{ + bool flipped = mux_state & USB_PD_MUX_POLARITY_INVERTED; + + /* Set the SBU polarity mux */ + RETURN_ERROR(ioex_set_flip(me->usb_port, mux_state)); + + /* Remove flipped from the state for easier compraisons */ + mux_state = mux_state & ~USB_PD_MUX_POLARITY_INVERTED; + + RETURN_ERROR(anx7483_set_default_tuning(me, mux_state)); + + if (mux_state == USB_PD_MUX_USB_ENABLED) { + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX1, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX2, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_DRX1, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_DRX2, + ANX7483_EQ_SETTING_12_5DB)); + } else if (mux_state == USB_PD_MUX_DP_ENABLED) { + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX1, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX2, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_UTX1, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_UTX2, + ANX7483_EQ_SETTING_12_5DB)); + } else if (mux_state == USB_PD_MUX_DOCK && !flipped) { + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX1, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX2, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_DRX1, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_UTX2, + ANX7483_EQ_SETTING_12_5DB)); + } else if (mux_state == USB_PD_MUX_DOCK && flipped) { + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX1, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX2, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_UTX1, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_DRX2, + ANX7483_EQ_SETTING_12_5DB)); + } + + return EC_SUCCESS; +} diff --git a/zephyr/projects/skyrim/usbc.dts b/zephyr/projects/skyrim/usbc.dts new file mode 100644 index 0000000000..8486927e8d --- /dev/null +++ b/zephyr/projects/skyrim/usbc.dts @@ -0,0 +1,26 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + usbc { + #address-cells = <1>; + #size-cells = <0>; + + usbc_port0: port0@0 { + compatible = "named-usbc-port"; + reg = <0>; + bc12 = <&bc12_port0>; + tcpc = <&tcpc_port0>; + chg = <&charger>; + }; + + usbc_port1: port1@1 { + compatible = "named-usbc-port"; + reg = <1>; + bc12 = <&bc12_port1>; + tcpc = <&tcpc_port1>; + }; + }; +}; diff --git a/zephyr/projects/skyrim/winterhold.dts b/zephyr/projects/skyrim/winterhold.dts new file mode 100644 index 0000000000..6113923ed8 --- /dev/null +++ b/zephyr/projects/skyrim/winterhold.dts @@ -0,0 +1,126 @@ +/* Copyright 2021 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <dt-bindings/usbc_mux.h> + +#include "i2c_common.dtsi" + +/ { + named-gpios { + /* Winterhold-specific GPIO customizations */ + }; + + named-temp-sensors { + compatible = "cros-ec,temp-sensors"; + soc-pct2075 { + temp_host_high = <100>; + temp_host_halt = <105>; + temp_host_release_high = <80>; + temp_host_release_halt = <80>; + temp_fan_off = <0>; + temp_fan_max = <70>; + power-good-pin = <&gpio_pg_pwr_s5>; + sensor = <&soc_pct2075>; + }; + amb-pct2075 { + power-good-pin = <&gpio_pg_pwr_s5>; + sensor = <&amb_pct2075>; + }; + }; + + /* + * Note this is expected to vary per-board, so we keep it in the board + * dts files. + */ + Winterhold-fw-config { + compatible = "cros-ec,cbi-fw-config"; + + /* + * FW_CONFIG field to enable KB back light or not. + */ + kb-bl { + enum-name = "FW_KB_BL"; + start = <1>; + size = <1>; + + no-kb-bl { + compatible = "cros-ec,cbi-fw-config-value"; + enum-name = "FW_KB_BL_NOT_PRESENT"; + value = <0>; + }; + kb-bl-present { + compatible = "cros-ec,cbi-fw-config-value"; + enum-name = "FW_KB_BL_PRESENT"; + value = <1>; + }; + }; + }; + + /* Rotation matrices for motion sensors. */ + motionsense-rotation-ref { + compatible = "cros-ec,motionsense-rotation-ref"; + lid_rot_ref: lid-rotation-ref { + mat33 = <0 (-1) 0 + 1 0 0 + 0 0 1>; + }; + + base_rot_ref: base-rotation-ref { + mat33 = <0 1 0 + (-1) 0 0 + 0 0 1>; + }; + }; +}; + +&i2c0_0 { + anx7483_port0: anx7483@3e { + compatible = "analogix,anx7483"; + reg = <0x3e>; + board-set = "board_anx7483_c0_mux_set"; + }; + ppc_port0: nx20p348x@71 { + compatible = "nxp,nx20p348x"; + status = "okay"; + reg = <0x71>; + }; +}; + +&i2c1_0 { + anx7483_port1: anx7483@3e { + compatible = "analogix,anx7483"; + reg = <0x3e>; + board-set = "board_anx7483_c1_mux_set"; + }; + ppc_port1: nx20p348x@71 { + compatible = "nxp,nx20p348x"; + status = "okay"; + reg = <0x71>; + }; +}; + +&i2c4_1 { + charger: isl9238@9 { + compatible = "intersil,isl923x"; + status = "okay"; + reg = <0x9>; + }; +}; + +&usbc_port0 { + ppc = <&ppc_port0>; + usb-mux-chain-0 { + compatible = "cros-ec,usb-mux-chain"; + usb-muxes = <&amd_fp6_port0 &anx7483_port0>; + }; +}; + +&usbc_port1 { + ppc = <&ppc_port1>; + usb-mux-chain-1-anx { + compatible = "cros-ec,usb-mux-chain"; + usb-muxes = <&amd_fp6_port1 &anx7483_port1>; + }; +}; diff --git a/zephyr/projects/trogdor/lazor/BUILD.py b/zephyr/projects/trogdor/lazor/BUILD.py new file mode 100644 index 0000000000..ca1a26bdcf --- /dev/null +++ b/zephyr/projects/trogdor/lazor/BUILD.py @@ -0,0 +1,25 @@ +# Copyright 2021 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +"""Define zmake projects for lazor.""" + +register_npcx_project( + project_name="lazor", + zephyr_board="npcx7", + dts_overlays=[ + "adc.dts", + "battery.dts", + "display.dts", + "gpio.dts", + "i2c.dts", + "host_interface_npcx.dts", + "interrupts.dts", + "keyboard.dts", + "led.dts", + "motionsense.dts", + "pwm_led.dts", + "usbc.dts", + "default_gpio_pinctrl.dts", + ], +) diff --git a/zephyr/projects/trogdor/lazor/CMakeLists.txt b/zephyr/projects/trogdor/lazor/CMakeLists.txt new file mode 100644 index 0000000000..b6d5024707 --- /dev/null +++ b/zephyr/projects/trogdor/lazor/CMakeLists.txt @@ -0,0 +1,23 @@ +# Copyright 2021 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +cmake_minimum_required(VERSION 3.13.1) + +find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}") +project(lazor) + +cros_ec_library_include_directories(include) + +zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC + "src/power.c" + "src/usb_pd_policy.c" + "src/usbc_config.c") + +zephyr_library_sources( + "src/sku.c" + "src/switchcap.c") + +# Board specific implementation +zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_I2C + "src/i2c.c") diff --git a/zephyr/projects/trogdor/lazor/adc.dts b/zephyr/projects/trogdor/lazor/adc.dts new file mode 100644 index 0000000000..b834001587 --- /dev/null +++ b/zephyr/projects/trogdor/lazor/adc.dts @@ -0,0 +1,48 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <zephyr/dt-bindings/adc/adc.h> + +/ { + named-adc-channels { + compatible = "named-adc-channels"; + + vbus { + enum-name = "ADC_VBUS"; + io-channels = <&adc0 1>; + /* Measure VBUS through a 1/10 voltage divider */ + mul = <10>; + }; + amon_bmon { + enum-name = "ADC_AMON_BMON"; + io-channels = <&adc0 2>; + /* + * Adapter current output or battery charging/ + * discharging current (uV) 18x amplification on + * charger side. + */ + mul = <1000>; + div = <18>; + }; + psys { + enum-name = "ADC_PSYS"; + io-channels = <&adc0 3>; + /* + * ISL9238 PSYS output is 1.44 uA/W over 5.6K resistor, + * to read 0.8V @ 99 W, i.e. 124000 uW/mV. + */ + mul = <124000>; + }; + }; + +}; + +&adc0 { + status = "okay"; + pinctrl-0 = <&adc0_chan1_gp44 + &adc0_chan2_gp43 + &adc0_chan3_gp42>; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/trogdor/lazor/battery.dts b/zephyr/projects/trogdor/lazor/battery.dts new file mode 100644 index 0000000000..2b17dd4761 --- /dev/null +++ b/zephyr/projects/trogdor/lazor/battery.dts @@ -0,0 +1,24 @@ +/* Copyright 2021 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + batteries { + default_battery: ap16l5j { + compatible = "panasonic,ap16l5j", "battery-smart"; + }; + ap16l5j_009 { + compatible = "panasonic,ap16l5j-009", "battery-smart"; + }; + ap16l8j { + compatible = "lgc,ap16l8j", "battery-smart"; + }; + lgc_ap18c8k { + compatible = "lgc,ap18c8k", "battery-smart"; + }; + murata_ap18c4k { + compatible = "murata,ap18c4k", "battery-smart"; + }; + }; +}; diff --git a/zephyr/projects/trogdor/lazor/default_gpio_pinctrl.dts b/zephyr/projects/trogdor/lazor/default_gpio_pinctrl.dts new file mode 100644 index 0000000000..1819bdbc3e --- /dev/null +++ b/zephyr/projects/trogdor/lazor/default_gpio_pinctrl.dts @@ -0,0 +1,43 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Adds the &alt1_no_lpc_espi setting over the NPCX7 default setting. */ +&{/def-io-conf-list} { + pinmux = <&alt0_gpio_no_spip + &alt0_gpio_no_fpip + &alt1_no_pwrgd + &alt1_no_lpc_espi + &alta_no_peci_en + &altd_npsl_in1_sl + &altd_npsl_in2_sl + &altd_psl_in3_sl + &altd_psl_in4_sl + &alt7_no_ksi0_sl + &alt7_no_ksi1_sl + &alt7_no_ksi2_sl + &alt7_no_ksi3_sl + &alt7_no_ksi4_sl + &alt7_no_ksi5_sl + &alt7_no_ksi6_sl + &alt7_no_ksi7_sl + &alt8_no_kso00_sl + &alt8_no_kso01_sl + &alt8_no_kso02_sl + &alt8_no_kso03_sl + &alt8_no_kso04_sl + &alt8_no_kso05_sl + &alt8_no_kso06_sl + &alt8_no_kso07_sl + &alt9_no_kso08_sl + &alt9_no_kso09_sl + &alt9_no_kso10_sl + &alt9_no_kso11_sl + &alt9_no_kso12_sl + &alt9_no_kso13_sl + &alt9_no_kso14_sl + &alt9_no_kso15_sl + &alta_no_kso16_sl + &alta_no_kso17_sl >; +}; diff --git a/zephyr/projects/trogdor/lazor/display.dts b/zephyr/projects/trogdor/lazor/display.dts new file mode 100644 index 0000000000..65d3a2d91b --- /dev/null +++ b/zephyr/projects/trogdor/lazor/display.dts @@ -0,0 +1,18 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + displight { + compatible = "cros-ec,displight"; + pwms = <&pwm5 0 PWM_HZ(4800) PWM_POLARITY_NORMAL>; + generic-pwm-channel = <1>; + }; +}; + +&pwm5 { + status = "okay"; + pinctrl-0 = <&pwm5_gpb7>; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/trogdor/lazor/gpio.dts b/zephyr/projects/trogdor/lazor/gpio.dts new file mode 100644 index 0000000000..a047d7e2f2 --- /dev/null +++ b/zephyr/projects/trogdor/lazor/gpio.dts @@ -0,0 +1,320 @@ +/* Copyright 2021 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <dt-bindings/wake_mask_event_defines.h> + +/ { + aliases { + gpio-wp = &gpio_ec_wp_odl; + gpio-kbd-kso2 = &gpio_ec_kso_02_inv; + }; + + named-gpios { + compatible = "named-gpios"; + + gpio_usb_c0_pd_int_odl: usb_c0_pd_int_odl { + gpios = <&gpioe 0 GPIO_INPUT>; + enum-name = "GPIO_USB_C0_PD_INT_ODL"; + }; + gpio_usb_c1_pd_int_odl: usb_c1_pd_int_odl { + gpios = <&gpiof 5 GPIO_INPUT>; + enum-name = "GPIO_USB_C1_PD_INT_ODL"; + }; + gpio_usb_c0_swctl_int_odl: usb_c0_swctl_int_odl { + gpios = <&gpio0 3 GPIO_INPUT>; + enum-name = "GPIO_USB_C0_SWCTL_INT_ODL"; + }; + gpio_usb_c1_swctl_int_odl: usb_c1_swctl_int_odl { + gpios = <&gpio4 0 GPIO_INPUT>; + enum-name = "GPIO_USB_C1_SWCTL_INT_ODL"; + }; + gpio_usb_c0_bc12_int_l: usb_c0_bc12_int_l { + gpios = <&gpio6 1 GPIO_INPUT_PULL_UP>; + }; + gpio_usb_c1_bc12_int_l: usb_c1_bc12_int_l { + gpios = <&gpio8 2 GPIO_INPUT_PULL_UP>; + }; + gpio_usb_a0_oc_odl: usb_a0_oc_odl { + gpios = <&gpiod 1 GPIO_INPUT_PULL_UP>; + }; + gpio_acok_od: acok_od { + gpios = <&gpio0 0 GPIO_INPUT>; + enum-name = "GPIO_AC_PRESENT"; + }; + gpio_ccd_mode_odl: ccd_mode_odl { + gpios = <&gpioe 3 GPIO_INPUT>; + enum-name = "GPIO_CCD_MODE_ODL"; + }; + gpio_ec_pwr_btn_odl: ec_pwr_btn_odl { + gpios = <&gpio0 1 GPIO_INPUT>; + enum-name = "GPIO_POWER_BUTTON_L"; + }; + gpio_ec_voldn_btn_odl: ec_voldn_btn_odl { + gpios = <&gpio7 0 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_VOLUME_DOWN_L"; + }; + gpio_ec_volup_btn_odl: ec_volup_btn_odl { + gpios = <&gpiof 2 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_VOLUME_UP_L"; + }; + gpio_ec_wp_odl: ec_wp_odl { + gpios = <&gpioa 1 (GPIO_INPUT | GPIO_ACTIVE_LOW)>; + }; + gpio_lid_open_ec: lid_open_ec { + gpios = <&gpiod 2 GPIO_INPUT>; + enum-name = "GPIO_LID_OPEN"; + }; + gpio_ap_rst_l: ap_rst_l { + gpios = <&gpioc 1 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; + enum-name = "GPIO_AP_RST_L"; + }; + gpio_ps_hold: ps_hold { + gpios = <&gpioa 4 GPIO_INPUT_PULL_DOWN>; + enum-name = "GPIO_PS_HOLD"; + }; + gpio_ap_suspend: ap_suspend { + gpios = <&gpio5 7 GPIO_INPUT>; + enum-name = "GPIO_AP_SUSPEND"; + }; + gpio_deprecated_ap_rst_req: deprecated_ap_rst_req { + gpios = <&gpioc 2 (GPIO_INPUT_PULL_DOWN | GPIO_VOLTAGE_1P8)>; + enum-name = "GPIO_DEPRECATED_AP_RST_REQ"; + }; + gpio_power_good: power_good { + gpios = <&gpio5 4 GPIO_INPUT_PULL_DOWN>; + enum-name = "GPIO_POWER_GOOD"; + }; + gpio_warm_reset_l: warm_reset_l { + gpios = <&gpiof 4 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; + enum-name = "GPIO_WARM_RESET_L"; + }; + ap_ec_spi_cs_l { + gpios = <&gpio5 3 GPIO_INPUT_PULL_DOWN>; + }; + gpio_tablet_mode_l: tablet_mode_l { + gpios = <&gpioc 6 GPIO_INPUT>; + enum-name = "GPIO_TABLET_MODE_L"; + }; + gpio_accel_gyro_int_l: accel_gyro_int_l { + gpios = <&gpioa 0 GPIO_INPUT>; + }; + gpio_da9313_gpio0: da9313_gpio0 { + gpios = <&gpioe 2 GPIO_INPUT>; + enum-name = "GPIO_DA9313_GPIO0"; + }; + /* + * Active low input + */ + gpio_switchcap_pg_int_l: switchcap_pg_int_l { + gpios = <&gpioe 2 (GPIO_ACTIVE_LOW | GPIO_INPUT)>; + }; + gpio_ec_rst_odl: ec_rst_odl { + gpios = <&gpio0 2 GPIO_INPUT>; + }; + ec_entering_rw { + gpios = <&gpioe 1 GPIO_OUTPUT_LOW>; + enum-name = "GPIO_ENTERING_RW"; + }; + ec_batt_pres_odl { + gpios = <&gpioe 5 GPIO_INPUT>; + enum-name = "GPIO_BATT_PRES_ODL"; + }; + pm845_resin_l { + gpios = <&gpio3 2 GPIO_ODR_HIGH>; + enum-name = "GPIO_PMIC_RESIN_L"; + }; + pmic_kpd_pwr_odl { + gpios = <&gpiod 6 GPIO_ODR_HIGH>; + enum-name = "GPIO_PMIC_KPD_PWR_ODL"; + }; + ec_int_l { + gpios = <&gpioa 2 GPIO_ODR_HIGH>; + enum-name = "GPIO_EC_INT_L"; + }; + qsip_on { + gpios = <&gpio5 0 GPIO_OUTPUT_LOW>; + }; + gpio_hibernate_l: hibernate_l { + gpios = <&gpio5 2 GPIO_OUTPUT_HIGH>; + }; + gpio_switchcap_on: switchcap_on { + gpios = <&gpiod 5 GPIO_OUTPUT_LOW>; + enum-name = "GPIO_SWITCHCAP_ON"; + }; + gpio_vbob_en: vbob_en { + gpios = <&gpiod 3 GPIO_OUTPUT_LOW>; + enum-name = "GPIO_VBOB_EN"; + }; + gpio_en_pp3300_a: en_pp3300_a { + gpios = <&gpioa 6 GPIO_OUTPUT_LOW>; + enum-name = "GPIO_EN_PP3300_A"; + }; + gpio_en_pp5000_a: en_pp5000_a { + gpios = <&gpio6 7 GPIO_OUTPUT_LOW>; + enum-name = "GPIO_EN_PP5000"; + }; + ec_bl_disable_l { + gpios = <&gpiob 6 GPIO_OUTPUT_LOW>; + enum-name = "GPIO_ENABLE_BACKLIGHT"; + }; + gpio_lid_accel_int_l: lid_accel_int_l { + gpios = <&gpio5 6 GPIO_INPUT>; + }; + trackpad_int_gate { + gpios = <&gpio7 4 GPIO_OUTPUT_LOW>; + }; + gpio_usb_c0_pd_rst_l: usb_c0_pd_rst_l { + gpios = <&gpiof 1 GPIO_ODR_HIGH>; + }; + gpio_usb_c1_pd_rst_l: usb_c1_pd_rst_l { + gpios = <&gpioe 4 GPIO_ODR_HIGH>; + }; + gpio_dp_mux_oe_l: dp_mux_oe_l { + gpios = <&gpio9 6 GPIO_ODR_HIGH>; + }; + gpio_dp_mux_sel: dp_mux_sel { + gpios = <&gpio4 5 GPIO_OUTPUT_LOW>; + }; + gpio_dp_hot_plug_det: dp_hot_plug_det { + gpios = <&gpio9 5 GPIO_OUTPUT_LOW>; + }; + gpio_en_usb_a_5v: en_usb_a_5v { + gpios = <&gpio8 6 GPIO_OUTPUT_LOW>; + enum-name = "GPIO_EN_USB_A_5V"; + }; + usb_a_cdp_ilim_en { + gpios = <&gpio7 5 GPIO_OUTPUT_HIGH>; + }; + gpio_ec_chg_led_y_c1: ec_chg_led_y_c1 { + #led-pin-cells = <1>; + gpios = <&gpioc 3 GPIO_OUTPUT_LOW>; + }; + gpio_ec_chg_led_b_c1: ec_chg_led_b_c1 { + #led-pin-cells = <1>; + gpios = <&gpioc 4 GPIO_OUTPUT_LOW>; + }; + gpio_brd_id0: brd_id0 { + gpios = <&gpioc 7 GPIO_INPUT>; + enum-name = "GPIO_BOARD_VERSION1"; + }; + gpio_brd_id1: brd_id1 { + gpios = <&gpio9 3 GPIO_INPUT>; + enum-name = "GPIO_BOARD_VERSION2"; + }; + gpio_brd_id2: brd_id2 { + gpios = <&gpio6 3 GPIO_INPUT>; + enum-name = "GPIO_BOARD_VERSION3"; + }; + gpio_sku_id0: sku_id0 { + gpios = <&gpiof 0 GPIO_INPUT>; + }; + gpio_sku_id1: sku_id1 { + gpios = <&gpio4 1 GPIO_INPUT>; + }; + gpio_sku_id2: sku_id2 { + gpios = <&gpiod 4 GPIO_INPUT>; + }; + arm_x86 { + gpios = <&gpio6 6 GPIO_OUTPUT_LOW>; + }; + ec-i2c-sensor-scl { + gpios = <&gpiob 3 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; + }; + ec-i2c-sensor-sda { + gpios = <&gpiob 2 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; + }; + gpio_ec_kso_02_inv: ec_kso_02_inv { + gpios = <&gpio1 7 (GPIO_OUTPUT_LOW | GPIO_ACTIVE_LOW)>; + }; + }; + + usba-port-enable-list { + compatible = "cros-ec,usba-port-enable-pins"; + enable-pins = <&gpio_en_usb_a_5v>; + }; + + hibernate-wake-pins { + compatible = "cros-ec,hibernate-wake-pins"; + wakeup-irqs = < + &int_ac_present + &int_power_button + &int_lid_open + &int_ec_rst + >; + }; + + ec-mkbp-host-event-wakeup-mask { + compatible = "ec-wake-mask-event"; + wakeup-mask = <( + HOST_EVENT_LID_OPEN | + HOST_EVENT_POWER_BUTTON | + HOST_EVENT_AC_CONNECTED | + HOST_EVENT_AC_DISCONNECTED | + HOST_EVENT_HANG_DETECT | + HOST_EVENT_RTC | + HOST_EVENT_MODE_CHANGE | + HOST_EVENT_DEVICE)>; + }; + + ec-mkbp-event-wakeup-mask { + compatible = "ec-wake-mask-event"; + wakeup-mask = <(MKBP_EVENT_KEY_MATRIX | + MKBP_EVENT_HOST_EVENT | + MKBP_EVENT_SENSOR_FIFO)>; + }; + + sku { + compatible = "cros-ec,gpio-id"; + + bits = < + &gpio_sku_id0 + &gpio_sku_id1 + &gpio_sku_id2 + >; + + system = "binary"; + }; + + board { + compatible = "cros-ec,gpio-id"; + + bits = < + &gpio_brd_id0 + &gpio_brd_id1 + &gpio_brd_id2 + >; + + system = "binary_first_base3"; + }; + + unused-pins { + compatible = "unused-gpios"; + unused-gpios = + <&gpio5 1 0>, + <&gpiod 0 0>, + <&gpiof 3 0>, + <&gpio0 4 0>, + <&gpioc 0 0>, + <&gpioa 7 0>, + <&gpio8 3 0>, + <&gpio8 1 0>, + <&gpio3 7 0>, + <&gpio7 6 0>, + <&gpio3 4 0>, + <&gpioc 5 0>, + <&gpioa 3 0>, + <&gpio7 3 0>, + <&gpiod 7 0>, + <&gpioa 5 0>, + <&gpiob 0 0>, + <&gpio9 4 0>, + <&gpiob 1 0>, + <&gpio6 2 0>, + <&gpio3 5 0>, + <&gpio9 7 0>, + <&gpio6 0 0>, + <&gpio7 2 0>; + }; +}; diff --git a/zephyr/projects/trogdor/lazor/gpio_led.dts b/zephyr/projects/trogdor/lazor/gpio_led.dts new file mode 100644 index 0000000000..c8c026506b --- /dev/null +++ b/zephyr/projects/trogdor/lazor/gpio_led.dts @@ -0,0 +1,33 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + gpio-led-pins { + compatible = "cros-ec,gpio-led-pins"; + + color_off: color-off { + led-color = "LED_OFF"; + led-id = "EC_LED_ID_BATTERY_LED"; + led-pins = <&gpio_ec_chg_led_y_c1 0>, + <&gpio_ec_chg_led_b_c1 0>; + }; + + color_amber: color-amber { + led-color = "LED_AMBER"; + led-id = "EC_LED_ID_BATTERY_LED"; + br-color = "EC_LED_COLOR_AMBER"; + led-pins = <&gpio_ec_chg_led_y_c1 1>, + <&gpio_ec_chg_led_b_c1 0>; + }; + + color_blue: color-blue { + led-color = "LED_BLUE"; + led-id = "EC_LED_ID_BATTERY_LED"; + br-color = "EC_LED_COLOR_BLUE"; + led-pins = <&gpio_ec_chg_led_y_c1 0>, + <&gpio_ec_chg_led_b_c1 1>; + }; + }; +}; diff --git a/zephyr/projects/trogdor/lazor/host_interface_npcx.dts b/zephyr/projects/trogdor/lazor/host_interface_npcx.dts new file mode 100644 index 0000000000..14efa3c6b2 --- /dev/null +++ b/zephyr/projects/trogdor/lazor/host_interface_npcx.dts @@ -0,0 +1,12 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* host interface */ +&shi { + status = "okay"; + pinctrl-0 = <&shi_gp46_47_53_55>; + pinctrl-1 = <&shi_gpio_gp46_47_53_55>; + pinctrl-names = "default", "sleep"; +}; diff --git a/zephyr/projects/trogdor/lazor/i2c.dts b/zephyr/projects/trogdor/lazor/i2c.dts new file mode 100644 index 0000000000..e19ad224a9 --- /dev/null +++ b/zephyr/projects/trogdor/lazor/i2c.dts @@ -0,0 +1,145 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + named-i2c-ports { + compatible = "named-i2c-ports"; + + i2c_power: power { + i2c-port = <&i2c0_0>; + remote-port = <0>; + enum-names = "I2C_PORT_POWER", + "I2C_PORT_BATTERY", + "I2C_PORT_VIRTUAL_BATTERY", + "I2C_PORT_CHARGER"; + }; + i2c_tcpc0: tcpc0 { + i2c-port = <&i2c1_0>; + enum-names = "I2C_PORT_TCPC0"; + }; + i2c_tcpc1: tcpc1 { + i2c-port = <&i2c2_0>; + enum-names = "I2C_PORT_TCPC1"; + }; + i2c_eeprom: eeprom { + i2c-port = <&i2c5_0>; + enum-names = "I2C_PORT_EEPROM"; + }; + i2c_sensor: sensor { + i2c-port = <&i2c7_0>; + enum-names = "I2C_PORT_SENSOR", + "I2C_PORT_ACCEL"; + }; + }; + +}; + +&i2c0_0 { + status = "okay"; + clock-frequency = <I2C_BITRATE_STANDARD>; + pinctrl-0 = <&i2c0_0_sda_scl_gpb4_b5>; + pinctrl-names = "default"; + + bc12_port0: pi3usb9201@5f { + compatible = "pericom,pi3usb9201"; + status = "okay"; + reg = <0x5f>; + irq = <&int_usb_c0_bc12>; + }; + + charger: isl923x@9 { + compatible = "intersil,isl923x"; + status = "okay"; + reg = <0x9>; + }; +}; + +&i2c_ctrl0 { + status = "okay"; +}; + +&i2c1_0 { + status = "okay"; + clock-frequency = <I2C_BITRATE_FAST_PLUS>; + pinctrl-0 = <&i2c1_0_sda_scl_gp87_90>; + pinctrl-names = "default"; + + ppc_port0: sn5s330@40 { + compatible = "ti,sn5s330"; + status = "okay"; + reg = <0x40>; + }; + + tcpc_port0: ps8xxx@b { + compatible = "parade,ps8xxx"; + status = "okay"; + reg = <0xb>; + }; +}; + +&i2c_ctrl1 { + status = "okay"; +}; + +&i2c2_0 { + status = "okay"; + clock-frequency = <I2C_BITRATE_FAST_PLUS>; + pinctrl-0 = <&i2c2_0_sda_scl_gp91_92>; + pinctrl-names = "default"; + + ppc_port1: sn5s330@40{ + compatible = "ti,sn5s330"; + status = "okay"; + reg = <0x40>; + }; + + tcpc_port1: ps8xxx@b { + compatible = "parade,ps8xxx"; + status = "okay"; + reg = <0xb>; + }; +}; + +&i2c_ctrl2 { + status = "okay"; +}; + +&i2c3_0 { + /* Not used as no WLC connected */ + clock-frequency = <I2C_BITRATE_FAST>; +}; + +&i2c_ctrl3 { + status = "okay"; +}; + +&i2c5_0 { + status = "okay"; + clock-frequency = <I2C_BITRATE_FAST>; + pinctrl-0 = <&i2c5_0_sda_scl_gp33_36>; + pinctrl-names = "default"; + + bc12_port1: pi3usb9201@5f { + compatible = "pericom,pi3usb9201"; + status = "okay"; + reg = <0x5f>; + irq = <&int_usb_c1_bc12>; + }; +}; + +&i2c_ctrl5 { + status = "okay"; +}; + +&i2c7_0 { + status = "okay"; + clock-frequency = <I2C_BITRATE_FAST>; + pinctrl-0 = <&i2c7_0_sda_scl_gpb2_b3>; + pinctrl-names = "default"; +}; + +&i2c_ctrl7 { + status = "okay"; +}; diff --git a/zephyr/projects/trogdor/lazor/include/sku.h b/zephyr/projects/trogdor/lazor/include/sku.h new file mode 100644 index 0000000000..76825bbba1 --- /dev/null +++ b/zephyr/projects/trogdor/lazor/include/sku.h @@ -0,0 +1,17 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Lazor board-specific SKU configuration */ + +#ifndef __ZEPHYR_LAZOR_SKU_H +#define __ZEPHYR_LAZOR_SKU_H + +int board_get_version(void); +int board_is_clamshell(void); +int board_has_da9313(void); +int board_has_ln9310(void); +int board_has_buck_ic(void); + +#endif /* __ZEPHYR_LAZOR_SKU_H */ diff --git a/zephyr/projects/trogdor/lazor/interrupts.dts b/zephyr/projects/trogdor/lazor/interrupts.dts new file mode 100644 index 0000000000..5c2ed35e90 --- /dev/null +++ b/zephyr/projects/trogdor/lazor/interrupts.dts @@ -0,0 +1,140 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + aliases { + int-wp = &int_wp; + }; + + gpio-interrupts { + compatible = "cros-ec,gpio-interrupts"; + + int_ac_present: ac_present { + irq-pin = <&gpio_acok_od>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "extpower_interrupt"; + }; + int_lid_open: lid_open { + irq-pin = <&gpio_lid_open_ec>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "lid_interrupt"; + }; + int_wp: wp { + irq-pin = <&gpio_ec_wp_odl>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "switch_interrupt"; + }; + int_power_button: power_button { + irq-pin = <&gpio_ec_pwr_btn_odl>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "power_button_interrupt"; + }; + int_volume_up: volume_up { + irq-pin = <&gpio_ec_volup_btn_odl>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "button_interrupt"; + }; + int_volume_down: volume_down { + irq-pin = <&gpio_ec_voldn_btn_odl>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "button_interrupt"; + }; + /* + * Note this is an active low input, so + * the direction is from logical low to + * logical high. + */ + int_switchcap_pg: switchcap_pg { + irq-pin = <&gpio_switchcap_pg_int_l>; + flags = <GPIO_INT_EDGE_RISING>; + handler = "ln9310_interrupt"; + }; + int_ap_rst: ap_rst { + irq-pin = <&gpio_ap_rst_l>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "chipset_ap_rst_interrupt"; + }; + int_ap_suspend: ap_suspend { + irq-pin = <&gpio_ap_suspend>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "power_signal_interrupt"; + }; + int_deprecated_ap_rst_req: deprecated_ap_rst_req { + irq-pin = <&gpio_deprecated_ap_rst_req>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "power_signal_interrupt"; + }; + int_power_good: power_good { + irq-pin = <&gpio_power_good>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "chipset_power_good_interrupt"; + }; + int_ps_hold: ps_hold { + irq-pin = <&gpio_ps_hold>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "power_signal_interrupt"; + }; + int_warm_reset: warm_reset { + irq-pin = <&gpio_warm_reset_l>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "chipset_warm_reset_interrupt"; + }; + int_usb_c0_tcpc: usb_c0_tcpc { + irq-pin = <&gpio_usb_c0_pd_int_odl>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "tcpc_alert_event"; + }; + int_usb_c1_tcpc: usb_c1_tcpc { + irq-pin = <&gpio_usb_c1_pd_int_odl>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "tcpc_alert_event"; + }; + int_usb_c0_swctl: usb_c0_swctl { + irq-pin = <&gpio_usb_c0_swctl_int_odl>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "ppc_interrupt"; + }; + int_usb_c1_swctl: usb_c1_swctl { + irq-pin = <&gpio_usb_c1_swctl_int_odl>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "ppc_interrupt"; + }; + int_usb_c0_bc12: usb_c0_bc12 { + irq-pin = <&gpio_usb_c0_bc12_int_l>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "usb0_evt"; + }; + int_usb_c1_bc12: usb_c1_bc12 { + irq-pin = <&gpio_usb_c1_bc12_int_l>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "usb1_evt"; + }; + int_usb_a0_oc: usb_a0_oc { + irq-pin = <&gpio_usb_a0_oc_odl>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "usba_oc_interrupt"; + }; + int_ccd_mode: ccd_mode { + irq-pin = <&gpio_ccd_mode_odl>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "board_connect_c0_sbu"; + }; + int_accel: accel { + irq-pin = <&gpio_accel_gyro_int_l>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "bmi160_interrupt"; + }; + int_tablet_mode: tablet_mode { + irq-pin = <&gpio_tablet_mode_l>; + flags = <GPIO_INT_EDGE_BOTH>; + handler = "gmr_tablet_switch_isr"; + }; + int_ec_rst: ec_rst { + irq-pin = <&gpio_ec_rst_odl>; + flags = <GPIO_INT_EDGE_FALLING>; + handler = "wake_isr"; + }; + }; +}; diff --git a/zephyr/projects/trogdor/lazor/keyboard.dts b/zephyr/projects/trogdor/lazor/keyboard.dts new file mode 100644 index 0000000000..b8689b883c --- /dev/null +++ b/zephyr/projects/trogdor/lazor/keyboard.dts @@ -0,0 +1,38 @@ +/* Copyright 2021 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + cros-keyscan { + compatible = "cros-keyscan"; + + actual-key-mask = < + 0x14 /* C0 */ + 0xff /* C1 */ + 0xff /* C2 */ + 0xff /* C3 */ + 0xff /* C4 */ + 0xf5 /* C5 */ + 0xff /* C6 */ + 0xa4 /* C7 */ + 0xff /* C8 */ + 0xfe /* C9 */ + 0x55 /* C10 */ + 0xfa /* C11 */ + 0xca /* C12 */ + >; + }; + + kblight { + compatible = "cros-ec,kblight-pwm"; + pwms = <&pwm3 0 PWM_KHZ(10) PWM_POLARITY_NORMAL>; + generic-pwm-channel = <0>; + }; +}; + +&pwm3 { + status = "okay"; + pinctrl-0 = <&pwm3_gp80>; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/trogdor/lazor/led.dts b/zephyr/projects/trogdor/lazor/led.dts new file mode 100644 index 0000000000..4527afd34c --- /dev/null +++ b/zephyr/projects/trogdor/lazor/led.dts @@ -0,0 +1,90 @@ +/ { + led-colors { + compatible = "cros-ec,led-policy"; + + power-state-charge { + charge-state = "PWR_STATE_CHARGE"; + + color-0 { + led-color = <&color_amber>; + }; + }; + + power-state-discharge-s0 { + charge-state = "PWR_STATE_DISCHARGE"; + chipset-state = "POWER_S0"; + + color-0 { + led-color = <&color_blue>; + }; + }; + + power-state-discharge-s3 { + charge-state = "PWR_STATE_DISCHARGE"; + chipset-state = "POWER_S3"; + + /* Amber 1 sec, off 3 sec */ + color-0 { + led-color = <&color_amber>; + period-ms = <1000>; + }; + color-1 { + led-color = <&color_off>; + period-ms = <3000>; + }; + }; + + power-state-discharge-s5 { + charge-state = "PWR_STATE_DISCHARGE"; + chipset-state = "POWER_S5"; + + color-0 { + led-color = <&color_off>; + }; + }; + + power-state-error { + charge-state = "PWR_STATE_ERROR"; + + /* Amber 1 sec, off 1 sec */ + color-0 { + led-color = <&color_amber>; + period-ms = <1000>; + }; + color-1 { + led-color = <&color_off>; + period-ms = <1000>; + }; + }; + + power-state-near-full { + charge-state = "PWR_STATE_CHARGE_NEAR_FULL"; + + color-0 { + led-color = <&color_blue>; + }; + }; + + power-state-forced-idle { + charge-state = "PWR_STATE_FORCED_IDLE"; + + /* Blue 2 sec, Amber 2 sec */ + color-0 { + led-color = <&color_blue>; + period-ms = <2000>; + }; + color-1 { + led-color = <&color_amber>; + period-ms = <2000>; + }; + }; + + power-state-idle { + charge-state = "PWR_STATE_IDLE"; + + color-0 { + led-color = <&color_blue>; + }; + }; + }; +}; diff --git a/zephyr/projects/trogdor/lazor/motionsense.dts b/zephyr/projects/trogdor/lazor/motionsense.dts new file mode 100644 index 0000000000..75fe31b997 --- /dev/null +++ b/zephyr/projects/trogdor/lazor/motionsense.dts @@ -0,0 +1,181 @@ +/* Copyright 2020 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <dt-bindings/motionsense/utils.h> + + +/ { + aliases { + /* + * motion sense's <>_INT_EVENT is handled + * by alias. Using the alias, each driver creates + * its own <>_INT_EVENT. + */ + bmi160-int = &base_accel; + }; + + /* + * Declare mutexes used by sensor drivers. + * A mutex node is used to create an instance of mutex_t. + * A mutex node is referenced by a sensor node if the + * corresponding sensor driver needs to use the + * instance of the mutex. + */ + motionsense-mutex { + compatible = "cros-ec,motionsense-mutex"; + lid_mutex: lid-mutex { + }; + + mutex_bmi160: bmi160-mutex { + }; + }; + + /* Rotation matrix used by drivers. */ + motionsense-rotation-ref { + compatible = "cros-ec,motionsense-rotation-ref"; + lid_rot_ref: lid-rotation-ref { + mat33 = <(-1) 0 0 + 0 (-1) 0 + 0 0 1>; + }; + + base_rot_ref: base-rotation-ref { + mat33 = <1 0 0 + 0 (-1) 0 + 0 0 (-1)>; + }; + }; + + /* + * Driver specific data. A driver-specific data can be shared with + * different motion sensors while they are using the same driver. + * + * If a node's compatible starts with "cros-ec,accelgyro-", it is for + * a common structure defined in accelgyro.h. + * e.g) compatible = "cros-ec,accelgyro-als-drv-data" is for + * "struct als_drv_data_t" in accelgyro.h + */ + motionsense-sensor-data { + bma255_data: bma255-drv-data { + compatible = "cros-ec,drvdata-bma255"; + status = "okay"; + }; + + bmi160_data: bmi160-drv-data { + compatible = "cros-ec,drvdata-bmi160"; + status = "okay"; + }; + + kx022_data: kx022-drv-data { + compatible = "cros-ec,drvdata-kionix"; + status = "okay"; + }; + }; + + /* + * List of motion sensors that creates motion_sensors array. + * The nodelabel "lid_accel" and "base_accel" are used to indicate + * motion sensor IDs for lid angle calculation. + */ + motionsense-sensor { + lid_accel: lid-accel { + compatible = "cros-ec,bma255"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3_S5"; + location = "MOTIONSENSE_LOC_LID"; + mutex = <&lid_mutex>; + port = <&i2c_sensor>; + rot-standard-ref = <&lid_rot_ref>; + default-range = <2>; + drv-data = <&bma255_data>; + i2c-spi-addr-flags = "BMA2x2_I2C_ADDR1_FLAGS"; + configs { + compatible = + "cros-ec,motionsense-sensor-config"; + ec-s0 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + ec-s3 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + }; + }; + + base_accel: base-accel { + compatible = "cros-ec,bmi160-accel"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3_S5"; + location = "MOTIONSENSE_LOC_BASE"; + mutex = <&mutex_bmi160>; + port = <&i2c_sensor>; + rot-standard-ref = <&base_rot_ref>; + drv-data = <&bmi160_data>; + configs { + compatible = + "cros-ec,motionsense-sensor-config"; + ec-s0 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + ec-s3 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + }; + }; + + base-gyro { + compatible = "cros-ec,bmi160-gyro"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3_S5"; + location = "MOTIONSENSE_LOC_BASE"; + mutex = <&mutex_bmi160>; + port = <&i2c_sensor>; + rot-standard-ref = <&base_rot_ref>; + drv-data = <&bmi160_data>; + }; + }; + + /* + * List of alternative motion sensors that creates + * motion_sensors_alt array. + */ + motionsense-sensor-alt { + alt_lid_accel { + compatible = "cros-ec,kx022"; + status = "okay"; + active-mask = "SENSOR_ACTIVE_S0_S3_S5"; + location = "MOTIONSENSE_LOC_LID"; + mutex = <&lid_mutex>; + port = <&i2c_sensor>; + rot-standard-ref = <&lid_rot_ref>; + drv-data = <&kx022_data>; + alternate-for = <&lid_accel>; + configs { + compatible = + "cros-ec,motionsense-sensor-config"; + ec-s0 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + ec-s3 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + }; + }; + }; + + motionsense-sensor-info { + compatible = "cros-ec,motionsense-sensor-info"; + + /* + * list of GPIO interrupts that have to + * be enabled at initial stage + */ + sensor-irqs = <&int_accel>; + /* list of sensors in force mode */ + accel-force-mode-sensors = <&lid_accel>; + }; +}; diff --git a/zephyr/projects/trogdor/lazor/prj.conf b/zephyr/projects/trogdor/lazor/prj.conf new file mode 100644 index 0000000000..358de69d68 --- /dev/null +++ b/zephyr/projects/trogdor/lazor/prj.conf @@ -0,0 +1,164 @@ +# Copyright 2021 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +CONFIG_CROS_EC=y +# +# Lazor actually has a NPCX7M6FC, but +# the NPCX7M7FC is actually the same die, without the +# extra RAM being tested. The code size really could +# do with the extra space, so we pretend the EC is the +# part with the larger RAM. YMMV. +# +CONFIG_SOC_NPCX7M7FC=y +CONFIG_SOC_SERIES_NPCX7=y +CONFIG_SHIMMED_TASKS=y +CONFIG_PLATFORM_EC=y +CONFIG_PLATFORM_EC_BRINGUP=y +CONFIG_PLATFORM_EC_EXTPOWER_GPIO=y +CONFIG_PLATFORM_EC_SWITCH=y +CONFIG_PLATFORM_EC_LID_SWITCH=y +CONFIG_PLATFORM_EC_BACKLIGHT_LID=y +CONFIG_PLATFORM_EC_POWER_BUTTON=y + +# I2C +CONFIG_I2C=y + +# LED +CONFIG_PLATFORM_EC_LED_DT=y + +# PWM +CONFIG_PWM=y +CONFIG_PWM_SHELL=n + +# Application Processor is Qualcomm SC7180 +CONFIG_AP_ARM_QUALCOMM_SC7180=y + +# Board version is selected over GPIO board ID pins. +CONFIG_PLATFORM_EC_BOARD_VERSION_GPIO=y + +# LN9310 Switchcap +CONFIG_PLATFORM_EC_SWITCHCAP_LN9310=y + +# Power Sequencing +CONFIG_PLATFORM_EC_POWERSEQ=y +CONFIG_PLATFORM_EC_POWERSEQ_HOST_SLEEP=y +CONFIG_PLATFORM_EC_POWER_SLEEP_FAILURE_DETECTION=y +CONFIG_PLATFORM_EC_CHIPSET_RESET_HOOK=y +CONFIG_PLATFORM_EC_CHIPSET_RESUME_INIT_HOOK=y + +# Trogdor family does not use EFS2 +CONFIG_PLATFORM_EC_VBOOT_EFS2=n + +# MKBP event +CONFIG_PLATFORM_EC_MKBP_EVENT=y +CONFIG_PLATFORM_EC_MKBP_USE_GPIO=y + +# Keyboard +CONFIG_PLATFORM_EC_KEYBOARD=y +CONFIG_PLATFORM_EC_KEYBOARD_PROTOCOL_MKBP=y +CONFIG_PLATFORM_EC_MKBP_INPUT_DEVICES=y +CONFIG_PLATFORM_EC_KEYBOARD_COL2_INVERTED=y +CONFIG_PLATFORM_EC_VOLUME_BUTTONS=y +CONFIG_PLATFORM_EC_CMD_BUTTON=y +CONFIG_CROS_KB_RAW_NPCX=y + +# ADC +CONFIG_ADC=y +CONFIG_ADC_SHELL=n + +# Battery +CONFIG_PLATFORM_EC_BATTERY=y +CONFIG_PLATFORM_EC_BATTERY_SMART=y +CONFIG_PLATFORM_EC_I2C_VIRTUAL_BATTERY=y +CONFIG_PLATFORM_EC_I2C_PASSTHRU_RESTRICTED=y +CONFIG_PLATFORM_EC_BATTERY_FUEL_GAUGE=y +CONFIG_PLATFORM_EC_BATTERY_CUT_OFF=y +CONFIG_PLATFORM_EC_BATTERY_PRESENT_GPIO=y +CONFIG_PLATFORM_EC_CHARGER_ISL9238=y +CONFIG_PLATFORM_EC_CHARGE_RAMP_HW=y +CONFIG_PLATFORM_EC_USE_BATTERY_DEVICE_CHEMISTRY=y +CONFIG_PLATFORM_EC_BATTERY_DEVICE_CHEMISTRY="LION" +CONFIG_PLATFORM_EC_BATTERY_REVIVE_DISCONNECT=y +CONFIG_PLATFORM_EC_CHARGER_DISCHARGE_ON_AC=y +CONFIG_PLATFORM_EC_CHARGER_DISCHARGE_ON_AC_CHARGER=y +CONFIG_PLATFORM_EC_CHARGER_MIN_BAT_PCT_FOR_POWER_ON=2 +CONFIG_PLATFORM_EC_CHARGER_MIN_POWER_MW_FOR_POWER_ON=10000 +CONFIG_PLATFORM_EC_CHARGER_PROFILE_OVERRIDE=y +CONFIG_PLATFORM_EC_CHARGER_PSYS=y +CONFIG_PLATFORM_EC_CHARGER_PSYS_READ=y +CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR=10 +CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR_AC=20 +CONFIG_PLATFORM_EC_CONSOLE_CMD_CHARGER_ADC_AMON_BMON=y + +# USB-A +CONFIG_PLATFORM_EC_USBA=y + +# USB-C +CONFIG_PLATFORM_EC_BC12_DETECT_PI3USB9201=y +CONFIG_PLATFORM_EC_USB_PD_USB32_DRD=n +CONFIG_PLATFORM_EC_USBC_PPC_SN5S330=y +CONFIG_PLATFORM_EC_USBC_RETIMER_FW_UPDATE=n +CONFIG_PLATFORM_EC_USBC_SS_MUX_DFP_ONLY=y +CONFIG_PLATFORM_EC_USB_DRP_ACC_TRYSRC=y +CONFIG_PLATFORM_EC_USB_PD_5V_EN_CUSTOM=y +CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_TCPC=y +CONFIG_PLATFORM_EC_USB_PD_DISCHARGE_PPC=y +CONFIG_PLATFORM_EC_USB_PD_REV30=n +CONFIG_PLATFORM_EC_USB_PD_TBT_COMPAT_MODE=n +CONFIG_PLATFORM_EC_USB_PD_USB4=n +CONFIG_PLATFORM_EC_USB_PD_TCPC_LOW_POWER=y +CONFIG_PLATFORM_EC_USB_PD_TCPM_MULTI_PS8XXX=y +CONFIG_PLATFORM_EC_USB_PD_TCPM_PS8751=y +CONFIG_PLATFORM_EC_USB_PD_TCPM_PS8805=y +CONFIG_PLATFORM_EC_USB_PD_TCPC_RUNTIME_CONFIG=n +CONFIG_PLATFORM_EC_USB_MUX_RUNTIME_CONFIG=n +CONFIG_PLATFORM_EC_USB_PD_LOGGING=y + +# USB ID +# This is allocated specifically for Trogdor +# http://google3/hardware/standards/usb/ +# TODO(b/183608112): Move to device tree +CONFIG_PLATFORM_EC_USB_PID=0x5043 + +# RTC +CONFIG_PLATFORM_EC_RTC=y +CONFIG_CROS_RTC_NPCX=y +CONFIG_PLATFORM_EC_HOSTCMD_RTC=y +CONFIG_PLATFORM_EC_CONSOLE_CMD_RTC=y + +# EC software sync +CONFIG_PLATFORM_EC_VBOOT_HASH=y + +# Sensors +CONFIG_PLATFORM_EC_MOTIONSENSE=y +CONFIG_PLATFORM_EC_ACCEL_FIFO=y +CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCELS=y +CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCEL_INFO=y +CONFIG_PLATFORM_EC_GMR_TABLET_MODE=y +CONFIG_PLATFORM_EC_LID_ANGLE=y +CONFIG_PLATFORM_EC_LID_ANGLE_UPDATE=y +CONFIG_PLATFORM_EC_SENSOR_TIGHT_TIMESTAMPS=y +CONFIG_PLATFORM_EC_TABLET_MODE=y +CONFIG_PLATFORM_EC_TABLET_MODE_SWITCH=y + +# Sensor Drivers +CONFIG_PLATFORM_EC_ACCEL_BMA255=y +CONFIG_PLATFORM_EC_ACCELGYRO_BMI160=y +CONFIG_PLATFORM_EC_ACCELGYRO_BMI_COMM_I2C=y + +# Console history +CONFIG_SHELL_HISTORY=y +CONFIG_SHELL_CMDS=y +CONFIG_SHELL_HELP=n +CONFIG_SHELL_MINIMAL=y + +# Taskinfo +CONFIG_THREAD_MONITOR=y +CONFIG_KERNEL_SHELL=y + +CONFIG_SYSCON=y + +# Features should be enabled. But the code RAM is not enough, disable them. +#CONFIG_PLATFORM_EC_ACCEL_SPOOF_MODE=y +#CONFIG_PLATFORM_EC_EMULATED_SYSRQ=y diff --git a/zephyr/projects/trogdor/lazor/pwm_led.dts b/zephyr/projects/trogdor/lazor/pwm_led.dts new file mode 100644 index 0000000000..0582966d6a --- /dev/null +++ b/zephyr/projects/trogdor/lazor/pwm_led.dts @@ -0,0 +1,59 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + pwm_pins { + compatible = "cros-ec,pwm-pin-config"; + + pwm_y: pwm_y { + #led-pin-cells = <1>; + pwms = <&pwm0 0 PWM_HZ(324) PWM_POLARITY_NORMAL>; + }; + + pwm_b: pwm_b { + #led-pin-cells = <1>; + pwms = <&pwm2 0 PWM_HZ(324) PWM_POLARITY_NORMAL>; + }; + }; + + pwm-led-pins { + compatible = "cros-ec,pwm-led-pins"; + + color_off: color-off { + led-color = "LED_OFF"; + led-id = "EC_LED_ID_BATTERY_LED"; + led-pins = <&pwm_y 0>, + <&pwm_b 0>; + }; + + color_amber: color-amber { + led-color = "LED_AMBER"; + led-id = "EC_LED_ID_BATTERY_LED"; + br-color = "EC_LED_COLOR_AMBER"; + led-pins = <&pwm_y 100>, + <&pwm_b 0>; + }; + + color_blue: color-blue { + led-color = "LED_BLUE"; + led-id = "EC_LED_ID_BATTERY_LED"; + br-color = "EC_LED_COLOR_BLUE"; + led-pins = <&pwm_y 0>, + <&pwm_b 100>; + }; + }; +}; + +&pwm0 { + status = "okay"; + pinctrl-0 = <&pwm0_gpc3>; + pinctrl-names = "default"; +}; + +&pwm2 { + status = "okay"; + pinctrl-0 = <&pwm2_gpc4>; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/trogdor/lazor/src/hibernate.c b/zephyr/projects/trogdor/lazor/src/hibernate.c new file mode 100644 index 0000000000..388ff1b087 --- /dev/null +++ b/zephyr/projects/trogdor/lazor/src/hibernate.c @@ -0,0 +1,48 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "common.h" +#include "sku.h" +#include "system.h" +#include "usbc_ppc.h" + +void board_hibernate(void) +{ + int i; + + if (!board_is_clamshell()) { + /* + * Sensors are unpowered in hibernate. Apply PD to the + * interrupt lines such that they don't float. + */ + gpio_pin_configure_dt( + GPIO_DT_FROM_NODELABEL(gpio_accel_gyro_int_l), + GPIO_DISCONNECTED); + gpio_pin_configure_dt( + GPIO_DT_FROM_NODELABEL(gpio_lid_accel_int_l), + GPIO_DISCONNECTED); + } + + /* + * Board rev 5+ has the hardware fix. Don't need the following + * workaround. + */ + if (system_get_board_version() >= 5) + return; + + /* + * Enable the PPC power sink path before EC enters hibernate; + * otherwise, ACOK won't go High and can't wake EC up. Check the + * bug b/170324206 for details. + */ + for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) + ppc_vbus_sink_enable(i, 1); +} + +void board_hibernate_late(void) +{ + /* Set the hibernate GPIO to turn off the rails */ + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_hibernate_l), 0); +} diff --git a/zephyr/projects/trogdor/lazor/src/i2c.c b/zephyr/projects/trogdor/lazor/src/i2c.c new file mode 100644 index 0000000000..6d737b410f --- /dev/null +++ b/zephyr/projects/trogdor/lazor/src/i2c.c @@ -0,0 +1,17 @@ +/* Copyright 2021 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "i2c/i2c.h" +#include "i2c.h" + +/* Lazor board specific i2c implementation */ + +#ifdef CONFIG_PLATFORM_EC_I2C_PASSTHRU_RESTRICTED +int board_allow_i2c_passthru(const struct i2c_cmd_desc_t *cmd_desc) +{ + return (i2c_get_device_for_port(cmd_desc->port) == + i2c_get_device_for_port(I2C_PORT_VIRTUAL_BATTERY)); +} +#endif diff --git a/zephyr/projects/trogdor/lazor/src/power.c b/zephyr/projects/trogdor/lazor/src/power.c new file mode 100644 index 0000000000..96f9bc43c5 --- /dev/null +++ b/zephyr/projects/trogdor/lazor/src/power.c @@ -0,0 +1,58 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <zephyr/init.h> +#include <zephyr/drivers/gpio.h> + +#include <ap_power/ap_power.h> +#include "power.h" +#include "task.h" +#include "gpio.h" + +static void board_power_change(struct ap_power_ev_callback *cb, + struct ap_power_ev_data data) +{ + switch (data.event) { + default: + return; + + case AP_POWER_PRE_INIT: + /* Turn on the 3.3V rail */ + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_en_pp3300_a), 1); + + /* Turn on the 5V rail. */ +#ifdef CONFIG_POWER_PP5000_CONTROL + power_5v_enable(task_get_current(), 1); +#else /* !defined(CONFIG_POWER_PP5000_CONTROL) */ + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_en_pp5000_a), 1); +#endif /* defined(CONFIG_POWER_PP5000_CONTROL) */ + break; + + case AP_POWER_SHUTDOWN_COMPLETE: + /* Turn off the 5V rail. */ +#ifdef CONFIG_POWER_PP5000_CONTROL + power_5v_enable(task_get_current(), 0); +#else /* !defined(CONFIG_POWER_PP5000_CONTROL) */ + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_en_pp5000_a), 0); +#endif /* defined(CONFIG_POWER_PP5000_CONTROL) */ + + /* Turn off the 3.3V and 5V rails. */ + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_en_pp3300_a), 0); + break; + } +} + +static int board_power_handler_init(const struct device *unused) +{ + static struct ap_power_ev_callback cb; + + /* Setup a suspend/resume callback */ + ap_power_ev_init_callback(&cb, board_power_change, + AP_POWER_PRE_INIT | + AP_POWER_SHUTDOWN_COMPLETE); + ap_power_ev_add_callback(&cb); + return 0; +} +SYS_INIT(board_power_handler_init, APPLICATION, 1); diff --git a/zephyr/projects/trogdor/lazor/src/sku.c b/zephyr/projects/trogdor/lazor/src/sku.c new file mode 100644 index 0000000000..1d88437031 --- /dev/null +++ b/zephyr/projects/trogdor/lazor/src/sku.c @@ -0,0 +1,92 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "common.h" +#include "config.h" +#include "console.h" +#include "driver/ln9310.h" +#include "tcpm/ps8xxx_public.h" +#include "hooks.h" +#include "sku.h" +#include "system.h" +#include "util.h" + +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) + +static uint8_t sku_id; + +enum board_model { + LAZOR, + LIMOZEEN, + UNKNOWN, +}; + +static const char *const model_name[] = { + "LAZOR", + "LIMOZEEN", + "UNKNOWN", +}; + +static enum board_model get_model(void) +{ + if (sku_id == 0 || sku_id == 1 || sku_id == 2 || sku_id == 3) + return LAZOR; + if (sku_id == 4 || sku_id == 5 || sku_id == 6) + return LIMOZEEN; + return UNKNOWN; +} + +/* Read SKU ID from GPIO and initialize variables for board variants */ +static void sku_init(void) +{ + sku_id = system_get_sku_id(); + CPRINTS("SKU: %u (%s)", sku_id, model_name[get_model()]); +} +DECLARE_HOOK(HOOK_INIT, sku_init, HOOK_PRIO_POST_I2C); + +enum battery_cell_type board_get_battery_cell_type(void) +{ + switch (get_model()) { + case LIMOZEEN: + return BATTERY_CELL_TYPE_3S; + default: + return BATTERY_CELL_TYPE_UNKNOWN; + } +} + +int board_is_clamshell(void) +{ + return get_model() == LIMOZEEN; +} + +__override uint16_t board_get_ps8xxx_product_id(int port) +{ + /* + * Lazor (SKU_ID: 0, 1, 2, 3) rev 3+ changes TCPC from PS8751 to + * PS8805. + * + * Limozeen (SKU_ID: 4, 5, 6) all-rev uses PS8805. + */ + if (get_model() == LAZOR && system_get_board_version() < 3) + return PS8751_PRODUCT_ID; + + return PS8805_PRODUCT_ID; +} + +int board_has_da9313(void) +{ + return get_model() == LAZOR; +} + +int board_has_buck_ic(void) +{ + return get_model() == LIMOZEEN && system_get_board_version() >= 8; +} + +int board_has_ln9310(void) +{ + return get_model() == LIMOZEEN && system_get_board_version() < 8; +} diff --git a/zephyr/projects/trogdor/lazor/src/switchcap.c b/zephyr/projects/trogdor/lazor/src/switchcap.c new file mode 100644 index 0000000000..d8205cbcfc --- /dev/null +++ b/zephyr/projects/trogdor/lazor/src/switchcap.c @@ -0,0 +1,128 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <zephyr/drivers/gpio.h> + +#include "common.h" +#include "config.h" +#include "console.h" +#include "driver/ln9310.h" +#include "gpio/gpio_int.h" +#include "hooks.h" +#include "i2c.h" +#include "power/qcom.h" +#include "system.h" +#include "sku.h" + +#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_I2C, format, ##args) + +/* LN9310 switchcap */ +const struct ln9310_config_t ln9310_config = { + .i2c_port = I2C_PORT_POWER, + .i2c_addr_flags = LN9310_I2C_ADDR_0_FLAGS, +}; + +static void switchcap_init(void) +{ + if (board_has_da9313()) { + CPRINTS("Use switchcap: DA9313"); + + /* + * When the chip in power down mode, it outputs high-Z. + * Set pull-down to avoid floating. + */ + gpio_pin_configure_dt(GPIO_DT_FROM_NODELABEL(gpio_da9313_gpio0), + GPIO_INPUT | GPIO_PULL_DOWN); + + /* + * Configure DA9313 enable, push-pull output. Don't set the + * level here; otherwise, it will override its value and + * shutdown the switchcap when sysjump to RW. + */ + gpio_pin_configure_dt(GPIO_DT_FROM_NODELABEL(gpio_switchcap_on), + GPIO_OUTPUT); + } else if (board_has_ln9310()) { + CPRINTS("Use switchcap: LN9310"); + + /* Enable interrupt for LN9310 */ + gpio_enable_dt_interrupt( + GPIO_INT_FROM_NODELABEL(int_switchcap_pg)); + + /* + * Configure LN9310 enable, open-drain output. Don't set the + * level here; otherwise, it will override its value and + * shutdown the switchcap when sysjump to RW. + * + * Note that the gpio.inc configures it GPIO_OUT_LOW. When + * sysjump to RW, will output push-pull a short period of + * time. As it outputs LOW, should be fine. + * + * This GPIO changes like: + * (1) EC boots from RO -> high-Z + * (2) GPIO init according to gpio.inc -> push-pull LOW + * (3) This function configures it -> open-drain HIGH + * (4) Power sequence turns on the switchcap -> open-drain LOW + * (5) EC sysjumps to RW + * (6) GPIO init according to gpio.inc -> push-pull LOW + * (7) This function configures it -> open-drain LOW + */ + gpio_pin_configure_dt(GPIO_DT_FROM_NODELABEL(gpio_switchcap_on), + GPIO_OUTPUT | GPIO_OPEN_DRAIN); + + /* Only configure the switchcap if not sysjump */ + if (!system_jumped_late()) { + /* + * Deassert the enable pin, so the + * switchcap won't be enabled after the switchcap is + * configured from standby mode to switching mode. + */ + gpio_pin_set_dt( + GPIO_DT_FROM_NODELABEL(gpio_switchcap_on), 0); + ln9310_init(); + } + } else if (board_has_buck_ic()) { + CPRINTS("Use Buck IC"); + } else { + CPRINTS("ERROR: No switchcap solution"); + } +} +DECLARE_HOOK(HOOK_INIT, switchcap_init, HOOK_PRIO_DEFAULT); + +void board_set_switchcap_power(int enable) +{ + if (board_has_da9313()) { + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_switchcap_on), + enable); + } else if (board_has_ln9310()) { + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_switchcap_on), + enable); + ln9310_software_enable(enable); + } else if (board_has_buck_ic()) { + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_vbob_en), enable); + } +} + +int board_is_switchcap_enabled(void) +{ + if (board_has_da9313() || board_has_ln9310()) + return gpio_pin_get_dt( + GPIO_DT_FROM_NODELABEL(gpio_switchcap_on)); + + /* Board has buck ic*/ + return gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_vbob_en)); +} + +int board_is_switchcap_power_good(void) +{ + if (board_has_da9313()) + return gpio_pin_get_dt( + GPIO_DT_FROM_NODELABEL(gpio_da9313_gpio0)); + else if (board_has_ln9310()) + return ln9310_power_good(); + + /* Board has buck ic no way to check POWER GOOD */ + return 1; +} diff --git a/zephyr/projects/trogdor/lazor/src/usb_pd_policy.c b/zephyr/projects/trogdor/lazor/src/usb_pd_policy.c new file mode 100644 index 0000000000..8d046826f9 --- /dev/null +++ b/zephyr/projects/trogdor/lazor/src/usb_pd_policy.c @@ -0,0 +1,261 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <zephyr/drivers/gpio.h> + +#include "charge_manager.h" +#include "chipset.h" +#include "console.h" +#include "system.h" +#include "usb_mux.h" +#include "usbc_ppc.h" +#include "util.h" + +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) + +int pd_check_vconn_swap(int port) +{ + /* In G3, do not allow vconn swap since PP5000 rail is off */ + return gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_en_pp5000_a)); +} + +static uint8_t vbus_en[CONFIG_USB_PD_PORT_MAX_COUNT]; +#if CONFIG_USB_PD_PORT_MAX_COUNT == 1 +static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = { TYPEC_RP_1A5 }; +#else +static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = { TYPEC_RP_1A5, + TYPEC_RP_1A5 }; +#endif + +static void board_vbus_update_source_current(int port) +{ + /* Both port are controlled by PPC SN5S330. */ + ppc_set_vbus_source_current_limit(port, vbus_rp[port]); + ppc_vbus_source_enable(port, vbus_en[port]); +} + +void pd_power_supply_reset(int port) +{ + int prev_en; + + prev_en = vbus_en[port]; + + /* Disable VBUS */ + vbus_en[port] = 0; + board_vbus_update_source_current(port); + + /* Enable discharge if we were previously sourcing 5V */ + if (prev_en) + pd_set_vbus_discharge(port, 1); + + /* notify host of power info change */ + pd_send_host_event(PD_EVENT_POWER_CHANGE); +} + +int pd_set_power_supply_ready(int port) +{ + /* Disable charging */ + board_vbus_sink_enable(port, 0); + + pd_set_vbus_discharge(port, 0); + + /* Provide VBUS */ + vbus_en[port] = 1; + board_vbus_update_source_current(port); + + /* notify host of power info change */ + pd_send_host_event(PD_EVENT_POWER_CHANGE); + + return EC_SUCCESS; /* we are ready */ +} + +int board_vbus_source_enabled(int port) +{ + return vbus_en[port]; +} + +__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp) +{ + vbus_rp[port] = rp; + board_vbus_update_source_current(port); +} + +int pd_snk_is_vbus_provided(int port) +{ + return tcpm_check_vbus_level(port, VBUS_PRESENT); +} + +/* ----------------- Vendor Defined Messages ------------------ */ +#ifdef CONFIG_USB_PD_ALT_MODE_DFP +__override int svdm_dp_config(int port, uint32_t *payload) +{ + int opos = pd_alt_mode(port, TCPCI_MSG_SOP, USB_SID_DISPLAYPORT); + uint8_t pin_mode = get_dp_pin_mode(port); + + if (!pin_mode) + return 0; + + /* + * Defer setting the usb_mux until HPD goes high, svdm_dp_attention(). + * The AP only supports one DP phy. An external DP mux switches between + * the two ports. Should switch those muxes when it is really used, + * i.e. HPD high; otherwise, the real use case is preempted, like: + * (1) plug a dongle without monitor connected to port-0, + * (2) plug a dongle without monitor connected to port-1, + * (3) plug a monitor to the port-1 dongle. + */ + + payload[0] = + VDO(USB_SID_DISPLAYPORT, 1, CMD_DP_CONFIG | VDO_OPOS(opos)); + payload[1] = VDO_DP_CFG(pin_mode, /* pin mode */ + 1, /* DPv1.3 signaling */ + 2); /* UFP connected */ + return 2; +}; + +__override void svdm_dp_post_config(int port) +{ + dp_flags[port] |= DP_FLAGS_DP_ON; +} + +/** + * Is the port fine to be muxed its DisplayPort lines? + * + * Only one port can be muxed to DisplayPort at a time. + * + * @param port Port number of TCPC. + * @return 1 is fine; 0 is bad as other port is already muxed; + */ +static int is_dp_muxable(int port) +{ + int i; + + for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) + if (i != port) { + if (usb_mux_get(i) & USB_PD_MUX_DP_ENABLED) + return 0; + } + + return 1; +} + +__override int svdm_dp_attention(int port, uint32_t *payload) +{ + const struct gpio_dt_spec *hpd = + GPIO_DT_FROM_NODELABEL(gpio_dp_hot_plug_det); + int lvl = PD_VDO_DPSTS_HPD_LVL(payload[1]); + int irq = PD_VDO_DPSTS_HPD_IRQ(payload[1]); + int cur_lvl = gpio_pin_get_dt(hpd); + mux_state_t mux_state; + + dp_status[port] = payload[1]; + + if (!is_dp_muxable(port)) { + /* TODO(waihong): Info user? */ + CPRINTS("p%d: The other port is already muxed.", port); + return 0; + } + + /* + * Initial implementation to handle HPD. Only the first-plugged port + * works, i.e. sending HPD signal to AP. The second-plugged port + * will be ignored. + * + * TODO(waihong): Continue the above case, if the first-plugged port + * is then unplugged, switch to the second-plugged port and signal AP? + */ + if (lvl) { + /* + * Enable and switch the DP port selection mux to the + * correct port. + * + * TODO(waihong): Better to move switching DP mux to + * the usb_mux abstraction. + */ + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_dp_mux_sel), + port == 1); + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_dp_mux_oe_l), 0); + + /* Connect the SBU lines in PPC chip. */ + if (IS_ENABLED(CONFIG_USBC_PPC_SBU)) + ppc_set_sbu(port, 1); + + /* + * Connect the USB SS/DP lines in TCPC chip. + * + * When mf_pref not true, still use the dock muxing + * because of the board USB-C topology (limited to 2 + * lanes DP). + */ + usb_mux_set(port, USB_PD_MUX_DOCK, USB_SWITCH_CONNECT, + polarity_rm_dts(pd_get_polarity(port))); + } else { + /* Disconnect the DP port selection mux. */ + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_dp_mux_oe_l), 1); + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_dp_mux_sel), 0); + + /* Disconnect the SBU lines in PPC chip. */ + if (IS_ENABLED(CONFIG_USBC_PPC_SBU)) + ppc_set_sbu(port, 0); + + /* Disconnect the DP but keep the USB SS lines in TCPC chip. */ + usb_mux_set(port, USB_PD_MUX_USB_ENABLED, USB_SWITCH_CONNECT, + polarity_rm_dts(pd_get_polarity(port))); + } + + if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) && (irq || lvl)) + /* + * Wake up the AP. IRQ or level high indicates a DP sink is now + * present. + */ + pd_notify_dp_alt_mode_entry(port); + + /* Configure TCPC for the HPD event, for proper muxing */ + mux_state = (lvl ? USB_PD_MUX_HPD_LVL : USB_PD_MUX_HPD_LVL_DEASSERTED) | + (irq ? USB_PD_MUX_HPD_IRQ : USB_PD_MUX_HPD_IRQ_DEASSERTED); + usb_mux_hpd_update(port, mux_state); + + /* Signal AP for the HPD event, through GPIO to AP */ + if (irq & cur_lvl) { + uint64_t now = get_time().val; + /* Wait for the minimum spacing between IRQ_HPD if needed */ + if (now < svdm_hpd_deadline[port]) + usleep(svdm_hpd_deadline[port] - now); + + /* Generate IRQ_HPD pulse */ + gpio_pin_set_dt(hpd, 0); + usleep(HPD_DSTREAM_DEBOUNCE_IRQ); + gpio_pin_set_dt(hpd, 1); + + /* Set the minimum time delay (2ms) for the next HPD IRQ */ + svdm_hpd_deadline[port] = + get_time().val + HPD_USTREAM_DEBOUNCE_LVL; + } else if (irq & !lvl) { + CPRINTF("ERR:HPD:IRQ&LOW\n"); + return 0; + } + gpio_pin_set_dt(hpd, lvl); + /* Set the minimum time delay (2ms) for the next HPD IRQ */ + svdm_hpd_deadline[port] = get_time().val + HPD_USTREAM_DEBOUNCE_LVL; + + return 1; +} + +__override void svdm_exit_dp_mode(int port) +{ + if (is_dp_muxable(port)) { + /* Disconnect the DP port selection mux. */ + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_dp_mux_oe_l), 1); + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_dp_mux_sel), 0); + + /* Signal AP for the HPD low event */ + usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED | + USB_PD_MUX_HPD_IRQ_DEASSERTED); + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_dp_hot_plug_det), + 0); + } +} +#endif /* CONFIG_USB_PD_ALT_MODE_DFP */ diff --git a/zephyr/projects/trogdor/lazor/src/usbc_config.c b/zephyr/projects/trogdor/lazor/src/usbc_config.c new file mode 100644 index 0000000000..f6bfdfb186 --- /dev/null +++ b/zephyr/projects/trogdor/lazor/src/usbc_config.c @@ -0,0 +1,335 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Lazor board-specific USB-C configuration */ + +#include "battery_fuel_gauge.h" +#include "bc12/pi3usb9201_public.h" +#include "charger.h" +#include "charger/isl923x_public.h" +#include "charge_manager.h" +#include "charge_state.h" +#include "common.h" +#include "config.h" +#include "driver/ln9310.h" +#include "gpio_signal.h" +#include "gpio/gpio_int.h" +#include "hooks.h" +#include "ppc/sn5s330_public.h" +#include "system.h" +#include "tcpm/ps8xxx_public.h" +#include "tcpm/tcpci.h" +#include "timer.h" +#include "usb_pd.h" +#include "usb_mux.h" +#include "usbc_ocp.h" +#include "usbc_ppc.h" + +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) + +int charger_profile_override(struct charge_state_data *curr) +{ + int usb_mv; + int port; + + if (curr->state != ST_CHARGE) + return 0; + + /* Lower the max requested voltage to 5V when battery is full. */ + if (chipset_in_state(CHIPSET_STATE_ANY_OFF) && + !(curr->batt.flags & BATT_FLAG_BAD_STATUS) && + !(curr->batt.flags & BATT_FLAG_WANT_CHARGE) && + (curr->batt.status & STATUS_FULLY_CHARGED)) + usb_mv = 5000; + else + usb_mv = PD_MAX_VOLTAGE_MV; + + if (pd_get_max_voltage() != usb_mv) { + CPRINTS("VBUS limited to %dmV", usb_mv); + for (port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; port++) + pd_set_external_voltage_limit(port, usb_mv); + } + + return 0; +} + +enum ec_status charger_profile_override_get_param(uint32_t param, + uint32_t *value) +{ + return EC_RES_INVALID_PARAM; +} + +enum ec_status charger_profile_override_set_param(uint32_t param, + uint32_t value) +{ + return EC_RES_INVALID_PARAM; +} + +static void usba_oc_deferred(void) +{ + /* Use next number after all USB-C ports to indicate the USB-A port */ + board_overcurrent_event( + CONFIG_USB_PD_PORT_MAX_COUNT, + !gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_a0_oc_odl))); +} +DECLARE_DEFERRED(usba_oc_deferred); + +void usba_oc_interrupt(enum gpio_signal signal) +{ + hook_call_deferred(&usba_oc_deferred_data, 0); +} + +void ppc_interrupt(enum gpio_signal signal) +{ + switch (signal) { + case GPIO_SIGNAL(DT_NODELABEL(gpio_usb_c0_swctl_int_odl)): + sn5s330_interrupt(0); + break; + case GPIO_SIGNAL(DT_NODELABEL(gpio_usb_c1_swctl_int_odl)): + sn5s330_interrupt(1); + break; + default: + break; + } +} + +static void board_connect_c0_sbu_deferred(void) +{ + /* + * If CCD_MODE_ODL asserts, it means there's a debug accessory connected + * and we should enable the SBU FETs. + */ + ppc_set_sbu(0, 1); +} +DECLARE_DEFERRED(board_connect_c0_sbu_deferred); + +void board_connect_c0_sbu(enum gpio_signal s) +{ + hook_call_deferred(&board_connect_c0_sbu_deferred_data, 0); +} + +/* GPIO Interrupt Handlers */ +void tcpc_alert_event(enum gpio_signal signal) +{ + int port = -1; + + switch (signal) { + case GPIO_USB_C0_PD_INT_ODL: + port = 0; + break; + case GPIO_USB_C1_PD_INT_ODL: + port = 1; + break; + default: + return; + } + + schedule_deferred_pd_interrupt(port); +} + +/* + * Port-0/1 USB mux driver. + * + * The USB mux is handled by TCPC chip and the HPD update is through a GPIO + * to AP. But the TCPC chip is also needed to know the HPD status; otherwise, + * the mux misbehaves. + */ +const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = { + { + .mux = + &(const struct usb_mux){ + .usb_port = 0, + .driver = &tcpci_tcpm_usb_mux_driver, + .hpd_update = &ps8xxx_tcpc_update_hpd_status, + }, + }, + { + .mux = + &(const struct usb_mux){ + .usb_port = 1, + .driver = &tcpci_tcpm_usb_mux_driver, + .hpd_update = &ps8xxx_tcpc_update_hpd_status, + }, + } +}; + +__override int board_get_default_battery_type(void) +{ + /* + * A 2S battery is set as default. If the board is configured to use + * a 3S battery, according to its SKU_ID, return a 3S battery as + * default. It helps to configure the charger to output a correct + * voltage in case the battery is not attached. + */ + if (board_get_battery_cell_type() == BATTERY_CELL_TYPE_3S) + return BATTERY_LGC_AP18C8K; + + return DEFAULT_BATTERY_TYPE; +} + +/* Initialize board USC-C things */ +static void board_init_usbc(void) +{ + /* Enable USB-A overcurrent interrupt */ + gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_a0_oc)); + /* + * The H1 SBU line for CCD are behind PPC chip. The PPC internal FETs + * for SBU may be disconnected after DP alt mode is off. Should enable + * the CCD_MODE_ODL interrupt to make sure the SBU FETs are connected. + */ + gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_ccd_mode)); +} +DECLARE_HOOK(HOOK_INIT, board_init_usbc, HOOK_PRIO_DEFAULT); + +void board_tcpc_init(void) +{ + /* Only reset TCPC if not sysjump */ + if (!system_jumped_late()) { + /* TODO(crosbug.com/p/61098): How long do we need to wait? */ + board_reset_pd_mcu(); + } + + /* Enable PPC interrupts */ + gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0_swctl)); + + /* Enable TCPC interrupts */ + gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0_tcpc)); + gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0_tcpc)); + + /* + * Initialize HPD to low; after sysjump SOC needs to see + * HPD pulse to enable video path + */ + for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port) + usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED | + USB_PD_MUX_HPD_IRQ_DEASSERTED); +} +DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_POST_I2C); + +void board_reset_pd_mcu(void) +{ + cprints(CC_USB, "Resetting TCPCs..."); + cflush(); + + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_c0_pd_rst_l), 0); + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_c1_pd_rst_l), 0); + msleep(PS8XXX_RESET_DELAY_MS); + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_c0_pd_rst_l), 1); + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_c1_pd_rst_l), 1); +} + +void board_set_tcpc_power_mode(int port, int mode) +{ + /* Ignore the "mode" to turn the chip on. We can only do a reset. */ + if (mode) + return; + + board_reset_pd_mcu(); +} + +int board_vbus_sink_enable(int port, int enable) +{ + /* Both ports are controlled by PPC SN5S330 */ + return ppc_vbus_sink_enable(port, enable); +} + +int board_is_sourcing_vbus(int port) +{ + /* Both ports are controlled by PPC SN5S330 */ + return ppc_is_sourcing_vbus(port); +} + +void board_overcurrent_event(int port, int is_overcurrented) +{ + /* TODO(b/120231371): Notify AP */ + CPRINTS("p%d: overcurrent!", port); +} + +int board_set_active_charge_port(int port) +{ + int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT); + int i; + + if (!is_real_port && port != CHARGE_PORT_NONE) + return EC_ERROR_INVAL; + + if (port == CHARGE_PORT_NONE) { + CPRINTS("Disabling all charging port"); + + /* Disable all ports. */ + for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) { + /* + * Do not return early if one fails otherwise we can + * get into a boot loop assertion failure. + */ + if (board_vbus_sink_enable(i, 0)) + CPRINTS("Disabling p%d sink path failed.", i); + } + + return EC_SUCCESS; + } + + /* Check if the port is sourcing VBUS. */ + if (board_is_sourcing_vbus(port)) { + CPRINTS("Skip enable p%d", port); + return EC_ERROR_INVAL; + } + + CPRINTS("New charge port: p%d", port); + + /* + * Turn off the other ports' sink path FETs, before enabling the + * requested charge port. + */ + for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) { + if (i == port) + continue; + + if (board_vbus_sink_enable(i, 0)) + CPRINTS("p%d: sink path disable failed.", i); + } + + /* Enable requested charge port. */ + if (board_vbus_sink_enable(port, 1)) { + CPRINTS("p%d: sink path enable failed.", port); + return EC_ERROR_UNKNOWN; + } + + return EC_SUCCESS; +} + +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) +{ + /* + * Ignore lower charge ceiling on PD transition if our battery is + * critical, as we may brownout. + */ + if (supplier == CHARGE_SUPPLIER_PD && charge_ma < 1500 && + charge_get_percent() < CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON) { + CPRINTS("Using max ilim %d", max_ma); + charge_ma = max_ma; + } + + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); +} + +uint16_t tcpc_get_alert_status(void) +{ + uint16_t status = 0; + + if (!gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_c0_pd_int_odl))) + if (gpio_pin_get_dt( + GPIO_DT_FROM_NODELABEL(gpio_usb_c0_pd_rst_l))) + status |= PD_STATUS_TCPC_ALERT_0; + if (!gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_c0_pd_int_odl))) + if (gpio_pin_get_dt( + GPIO_DT_FROM_NODELABEL(gpio_usb_c1_pd_rst_l))) + status |= PD_STATUS_TCPC_ALERT_1; + + return status; +} diff --git a/zephyr/projects/trogdor/lazor/usbc.dts b/zephyr/projects/trogdor/lazor/usbc.dts new file mode 100644 index 0000000000..7864c2716b --- /dev/null +++ b/zephyr/projects/trogdor/lazor/usbc.dts @@ -0,0 +1,36 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + usbc { + #address-cells = <1>; + #size-cells = <0>; + + /* TODO(b/227359762): lazor: move UBC-C configuration into the + * devicetree + */ + port0@0 { + compatible = "named-usbc-port"; + reg = <0>; + + bc12 = <&bc12_port0>; + tcpc = <&tcpc_port0>; + + ppc = <&ppc_port0>; + + chg = <&charger>; + }; + + port1@1 { + compatible = "named-usbc-port"; + reg = <1>; + + bc12 = <&bc12_port1>; + tcpc = <&tcpc_port1>; + + ppc = <&ppc_port1>; + }; + }; +}; |