diff options
| -rw-r--r-- | board/asurada_scp/board.c | 9 | ||||
| -rw-r--r-- | board/asurada_scp/board.h | 48 | ||||
| -rw-r--r-- | board/asurada_scp/build.mk | 12 | ||||
| -rw-r--r-- | board/asurada_scp/ec.tasklist | 12 | ||||
| -rw-r--r-- | board/asurada_scp/gpio.inc | 10 |
5 files changed, 91 insertions, 0 deletions
diff --git a/board/asurada_scp/board.c b/board/asurada_scp/board.c new file mode 100644 index 0000000000..06b790cd81 --- /dev/null +++ b/board/asurada_scp/board.c @@ -0,0 +1,9 @@ +/* Copyright 2020 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ +/* Asurada SCP configuration */ + +#include "registers.h" + +#include "gpio_list.h" diff --git a/board/asurada_scp/board.h b/board/asurada_scp/board.h new file mode 100644 index 0000000000..548ce09f2c --- /dev/null +++ b/board/asurada_scp/board.h @@ -0,0 +1,48 @@ +/* Copyright 2020 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Asurada SCP configuration */ + +#ifndef __CROS_EC_BOARD_H +#define __CROS_EC_BOARD_H + +#define CONFIG_FLASH_SIZE 0x58000 +#define CONFIG_LTO +#define CONFIG_UART_CONSOLE 0 + +/* + * RW only, no flash + * +-------------------- 0x0 + * | ROM vectortable, .text, .rodata, .data LMA + * +-------------------- 0x58000 + * | RAM .bss, .data + * +-------------------- 0x7BDB0 + * | IPI shared buffer with AP (288 + 8) * 2 + * +-------------------- 0x7C000 + * | 8KB I-CACHE + * +-------------------- 0x7E000 + * | 8KB D-CACHE + * +-------------------- 0x80000 + */ +#define ICACHE_BASE 0x7C000 +#define CONFIG_ROM_BASE 0x0 +#define CONFIG_RAM_BASE 0x58000 +#define CONFIG_ROM_SIZE (CONFIG_RAM_BASE - CONFIG_ROM_BASE) +#define CONFIG_RAM_SIZE (CONFIG_IPC_SHARED_OBJ_ADDR - CONFIG_RAM_BASE) +#define CONFIG_CODE_RAM_SIZE CONFIG_RAM_BASE +#define CONFIG_DATA_RAM_SIZE (ICACHE_BASE - CONFIG_RAM_BASE) +#define CONFIG_RO_MEM_OFF 0 + +/* IPI configs */ +#define CONFIG_IPC_SHARED_OBJ_BUF_SIZE 288 +#define CONFIG_IPC_SHARED_OBJ_ADDR \ + (ICACHE_BASE - \ + (CONFIG_IPC_SHARED_OBJ_BUF_SIZE + 2 * 4 /* int32_t */) * 2) + +#ifndef __ASSEMBLER__ +#include "gpio_signal.h" +#endif /* !__ASSEMBLER__ */ + +#endif /* __CROS_EC_BOARD_H */ diff --git a/board/asurada_scp/build.mk b/board/asurada_scp/build.mk new file mode 100644 index 0000000000..33debd81a6 --- /dev/null +++ b/board/asurada_scp/build.mk @@ -0,0 +1,12 @@ +# -*- makefile -*- +# Copyright 2020 The Chromium OS Authors. All rights reserved. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. +# +# Board specific files build +# + +CHIP:=mt8192_scp +CHIP_VARIANT:=mt8192 + +board-y=board.o diff --git a/board/asurada_scp/ec.tasklist b/board/asurada_scp/ec.tasklist new file mode 100644 index 0000000000..a2d8da2a6b --- /dev/null +++ b/board/asurada_scp/ec.tasklist @@ -0,0 +1,12 @@ +/* Copyright 2020 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/** + * See CONFIG_TASK_LIST in config.h for details. + */ + +#define CONFIG_TASK_LIST \ + TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \ + TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) diff --git a/board/asurada_scp/gpio.inc b/board/asurada_scp/gpio.inc new file mode 100644 index 0000000000..3222a34e08 --- /dev/null +++ b/board/asurada_scp/gpio.inc @@ -0,0 +1,10 @@ +/* -*- mode:c -*- + * + * Copyright 2020 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Unimplemented signals which we need to emulate for now */ +UNIMPLEMENTED(ENTERING_RW) +UNIMPLEMENTED(WP_L) |