ish: Trim down the release branchstabilize-wristpin-14469.59.B-ishstabilize-voshyr-14637.B-ishstabilize-quickfix-14695.187.B-ishstabilize-quickfix-14695.124.B-ishstabilize-quickfix-14526.91.B-ishstabilize-14695.85.B-ishstabilize-14695.107.B-ishstabilize-14682.B-ishstabilize-14633.B-ishstabilize-14616.B-ishstabilize-14589.B-ishstabilize-14588.98.B-ishstabilize-14588.14.B-ishstabilize-14588.123.B-ishstabilize-14536.B-ishstabilize-14532.B-ishstabilize-14528.B-ishstabilize-14526.89.B-ishstabilize-14526.84.B-ishstabilize-14526.73.B-ishstabilize-14526.67.B-ishstabilize-14526.57.B-ishstabilize-14498.B-ishstabilize-14496.B-ishstabilize-14477.B-ishstabilize-14469.9.B-ishstabilize-14469.8.B-ishstabilize-14469.58.B-ishstabilize-14469.41.B-ishstabilize-14442.B-ishstabilize-14438.B-ishstabilize-14411.B-ishstabilize-14396.B-ishstabilize-14395.B-ishstabilize-14388.62.B-ishstabilize-14388.61.B-ishstabilize-14388.52.B-ishstabilize-14385.B-ishstabilize-14345.B-ishstabilize-14336.B-ishstabilize-14333.B-ishrelease-R99-14469.B-ishrelease-R98-14388.B-ishrelease-R102-14695.B-ishrelease-R101-14588.B-ishrelease-R100-14526.B-ishfirmware-cherry-14454.B-ishfirmware-brya-14505.B-ishfirmware-brya-14505.71.B-ishfactory-kukui-14374.B-ishfactory-guybrush-14600.B-ishfactory-cherry-14455.B-ishfactory-brya-14517.B-ish

In the interest of making long-term branch maintenance incur as little
technical debt on us as possible, we should not maintain any files on
the branch we are not actually using.

This has the added effect of making it extremely clear when merging CLs
from the main branch when changes have the possibility to affect us.

The follow-on CL adds a convenience script to actually pull updates from
the main branch and generate a CL for the update.

BUG=b:204206272
BRANCH=ish
TEST=make BOARD=arcada_ish && make BOARD=drallion_ish

Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I17e4694c38219b5a0823e0a3e55a28d1348f4b18
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3262038
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Tom Hughes <tomhughes@chromium.org>

8 files changed, 0 insertions, 368 deletions

diff --git a/util/openocd/lm4_chip.cfg b/util/openocd/lm4_chip.cfg
deleted file mode 100644
index 3dffa2dc66..0000000000
--- a/util/openocd/lm4_chip.cfg
+++ /dev/null
@@ -1,11 +0,0 @@
-
-ftdi_layout_init 0x0018 0x009b
-
-# open collector oe only
-ftdi_layout_signal nSRST -oe 0x0020
-
-reset_config trst_only
-
-source [find target/stellaris.cfg]
-source [find lm4x_cmds.tcl]
-
diff --git a/util/openocd/lm4x_cmds.tcl b/util/openocd/lm4x_cmds.tcl
deleted file mode 100644
index 59c2dbdeb6..0000000000
--- a/util/openocd/lm4x_cmds.tcl
+++ /dev/null
@@ -1,51 +0,0 @@
-# Copyright 2012 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Command automation for Blizzard LM4F chip
-
-# Program internal flash
-
-proc flash_lm4 {path offset} {
-	reset halt;
-	flash write_image erase $path $offset;
-	reset
-}
-
-proc flash_lm4_board {board} {
-	flash_lm4 ../../build/$board/ec.bin 0
-}
-
-proc flash_lm4_ro {board} {
-	flash_lm4 ../../build/$board/RO/ec.RO.flat 0
-}
-
-proc flash_lm4_rw {board} {
-	flash_lm4 ../../build/$board/RW/ec.RW.bin 131072
-}
-
-# Boards with CONFIG_FLASH_PSTATE_BANK have pstate following RO
-proc unprotect_pstate { } {
-	reset halt
-	flash erase_sector 0 126 127
-	reset
-}
-
-# Boot a software using internal RAM only
-
-proc ramboot_lm4 {path} {
-	reset halt
-	load_image $path 0x20000000 bin
-	reg 15 0x20000400
-	resume
-}
-
-proc ramboot_lm4_board {board} {
-	ramboot_lm4 ../../../build/$board/ec.RO.flat
-}
-
-proc flash_emerged_board {board} {
-	set firmware_image ../../../../../../chroot/build/$board/firmware/ec.bin
-
-	flash_lm4 $firmware_image 0
-}
diff --git a/util/openocd/npcx.cfg b/util/openocd/npcx.cfg
deleted file mode 100644
index 0ab2b42888..0000000000
--- a/util/openocd/npcx.cfg
+++ /dev/null
@@ -1,61 +0,0 @@
-# Copyright 2014 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# nuvoton-m4 devices support both JTAG and SWD transports.
-#
-
-source [find target/swj-dp.tcl]
-
-if { [info exists CHIPNAME] } {
-   set  _CHIPNAME $CHIPNAME
-} else {
-   set  _CHIPNAME npcx_ec
-}
-
-if { [info exists ENDIAN] } {
-   set  _ENDIAN $ENDIAN
-} else {
-   set  _ENDIAN little
-}
-
-# Work-area is a space in RAM used for flash programming
-# By default use 16kB
-if { [info exists WORKAREASIZE] } {
-   set  _WORKAREASIZE $WORKAREASIZE
-} else {
-   set  _WORKAREASIZE 0x8000
-}
-
-#jtag scan chain
-if { [info exists CPUTAPID ] } {
-   set _CPUTAPID $CPUTAPID
-} else {
-   set _CPUTAPID 0x4BA00477
-}
-
-#jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
-swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position \
-		$_CHIPNAME.cpu -work-area-phys 0x200C0000 \
-		-work-area-size $_WORKAREASIZE
-
-# JTAG speed
-adapter_khz 100
-
-adapter_nsrst_delay 100
-jtag_ntrst_delay 100
-
-# use sysresetreq to perform a system reset
-cortex_m reset_config sysresetreq
-
-#reset configuration
-reset_config trst_and_srst
-
-$_TARGETNAME configure -event reset-start {
-	echo "NPCX Reset..."
-	halt
-	adapter_khz 1000
-}
diff --git a/util/openocd/npcx_chip.cfg b/util/openocd/npcx_chip.cfg
deleted file mode 100644
index ddd01df5a4..0000000000
--- a/util/openocd/npcx_chip.cfg
+++ /dev/null
@@ -1,11 +0,0 @@
-
-source [find npcx.cfg]
-source [find npcx_cmds.tcl]
-
-ftdi_layout_init 0x0018 0x009b
-
-# open collector oe only
-ftdi_layout_signal nSRST -oe 0x0020
-
-reset_config trst_only
-
diff --git a/util/openocd/npcx_cmds.tcl b/util/openocd/npcx_cmds.tcl
deleted file mode 100644
index 759e897131..0000000000
--- a/util/openocd/npcx_cmds.tcl
+++ /dev/null
@@ -1,184 +0,0 @@
-# Copyright 2014 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Command automation for NPCX5M5G chip
-
-# Program spi flash
-source [find mem_helper.tcl]
-
-proc flash_npcx {image_path cram_addr image_offset image_size spifw_image} {
-	set UPLOAD_FLAG 0x200C4000;
-	set UUT_TAG 0x200C3000;
-
-	echo "*** NPCX Reset and halt CPU first ***"
-	reset halt
-
-	# Clear whole Code RAM
-	mwb $cram_addr 0xFF $image_size
-	# Upload binary image to Code RAM
-	load_image $image_path $cram_addr
-
-	# Upload program spi image FW to lower 16KB Data RAM
-	load_image $spifw_image 0x200C3020
-
-	# Set sp to upper 16KB Data RAM
-	reg sp 0x200C8000
-	# Set spi offset address of uploaded image
-	reg r0 $image_offset
-	# Set spi program size of uploaded image
-	reg r1 $image_size
-	# Set pc to start of spi program function
-	reg pc 0x200C3021
-	# Clear upload flag
-	mww $UPLOAD_FLAG 0x0
-
-	# Clear UUT Tag
-	mww $UUT_TAG 0x0
-
-	echo "*** Program ...  ***"
-	# Start to program spi flash
-	resume
-
-	# Wait for any pending flash operations to complete
-	while {[expr [mrw $UPLOAD_FLAG] & 0x01] == 0} { sleep 1000 }
-
-	if {[expr [mrw $UPLOAD_FLAG] & 0x02] == 0} {
-		echo "*** Program Fail ***"
-	} else {
-		echo "*** Program Done ***"
-	}
-
-	# Halt CPU
-	halt
-}
-
-proc flash_npcx5m5g {image_path image_offset spifw_image} {
-	# 96 KB for RO & RW regions
-	set fw_size   0x18000
-	# Code RAM start address
-	set cram_addr 0x100A8000
-
-	echo "*** Start to program npcx5m5g with $image_path ***"
-	flash_npcx $image_path $cram_addr $image_offset $fw_size $spifw_image
-	echo "*** Finish program npcx5m5g ***\r\n"
-}
-
-proc flash_npcx5m6g {image_path image_offset spifw_image} {
-	# 224 KB for RO & RW regions
-	set fw_size   0x38000
-	# Code RAM start address
-	set cram_addr 0x10088000
-
-	echo "*** Start to program npcx5m6g with $image_path ***"
-	flash_npcx $image_path $cram_addr $image_offset $fw_size $spifw_image
-	echo "*** Finish program npcx5m6g ***\r\n"
-}
-
-proc flash_npcx7m6x {image_path image_offset spifw_image} {
-	# 192 KB for RO & RW regions
-	set fw_size   0x30000
-	# Code RAM start address
-	set cram_addr 0x10090000
-
-	echo "*** Start to program npcx7m6f/g/w with $image_path ***"
-	flash_npcx $image_path $cram_addr $image_offset $fw_size $spifw_image
-	echo "*** Finish program npcx7m6f/g/w ***\r\n"
-}
-
-proc flash_npcx7m7x {image_path image_offset spifw_image} {
-	# 320 KB for RO & RW regions
-	set fw_size   0x50000
-	# Code RAM start address
-	set cram_addr 0x10070000
-
-	echo "*** Start to program npcx7m7f/g/w with $image_path ***"
-	flash_npcx $image_path $cram_addr $image_offset $fw_size $spifw_image
-	echo "*** Finish program npcx7m7f/g/w ***\r\n"
-}
-
-proc flash_npcx_ro {chip_name image_dir image_offset} {
-	set MPU_RNR  0xE000ED98;
-	set MPU_RASR 0xE000EDA0;
-
-	# images path
-	set ro_image_path $image_dir/RO/ec.RO.flat
-	set spifw_image $image_dir/chip/npcx/spiflashfw/npcx_monitor.bin
-
-	# Halt CPU first
-	halt
-
-	# disable MPU for Data RAM
-	mww $MPU_RNR  0x1
-	mww $MPU_RASR 0x0
-
-	if {$chip_name == "npcx_5m5g_jtag"} {
-		# program RO region
-		flash_npcx5m5g $ro_image_path $image_offset $spifw_image
-	} elseif {$chip_name == "npcx_5m6g_jtag"} {
-		# program RO region
-		flash_npcx5m6g $ro_image_path $image_offset $spifw_image
-	} elseif {$chip_name == "npcx_7m6x_jtag"} {
-		# program RO region
-		flash_npcx7m6x $ro_image_path $image_offset $spifw_image
-	} elseif {$chip_name == "npcx_7m7x_jtag"} {
-		# program RO region
-		flash_npcx7m7x $ro_image_path $image_offset $spifw_image
-	} else {
-		echo $chip_name "no supported."
-	}
-}
-
-proc flash_npcx_all {chip_name image_dir image_offset} {
-	set MPU_RNR  0xE000ED98;
-	set MPU_RASR 0xE000EDA0;
-
-	# images path
-	set ro_image_path $image_dir/RO/ec.RO.flat
-	set rw_image_path $image_dir/RW/ec.RW.bin
-	set spifw_image $image_dir/chip/npcx/spiflashfw/npcx_monitor.bin
-
-	# Halt CPU first
-	halt
-
-	# disable MPU for Data RAM
-	mww $MPU_RNR  0x1
-	mww $MPU_RASR 0x0
-
-	if {$chip_name == "npcx_5m5g_jtag"} {
-		# RW images offset - 128 KB
-		set rw_image_offset  [expr ($image_offset + 0x20000)]
-		# program RO region
-		flash_npcx5m5g $ro_image_path $image_offset $spifw_image
-		# program RW region
-		flash_npcx5m5g $rw_image_path $rw_image_offset $spifw_image
-	} elseif {$chip_name == "npcx_5m6g_jtag"} {
-		# RW images offset - 256 KB
-		set rw_image_offset  [expr ($image_offset + 0x40000)]
-		# program RO region
-		flash_npcx5m6g $ro_image_path $image_offset $spifw_image
-		# program RW region
-		flash_npcx5m6g $rw_image_path $rw_image_offset $spifw_image
-	} elseif {$chip_name == "npcx_7m6x_jtag"} {
-		# RW images offset - 256 KB
-		set rw_image_offset  [expr ($image_offset + 0x40000)]
-		# program RO region
-		flash_npcx7m6x $ro_image_path $image_offset $spifw_image
-		# program RW region
-		flash_npcx7m6x $rw_image_path $rw_image_offset $spifw_image
-	} elseif {$chip_name == "npcx_7m7x_jtag"} {
-		# RW images offset - 512 KB
-		set rw_image_offset  [expr ($image_offset + 0x80000)]
-		# program RO region
-		flash_npcx7m7x $ro_image_path $image_offset $spifw_image
-		# program RW region
-		flash_npcx7m7x $rw_image_path $rw_image_offset $spifw_image
-	} else {
-		echo $chip_name "no supported."
-	}
-}
-
-proc reset_halt_cpu { } {
-	echo "*** NPCX Reset and halt CPU first ***"
-	reset halt
-}
diff --git a/util/openocd/nrf51_chip.cfg b/util/openocd/nrf51_chip.cfg
deleted file mode 100644
index f0e78897d6..0000000000
--- a/util/openocd/nrf51_chip.cfg
+++ /dev/null
@@ -1,14 +0,0 @@
-
-#nRF51 uses SWD
-transport select swd
-# Since nTRST is repurposed, we need a different layout_init setting
-ftdi_layout_init 0x0008 0x009b
-
-ftdi_layout_signal SWDIO_OE -nalias nTRST
-ftdi_layout_signal SWD_EN -alias TMS
-
-#Disable fast flashing, it only works with ST-Link and CMSIS-DAP
-set WORKAREASIZE 0
-source [find target/nrf51.cfg]
-source [find nrf51_cmds.tcl]
-
diff --git a/util/openocd/nrf51_cmds.tcl b/util/openocd/nrf51_cmds.tcl
deleted file mode 100644
index 711b27574d..0000000000
--- a/util/openocd/nrf51_cmds.tcl
+++ /dev/null
@@ -1,22 +0,0 @@
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Command automation for Nordic nRF51 chip
-
-proc flash_nrf51 {path offset} {
-	reset halt;
-	program $path $offset;
-}
-
-proc unprotect_nrf51 { } {
-	reset halt;
-	nrf51 mass_erase;
-}
-
-# enable reset by writing 1 to the RESET register
-# This will disconnect the debugger with the following message:
-# Polling target nrf51.cpu failed, trying to reexamine
-proc exit_debug_mode_nrf51 { } {
-	mww 0x40000544 1;
-}
diff --git a/util/openocd/servo.cfg b/util/openocd/servo.cfg
deleted file mode 100644
index 8331a9bc08..0000000000
--- a/util/openocd/servo.cfg
+++ /dev/null
@@ -1,14 +0,0 @@
-telnet_port 4444
-gdb_port 3333
-gdb_memory_map enable
-gdb_flash_program enable
-
-interface ftdi
-# VID/PID for servo v2, servo v3
-ftdi_vid_pid 0x18d1 0x5002 0x18d1 0x5004 0x18d1 0x500d
-# Only initialize Port A
-ftdi_channel 0
-
-# unbuffered connection data == oe
-ftdi_layout_signal nTRST -data 0x0010 -oe 0x0010
-