puff: enable PP5000_HDMI and CPU C10 gating

TEST=Verified proto can turn off the relevant core rails:
 * Pretend to be an EVT board: ectool cbi set 0 1
 * Reboot EC
 * Drop to S0ix: echo freeze > /sys/power/state
 * Verify CPU_C10_GATE is asserted (powerindebug) and EN_S0_RAILS
   is deasserted (gpioget EN_S0_RAILS)
 * Wake system and ensure it resumes correctly
BUG=b:144719399
BRANCH=None

Change-Id: I8e4158ffac38461e8679ac49a084b4296bcef210
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2035432
Reviewed-by: Andrew McRae <amcrae@chromium.org>

2 files changed, 60 insertions, 7 deletions

diff --git a/power/cometlake-discrete.c b/power/cometlake-discrete.c
index b03e4b683b..5465920334 100644
--- a/power/cometlake-discrete.c
+++ b/power/cometlake-discrete.c
@@ -145,7 +145,8 @@ BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
  * action is required- power-good signals will not change, just the relevant
  * load switches (which are specified to meet the platform's minimum turn-on
  * time when CPU_C10_GATED is deasserted again) are turned off. This gating is
- * done asynchronously.
+ * done asynchronously directly in the interrupt handler because its timing is
+ * very tight.
  *
  * For further reference, Figure 421 and Table 370 in the Comet Lake U PDG
  * summarizes platform power rail requirements in a reasonably easy-to-digest
@@ -161,6 +162,7 @@ BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
  */
 static void shutdown_s0_rails(void)
 {
+	board_enable_s0_rails(0);
 	/*
 	 * Deassert VCCST_PG as early as possible to satisfy tCPU22; VDDQ is
 	 * derived directly from SLP_S3.
@@ -268,12 +270,6 @@ static enum power_state pgood_timeout(enum power_state new_state)
  */
 enum power_state power_handle_state(enum power_state state)
 {
-	/*
-	 * TODO(b/144719399) gate PP1050_STG and PP1200_PLLOC when C10 asserted
-	 * Puff proto also gates HDMI power on EN_S0_RAILS so for that board
-	 * we do not gate them since HDMI should remain powered.
-	 */
-
 	switch (state) {
 	case POWER_G3S5:
 		if (intel_x86_wait_power_up_ok() != EC_SUCCESS) {
@@ -330,6 +326,8 @@ enum power_state power_handle_state(enum power_state state)
 			return pgood_timeout(POWER_S3S5);
 		msleep(2);
 		gpio_set_level(GPIO_EC_PCH_PWROK, 1);
+
+		board_enable_s0_rails(1);
 		break;
 
 	case POWER_S0S3:
@@ -372,3 +370,21 @@ enum power_state power_handle_state(enum power_state state)
  */
 void chipset_handle_reboot(void) {}
 #endif /* CONFIG_VBOOT_EFS */
+
+void c10_gate_interrupt(enum gpio_signal signal)
+{
+	/*
+	 * Per PDG, gate VccSTG and VCCIO on (SLP_S3_L && CPU_C10_GATE_L).
+	 *
+	 * When in S3 we let the state machine do it since timing is less
+	 * critical; when in S0/S0ix we do it here because timing is very
+	 * tight.
+	 */
+	if (board_is_c10_gate_enabled() && gpio_get_level(GPIO_SLP_S3_L)) {
+		int enable_core = gpio_get_level(GPIO_CPU_C10_GATE_L);
+
+		gpio_set_level(GPIO_EN_S0_RAILS, enable_core);
+	}
+
+	return power_signal_interrupt(signal);
+}
diff --git a/power/cometlake-discrete.h b/power/cometlake-discrete.h
index 14e18e91e6..e69deb195c 100644
--- a/power/cometlake-discrete.h
+++ b/power/cometlake-discrete.h
@@ -97,4 +97,41 @@ enum power_signal {
 	POWER_SIGNAL_COUNT
 };
 
+/*
+ * Board-specific enable for any additional rails in S0.
+ *
+ * Input 0 to turn off, 1 to turn on.
+ */
+void board_enable_s0_rails(int enable);
+
+/*
+ * Board-specific flag for whether EN_S0_RAILS can be turned off when
+ * CPU_C10_GATED is asserted by the PCH.
+ *
+ * Return 0 if EN_S0_RAILS must be left on when in S0, even if the PCH asserts
+ * the C10 gate.
+ *
+ * If this can ever return 1, the CPU_C10_GATE_L input from the PCH must also
+ * be configured to call c10_gate_interrupt() rather than
+ * power_signal_interrupt() in order to actually control the relevant core
+ * rails.
+ *
+ * TODO: it is safe to remove this function and assume C10 gating is enabled if
+ * support for rev0 puff boards is no longer required- it was added only for the
+ * benefit of those boards.
+ */
+int board_is_c10_gate_enabled(void);
+
+/*
+ * Special interrupt for CPU_C10_GATE_L handling.
+ *
+ * Response time on resume from C10 has very strict timing requirements- no more
+ * than 65 uS to turn on, and the load switches are specified to turn on in 65
+ * uS max at 1V (30 uS typical). This means the response to changes on the C10
+ * gate input must be as fast as possible to meet PCH timing requirements- much
+ * faster than doing this handling in the power state machine can achieve
+ * (hundreds of microseconds).
+ */
+void c10_gate_interrupt(enum gpio_signal signal);
+
 #endif /* __CROS_EC_COMETLAKE_DISCRETE_H */