diff options
| author | Caveh Jalali <caveh@chromium.org> | 2023-03-10 22:51:18 -0800 |
|---|---|---|
| committer | Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> | 2023-04-02 00:47:17 +0000 |
| commit | fafe10a6fea351d7922ee68cff8c77066b8b8eca (patch) | |
| tree | cf175a6827d91102a81923bf5b04647d875b6c69 /driver | |
| parent | b201453a4d8be2fefbdab24de4d4e40c059b0099 (diff) | |
| download | chrome-ec-fafe10a6fea351d7922ee68cff8c77066b8b8eca.tar.gz | |
ppc/nx20p348x: Do not set reserved bit
When we configure the set of unmasked interrupts, we inadvertently also
set a reserved bit in the interrupt1 mask register that should remain at
its reset value.
BRANCH=none
BUG=none
TEST=verified bit is not set with ppc_dump
Change-Id: Ia90771e1556068ba37746f42f18bbd51c808d23b
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4331570
Reviewed-by: Madhu 🌱 <mparuchuri@google.com>
Reviewed-by: Fabio Baltieri <fabiobaltieri@google.com>
Reviewed-by: Scott Collyer <scollyer@chromium.org>
Diffstat (limited to 'driver')
| -rw-r--r-- | driver/ppc/nx20p348x.c | 1 | ||||
| -rw-r--r-- | driver/ppc/nx20p348x.h | 1 |
2 files changed, 2 insertions, 0 deletions
diff --git a/driver/ppc/nx20p348x.c b/driver/ppc/nx20p348x.c index 14dfb88e02..21f49e0983 100644 --- a/driver/ppc/nx20p348x.c +++ b/driver/ppc/nx20p348x.c @@ -311,6 +311,7 @@ static int nx20p348x_init(int port) /* Mask interrupts for interrupt 1 register */ mask = ~(NX20P348X_INT1_OC_5VSRC | NX20P348X_INT1_SC_5VSRC | NX20P348X_INT1_RCP_5VSRC | NX20P348X_INT1_DBEXIT_ERR); + mask &= ~NX20P3481_INT1_RESERVED; if (IS_ENABLED(CONFIG_USBC_PPC_NX20P3481)) { /* Unmask Fast Role Swap detect interrupt */ mask &= ~NX20P3481_INT1_FRS_DET; diff --git a/driver/ppc/nx20p348x.h b/driver/ppc/nx20p348x.h index 94e7a8d06e..9bab7298be 100644 --- a/driver/ppc/nx20p348x.h +++ b/driver/ppc/nx20p348x.h @@ -96,6 +96,7 @@ /* Interrupt 1 Register Bits (0x04) */ #define NX20P348X_INT1_DBEXIT_ERR BIT(7) #define NX20P3481_INT1_FRS_DET BIT(6) +#define NX20P3481_INT1_RESERVED BIT(5) #define NX20P348X_INT1_OV_5VSRC BIT(4) #define NX20P348X_INT1_RCP_5VSRC BIT(3) #define NX20P348X_INT1_SC_5VSRC BIT(2) |