diff options
| author | Bossen WU <bossen.wu@stmicro.corp-partner.google.com> | 2021-05-18 17:21:56 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-06-30 08:36:48 +0000 |
| commit | 59b286058cf184e1dfc8b8332aa8adc811d8221d (patch) | |
| tree | caa7a17d679e52b6ed81de8eca011a7baccf7beb /chip | |
| parent | 55f7cce1dcc9441979426fbe4226b3308a5df60e (diff) | |
| download | chrome-ec-59b286058cf184e1dfc8b8332aa8adc811d8221d.tar.gz | |
stm32: add stm32l431 ec in chip/stm32 : system / clock / timer
stm32l431 related driver: system / clock / timer.
The stm32l476g-eval is the only board which would be impacted.
BRANCH=main
BUG=b:188117811
TEST=make buildall
Signed-off-by: Bossen WU <bossen.wu@stmicro.corp-partner.google.com>
Change-Id: Idf335005d8188f6959835aa40179a6bd771c5114
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2905165
Reviewed-by: Eric Yilun Lin <yllin@google.com>
Diffstat (limited to 'chip')
| -rw-r--r-- | chip/stm32/clock-l4.h | 110 | ||||
| -rw-r--r-- | chip/stm32/clock-stm32l4.c | 779 | ||||
| -rw-r--r-- | chip/stm32/config-stm32l431.h | 25 | ||||
| -rw-r--r-- | chip/stm32/config_chip.h | 9 | ||||
| -rw-r--r-- | chip/stm32/hwtimer32.c | 42 | ||||
| -rw-r--r-- | chip/stm32/registers-stm32l4.h | 2092 | ||||
| -rw-r--r-- | chip/stm32/system.c | 16 |
7 files changed, 2575 insertions, 498 deletions
diff --git a/chip/stm32/clock-l4.h b/chip/stm32/clock-l4.h new file mode 100644 index 0000000000..d237b84580 --- /dev/null +++ b/chip/stm32/clock-l4.h @@ -0,0 +1,110 @@ +/* Copyright 2021 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Clocks and power management settings */ + +#ifndef __CROS_EC_CLOCK_L4_H +#define __CROS_EC_CLOCK_L4_H + +#include "chipset.h" +#include "clock.h" +#include "common.h" +#include "console.h" +#include "cpu.h" +#include "hooks.h" +#include "hwtimer.h" +#include "registers.h" +#include "system.h" +#include "task.h" +#include "timer.h" +#include "util.h" + +#define STM32L4_RTC_REQ 1000000 +#define STM32L4_LSI_CLOCK 32000 + +/* Lock and unlock RTC write access */ +static inline void rtc_lock_regs(void) +{ + STM32_RTC_WPR = 0xff; +} +static inline void rtc_unlock_regs(void) +{ + STM32_RTC_WPR = 0xca; + STM32_RTC_WPR = 0x53; +} + +struct rtc_time_reg { + uint32_t rtc_ssr; /* subseconds */ + uint32_t rtc_tr; /* hours, minutes, seconds */ + uint32_t rtc_dr; /* years, months, dates, week days */ +}; + +/* Save the RTC alarm wake time */ +struct wake_time { + timestamp_t ts; + uint32_t rtc_alrmar; /* the value of register STM32_RTC_ALRMAR */ +}; + +/* Convert between RTC regs in BCD and seconds */ +uint32_t rtc_to_sec(const struct rtc_time_reg *rtc); + +/* Convert between seconds and RTC regs */ +void sec_to_rtc(uint32_t sec, struct rtc_time_reg *rtc); + +/* Calculate microseconds from rtc sub-second register. */ +uint32_t rtcss_to_us(uint32_t rtcss); + +/* Calculate rtc sub-second register value from microseconds. */ +uint32_t us_to_rtcss(uint32_t us); + +/* Return sub-10-sec time diff between two rtc readings */ +uint32_t get_rtc_diff(const struct rtc_time_reg *rtc0, + const struct rtc_time_reg *rtc1); + +/* Read RTC values */ +void rtc_read(struct rtc_time_reg *rtc); + +/* Set RTC value */ +void rtc_set(uint32_t sec); + +/* Set RTC wakeup, save alarm wakeup time when save_alarm != 0 */ +void set_rtc_alarm(uint32_t delay_s, uint32_t delay_us, + struct rtc_time_reg *rtc, uint8_t save_alarm); + +/* Clear RTC wakeup */ +void reset_rtc_alarm(struct rtc_time_reg *rtc); + +/* + * Return the remaining seconds before the RTC alarm goes off. + * Sub-seconds are ignored. Returns 0 if alarm is not set. + */ +uint32_t get_rtc_alarm(void); + +/* RTC init */ +void rtc_init(void); + +/* Init clock blocks and functionality */ +void clock_init(void); + +/* Init high speed clock config */ +void config_hispeed_clock(void); + +/* Get timer clock frequency (for STM32 only) */ +int clock_get_timer_freq(void); + +/* + * Return 1 if host_wake_time is nonzero and the saved host_wake_time + * is expired at a given time, ts. + */ +bool is_host_wake_alarm_expired(timestamp_t ts); + +/* Set RTC wakeup based on the value saved in host_wake_time */ +void restore_host_wake_alarm(void); + +#ifdef CONFIG_LOW_POWER_IDLE +void low_power_init(void); +#endif + +#endif /* __CROS_EC_CLOCK_L4_H */ diff --git a/chip/stm32/clock-stm32l4.c b/chip/stm32/clock-stm32l4.c index 1bba787779..540695deb1 100644 --- a/chip/stm32/clock-stm32l4.c +++ b/chip/stm32/clock-stm32l4.c @@ -7,18 +7,43 @@ #include "chipset.h" #include "clock.h" +#include "clock-l4.h" #include "common.h" #include "console.h" #include "cpu.h" #include "hooks.h" +#include "host_command.h" #include "registers.h" +#include "rtc.h" +#include "timer.h" +#include "uart.h" #include "util.h" +/* Console output macros */ +#define CPUTS(outstr) cputs(CC_CLOCK, outstr) +#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args) + /* High-speed oscillator is 16 MHz */ #define STM32_HSI_CLOCK 16000000 /* Multi-speed oscillator is 4 MHz by default */ #define STM32_MSI_CLOCK 4000000 +/* Real Time Clock (RTC) */ + +#ifdef CONFIG_STM32_CLOCK_HSE_HZ +#define RTC_PREDIV_A 39 +#define RTC_FREQ ((STM32L4_RTC_REQ) / (RTC_PREDIV_A + 1)) /* Hz */ +#else /* from LSI clock */ +#define RTC_PREDIV_A 1 +#define RTC_FREQ (STM32L4_LSI_CLOCK / (RTC_PREDIV_A + 1)) /* Hz */ +#endif +#define RTC_PREDIV_S (RTC_FREQ - 1) +/* + * Scaling factor to ensure that the intermediate values computed from/to the + * RTC frequency are fitting in a 32-bit integer. + */ +#define SCALING 1000 + enum clock_osc { OSC_INIT = 0, /* Uninitialized */ OSC_HSI, /* High-speed internal oscillator */ @@ -71,6 +96,9 @@ static void clock_enable_osc(enum clock_osc osc) break; #ifdef STM32_HSE_CLOCK case OSC_HSE: +#ifdef STM32_HSE_BYP + STM32_RCC_CR |= STM32_RCC_CR_HSEBYP; +#endif ready = STM32_RCC_CR_HSERDY; on = STM32_RCC_CR_HSEON; break; @@ -92,6 +120,7 @@ static void clock_switch_osc(enum clock_osc osc) { uint32_t sw; uint32_t sws; + uint32_t val; switch (osc) { case OSC_HSI: @@ -115,9 +144,11 @@ static void clock_switch_osc(enum clock_osc osc) default: return; } - - STM32_RCC_CFGR = sw; - while ((STM32_RCC_CFGR & STM32_RCC_CFGR_SWS_MASK) != sws) + val = STM32_RCC_CFGR; + val &= ~STM32_RCC_CFGR_SW; + val |= sw; + STM32_RCC_CFGR = val; + while ((STM32_RCC_CFGR & STM32_RCC_CFGR_SWS_MSK) != sws) ; } @@ -135,8 +166,57 @@ static int stm32_configure_pll(enum clock_osc osc, uint8_t m, uint8_t n, uint8_t r) { uint32_t val; + bool pll_unchanged; int f; + val = STM32_RCC_PLLCFGR; + pll_unchanged = true; + + if (osc == OSC_HSI) + if ((val & STM32_RCC_PLLCFGR_PLLSRC_MSK) != + STM32_RCC_PLLCFGR_PLLSRC_HSI) + pll_unchanged = false; + + if (osc == OSC_MSI) + if ((val & STM32_RCC_PLLCFGR_PLLSRC_MSK) != + STM32_RCC_PLLCFGR_PLLSRC_MSI) + pll_unchanged = false; + +#ifdef STM32_HSE_CLOCK + if (osc == OSC_HSE) + if ((val & STM32_RCC_PLLCFGR_PLLSRC_MSK) != + STM32_RCC_PLLCFGR_PLLSRC_HSE) + pll_unchanged = false; +#endif + + if ((val & STM32_RCC_PLLCFGR_PLLM_MSK) != + ((m - 1) << STM32_RCC_PLLCFGR_PLLM_POS)) + pll_unchanged = false; + + if ((val & STM32_RCC_PLLCFGR_PLLN_MSK) != + (n << STM32_RCC_PLLCFGR_PLLN_POS)) + pll_unchanged = false; + + if ((val & STM32_RCC_PLLCFGR_PLLR_MSK) != + (((r >> 1) - 1) << STM32_RCC_PLLCFGR_PLLR_POS)) + pll_unchanged = false; + + if (pll_unchanged == true) { + if (osc == OSC_HSI) + f = STM32_HSI_CLOCK; + else + f = STM32_MSI_CLOCK; + + if (!(STM32_RCC_CR & STM32_RCC_CR_PLLRDY)) { + STM32_RCC_CR |= STM32_RCC_CR_PLLON; + STM32_RCC_PLLCFGR |= STM32_RCC_PLLCFGR_PLLREN; + + while ((STM32_RCC_CR & STM32_RCC_CR_PLLRDY) == 0) + ; + } + /* (f * n) shouldn't overflow based on their max values */ + return (f * n / m / r); + } /* 1 */ STM32_RCC_CR &= ~STM32_RCC_CR_PLLON; @@ -147,7 +227,7 @@ static int stm32_configure_pll(enum clock_osc osc, /* 3 */ val = STM32_RCC_PLLCFGR; - val &= ~STM32_RCC_PLLCFGR_PLLSRC_MASK; + val &= ~STM32_RCC_PLLCFGR_PLLSRC_MSK; switch (osc) { case OSC_HSI: val |= STM32_RCC_PLLCFGR_PLLSRC_HSI; @@ -168,27 +248,27 @@ static int stm32_configure_pll(enum clock_osc osc, } ASSERT(m > 0 && m < 9); - val &= ~STM32_RCC_PLLCFGR_PLLM_MASK; - val |= (m - 1) << STM32_RCC_PLLCFGR_PLLM_SHIFT; + val &= ~STM32_RCC_PLLCFGR_PLLM_MSK; + val |= (m - 1) << STM32_RCC_PLLCFGR_PLLM_POS; /* Max and min values are from TRM */ ASSERT(n > 7 && n < 87); - val &= ~STM32_RCC_PLLCFGR_PLLN_MASK; - val |= n << STM32_RCC_PLLCFGR_PLLN_SHIFT; + val &= ~STM32_RCC_PLLCFGR_PLLN_MSK; + val |= n << STM32_RCC_PLLCFGR_PLLN_POS; - val &= ~STM32_RCC_PLLCFGR_PLLR_MASK; + val &= ~STM32_RCC_PLLCFGR_PLLR_MSK; switch (r) { case 2: - val |= 0 << STM32_RCC_PLLCFGR_PLLR_SHIFT; + val |= 0 << STM32_RCC_PLLCFGR_PLLR_POS; break; case 4: - val |= 1 << STM32_RCC_PLLCFGR_PLLR_SHIFT; + val |= 1 << STM32_RCC_PLLCFGR_PLLR_POS; break; case 6: - val |= 2 << STM32_RCC_PLLCFGR_PLLR_SHIFT; + val |= 2 << STM32_RCC_PLLCFGR_PLLR_POS; break; case 8: - val |= 3 << STM32_RCC_PLLCFGR_PLLR_SHIFT; + val |= 3 << STM32_RCC_PLLCFGR_PLLR_POS; break; default: return -1; @@ -201,7 +281,7 @@ static int stm32_configure_pll(enum clock_osc osc, /* 5 */ val = STM32_RCC_PLLCFGR; - val |= 1 << STM32_RCC_PLLCFGR_PLLREN_SHIFT; + val |= 1 << STM32_RCC_PLLCFGR_PLLREN_POS; STM32_RCC_PLLCFGR = val; /* (f * n) shouldn't overflow based on their max values */ @@ -229,8 +309,8 @@ static void clock_set_osc(enum clock_osc osc, enum clock_osc pll_osc) /* Ensure that HSI is ON */ clock_enable_osc(osc); - /* Disable LPSDSR */ - STM32_PWR_CR &= ~STM32_PWR_CR_LPSDSR; + /* Set HSI as system clock after exiting stop mode */ + STM32_RCC_CFGR |= STM32_RCC_CFGR_STOPWUCK; /* Switch to HSI */ clock_switch_osc(osc); @@ -243,21 +323,23 @@ static void clock_set_osc(enum clock_osc osc, enum clock_osc pll_osc) case OSC_MSI: /* Switch to MSI @ 1MHz */ - STM32_RCC_ICSCR = - (STM32_RCC_ICSCR & ~STM32_RCC_ICSCR_MSIRANGE_MASK) | + STM32_RCC_CR = + (STM32_RCC_CR & ~STM32_RCC_ICSCR_MSIRANGE_MASK) | STM32_RCC_ICSCR_MSIRANGE_1MHZ; /* Ensure that MSI is ON */ clock_enable_osc(osc); + /* + * Set MSI as system clock after exiting stop mode + */ + STM32_RCC_CFGR &= ~STM32_RCC_CFGR_STOPWUCK; + /* Switch to MSI */ clock_switch_osc(osc); /* Disable HSI */ STM32_RCC_CR &= ~STM32_RCC_CR_HSION; - /* Enable LPSDSR */ - STM32_PWR_CR |= STM32_PWR_CR_LPSDSR; - freq = STM32_MSI_CLOCK; break; @@ -279,20 +361,76 @@ static void clock_set_osc(enum clock_osc osc, enum clock_osc pll_osc) #endif case OSC_PLL: /* Ensure that source clock is stable */ - clock_enable_osc(pll_osc); - - /* Configure PLLCFGR */ - freq = stm32_configure_pll(pll_osc, STM32_PLLM, - STM32_PLLN, STM32_PLLR); + if (pll_osc == OSC_INIT) { + if ((STM32_RCC_CFGR & STM32_RCC_CFGR_SWS_MSK) != + STM32_RCC_CFGR_SWS_PLL) { + STM32_RCC_CFGR |= STM32_RCC_CFGR_STOPWUCK; + clock_enable_osc(OSC_HSI); + freq = stm32_configure_pll(OSC_HSI, STM32_PLLM, + STM32_PLLN, + STM32_PLLR); + } else { + /* already set PLL, skip */ + freq = STM32_HSI_CLOCK * STM32_PLLN / + STM32_PLLM / STM32_PLLR; + break; + } + } else { + clock_enable_osc(pll_osc); + /* Configure PLLCFGR */ + freq = stm32_configure_pll(pll_osc, STM32_PLLM, + STM32_PLLN, STM32_PLLR); + } ASSERT(freq > 0); - /* Adjust flash latency as instructed in TRM */ - val = STM32_FLASH_ACR; - val &= ~STM32_FLASH_ACR_LATENCY_MASK; - /* Flash 4 wait state. TODO: Should depend on freq. */ - val |= 4 << STM32_FLASH_ACR_LATENCY_SHIFT; - STM32_FLASH_ACR = val; - while (STM32_FLASH_ACR != val) + /* Change to Range 1 if Freq > 26MHz */ + if (freq > 26000000U) { + /* Set VCO range 1 */ + val = STM32_RCC_CR; + val &= ~PWR_CR1_VOS_MSK; + val |= PWR_CR1_VOS_0; + STM32_RCC_CR = val; + + /* + * Set Flash latency according to frequency + */ + val = STM32_FLASH_ACR; + val &= ~STM32_FLASH_ACR_LATENCY_MASK; + if (freq <= 16000000U) { + val = val; + } else if (freq <= 32000000U) { + val |= 1; + } else if (freq <= 48000000U) { + val |= 2; + } else if (freq <= 64000000U) { + val |= 3; + } else if (freq <= 80000000U) { + val |= 4; + } else { + val |= 4; + CPUTS("Incorrect Frequency setting in VOS1!\n"); + } + STM32_FLASH_ACR = val; + } else { + val = STM32_FLASH_ACR; + val &= ~STM32_FLASH_ACR_LATENCY_MASK; + + if (freq <= 6000000U) { + val = val; + } else if (freq <= 12000000U) { + val |= 1; + } else if (freq <= 18000000U) { + val |= 2; + } else if (freq <= 26000000U) { + val |= 3; + } else { + val |= 4; + CPUTS("Incorrect Frequency setting in VOS2!\n"); + } + STM32_FLASH_ACR = val; + } + + while (val != STM32_FLASH_ACR) ; /* Switch to PLL */ @@ -324,24 +462,114 @@ void clock_enable_module(enum module_id module, int enable) new_mask = clock_mask & ~BIT(module); /* Only change clock if needed */ - if ((!!new_mask) != (!!clock_mask)) { + if (new_mask != clock_mask) { + if (module == MODULE_ADC) { + STM32_RCC_APB2ENR |= STM32_RCC_PB2_SYSCFGEN; + STM32_RCC_APB1ENR1 |= STM32_RCC_PB1_PWREN; - /* Flush UART before switching clock speed */ - cflush(); - - clock_set_osc(new_mask ? OSC_HSI : OSC_MSI, OSC_INIT); + /* ADC select bit 28/29 */ + STM32_RCC_CCIPR &= ~STM32_RCC_CCIPR_ADCSEL_MSK; + STM32_RCC_CCIPR |= (STM32_RCC_CCIPR_ADCSEL_0 | + STM32_RCC_CCIPR_ADCSEL_1); + /* ADC clock enable */ + if (enable) + STM32_RCC_AHB2ENR |= STM32_RCC_HB2_ADC1; + else + STM32_RCC_AHB2ENR &= ~STM32_RCC_HB2_ADC1; + } else if (module == MODULE_SPI_FLASH) { + if (enable) + STM32_RCC_APB1ENR1 |= STM32_RCC_PB1_SPI2; + else + STM32_RCC_APB1ENR1 &= ~STM32_RCC_PB1_SPI2; + } else if (module == MODULE_SPI || + module == MODULE_SPI_CONTROLLER) { + if (enable) + STM32_RCC_APB2ENR |= STM32_RCC_APB2ENR_SPI1EN; + else if ((new_mask & (BIT(MODULE_SPI) | + BIT(MODULE_SPI_CONTROLLER))) == 0) + STM32_RCC_APB2ENR &= ~STM32_RCC_APB2ENR_SPI1EN; + } } clock_mask = new_mask; } +void rtc_init(void) +{ + /* Enable RTC Alarm in EXTI */ + STM32_EXTI_RTSR |= EXTI_RTC_ALR_EVENT; + task_enable_irq(STM32_IRQ_RTC_ALARM); + + /* RTC was initilized, avoid initialization again */ + if (STM32_RTC_ISR & STM32_RTC_ISR_INITS) + return; + + rtc_unlock_regs(); + + /* Enter RTC initialize mode */ + STM32_RTC_ISR |= STM32_RTC_ISR_INIT; + while (!(STM32_RTC_ISR & STM32_RTC_ISR_INITF)) + ; + + /* Set clock prescalars */ + STM32_RTC_PRER = (RTC_PREDIV_A << 16) | RTC_PREDIV_S; + + /* Start RTC timer */ + STM32_RTC_ISR &= ~STM32_RTC_ISR_INIT; + while (STM32_RTC_ISR & STM32_RTC_ISR_INITF) + ; + + /* Enable RTC alarm interrupt */ + STM32_RTC_CR |= STM32_RTC_CR_ALRAIE | STM32_RTC_CR_BYPSHAD; + + rtc_lock_regs(); +} + +#if defined(CONFIG_CMD_RTC) || defined(CONFIG_HOSTCMD_RTC) +void rtc_set(uint32_t sec) +{ + struct rtc_time_reg rtc; + + sec_to_rtc(sec, &rtc); + rtc_unlock_regs(); + + /* Disable alarm */ + STM32_RTC_CR &= ~STM32_RTC_CR_ALRAE; + + /* Enter RTC initialize mode */ + STM32_RTC_ISR |= STM32_RTC_ISR_INIT; + while (!(STM32_RTC_ISR & STM32_RTC_ISR_INITF)) + ; + + /* Set clock prescalars */ + STM32_RTC_PRER = (RTC_PREDIV_A << 16) | RTC_PREDIV_S; + + STM32_RTC_TR = rtc.rtc_tr; + STM32_RTC_DR = rtc.rtc_dr; + /* Start RTC timer */ + STM32_RTC_ISR &= ~STM32_RTC_ISR_INIT; + + rtc_lock_regs(); +} +#endif + + void clock_init(void) { #ifdef STM32_HSE_CLOCK clock_set_osc(OSC_PLL, OSC_HSE); #else +#ifdef STM32_USE_PLL + clock_set_osc(OSC_PLL, OSC_INIT); +#else clock_set_osc(OSC_HSI, OSC_INIT); #endif +#endif + +#ifdef CONFIG_LOW_POWER_IDLE + low_power_init(); + rtc_init(); +#endif } static void clock_chipset_startup(void) @@ -390,3 +618,478 @@ DECLARE_CONSOLE_COMMAND(clock, command_clock, #endif , "Set clock frequency"); + +uint32_t rtcss_to_us(uint32_t rtcss) +{ + return ((RTC_PREDIV_S - (rtcss & 0x7FFF)) * (SECOND / SCALING) / + (RTC_FREQ / SCALING)); +} + +uint32_t us_to_rtcss(uint32_t us) +{ + return (RTC_PREDIV_S - + (us * (RTC_FREQ / SCALING) / (SECOND / SCALING))); +} + + +/* Convert decimal to BCD */ +static uint8_t u8_to_bcd(uint8_t val) +{ + /* Fast division by 10 (when lacking HW div) */ + uint32_t quot = ((uint32_t)val * 0xCCCD) >> 19; + uint32_t rem = val - quot * 10; + + return rem | (quot << 4); +} + +/* Convert between RTC regs in BCD and seconds */ +static uint32_t rtc_tr_to_sec(uint32_t rtc_tr) +{ + uint32_t sec; + + /* convert the hours field */ + sec = (((rtc_tr & RTC_TR_HT) >> RTC_TR_HT_POS) * 10 + + ((rtc_tr & RTC_TR_HU) >> RTC_TR_HU_POS)) * 3600; + /* convert the minutes field */ + sec += (((rtc_tr & RTC_TR_MNT) >> RTC_TR_MNT_POS) * 10 + + ((rtc_tr & RTC_TR_MNU) >> RTC_TR_MNU_POS)) * 60; + /* convert the seconds field */ + sec += ((rtc_tr & RTC_TR_ST) >> RTC_TR_ST_POS) * 10 + + (rtc_tr & RTC_TR_SU); + return sec; +} + +static uint32_t sec_to_rtc_tr(uint32_t sec) +{ + uint32_t rtc_tr; + uint8_t hour; + uint8_t min; + + sec %= SECS_PER_DAY; + /* convert the hours field */ + hour = sec / 3600; + rtc_tr = u8_to_bcd(hour) << 16; + /* convert the minutes field */ + sec -= hour * 3600; + min = sec / 60; + rtc_tr |= u8_to_bcd(min) << 8; + /* convert the seconds field */ + sec -= min * 60; + rtc_tr |= u8_to_bcd(sec); + + return rtc_tr; +} + +/* Register setup before RTC alarm is allowed for update */ +static void pre_work_set_rtc_alarm(void) +{ + rtc_unlock_regs(); + + /* Make sure alarm is disabled */ + STM32_RTC_CR &= ~STM32_RTC_CR_ALRAE; + while (!(STM32_RTC_ISR & STM32_RTC_ISR_ALRAWF)) + ; + STM32_RTC_ISR &= ~STM32_RTC_ISR_ALRAF; + STM32_EXTI_PR = BIT(18); +} + +/* Register setup after RTC alarm is updated */ +static void post_work_set_rtc_alarm(void) +{ + /* Enable alarm and alarm interrupt */ + STM32_EXTI_IMR |= BIT(18); + STM32_EXTI_RTSR |= BIT(18); + STM32_RTC_CR |= (STM32_RTC_CR_ALRAE); + + rtc_lock_regs(); +} + +#ifdef CONFIG_HOSTCMD_RTC +static struct wake_time host_wake_time; + +bool is_host_wake_alarm_expired(timestamp_t ts) +{ + return host_wake_time.ts.val && + timestamp_expired(host_wake_time.ts, &ts); +} + +void restore_host_wake_alarm(void) +{ + if (!host_wake_time.ts.val) + return; + + pre_work_set_rtc_alarm(); + + /* Set alarm time */ + STM32_RTC_ALRMAR = host_wake_time.rtc_alrmar; + + post_work_set_rtc_alarm(); +} + +static uint32_t rtc_dr_to_sec(uint32_t rtc_dr) +{ + struct calendar_date time; + uint32_t sec; + + time.year = (((rtc_dr & 0xf00000) >> 20) * 10 + + ((rtc_dr & 0xf0000) >> 16)); + time.month = (((rtc_dr & 0x1000) >> 12) * 10 + + ((rtc_dr & 0xf00) >> 8)); + time.day = ((rtc_dr & 0x30) >> 4) * 10 + (rtc_dr & 0xf); + + sec = date_to_sec(time); + + return sec; +} + +static uint32_t sec_to_rtc_dr(uint32_t sec) +{ + struct calendar_date time; + uint32_t rtc_dr; + + time = sec_to_date(sec); + + rtc_dr = u8_to_bcd(time.year) << 16; + rtc_dr |= u8_to_bcd(time.month) << 8; + rtc_dr |= u8_to_bcd(time.day); + + return rtc_dr; +} +#endif + +uint32_t rtc_to_sec(const struct rtc_time_reg *rtc) +{ + uint32_t sec = 0; + +#ifdef CONFIG_HOSTCMD_RTC + sec = rtc_dr_to_sec(rtc->rtc_dr); +#endif + return sec + (rtcss_to_us(rtc->rtc_ssr) / SECOND) + + rtc_tr_to_sec(rtc->rtc_tr); +} + +void sec_to_rtc(uint32_t sec, struct rtc_time_reg *rtc) +{ + rtc->rtc_dr = 0; +#ifdef CONFIG_HOSTCMD_RTC + rtc->rtc_dr = sec_to_rtc_dr(sec); +#endif + rtc->rtc_tr = sec_to_rtc_tr(sec); + rtc->rtc_ssr = 0; +} + +/* Return sub-10-sec time diff between two rtc readings + * + * Note: this function assumes rtc0 was sampled before rtc1. + * Additionally, this function only looks at the difference mod 10 + * seconds. + */ +uint32_t get_rtc_diff(const struct rtc_time_reg *rtc0, + const struct rtc_time_reg *rtc1) +{ + uint32_t rtc0_val, rtc1_val, diff; + + rtc0_val = (rtc0->rtc_tr & RTC_TR_SU) * SECOND + + rtcss_to_us(rtc0->rtc_ssr); + rtc1_val = (rtc1->rtc_tr & RTC_TR_SU) * SECOND + + rtcss_to_us(rtc1->rtc_ssr); + diff = rtc1_val; + if (rtc1_val < rtc0_val) { + /* rtc_ssr has wrapped, since we assume rtc0 < rtc1, add + * 10 seconds to get the correct value + */ + diff += 10 * SECOND; + } + diff -= rtc0_val; + return diff; +} + +void rtc_read(struct rtc_time_reg *rtc) +{ + /* + * Read current time synchronously. Each register must be read + * twice with identical values because glitches may occur for reads + * close to the RTCCLK edge. + */ + do { + rtc->rtc_dr = STM32_RTC_DR; + + do { + rtc->rtc_tr = STM32_RTC_TR; + + do { + rtc->rtc_ssr = STM32_RTC_SSR; + } while (rtc->rtc_ssr != STM32_RTC_SSR); + + } while (rtc->rtc_tr != STM32_RTC_TR); + + } while (rtc->rtc_dr != STM32_RTC_DR); +} + +void set_rtc_alarm(uint32_t delay_s, uint32_t delay_us, + struct rtc_time_reg *rtc, uint8_t save_alarm) +{ + uint32_t alarm_sec = 0; + uint32_t alarm_us = 0; + + if (delay_s == EC_RTC_ALARM_CLEAR && !delay_us) { + reset_rtc_alarm(rtc); + return; + } + + /* Alarm timeout must be within 1 day (86400 seconds) */ + ASSERT((delay_s + delay_us / SECOND) < SECS_PER_DAY); + + pre_work_set_rtc_alarm(); + rtc_read(rtc); + + /* Calculate alarm time */ + alarm_sec = rtc_tr_to_sec(rtc->rtc_tr) + delay_s; + + if (delay_us) { + alarm_us = rtcss_to_us(rtc->rtc_ssr) + delay_us; + alarm_sec = alarm_sec + alarm_us / SECOND; + alarm_us = alarm_us % SECOND; + } + + /* + * If seconds is greater than 1 day, subtract by 1 day to deal with + * 24-hour rollover. + */ + if (alarm_sec >= SECS_PER_DAY) + alarm_sec -= SECS_PER_DAY; + + /* + * Set alarm time in seconds and check for match on + * hours, minutes, and seconds. + */ + STM32_RTC_ALRMAR = sec_to_rtc_tr(alarm_sec) | 0xc0000000; + + /* + * Set alarm time in subseconds and check for match on subseconds. + * If the caller doesn't specify subsecond delay (e.g. host command), + * just align the alarm time to second. + */ + STM32_RTC_ALRMASSR = delay_us ? + (us_to_rtcss(alarm_us) | 0x0f000000) : 0; + +#ifdef CONFIG_HOSTCMD_RTC + /* + * If alarm is set by the host, preserve the wake time timestamp + * and alarm registers. + */ + if (save_alarm) { + host_wake_time.ts.val = delay_s * SECOND + get_time().val; + host_wake_time.rtc_alrmar = STM32_RTC_ALRMAR; + } +#endif + post_work_set_rtc_alarm(); +} + +uint32_t get_rtc_alarm(void) +{ + struct rtc_time_reg now; + uint32_t now_sec; + uint32_t alarm_sec; + + if (!(STM32_RTC_CR & STM32_RTC_CR_ALRAE)) + return 0; + + rtc_read(&now); + + now_sec = rtc_tr_to_sec(now.rtc_tr); + alarm_sec = rtc_tr_to_sec(STM32_RTC_ALRMAR & 0x3fffff); + + return ((alarm_sec < now_sec) ? SECS_PER_DAY : 0) + + (alarm_sec - now_sec); +} + +void reset_rtc_alarm(struct rtc_time_reg *rtc) +{ + rtc_unlock_regs(); + + /* Disable alarm */ + STM32_RTC_CR &= ~STM32_RTC_CR_ALRAE; + STM32_RTC_ISR &= ~STM32_RTC_ISR_ALRAF; + + /* Disable RTC alarm interrupt */ + STM32_EXTI_IMR &= ~BIT(18); + STM32_EXTI_PR = BIT(18); + + /* Clear the pending RTC alarm IRQ in NVIC */ + task_clear_pending_irq(STM32_IRQ_RTC_ALARM); + + /* Read current time */ + rtc_read(rtc); + + rtc_lock_regs(); +} + +#ifdef CONFIG_HOSTCMD_RTC +static void set_rtc_host_event(void) +{ + host_set_single_event(EC_HOST_EVENT_RTC); +} +DECLARE_DEFERRED(set_rtc_host_event); +#endif + +test_mockable_static +void __rtc_alarm_irq(void) +{ + struct rtc_time_reg rtc; + + reset_rtc_alarm(&rtc); + +#ifdef CONFIG_HOSTCMD_RTC + /* Wake up the host if there is a saved rtc wake alarm. */ + if (host_wake_time.ts.val) { + host_wake_time.ts.val = 0; + hook_call_deferred(&set_rtc_host_event_data, 0); + } +#endif +} +DECLARE_IRQ(STM32_IRQ_RTC_ALARM, __rtc_alarm_irq, 1); + + +void print_system_rtc(enum console_channel ch) +{ + uint32_t sec; + struct rtc_time_reg rtc; + + rtc_read(&rtc); + sec = rtc_to_sec(&rtc); + + cprintf(ch, "RTC: 0x%08x (%d.00 s)\n", sec, sec); +} + + +#ifdef CONFIG_LOW_POWER_IDLE +/* Low power idle statistics */ +static int idle_sleep_cnt; +static int idle_dsleep_cnt; +static uint64_t idle_dsleep_time_us; +static int dsleep_recovery_margin_us = 1000000; + +/* STOP_MODE_LATENCY: delay to wake up from STOP mode with main regulator off */ +#define STOP_MODE_LATENCY 50 /* us */ +/* PLL_LOCK_LATENCY: delay to switch from HSI to PLL */ +#define PLL_LOCK_LATENCY 150 /* us */ +/* + * SET_RTC_MATCH_DELAY: max time to set RTC match alarm. If we set the alarm + * in the past, it will never wake up and cause a watchdog. + */ +#define SET_RTC_MATCH_DELAY 120 /* us */ + + +void low_power_init(void) +{ + /* Enter stop1 mode */ + uint32_t val; + + val = STM32_PWR_CR1; + val &= ~PWR_CR1_LPMS_MSK; + val |= PWR_CR1_LPMS_STOP1; + STM32_PWR_CR1 = val; +} + +void clock_refresh_console_in_use(void) +{ +} + +void __idle(void) +{ + timestamp_t t0; + uint32_t rtc_diff; + int next_delay, margin_us; + struct rtc_time_reg rtc0, rtc1; + + while (1) { + asm volatile("cpsid i"); + + t0 = get_time(); + next_delay = __hw_clock_event_get() - t0.le.lo; + + if (DEEP_SLEEP_ALLOWED && + (next_delay > (STOP_MODE_LATENCY + PLL_LOCK_LATENCY + + SET_RTC_MATCH_DELAY))) { + /* Deep-sleep in STOP mode */ + idle_dsleep_cnt++; + + uart_enable_wakeup(1); + + /* Set deep sleep bit */ + CPU_SCB_SYSCTRL |= 0x4; + + set_rtc_alarm(0, next_delay - STOP_MODE_LATENCY + - PLL_LOCK_LATENCY, + &rtc0, 0); + + + /* ensure outstanding memory transactions complete */ + asm volatile("dsb"); + + asm("wfi"); + + CPU_SCB_SYSCTRL &= ~0x4; + + /* turn on PLL and wait until it's ready */ + STM32_RCC_APB1ENR1 |= STM32_RCC_APB1ENR1_PWREN; + clock_wait_bus_cycles(BUS_APB, 2); + + stm32_configure_pll(OSC_HSI, STM32_PLLM, + STM32_PLLN, STM32_PLLR); + + /* Switch to PLL */ + clock_switch_osc(OSC_PLL); + + uart_enable_wakeup(0); + + /* Fast forward timer according to RTC counter */ + reset_rtc_alarm(&rtc1); + rtc_diff = get_rtc_diff(&rtc0, &rtc1); + t0.val = t0.val + rtc_diff; + force_time(t0); + + /* Record time spent in deep sleep. */ + idle_dsleep_time_us += rtc_diff; + + /* Calculate how close we were to missing deadline */ + margin_us = next_delay - rtc_diff; + if (margin_us < 0) + /* Use CPUTS to save stack space */ + CPUTS("Idle overslept!\n"); + + /* Record the closest to missing a deadline. */ + if (margin_us < dsleep_recovery_margin_us) + dsleep_recovery_margin_us = margin_us; + } else { + idle_sleep_cnt++; + + /* Normal idle : only CPU clock stopped */ + asm("wfi"); + } + asm volatile("cpsie i"); + } +} + +/*****************************************************************************/ +/* Console commands */ +/* Print low power idle statistics. */ +static int command_idle_stats(int argc, char **argv) +{ + timestamp_t ts = get_time(); + + ccprintf("Num idle calls that sleep: %d\n", idle_sleep_cnt); + ccprintf("Num idle calls that deep-sleep: %d\n", idle_dsleep_cnt); + ccprintf("Time spent in deep-sleep: %.6llus\n", + idle_dsleep_time_us); + ccprintf("Total time on: %.6llus\n", ts.val); + ccprintf("Deep-sleep closest to wake deadline: %dus\n", + dsleep_recovery_margin_us); + + return EC_SUCCESS; +} +DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats, + "", + "Print last idle stats"); +#endif /* CONFIG_LOW_POWER_IDLE */ diff --git a/chip/stm32/config-stm32l431.h b/chip/stm32/config-stm32l431.h new file mode 100644 index 0000000000..fb2eff77ba --- /dev/null +++ b/chip/stm32/config-stm32l431.h @@ -0,0 +1,25 @@ +/* Copyright 2021 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Memory mapping */ +#define CONFIG_FLASH_SIZE_BYTES 0x00040000 /* 256 kB */ +#define CONFIG_FLASH_BANK_SIZE \ + 0x800 /* 2 kB. NOTE: BANK in chrome-ec means page */ +#define CONFIG_FLASH_ERASE_SIZE 0x800 /* 2 KB */ +#define CONFIG_FLASH_WRITE_SIZE 0x8 /* 64 bits */ + +/* Ideal write size in page-mode */ +#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x100 /* 256 (32 double words) */ + +/* + * SRAM1 (48kB) at 0x20000000 + * SRAM2 (16kB) at 0x10000000 (and aliased at 0x2000C000) + * so they are contiguous. + */ +#define CONFIG_RAM_BASE 0x20000000 +#define CONFIG_RAM_SIZE 0x00010000 /* 64 kB */ + +/* Number of IRQ vectors on the NVIC */ +#define CONFIG_IRQ_COUNT 82 diff --git a/chip/stm32/config_chip.h b/chip/stm32/config_chip.h index 816737731f..8b34f2fc44 100644 --- a/chip/stm32/config_chip.h +++ b/chip/stm32/config_chip.h @@ -16,6 +16,13 @@ #else /* CPU core BFD configuration */ #include "core/cortex-m/config_core.h" +#define STM32_IRQ_EXTI0_PRIORITY 1 +#define STM32_IRQ_EXTI1_PRIORITY 1 +#define STM32_IRQ_EXTI2_PRIORITY 1 +#define STM32_IRQ_EXTI3_PRIORITY 1 +#define STM32_IRQ_EXTI4_PRIORITY 1 +#define STM32_IRQ_EXTI9_5_PRIORITY 1 +#define STM32_IRQ_EXTI15_10_PRIORITY 1 #endif /* Default to UART 1 for EC console */ @@ -63,6 +70,8 @@ #include "config-stm32g41xb.h" #elif defined(CHIP_VARIANT_STM32G473XC) #include "config-stm32g473xc.h" +#elif defined(CHIP_VARIANT_STM32L431X) +#include "config-stm32l431.h" #else #error "Unsupported chip variant" #endif diff --git a/chip/stm32/hwtimer32.c b/chip/stm32/hwtimer32.c index a643ccc134..963fa44e51 100644 --- a/chip/stm32/hwtimer32.c +++ b/chip/stm32/hwtimer32.c @@ -127,10 +127,22 @@ defined(CHIP_FAMILY_STM32H7) else if (n >= 15 && n <= 17) mask = STM32_RCC_APB2ENR_TIM15 << (n - 15); #endif +#if defined(CHIP_FAMILY_STM32L4) + if (n >= 2 && n <= 7) { + reg = &STM32_RCC_APB1ENR1; + mask = STM32_RCC_PB1_TIM2 << (n - 2); + } else if (n == 1 || n == 15 || n == 16) { + reg = &STM32_RCC_APB2ENR; + mask = (n == 1) ? STM32_RCC_APB2ENR_TIM1EN : + (n == 15) ? STM32_RCC_APB2ENR_TIM15EN : + STM32_RCC_APB2ENR_TIM16EN; + } +#else if (n >= 2 && n <= 7) { reg = &STM32_RCC_APB1ENR; mask = STM32_RCC_PB1_TIM2 << (n - 2); } +#endif if (!mask) return; @@ -258,6 +270,8 @@ const struct irq_priority __keep IRQ_PRIORITY(IRQ_WD) void hwtimer_setup_watchdog(void) { + int freq; + /* Enable clock */ __hw_timer_enable_clock(TIM_WATCHDOG, 1); /* Delay 1 APB clock cycle after the clock is enabled */ @@ -272,13 +286,31 @@ void hwtimer_setup_watchdog(void) STM32_TIM_CR2(TIM_WATCHDOG) = 0x0000; STM32_TIM_SMCR(TIM_WATCHDOG) = 0x0000; - /* AUto-reload value */ - STM32_TIM_ARR(TIM_WATCHDOG) = CONFIG_AUX_TIMER_PERIOD_MS; + /* + * all timers has 16-bit prescale. + * For clock freq > 64MHz, 16bit prescale cannot meet 1KHz. + * set prescale as 10KHz and 10 times arr value instead. + * For clock freq < 64MHz, timer runs at 1KHz. + */ + freq = clock_get_timer_freq(); - /* Update prescaler: watchdog timer runs at 1KHz */ - STM32_TIM_PSC(TIM_WATCHDOG) = - (clock_get_timer_freq() / SECOND * MSEC) - 1; + if (freq <= 64000000 || !IS_ENABLED(CHIP_FAMILY_STM32L4)) { + /* AUto-reload value */ + STM32_TIM_ARR(TIM_WATCHDOG) = CONFIG_AUX_TIMER_PERIOD_MS; + + /* Update prescaler: watchdog timer runs at 1KHz */ + STM32_TIM_PSC(TIM_WATCHDOG) = + (freq / SECOND * MSEC) - 1; + } +#ifdef CHIP_FAMILY_STM32L4 + else { + /* 10 times ARR value with 10KHz timer */ + STM32_TIM_ARR(TIM_WATCHDOG) = CONFIG_AUX_TIMER_PERIOD_MS * 10; + /* Update prescaler: watchdog timer runs at 10KHz */ + STM32_TIM_PSC(TIM_WATCHDOG) = (freq / SECOND / 10 * MSEC) - 1; + } +#endif /* Reload the pre-scaler */ STM32_TIM_EGR(TIM_WATCHDOG) = 0x0001; diff --git a/chip/stm32/registers-stm32l4.h b/chip/stm32/registers-stm32l4.h index d8bbf2f60d..29965fe2ee 100644 --- a/chip/stm32/registers-stm32l4.h +++ b/chip/stm32/registers-stm32l4.h @@ -19,239 +19,255 @@ #error "This header file should not be included directly." #endif -/* --- IRQ numbers --- */ -#define STM32_IRQ_WWDG 0 -#define STM32_IRQ_PVD 1 -#define STM32_IRQ_TAMPER_STAMP 2 -#define STM32_IRQ_RTC_WAKEUP 3 -#define STM32_IRQ_FLASH 4 -#define STM32_IRQ_RCC 5 -#define STM32_IRQ_EXTI0 6 -#define STM32_IRQ_EXTI1 7 -#define STM32_IRQ_EXTI2 8 -#define STM32_IRQ_EXTI3 9 -#define STM32_IRQ_EXTI4 10 -#define STM32_IRQ_DMA_CHANNEL_1 11 -#define STM32_IRQ_DMA_CHANNEL_2 12 -#define STM32_IRQ_DMA_CHANNEL_3 13 -#define STM32_IRQ_DMA_CHANNEL_4 14 -#define STM32_IRQ_DMA_CHANNEL_5 15 -#define STM32_IRQ_DMA_CHANNEL_6 16 -#define STM32_IRQ_DMA_CHANNEL_7 17 -#define STM32_IRQ_USB_HP 19 -#define STM32_IRQ_USB_LP 20 - -#define STM32_IRQ_ADC1 18 /* STM32L4 only */ -#define STM32_IRQ_CAN_TX 19 /* STM32F373 only */ -#define STM32_IRQ_USB_LP_CAN_RX 20 /* STM32F373 only */ -#define STM32_IRQ_DAC 21 -#define STM32_IRQ_CAN_RX1 21 /* STM32F373 only */ - -#define STM32_IRQ_COMP 22 - -#define STM32_IRQ_CAN_SCE 22 /* STM32F373 only */ -#define STM32_IRQ_EXTI9_5 23 -#define STM32_IRQ_LCD 24 /* STM32L15X only */ -#define STM32_IRQ_TIM15 24 /* STM32F373 only */ -#define STM32_IRQ_TIM9 25 /* STM32L15X only */ -#define STM32_IRQ_TIM16 25 /* STM32F373 only */ -#define STM32_IRQ_TIM10 26 /* STM32L15X only */ -#define STM32_IRQ_TIM17 26 /* STM32F373 only */ -#define STM32_IRQ_TIM11 27 /* STM32L15X only */ -#define STM32_IRQ_TIM18_DAC2 27 /* STM32F373 only */ -#define STM32_IRQ_TIM2 28 -#define STM32_IRQ_TIM3 29 -#define STM32_IRQ_TIM4 30 -#define STM32_IRQ_I2C1_EV 31 -#define STM32_IRQ_I2C1_ER 32 -#define STM32_IRQ_I2C2_EV 33 -#define STM32_IRQ_I2C2_ER 34 -#define STM32_IRQ_SPI1 35 -#define STM32_IRQ_SPI2 36 -#define STM32_IRQ_USART1 37 -#define STM32_IRQ_USART2 38 -#define STM32_IRQ_USART3 39 -#define STM32_IRQ_EXTI15_10 40 -#define STM32_IRQ_RTC_ALARM 41 -#define STM32_IRQ_USB_FS_WAKEUP 42 /* STM32L15X */ -#define STM32_IRQ_CEC 42 /* STM32F373 only */ -#define STM32_IRQ_TIM6_BASIC 43 /* STM32L15X only */ -#define STM32_IRQ_TIM12 43 /* STM32F373 only */ -#define STM32_IRQ_TIM7_BASIC 44 /* STM32L15X only */ -#define STM32_IRQ_TIM13 44 /* STM32F373 only */ -#define STM32_IRQ_TIM14 45 /* STM32F373 only */ -#define STM32_IRQ_TIM5 50 /* STM32F373 */ -#define STM32_IRQ_SPI3 51 /* STM32F373 */ -#define STM32_IRQ_USART4 52 /* STM32F446 only */ -#define STM32_IRQ_USART5 53 /* STM32F446 only */ -#define STM32_IRQ_TIM6_DAC 54 /* STM32F373 */ -#define STM32_IRQ_TIM7 55 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL1 56 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL2 57 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL3 58 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL4 59 /* STM32F373 only */ -/* if MISC_REMAP bits are set */ -#define STM32_IRQ_DMA2_CHANNEL5 60 /* STM32F373 */ -#define STM32_IRQ_SDADC1 61 /* STM32F373 only */ -#define STM32_IRQ_SDADC2 62 /* STM32F373 only */ -#define STM32_IRQ_SDADC3 63 /* STM32F373 only */ -#define STM32_IRQ_DMA2_CHANNEL6 68 /* STM32L4 only */ -#define STM32_IRQ_DMA2_CHANNEL7 69 /* STM32L4 only */ -#define STM32_IRQ_LPUART 70 /* STM32L4 only */ -#define STM32_IRQ_USART9 70 /* STM32L4 only */ -#define STM32_IRQ_USART6 71 /* STM32F446 only */ -#define STM32_IRQ_I2C3_EV 72 /* STM32F446 only */ -#define STM32_IRQ_I2C3_ER 73 /* STM32F446 only */ -#define STM32_IRQ_USB_WAKEUP 76 /* STM32F373 only */ -#define STM32_IRQ_TIM19 78 /* STM32F373 only */ -#define STM32_IRQ_AES 79 /* STM32L4 only */ -#define STM32_IRQ_RNG 80 /* STM32L4 only */ -#define STM32_IRQ_FPU 81 /* STM32F373 only */ - +/****** STM32 specific Interrupt Numbers ********/ +#define STM32_IRQ_WWDG 0 +#define STM32_IRQ_PVD_PVM 1 +#define STM32_IRQ_TAMP_STAMP 2 +#define STM32_IRQ_RTC_WKUP 3 +#define STM32_IRQ_FLASH 4 +#define STM32_IRQ_RCC 5 +#define STM32_IRQ_EXTI0 6 +#define STM32_IRQ_EXTI1 7 +#define STM32_IRQ_EXTI2 8 +#define STM32_IRQ_EXTI3 9 +#define STM32_IRQ_EXTI4 10 +#define STM32_IRQ_DMA_CHANNEL_1 11 +#define STM32_IRQ_DMA_CHANNEL_2 12 +#define STM32_IRQ_DMA_CHANNEL_3 13 +#define STM32_IRQ_DMA_CHANNEL_4 14 +#define STM32_IRQ_DMA_CHANNEL_5 15 +#define STM32_IRQ_DMA_CHANNEL_6 16 +#define STM32_IRQ_DMA_CHANNEL_7 17 +#define STM32_IRQ_ADC1 18 +#define STM32_IRQ_CAN1_TX 19 +#define STM32_IRQ_CAN1_RX0 20 +#define STM32_IRQ_CAN1_RX1 21 +#define STM32_IRQ_CAN1_SCE 22 +#define STM32_IRQ_EXTI9_5 23 +#define STM32_IRQ_TIM1_BRK_TIM15 24 +#define STM32_IRQ_TIM1_UP_TIM16 25 +#define STM32_IRQ_TIM1_TRG_COM 26 +#define STM32_IRQ_TIM1_CC 27 +#define STM32_IRQ_TIM2 28 +#define STM32_IRQ_I2C1_EV 31 +#define STM32_IRQ_I2C1_ER 32 +#define STM32_IRQ_I2C2_EV 33 +#define STM32_IRQ_I2C2_ER 34 +#define STM32_IRQ_SPI1 35 +#define STM32_IRQ_SPI2 36 +#define STM32_IRQ_USART1 37 +#define STM32_IRQ_USART2 38 +#define STM32_IRQ_USART3 39 +#define STM32_IRQ_EXTI15_10 40 +#define STM32_IRQ_RTC_ALARM 41 +#define STM32_IRQ_SDMMC1 49 +#define STM32_IRQ_TIM5 50 +#define STM32_IRQ_SPI3 51 +#define STM32_IRQ_TIM6_DAC 54 +#define STM32_IRQ_TIM7 55 +#define STM32_IRQ_DMA2_CHANNEL1 56 +#define STM32_IRQ_DMA2_CHANNEL2 57 +#define STM32_IRQ_DMA2_CHANNEL3 58 +#define STM32_IRQ_DMA2_CHANNEL4 59 +#define STM32_IRQ_DMA2_CHANNEL5 60 +#define STM32_IRQ_COMP 64 +#define LSTM32_IRQ_PTIM1 65 +#define STM32_IRQ_LPTIM2 66 +#define STM32_IRQ_DMA2_CHANNEL6 68 +#define STM32_IRQ_DMA2_CHANNEL7 69 +#define STM32_IRQ_LPUART1 70 +#define STM32_IRQ_QUADSPI 71 +#define STM32_IRQ_I2C3_EV 72 +#define STM32_IRQ_I2C3_ER 73 +#define STM32_IRQ_SAI1 74 +#define STM32_IRQ_SWPMI1 76 +#define STM32_IRQ_TSC 77 +#define STM32_IRQ_RNG 80 +#define STM32_IRQ_FPU 81 +#define STM32_IRQ_CRS 82 /* To simplify code generation, define DMA channel 9..10 */ #define STM32_IRQ_DMA_CHANNEL_9 STM32_IRQ_DMA2_CHANNEL1 #define STM32_IRQ_DMA_CHANNEL_10 STM32_IRQ_DMA2_CHANNEL2 -#define STM32_IRQ_DMA_CHANNEL_13 STM32_IRQ_DMA2_CHANNEL6 -#define STM32_IRQ_DMA_CHANNEL_14 STM32_IRQ_DMA2_CHANNEL7 - -/* aliases for easier code sharing */ -#define STM32_IRQ_I2C1 STM32_IRQ_I2C1_EV -#define STM32_IRQ_I2C2 STM32_IRQ_I2C2_EV -#define STM32_IRQ_I2C3 STM32_IRQ_I2C3_EV - +#define STM32_IRQ_DMA_CHANNEL_11 STM32_IRQ_DMA2_CHANNEL3 +#define STM32_IRQ_DMA_CHANNEL_12 STM32_IRQ_DMA2_CHANNEL4 +#define STM32_IRQ_DMA_CHANNEL_13 STM32_IRQ_DMA2_CHANNEL5 +#define STM32_IRQ_DMA_CHANNEL_14 STM32_IRQ_DMA2_CHANNEL6 +#define STM32_IRQ_DMA_CHANNEL_15 STM32_IRQ_DMA2_CHANNEL7 +#define STM32_IRQ_USART9 STM32_IRQ_LPUART1 /* Peripheral base addresses */ -#define STM32_ADC1_BASE 0x40012400 -#define STM32_ADC_BASE 0x40012700 /* STM32L15X only */ - -#define STM32_CEC_BASE 0x40007800 /* STM32F373 */ -#define STM32_CRC_BASE 0x40023000 -#define STM32_CRS_BASE 0x40006c00 /* STM32F0XX */ -#define STM32_DAC_BASE 0x40007400 - - -#define STM32_DBGMCU_BASE 0xE0042000 - -#define STM32_DMA1_BASE 0x40020000 -#define STM32_DMA2_BASE 0x40020400 - -#define STM32_EXTI_BASE 0x40010400 - -#define STM32_FLASH_REGS_BASE 0x40022000 - -#define STM32_GPIOA_BASE 0x48000000 -#define STM32_GPIOB_BASE 0x48000400 -#define STM32_GPIOC_BASE 0x48000800 -#define STM32_GPIOD_BASE 0x48000C00 -#define STM32_GPIOE_BASE 0x48001000 -#define STM32_GPIOF_BASE 0x48001400 -#define STM32_GPIOG_BASE 0x48001800 /* only for stm32l4x6 */ -#define STM32_GPIOH_BASE 0x48001C00 /* only for stm32l4 */ - -#define STM32_I2C1_BASE 0x40005400 -#define STM32_I2C2_BASE 0x40005800 -#define STM32_I2C3_BASE 0x40005C00 -#define STM32_I2C4_BASE 0x40006000 - -#define STM32_IWDG_BASE 0x40003000 -#define STM32_LCD_BASE 0x40002400 - +#define FLASH_BASE 0x08000000UL +#define FLASH_END 0x0803FFFFUL +#define FLASH_BANK1_END 0x0803FFFFUL +#define SRAM1_BASE 0x20000000UL +#define SRAM2_BASE 0x10000000UL +#define PERIPH_BASE 0x40000000UL +#define QSPI_BASE 0x90000000UL +#define QSPI_R_BASE 0xA0001000UL +#define SRAM1_BB_BASE 0x22000000UL +#define PERIPH_BB_BASE 0x42000000UL + +/* Legacy defines */ +#define SRAM_BASE SRAM1_BASE +#define SRAM_BB_BASE SRAM1_BB_BASE +#define SRAM1_SIZE_MAX 0x0000C000UL +#define SRAM2_SIZE 0x00004000UL +#define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFF75E0) +#define FLASH_SIZE (((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) \ + & (0x0000FFFFU)) == 0x0000FFFFU)) ? (0x100U << 10U) : \ + (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & \ + (0x0000FFFFU)) << 10U)) + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL) + +/*!< APB1 peripherals */ +#define STM32_TIM2_BASE (APB1PERIPH_BASE + 0x0000UL) +#define STM32_TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL) +#define STM32_TIM6_BASE (APB1PERIPH_BASE + 0x1000UL) +#define STM32_TIM7_BASE (APB1PERIPH_BASE + 0x1400UL) +#define STM32_RTC_BASE (APB1PERIPH_BASE + 0x2800UL) +#define STM32_WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL) +#define STM32_IWDG_BASE (APB1PERIPH_BASE + 0x3000UL) +#define STM32_SPI2_BASE (APB1PERIPH_BASE + 0x3800UL) +#define STM32_SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL) +#define STM32_USART2_BASE (APB1PERIPH_BASE + 0x4400UL) +#define STM32_USART3_BASE (APB1PERIPH_BASE + 0x4800UL) +#define STM32_I2C1_BASE (APB1PERIPH_BASE + 0x5400UL) +#define STM32_I2C2_BASE (APB1PERIPH_BASE + 0x5800UL) +#define STM32_I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL) +#define STM32_CRS_BASE (APB1PERIPH_BASE + 0x6000UL) +#define STM32_CAN1_BASE (APB1PERIPH_BASE + 0x6400UL) +#define STM32_PWR_BASE (APB1PERIPH_BASE + 0x7000UL) +#define STM32_DAC_BASE (APB1PERIPH_BASE + 0x7400UL) +#define STM32_DAC1_BASE (APB1PERIPH_BASE + 0x7400UL) +#define STM32_OPAMP_BASE (APB1PERIPH_BASE + 0x7800UL) +#define STM32_OPAMP1_BASE (APB1PERIPH_BASE + 0x7800UL) +#define STM32_LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00UL) +#define STM32_LPUART1_BASE (APB1PERIPH_BASE + 0x8000UL) +#define STM32_SWPMI1_BASE (APB1PERIPH_BASE + 0x8800UL) +#define STM32_LPTIM2_BASE (APB1PERIPH_BASE + 0x9400UL) + +#define STM32_USART9_BASE STM32_LPUART1_BASE + +/*!< APB2 peripherals */ +#define STM32_SYSCFG_BASE (APB2PERIPH_BASE + 0x0000UL) +#define STM32_VREFBUF_BASE (APB2PERIPH_BASE + 0x0030UL) +#define STM32_OMP1_BASE (APB2PERIPH_BASE + 0x0200UL) +#define STM32_COMP2_BASE (APB2PERIPH_BASE + 0x0204UL) +#define STM32_EXTI_BASE (APB2PERIPH_BASE + 0x0400UL) +#define STM32_FIREWALL_BASE (APB2PERIPH_BASE + 0x1C00UL) +#define STM32_SDMMC1_BASE (APB2PERIPH_BASE + 0x2800UL) +#define STM32_TIM1_BASE (APB2PERIPH_BASE + 0x2C00UL) +#define STM32_SPI1_BASE (APB2PERIPH_BASE + 0x3000UL) +#define STM32_USART1_BASE (APB2PERIPH_BASE + 0x3800UL) +#define STM32_TIM15_BASE (APB2PERIPH_BASE + 0x4000UL) +#define STM32_TIM16_BASE (APB2PERIPH_BASE + 0x4400UL) +#define STM32_SAI1_BASE (APB2PERIPH_BASE + 0x5400UL) +#define STM32_SAI1_Block_A_BASE (SAI1_BASE + 0x0004UL) +#define STM32_SAI1_Block_B_BASE (SAI1_BASE + 0x0024UL) + +/*!< AHB1 peripherals */ +#define STM32_DMA1_BASE (AHB1PERIPH_BASE) +#define STM32_DMA2_BASE (AHB1PERIPH_BASE + 0x0400UL) +#define STM32_RCC_BASE (AHB1PERIPH_BASE + 0x1000UL) +#define STM32_FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000UL) +#define STM32_CRC_BASE (AHB1PERIPH_BASE + 0x3000UL) +#define STM32_TSC_BASE (AHB1PERIPH_BASE + 0x4000UL) +#define STM32_DMA1_Channel1_BASE (DMA1_BASE + 0x0008UL) +#define STM32_DMA1_Channel2_BASE (DMA1_BASE + 0x001CUL) +#define STM32_DMA1_Channel3_BASE (DMA1_BASE + 0x0030UL) +#define STM32_DMA1_Channel4_BASE (DMA1_BASE + 0x0044UL) +#define STM32_DMA1_Channel5_BASE (DMA1_BASE + 0x0058UL) +#define STM32_DMA1_Channel6_BASE (DMA1_BASE + 0x006CUL) +#define STM32_DMA1_Channel7_BASE (DMA1_BASE + 0x0080UL) +#define STM32_DMA1_CSELR_BASE (DMA1_BASE + 0x00A8UL) +#define STM32_DMA2_Channel1_BASE (DMA2_BASE + 0x0008UL) +#define STM32_DMA2_Channel2_BASE (DMA2_BASE + 0x001CUL) +#define STM32_DMA2_Channel3_BASE (DMA2_BASE + 0x0030UL) +#define STM32_DMA2_Channel4_BASE (DMA2_BASE + 0x0044UL) +#define STM32_DMA2_Channel5_BASE (DMA2_BASE + 0x0058UL) +#define STM32_DMA2_Channel6_BASE (DMA2_BASE + 0x006CUL) +#define STM32_DMA2_Channel7_BASE (DMA2_BASE + 0x0080UL) +#define STM32_DMA2_CSELR_BASE (DMA2_BASE + 0x00A8UL) + +/*!< AHB2 peripherals */ +#define STM32_GPIOA_BASE (AHB2PERIPH_BASE + 0x0000UL) +#define STM32_GPIOB_BASE (AHB2PERIPH_BASE + 0x0400UL) +#define STM32_GPIOC_BASE (AHB2PERIPH_BASE + 0x0800UL) +#define STM32_GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00UL) +#define STM32_GPIOE_BASE (AHB2PERIPH_BASE + 0x1000UL) +#define STM32_GPIOF_BASE (AHB2PERIPH_BASE + 0x1400UL) +#define STM32_GPIOG_BASE (AHB2PERIPH_BASE + 0x1800UL) /* stm32l4x6 */ +#define STM32_GPIOH_BASE (AHB2PERIPH_BASE + 0x1C00UL) +#define STM32_ADC1_BASE (AHB2PERIPH_BASE + 0x08040000UL) +#define STM32_ADC1_COMMON_BASE (AHB2PERIPH_BASE + 0x08040300UL) +#define STM32_RNG_BASE (AHB2PERIPH_BASE + 0x08060800UL) + +/* Debug MCU registers base address */ +#define STM32_DBGMCU_BASE 0xE0042000UL +#define STM32_PACKAGE_BASE 0x1FFF7500UL +#define STM32_UID_BASE 0x1FFF7590UL +#define STM32_FLASHSIZE_BASE 0x1FFF75E0UL + +#define STM32_FLASH_REGS_BASE STM32_FLASH_R_BASE +#define STM32_UNIQUE_ID_BASE STM32_UID_BASE #define STM32_OPTB_BASE 0x1FFF7800 -#define STM32_PMSE_BASE 0x40013400 -#define STM32_PWR_BASE 0x40007000 - -#define STM32_RCC_BASE 0x40021000 - -#define STM32_RI_BASE 0x40007C00 /* STM32L1xx only */ -#define STM32_RNG_BASE 0x50060800 /* STM32L4 */ -#define STM32_RTC_BASE 0x40002800 - -#define STM32_SPI1_BASE 0x40013000 -#define STM32_SPI2_BASE 0x40003800 -#define STM32_SPI3_BASE 0x40003c00 /* STM32F373, STM32L4, STM32F7 */ - -#define STM32_SYSCFG_BASE 0x40010000 - -#define STM32_TIM1_BASE 0x40012c00 /* STM32F373 */ -#define STM32_TIM2_BASE 0x40000000 -#define STM32_TIM3_BASE 0x40000400 -#define STM32_TIM4_BASE 0x40000800 -#define STM32_TIM5_BASE 0x40000c00 /* STM32F373 */ -#define STM32_TIM6_BASE 0x40001000 -#define STM32_TIM7_BASE 0x40001400 -#define STM32_TIM12_BASE 0x40001800 /* STM32F373 */ -#define STM32_TIM13_BASE 0x40001c00 /* STM32F373 */ -#define STM32_TIM14_BASE 0x40002000 /* STM32F373 */ -#define STM32_TIM15_BASE 0x40014000 -#define STM32_TIM16_BASE 0x40014400 -#define STM32_TIM17_BASE 0x40014800 -#define STM32_TIM18_BASE 0x40009c00 /* STM32F373 only */ -#define STM32_TIM19_BASE 0x40015c00 /* STM32F373 only */ - -#define STM32_UNIQUE_ID_BASE 0x1ffff7ac - -#define STM32_USART1_BASE 0x40013800 -#define STM32_USART2_BASE 0x40004400 -#define STM32_USART3_BASE 0x40004800 -#define STM32_USART4_BASE 0x40004c00 -#define STM32_USART9_BASE 0x40008000 /* LPUART */ - -#define STM32_USB_CAN_SRAM_BASE 0x40006000 -#define STM32_USB_FS_BASE 0x40005C00 - -#define STM32_WWDG_BASE 0x40002C00 - - #ifndef __ASSEMBLER__ /* Register definitions */ /* --- USART --- */ -#define STM32_USART_CR1(base) STM32_USART_REG(base, 0x00) -#define STM32_USART_CR1_UE BIT(0) -#define STM32_USART_CR1_UESM BIT(1) -#define STM32_USART_CR1_RE BIT(2) -#define STM32_USART_CR1_TE BIT(3) -#define STM32_USART_CR1_RXNEIE BIT(5) -#define STM32_USART_CR1_TCIE BIT(6) -#define STM32_USART_CR1_TXEIE BIT(7) -#define STM32_USART_CR1_PS BIT(9) -#define STM32_USART_CR1_PCE BIT(10) -#define STM32_USART_CR1_M BIT(12) -#define STM32_USART_CR1_OVER8 BIT(15) -#define STM32_USART_CR2(base) STM32_USART_REG(base, 0x04) -#define STM32_USART_CR2_SWAP BIT(15) -#define STM32_USART_CR3(base) STM32_USART_REG(base, 0x08) -#define STM32_USART_CR3_EIE BIT(0) -#define STM32_USART_CR3_DMAR BIT(6) -#define STM32_USART_CR3_DMAT BIT(7) -#define STM32_USART_CR3_ONEBIT BIT(11) -#define STM32_USART_CR3_OVRDIS BIT(12) -#define STM32_USART_CR3_WUS_START_BIT (2 << 20) -#define STM32_USART_CR3_WUFIE BIT(22) -#define STM32_USART_BRR(base) STM32_USART_REG(base, 0x0C) -#define STM32_USART_GTPR(base) STM32_USART_REG(base, 0x10) -#define STM32_USART_RTOR(base) STM32_USART_REG(base, 0x14) -#define STM32_USART_RQR(base) STM32_USART_REG(base, 0x18) -#define STM32_USART_ISR(base) STM32_USART_REG(base, 0x1C) -#define STM32_USART_ICR(base) STM32_USART_REG(base, 0x20) -#define STM32_USART_ICR_ORECF BIT(3) -#define STM32_USART_ICR_TCCF BIT(6) -#define STM32_USART_RDR(base) STM32_USART_REG(base, 0x24) -#define STM32_USART_TDR(base) STM32_USART_REG(base, 0x28) -#define STM32_USART_PRESC(base) STM32_USART_REG(base, 0x2C) +#define STM32_USART_CR1(base) STM32_USART_REG(base, 0x00) +#define STM32_USART_CR1_UE BIT(0) +#define STM32_USART_CR1_UESM BIT(1) +#define STM32_USART_CR1_RE BIT(2) +#define STM32_USART_CR1_TE BIT(3) +#define STM32_USART_CR1_RXNEIE BIT(5) +#define STM32_USART_CR1_TCIE BIT(6) +#define STM32_USART_CR1_TXEIE BIT(7) +#define STM32_USART_CR1_PS BIT(9) +#define STM32_USART_CR1_PCE BIT(10) +#define STM32_USART_CR1_M BIT(12) +#define STM32_USART_CR1_OVER8 BIT(15) + +#define STM32_USART_CR2(base) STM32_USART_REG(base, 0x04) +#define STM32_USART_CR2_SWAP BIT(15) + +#define STM32_USART_CR3(base) STM32_USART_REG(base, 0x08) +#define STM32_USART_CR3_EIE BIT(0) +#define STM32_USART_CR3_DMAR BIT(6) +#define STM32_USART_CR3_DMAT BIT(7) +#define STM32_USART_CR3_ONEBIT BIT(11) +#define STM32_USART_CR3_OVRDIS BIT(12) +#define STM32_USART_CR3_WUS_START_BIT (2 << 20) +#define STM32_USART_CR3_WUFIE BIT(22) + +#define STM32_USART_BRR(base) STM32_USART_REG(base, 0x0C) +#define STM32_USART_GTPR(base) STM32_USART_REG(base, 0x10) +#define STM32_USART_RTOR(base) STM32_USART_REG(base, 0x14) +#define STM32_USART_RQR(base) STM32_USART_REG(base, 0x18) +#define STM32_USART_ISR(base) STM32_USART_REG(base, 0x1C) +#define STM32_USART_ICR(base) STM32_USART_REG(base, 0x20) +#define STM32_USART_ICR_ORECF BIT(3) +#define STM32_USART_ICR_TCCF BIT(6) +#define STM32_USART_RDR(base) STM32_USART_REG(base, 0x24) +#define STM32_USART_TDR(base) STM32_USART_REG(base, 0x28) +#define STM32_USART_PRESC(base) STM32_USART_REG(base, 0x2C) /* register alias */ -#define STM32_USART_SR(base) STM32_USART_ISR(base) -#define STM32_USART_SR_ORE BIT(3) -#define STM32_USART_SR_RXNE BIT(5) -#define STM32_USART_SR_TC BIT(6) -#define STM32_USART_SR_TXE BIT(7) +#define STM32_USART_SR(base) STM32_USART_ISR(base) +#define STM32_USART_SR_ORE BIT(3) +#define STM32_USART_SR_RXNE BIT(5) +#define STM32_USART_SR_TC BIT(6) +#define STM32_USART_SR_TXE BIT(7) /* --- GPIO --- */ - #define STM32_GPIO_MODER(b) REG32((b) + 0x00) #define STM32_GPIO_OTYPER(b) REG16((b) + 0x04) #define STM32_GPIO_OSPEEDR(b) REG32((b) + 0x08) @@ -263,7 +279,7 @@ #define STM32_GPIO_AFRL(b) REG32((b) + 0x20) #define STM32_GPIO_AFRH(b) REG32((b) + 0x24) #define STM32_GPIO_BRR(b) REG32((b) + 0x28) -#define STM32_GPIO_ASCR(b) REG32((b) + 0x2C) /* only for stm32l4 */ +#define STM32_GPIO_ASCR(b) REG32((b) + 0x2C) /* only for stm32l4x6 */ #define GPIO_ALT_F0 0x0 #define GPIO_ALT_F1 0x1 @@ -334,81 +350,60 @@ #define STM32_I2C_RXDR(n) REG32(stm32_i2c_reg(n, 0x24)) #define STM32_I2C_TXDR(n) REG32(stm32_i2c_reg(n, 0x28)) - /* --- Power / Reset / Clocks --- */ +#define STM32_PWR_CR1 REG32(STM32_PWR_BASE + 0x00) #define STM32_PWR_CR2 REG32(STM32_PWR_BASE + 0x04) #define STM32_PWR_CSR REG32(STM32_PWR_BASE + 0x10) - - -#define STM32_RCC_CR REG32(STM32_RCC_BASE + 0x00) -#define STM32_RCC_CR_MSION BIT(0) -#define STM32_RCC_CR_MSIRDY BIT(1) -#define STM32_RCC_CR_HSION BIT(8) -#define STM32_RCC_CR_HSIRDY BIT(10) -#define STM32_RCC_CR_HSEON BIT(16) -#define STM32_RCC_CR_HSERDY BIT(17) -#define STM32_RCC_CR_PLLON BIT(24) -#define STM32_RCC_CR_PLLRDY BIT(25) - -#define STM32_RCC_ICSCR REG32(STM32_RCC_BASE + 0x04) -#define STM32_RCC_ICSCR_MSIRANGE(n) ((n) << 13) -#define STM32_RCC_ICSCR_MSIRANGE_1MHZ STM32_RCC_ICSCR_MSIRANGE(4) -#define STM32_RCC_ICSCR_MSIRANGE_2MHZ STM32_RCC_ICSCR_MSIRANGE(5) -#define STM32_RCC_ICSCR_MSIRANGE_MASK STM32_RCC_ICSCR_MSIRANGE(7) - -#define STM32_RCC_CFGR REG32(STM32_RCC_BASE + 0x08) -#define STM32_RCC_CFGR_SW_MSI (0 << 0) -#define STM32_RCC_CFGR_SW_HSI (1 << 0) -#define STM32_RCC_CFGR_SW_HSE (2 << 0) -#define STM32_RCC_CFGR_SW_PLL (3 << 0) -#define STM32_RCC_CFGR_SW_MASK (3 << 0) -#define STM32_RCC_CFGR_SWS_MSI (0 << 2) -#define STM32_RCC_CFGR_SWS_HSI (1 << 2) -#define STM32_RCC_CFGR_SWS_HSE (2 << 2) -#define STM32_RCC_CFGR_SWS_PLL (3 << 2) -#define STM32_RCC_CFGR_SWS_MASK (3 << 2) - -#define STM32_RCC_PLLCFGR REG32(STM32_RCC_BASE + 0x0C) -#define STM32_RCC_PLLCFGR_PLLSRC_SHIFT (0) -#define STM32_RCC_PLLCFGR_PLLSRC_NONE (0 << STM32_RCC_PLLCFGR_PLLSRC_SHIFT) -#define STM32_RCC_PLLCFGR_PLLSRC_MSI (1 << STM32_RCC_PLLCFGR_PLLSRC_SHIFT) -#define STM32_RCC_PLLCFGR_PLLSRC_HSI (2 << STM32_RCC_PLLCFGR_PLLSRC_SHIFT) -#define STM32_RCC_PLLCFGR_PLLSRC_HSE (3 << STM32_RCC_PLLCFGR_PLLSRC_SHIFT) -#define STM32_RCC_PLLCFGR_PLLSRC_MASK (3 << STM32_RCC_PLLCFGR_PLLSRC_SHIFT) -#define STM32_RCC_PLLCFGR_PLLM_SHIFT (4) -#define STM32_RCC_PLLCFGR_PLLM_MASK (0x7 << STM32_RCC_PLLCFGR_PLLM_SHIFT) -#define STM32_RCC_PLLCFGR_PLLN_SHIFT (8) -#define STM32_RCC_PLLCFGR_PLLN_MASK (0x7f << STM32_RCC_PLLCFGR_PLLN_SHIFT) -#define STM32_RCC_PLLCFGR_PLLREN_SHIFT (24) -#define STM32_RCC_PLLCFGR_PLLREN_MASK (1 << STM32_RCC_PLLCFGR_PLLREN_SHIFT) -#define STM32_RCC_PLLCFGR_PLLR_SHIFT (25) -#define STM32_RCC_PLLCFGR_PLLR_MASK (3 << STM32_RCC_PLLCFGR_PLLR_SHIFT) - -#define STM32_RCC_AHB1RSTR REG32(STM32_RCC_BASE + 0x28) -#define STM32_RCC_AHB2RSTR REG32(STM32_RCC_BASE + 0x2C) -#define STM32_RCC_AHB3RSTR REG32(STM32_RCC_BASE + 0x30) -#define STM32_RCC_APB1RSTR1 REG32(STM32_RCC_BASE + 0x38) -#define STM32_RCC_APB1RSTR2 REG32(STM32_RCC_BASE + 0x3C) -#define STM32_RCC_APB2RSTR REG32(STM32_RCC_BASE + 0x40) - -#define STM32_RCC_AHB1ENR REG32(STM32_RCC_BASE + 0x48) -#define STM32_RCC_AHB1ENR_DMA1EN BIT(0) -#define STM32_RCC_AHB1ENR_DMA2EN BIT(1) - -#define STM32_RCC_AHB2ENR REG32(STM32_RCC_BASE + 0x4C) -#define STM32_RCC_AHB2ENR_GPIOMASK (0xff << 0) -#define STM32_RCC_AHB2ENR_RNGEN BIT(18) - -#define STM32_RCC_APB1ENR REG32(STM32_RCC_BASE + 0x58) -#define STM32_RCC_PWREN BIT(28) - -#define STM32_RCC_APB1ENR2 REG32(STM32_RCC_BASE + 0x5C) -#define STM32_RCC_APB1ENR2_LPUART1EN BIT(0) - -#define STM32_RCC_APB2ENR REG32(STM32_RCC_BASE + 0x60) -#define STM32_RCC_SYSCFGEN BIT(0) - -#define STM32_RCC_CCIPR REG32(STM32_RCC_BASE + 0x88) +#define STM32_PWR_SCR REG32(STM32_PWR_BASE + 0x18) + +#define PWR_CR1_LPMS_POS 0U +#define PWR_CR1_LPMS_MSK (0x7UL << PWR_CR1_LPMS_POS) +#define PWR_CR1_LPMS PWR_CR1_LPMS_MSK +#define PWR_CR1_LPMS_STOP0 (0x00000000UL) +#define PWR_CR1_LPMS_STOP1_POS 0U +#define PWR_CR1_LPMS_STOP1_MSK (0x1UL << PWR_CR1_LPMS_STOP1_POS) +#define PWR_CR1_LPMS_STOP1 PWR_CR1_LPMS_STOP1_MSK +#define PWR_CR1_LPMS_STOP2_POS 1U +#define PWR_CR1_LPMS_STOP2_MSK (0x1UL << PWR_CR1_LPMS_STOP2_POS) +#define PWR_CR1_LPMS_STOP2 PWR_CR1_LPMS_STOP2_MSK +#define PWR_CR1_LPMS_STANDBY_POS 0U +#define PWR_CR1_LPMS_STANDBY_MSK (0x3UL << PWR_CR1_LPMS_STANDBY_POS) +#define PWR_CR1_LPMS_STANDBY PWR_CR1_LPMS_STANDBY_MSK +#define PWR_CR1_LPMS_SHUTDOWN_POS 2U +#define PWR_CR1_LPMS_SHUTDOWN_MSK (0x1UL << PWR_CR1_LPMS_SHUTDOWN_POS) +#define PWR_CR1_LPMS_SHUTDOWN PWR_CR1_LPMS_SHUTDOWN_MSK +#define PWR_CR1_VOS_POS 9U +#define PWR_CR1_VOS_MSK (0x3UL << PWR_CR1_VOS_POS) +#define PWR_CR1_VOS PWR_CR1_VOS_MSK +#define PWR_CR1_VOS_0 (0x1UL << PWR_CR1_VOS_POS) +#define PWR_CR1_VOS_1 (0x2UL << PWR_CR1_VOS_POS) + + +/* --- Macro usage in ec code --- */ +#define STM32_RCC_AHB2ENR_GPIOMASK \ + (STM32_RCC_AHB2ENR_GPIOAEN | STM32_RCC_AHB2ENR_GPIOBEN | \ + STM32_RCC_AHB2ENR_GPIOCEN | STM32_RCC_AHB2ENR_GPIODEN | \ + STM32_RCC_AHB2ENR_GPIOEEN | STM32_RCC_AHB2ENR_GPIOHEN) +#define STM32_RCC_ICSCR_MSIRANGE(n) ((n) << STM32_RCC_CR_MSIRANGE_POS) +#define STM32_RCC_ICSCR_MSIRANGE_1MHZ STM32_RCC_ICSCR_MSIRANGE(4) +#define STM32_RCC_ICSCR_MSIRANGE_2MHZ STM32_RCC_ICSCR_MSIRANGE(5) +#define STM32_RCC_ICSCR_MSIRANGE_MASK STM32_RCC_CR_MSIRANGE_MSK +#define STM32_RCC_SYSCFGEN STM32_RCC_APB2ENR_SYSCFGEN + +#define STM32_RCC_PB2_TIM1 STM32_RCC_APB2ENR_TIM1EN +#define STM32_RCC_PB2_TIM15 STM32_RCC_APB2ENR_TIM15EN +#define STM32_RCC_PB2_TIM16 STM32_RCC_APB2ENR_TIM16EN +#ifndef CHIP_VARIANT_STM32L431X +#define STM32_RCC_PB2_TIM8 BIT(13) +#endif +#define STM32_RCC_PWREN STM32_RCC_APB1ENR1_PWREN + +#define STM32_RCC_AHB2ENR_GPIO_PORTA BIT(0) +#define STM32_RCC_AHB2ENR_GPIO_PORTB BIT(1) +#define STM32_RCC_AHB2ENR_GPIO_PORTC BIT(2) +#define STM32_RCC_AHB2ENR_GPIO_PORTD BIT(3) +#define STM32_RCC_AHB2ENR_GPIO_PORTE BIT(4) +#define STM32_RCC_AHB2ENR_GPIO_PORTH BIT(7) #define STM32_RCC_CCIPR_USART1SEL_SHIFT (0) #define STM32_RCC_CCIPR_USART1SEL_MASK (3 << STM32_RCC_CCIPR_USART1SEL_SHIFT) #define STM32_RCC_CCIPR_USART2SEL_SHIFT (2) @@ -443,9 +438,8 @@ #define STM32_RCC_CCIPR_SWPMI1SEL_MASK BIT(STM32_RCC_CCIPR_SWPMI1SEL_SHIFT) #define STM32_RCC_CCIPR_DFSDM1SEL_SHIFT (31) #define STM32_RCC_CCIPR_DFSDM1SEL_MASK BIT(STM32_RCC_CCIPR_DFSDM1SEL_SHIFT) - /* Possible clock sources for each peripheral */ -#define STM32_RCC_CCIPR_UART_PCLK 0 +#define STM32_RCC_CCIPR_UART_PCLK 0 #define STM32_RCC_CCIPR_UART_SYSCLK 1 #define STM32_RCC_CCIPR_UART_HSI16 2 #define STM32_RCC_CCIPR_UART_LSE 3 @@ -480,39 +474,1263 @@ #define STM32_RCC_CCIPR_DFSDM_PCLK 0 #define STM32_RCC_CCIPR_DFSDM_SYSCLK 1 -#define STM32_RCC_BDCR REG32(STM32_RCC_BASE + 0x90) - -#define STM32_RCC_CSR REG32(STM32_RCC_BASE + 0x94) - -#define STM32_RCC_CRRCR REG32(STM32_RCC_BASE + 0x98) - -#define STM32_RCC_CRRCR_HSI48ON BIT(0) -#define STM32_RCC_CRRCR_HSI48RDY BIT(1) -#define STM32_RCC_CRRCR_HSI48CAL_MASK (0x1ff << 7) -#define STM32_RCC_PB2_TIM1 BIT(11) -#define STM32_RCC_PB2_TIM8 BIT(13) -#define STM32_SYSCFG_EXTICR(n) REG32(STM32_SYSCFG_BASE + 8 + 4 * (n)) +#define STM32_RCC_CR REG32(STM32_RCC_BASE + 0x00) +#define STM32_RCC_ICSCR REG32(STM32_RCC_BASE + 0x04) +#define STM32_RCC_CFGR REG32(STM32_RCC_BASE + 0x08) +#define STM32_RCC_PLLCFGR REG32(STM32_RCC_BASE + 0x0C) +#define STM32_RCC_PLLSAI1CFGR REG32(STM32_RCC_BASE + 0x10) +#define STM32_RCC_RESERVED REG32(STM32_RCC_BASE + 0x14) +#define STM32_RCC_CIER REG32(STM32_RCC_BASE + 0x18) +#define STM32_RCC_CIFR REG32(STM32_RCC_BASE + 0x1C) +#define STM32_RCC_CICR REG32(STM32_RCC_BASE + 0x20) +#define STM32_RCC_RESERVED0 REG32(STM32_RCC_BASE + 0x24) +#define STM32_RCC_AHB1RSTR REG32(STM32_RCC_BASE + 0x28) +#define STM32_RCC_AHB2RSTR REG32(STM32_RCC_BASE + 0x2C) +#define STM32_RCC_AHB3RSTR REG32(STM32_RCC_BASE + 0x30) +#define STM32_RCC_RESERVED1 REG32(STM32_RCC_BASE + 0x34) +#define STM32_RCC_APB1RSTR1 REG32(STM32_RCC_BASE + 0x38) +#define STM32_RCC_APB1RSTR2 REG32(STM32_RCC_BASE + 0x3C) +#define STM32_RCC_APB2RSTR REG32(STM32_RCC_BASE + 0x40) +#define STM32_RCC_RESERVED2 REG32(STM32_RCC_BASE + 0x44) +#define STM32_RCC_AHB1ENR REG32(STM32_RCC_BASE + 0x48) +#define STM32_RCC_AHB2ENR REG32(STM32_RCC_BASE + 0x4C) +#define STM32_RCC_AHB3ENR REG32(STM32_RCC_BASE + 0x50) +#define STM32_RCC_RESERVED3 REG32(STM32_RCC_BASE + 0x54) +#define STM32_RCC_APB1ENR1 REG32(STM32_RCC_BASE + 0x58) +#define STM32_RCC_APB1ENR2 REG32(STM32_RCC_BASE + 0x5C) +#define STM32_RCC_APB2ENR REG32(STM32_RCC_BASE + 0x60) +#define STM32_RCC_RESERVED4 REG32(STM32_RCC_BASE + 0x64) +#define STM32_RCC_AHB1SMENR REG32(STM32_RCC_BASE + 0x68) +#define STM32_RCC_AHB2SMENR REG32(STM32_RCC_BASE + 0x6C) +#define STM32_RCC_AHB3SMENR REG32(STM32_RCC_BASE + 0x70) +#define STM32_RCC_RESERVED5 REG32(STM32_RCC_BASE + 0x74) +#define STM32_RCC_APB1SMENR1 REG32(STM32_RCC_BASE + 0x78) +#define STM32_RCC_APB1SMENR2 REG32(STM32_RCC_BASE + 0x7C) +#define STM32_RCC_APB2SMENR REG32(STM32_RCC_BASE + 0x80) +#define STM32_RCC_RESERVED6 REG32(STM32_RCC_BASE + 0x84) +#define STM32_RCC_CCIPR REG32(STM32_RCC_BASE + 0x88) +#define STM32_RCC_RESERVED7 REG32(STM32_RCC_BASE + 0x8C) +#define STM32_RCC_BDCR REG32(STM32_RCC_BASE + 0x90) +#define STM32_RCC_CSR REG32(STM32_RCC_BASE + 0x94) +#define STM32_RCC_CRRCR REG32(STM32_RCC_BASE + 0x98) + +#define STM32_RCC_PLLSAI1_SUPPORT +#define STM32_RCC_PLLP_SUPPORT +#define STM32_RCC_HSI48_SUPPORT +#define STM32_RCC_PLLP_DIV_2_31_SUPPORT +#define STM32_RCC_PLLSAI1P_DIV_2_31_SUPPORT + +#define STM32_RCC_APB1ENR STM32_RCC_APB1ENR1 + +/******************** BIT DEFINITION FOR STM32_RCC_CR REGISTER **************/ +#define STM32_RCC_CR_MSION_POS 0U +#define STM32_RCC_CR_MSION_MSK (0x1UL << STM32_RCC_CR_MSION_POS) +#define STM32_RCC_CR_MSION STM32_RCC_CR_MSION_MSK +#define STM32_RCC_CR_MSIRDY_POS 1U +#define STM32_RCC_CR_MSIRDY_MSK (0x1UL << STM32_RCC_CR_MSIRDY_POS) +#define STM32_RCC_CR_MSIRDY STM32_RCC_CR_MSIRDY_MSK +#define STM32_RCC_CR_MSIPLLEN_POS 2U +#define STM32_RCC_CR_MSIPLLEN_MSK (0x1UL << STM32_RCC_CR_MSIPLLEN_POS) +#define STM32_RCC_CR_MSIPLLEN STM32_RCC_CR_MSIPLLEN_MSK +#define STM32_RCC_CR_MSIRGSEL_POS 3U +#define STM32_RCC_CR_MSIRGSEL_MSK (0x1UL << STM32_RCC_CR_MSIRGSEL_POS) +#define STM32_RCC_CR_MSIRGSEL STM32_RCC_CR_MSIRGSEL_MSK + +/*!< MSIRANGE CONFIGURATION : 12 FREQUENCY RANGES AVAILABLE */ +#define STM32_RCC_CR_MSIRANGE_POS 4U +#define STM32_RCC_CR_MSIRANGE_MSK (0xFUL << STM32_RCC_CR_MSIRANGE_POS) +#define STM32_RCC_CR_MSIRANGE STM32_RCC_CR_MSIRANGE_MSK +#define STM32_RCC_CR_MSIRANGE_0 (0x0UL << STM32_RCC_CR_MSIRANGE_POS) +#define STM32_RCC_CR_MSIRANGE_1 (0x1UL << STM32_RCC_CR_MSIRANGE_POS) +#define STM32_RCC_CR_MSIRANGE_2 (0x2UL << STM32_RCC_CR_MSIRANGE_POS) +#define STM32_RCC_CR_MSIRANGE_3 (0x3UL << STM32_RCC_CR_MSIRANGE_POS) +#define STM32_RCC_CR_MSIRANGE_4 (0x4UL << STM32_RCC_CR_MSIRANGE_POS) +#define STM32_RCC_CR_MSIRANGE_5 (0x5UL << STM32_RCC_CR_MSIRANGE_POS) +#define STM32_RCC_CR_MSIRANGE_6 (0x6UL << STM32_RCC_CR_MSIRANGE_POS) +#define STM32_RCC_CR_MSIRANGE_7 (0x7UL << STM32_RCC_CR_MSIRANGE_POS) +#define STM32_RCC_CR_MSIRANGE_8 (0x8UL << STM32_RCC_CR_MSIRANGE_POS) +#define STM32_RCC_CR_MSIRANGE_9 (0x9UL << STM32_RCC_CR_MSIRANGE_POS) +#define STM32_RCC_CR_MSIRANGE_10 (0xAUL << STM32_RCC_CR_MSIRANGE_POS) +#define STM32_RCC_CR_MSIRANGE_11 (0xBUL << STM32_RCC_CR_MSIRANGE_POS) + +#define STM32_RCC_CR_HSION_POS 8U +#define STM32_RCC_CR_HSION_MSK (0x1UL << STM32_RCC_CR_HSION_POS) +#define STM32_RCC_CR_HSION STM32_RCC_CR_HSION_MSK +#define STM32_RCC_CR_HSIKERON_POS 9U +#define STM32_RCC_CR_HSIKERON_MSK (0x1UL << STM32_RCC_CR_HSIKERON_POS) +#define STM32_RCC_CR_HSIKERON STM32_RCC_CR_HSIKERON_MSK +#define STM32_RCC_CR_HSIRDY_POS 10U +#define STM32_RCC_CR_HSIRDY_MSK (0x1UL << STM32_RCC_CR_HSIRDY_POS) +#define STM32_RCC_CR_HSIRDY STM32_RCC_CR_HSIRDY_MSK +#define STM32_RCC_CR_HSIASFS_POS 11U +#define STM32_RCC_CR_HSIASFS_MSK (0x1UL << STM32_RCC_CR_HSIASFS_POS) +#define STM32_RCC_CR_HSIASFS STM32_RCC_CR_HSIASFS_MSK + +#define STM32_RCC_CR_HSEON_POS 16U +#define STM32_RCC_CR_HSEON_MSK (0x1UL << STM32_RCC_CR_HSEON_POS) +#define STM32_RCC_CR_HSEON STM32_RCC_CR_HSEON_MSK +#define STM32_RCC_CR_HSERDY_POS 17U +#define STM32_RCC_CR_HSERDY_MSK (0x1UL << STM32_RCC_CR_HSERDY_POS) +#define STM32_RCC_CR_HSERDY STM32_RCC_CR_HSERDY_MSK +#define STM32_RCC_CR_HSEBYP_POS 18U +#define STM32_RCC_CR_HSEBYP_MSK (0x1UL << STM32_RCC_CR_HSEBYP_POS) +#define STM32_RCC_CR_HSEBYP STM32_RCC_CR_HSEBYP_MSK +#define STM32_RCC_CR_CSSON_POS 19U +#define STM32_RCC_CR_CSSON_MSK (0x1UL << STM32_RCC_CR_CSSON_POS) +#define STM32_RCC_CR_CSSON STM32_RCC_CR_CSSON_MSK + +#define STM32_RCC_CR_PLLON_POS 24U +#define STM32_RCC_CR_PLLON_MSK (0x1UL << STM32_RCC_CR_PLLON_POS) +#define STM32_RCC_CR_PLLON STM32_RCC_CR_PLLON_MSK +#define STM32_RCC_CR_PLLRDY_POS 25U +#define STM32_RCC_CR_PLLRDY_MSK (0x1UL << STM32_RCC_CR_PLLRDY_POS) +#define STM32_RCC_CR_PLLRDY STM32_RCC_CR_PLLRDY_MSK +#define STM32_RCC_CR_PLLSAI1ON_POS 26U +#define STM32_RCC_CR_PLLSAI1ON_MSK (0x1UL << STM32_RCC_CR_PLLSAI1ON_POS) +#define STM32_RCC_CR_PLLSAI1ON STM32_RCC_CR_PLLSAI1ON_MSK +#define STM32_RCC_CR_PLLSAI1RDY_POS 27U +#define STM32_RCC_CR_PLLSAI1RDY_MSK (0x1UL << STM32_RCC_CR_PLLSAI1RDY_POS) +#define STM32_RCC_CR_PLLSAI1RDY STM32_RCC_CR_PLLSAI1RDY_MSK + +/******************** BIT DEFINITION FOR STM32_RCC_ICSCR REGISTER ***********/ +/*!< MSICAL CONFIGURATION */ +#define STM32_RCC_ICSCR_MSICAL_POS 0U +#define STM32_RCC_ICSCR_MSICAL_MSK (0xFFUL << STM32_RCC_ICSCR_MSICAL_POS) +#define STM32_RCC_ICSCR_MSICAL STM32_RCC_ICSCR_MSICAL_MSK +#define STM32_RCC_ICSCR_MSICAL_0 (0x01UL << STM32_RCC_ICSCR_MSICAL_POS) +#define STM32_RCC_ICSCR_MSICAL_1 (0x02UL << STM32_RCC_ICSCR_MSICAL_POS) +#define STM32_RCC_ICSCR_MSICAL_2 (0x04UL << STM32_RCC_ICSCR_MSICAL_POS) +#define STM32_RCC_ICSCR_MSICAL_3 (0x08UL << STM32_RCC_ICSCR_MSICAL_POS) +#define STM32_RCC_ICSCR_MSICAL_4 (0x10UL << STM32_RCC_ICSCR_MSICAL_POS) +#define STM32_RCC_ICSCR_MSICAL_5 (0x20UL << STM32_RCC_ICSCR_MSICAL_POS) +#define STM32_RCC_ICSCR_MSICAL_6 (0x40UL << STM32_RCC_ICSCR_MSICAL_POS) +#define STM32_RCC_ICSCR_MSICAL_7 (0x80UL << STM32_RCC_ICSCR_MSICAL_POS) + +/*!< MSITRIM CONFIGURATION */ +#define STM32_RCC_ICSCR_MSITRIM_POS 8U +#define STM32_RCC_ICSCR_MSITRIM_MSK (0xFFUL << STM32_RCC_ICSCR_MSITRIM_POS) +#define STM32_RCC_ICSCR_MSITRIM STM32_RCC_ICSCR_MSITRIM_MSK +#define STM32_RCC_ICSCR_MSITRIM_0 (0x01UL << STM32_RCC_ICSCR_MSITRIM_POS) +#define STM32_RCC_ICSCR_MSITRIM_1 (0x02UL << STM32_RCC_ICSCR_MSITRIM_POS) +#define STM32_RCC_ICSCR_MSITRIM_2 (0x04UL << STM32_RCC_ICSCR_MSITRIM_POS) +#define STM32_RCC_ICSCR_MSITRIM_3 (0x08UL << STM32_RCC_ICSCR_MSITRIM_POS) +#define STM32_RCC_ICSCR_MSITRIM_4 (0x10UL << STM32_RCC_ICSCR_MSITRIM_POS) +#define STM32_RCC_ICSCR_MSITRIM_5 (0x20UL << STM32_RCC_ICSCR_MSITRIM_POS) +#define STM32_RCC_ICSCR_MSITRIM_6 (0x40UL << STM32_RCC_ICSCR_MSITRIM_POS) +#define STM32_RCC_ICSCR_MSITRIM_7 (0x80UL << STM32_RCC_ICSCR_MSITRIM_POS) + +/*!< HSICAL CONFIGURATION */ +#define STM32_RCC_ICSCR_HSICAL_POS 16U +#define STM32_RCC_ICSCR_HSICAL_MSK (0xFFUL << STM32_RCC_ICSCR_HSICAL_POS) +#define STM32_RCC_ICSCR_HSICAL STM32_RCC_ICSCR_HSICAL_MSK +#define STM32_RCC_ICSCR_HSICAL_0 (0x01UL << STM32_RCC_ICSCR_HSICAL_POS) +#define STM32_RCC_ICSCR_HSICAL_1 (0x02UL << STM32_RCC_ICSCR_HSICAL_POS) +#define STM32_RCC_ICSCR_HSICAL_2 (0x04UL << STM32_RCC_ICSCR_HSICAL_POS) +#define STM32_RCC_ICSCR_HSICAL_3 (0x08UL << STM32_RCC_ICSCR_HSICAL_POS) +#define STM32_RCC_ICSCR_HSICAL_4 (0x10UL << STM32_RCC_ICSCR_HSICAL_POS) +#define STM32_RCC_ICSCR_HSICAL_5 (0x20UL << STM32_RCC_ICSCR_HSICAL_POS) +#define STM32_RCC_ICSCR_HSICAL_6 (0x40UL << STM32_RCC_ICSCR_HSICAL_POS) +#define STM32_RCC_ICSCR_HSICAL_7 (0x80UL << STM32_RCC_ICSCR_HSICAL_POS) + +/*!< HSITRIM CONFIGURATION */ +#define STM32_RCC_ICSCR_HSITRIM_POS 24U +#define STM32_RCC_ICSCR_HSITRIM_MSK (0x1FUL << STM32_RCC_ICSCR_HSITRIM_POS) +#define STM32_RCC_ICSCR_HSITRIM STM32_RCC_ICSCR_HSITRIM_MSK +#define STM32_RCC_ICSCR_HSITRIM_0 (0x01UL << STM32_RCC_ICSCR_HSITRIM_POS) +#define STM32_RCC_ICSCR_HSITRIM_1 (0x02UL << STM32_RCC_ICSCR_HSITRIM_POS) +#define STM32_RCC_ICSCR_HSITRIM_2 (0x04UL << STM32_RCC_ICSCR_HSITRIM_POS) +#define STM32_RCC_ICSCR_HSITRIM_3 (0x08UL << STM32_RCC_ICSCR_HSITRIM_POS) +#define STM32_RCC_ICSCR_HSITRIM_4 (0x10UL << STM32_RCC_ICSCR_HSITRIM_POS) + +/**************** BIT DEFINITION FOR STM32_RCC_CFGR REGISTER **************/ +/*!< SW CONFIGURATION */ +#define STM32_RCC_CFGR_SW_POS 0U +#define STM32_RCC_CFGR_SW_MSK (0x3UL << STM32_RCC_CFGR_SW_POS) +#define STM32_RCC_CFGR_SW STM32_RCC_CFGR_SW_MSK +#define STM32_RCC_CFGR_SW_0 (0x1UL << STM32_RCC_CFGR_SW_POS) +#define STM32_RCC_CFGR_SW_1 (0x2UL << STM32_RCC_CFGR_SW_POS) + +#define STM32_RCC_CFGR_SW_MSI (0x00000000UL) +#define STM32_RCC_CFGR_SW_HSI (0x00000001UL) +#define STM32_RCC_CFGR_SW_HSE (0x00000002UL) +#define STM32_RCC_CFGR_SW_PLL (0x00000003UL) + +/*!< SWS CONFIGURATION */ +#define STM32_RCC_CFGR_SWS_POS 2U +#define STM32_RCC_CFGR_SWS_MSK (0x3UL << STM32_RCC_CFGR_SWS_POS) +#define STM32_RCC_CFGR_SWS STM32_RCC_CFGR_SWS_MSK +#define STM32_RCC_CFGR_SWS_0 (0x1UL << STM32_RCC_CFGR_SWS_POS) +#define STM32_RCC_CFGR_SWS_1 (0x2UL << STM32_RCC_CFGR_SWS_POS) + +#define STM32_RCC_CFGR_SWS_MSI (0x00000000UL) +#define STM32_RCC_CFGR_SWS_HSI (0x00000004UL) +#define STM32_RCC_CFGR_SWS_HSE (0x00000008UL) +#define STM32_RCC_CFGR_SWS_PLL (0x0000000CUL) + +/*!< HPRE CONFIGURATION */ +#define STM32_RCC_CFGR_HPRE_POS 4U +#define STM32_RCC_CFGR_HPRE_MSK (0xFUL << STM32_RCC_CFGR_HPRE_POS) +#define STM32_RCC_CFGR_HPRE STM32_RCC_CFGR_HPRE_MSK +#define STM32_RCC_CFGR_HPRE_0 (0x1UL << STM32_RCC_CFGR_HPRE_POS) +#define STM32_RCC_CFGR_HPRE_1 (0x2UL << STM32_RCC_CFGR_HPRE_POS) +#define STM32_RCC_CFGR_HPRE_2 (0x4UL << STM32_RCC_CFGR_HPRE_POS) +#define STM32_RCC_CFGR_HPRE_3 (0x8UL << STM32_RCC_CFGR_HPRE_POS) + +#define STM32_RCC_CFGR_HPRE_DIV1 (0x00000000UL) +#define STM32_RCC_CFGR_HPRE_DIV2 (0x00000080UL) +#define STM32_RCC_CFGR_HPRE_DIV4 (0x00000090UL) +#define STM32_RCC_CFGR_HPRE_DIV8 (0x000000A0UL) +#define STM32_RCC_CFGR_HPRE_DIV16 (0x000000B0UL) +#define STM32_RCC_CFGR_HPRE_DIV64 (0x000000C0UL) +#define STM32_RCC_CFGR_HPRE_DIV128 (0x000000D0UL) +#define STM32_RCC_CFGR_HPRE_DIV256 (0x000000E0UL) +#define STM32_RCC_CFGR_HPRE_DIV512 (0x000000F0UL) + +/*!< PPRE1 CONFIGURATION */ +#define STM32_RCC_CFGR_PPRE1_POS 8U +#define STM32_RCC_CFGR_PPRE1_MSK (0x7UL << STM32_RCC_CFGR_PPRE1_POS) +#define STM32_RCC_CFGR_PPRE1 STM32_RCC_CFGR_PPRE1_MSK +#define STM32_RCC_CFGR_PPRE1_0 (0x1UL << STM32_RCC_CFGR_PPRE1_POS) +#define STM32_RCC_CFGR_PPRE1_1 (0x2UL << STM32_RCC_CFGR_PPRE1_POS) +#define STM32_RCC_CFGR_PPRE1_2 (0x4UL << STM32_RCC_CFGR_PPRE1_POS) + +#define STM32_RCC_CFGR_PPRE1_DIV1 (0x00000000UL) +#define STM32_RCC_CFGR_PPRE1_DIV2 (0x00000400UL) +#define STM32_RCC_CFGR_PPRE1_DIV4 (0x00000500UL) +#define STM32_RCC_CFGR_PPRE1_DIV8 (0x00000600UL) +#define STM32_RCC_CFGR_PPRE1_DIV16 (0x00000700UL) + +/*!< PPRE2 CONFIGURATION */ +#define STM32_RCC_CFGR_PPRE2_POS 11U +#define STM32_RCC_CFGR_PPRE2_MSK (0x7UL << STM32_RCC_CFGR_PPRE2_POS) +#define STM32_RCC_CFGR_PPRE2 STM32_RCC_CFGR_PPRE2_MSK +#define STM32_RCC_CFGR_PPRE2_0 (0x1UL << STM32_RCC_CFGR_PPRE2_POS) +#define STM32_RCC_CFGR_PPRE2_1 (0x2UL << STM32_RCC_CFGR_PPRE2_POS) +#define STM32_RCC_CFGR_PPRE2_2 (0x4UL << STM32_RCC_CFGR_PPRE2_POS) + +#define STM32_RCC_CFGR_PPRE2_DIV1 (0x00000000UL) +#define STM32_RCC_CFGR_PPRE2_DIV2 (0x00002000UL) +#define STM32_RCC_CFGR_PPRE2_DIV4 (0x00002800UL) +#define STM32_RCC_CFGR_PPRE2_DIV8 (0x00003000UL) +#define STM32_RCC_CFGR_PPRE2_DIV16 (0x00003800UL) + +#define STM32_RCC_CFGR_STOPWUCK_POS 15U +#define STM32_RCC_CFGR_STOPWUCK_MSK (0x1UL << STM32_RCC_CFGR_STOPWUCK_POS) +#define STM32_RCC_CFGR_STOPWUCK STM32_RCC_CFGR_STOPWUCK_MSK + +/*!< MCOSEL CONFIGURATION */ +#define STM32_RCC_CFGR_MCOSEL_POS 24U +#define STM32_RCC_CFGR_MCOSEL_MSK (0xFUL << STM32_RCC_CFGR_MCOSEL_POS) +#define STM32_RCC_CFGR_MCOSEL STM32_RCC_CFGR_MCOSEL_MSK +#define STM32_RCC_CFGR_MCOSEL_0 (0x1UL << STM32_RCC_CFGR_MCOSEL_POS) +#define STM32_RCC_CFGR_MCOSEL_1 (0x2UL << STM32_RCC_CFGR_MCOSEL_POS) +#define STM32_RCC_CFGR_MCOSEL_2 (0x4UL << STM32_RCC_CFGR_MCOSEL_POS) +#define STM32_RCC_CFGR_MCOSEL_3 (0x8UL << STM32_RCC_CFGR_MCOSEL_POS) + +#define STM32_RCC_CFGR_MCOPRE_POS 28U +#define STM32_RCC_CFGR_MCOPRE_MSK (0x7UL << STM32_RCC_CFGR_MCOPRE_POS) +#define STM32_RCC_CFGR_MCOPRE STM32_RCC_CFGR_MCOPRE_MSK +#define STM32_RCC_CFGR_MCOPRE_0 (0x1UL << STM32_RCC_CFGR_MCOPRE_POS) +#define STM32_RCC_CFGR_MCOPRE_1 (0x2UL << STM32_RCC_CFGR_MCOPRE_POS) +#define STM32_RCC_CFGR_MCOPRE_2 (0x4UL << STM32_RCC_CFGR_MCOPRE_POS) + +#define STM32_RCC_CFGR_MCOPRE_DIV1 (0x00000000UL) +#define STM32_RCC_CFGR_MCOPRE_DIV2 (0x10000000UL) +#define STM32_RCC_CFGR_MCOPRE_DIV4 (0x20000000UL) +#define STM32_RCC_CFGR_MCOPRE_DIV8 (0x30000000UL) +#define STM32_RCC_CFGR_MCOPRE_DIV16 (0x40000000UL) + +/* LEGACY ALIASES */ +#define STM32_RCC_CFGR_MCO_PRE STM32_RCC_CFGR_MCOPRE +#define STM32_RCC_CFGR_MCO_PRE_1 STM32_RCC_CFGR_MCOPRE_DIV1 +#define STM32_RCC_CFGR_MCO_PRE_2 STM32_RCC_CFGR_MCOPRE_DIV2 +#define STM32_RCC_CFGR_MCO_PRE_4 STM32_RCC_CFGR_MCOPRE_DIV4 +#define STM32_RCC_CFGR_MCO_PRE_8 STM32_RCC_CFGR_MCOPRE_DIV8 +#define STM32_RCC_CFGR_MCO_PRE_16 STM32_RCC_CFGR_MCOPRE_DIV16 + +/**************** BIT DEFINITION FOR STM32_RCC_PLLCFGR REGISTER ***********/ +#define STM32_RCC_PLLCFGR_PLLSRC_POS 0U +#define STM32_RCC_PLLCFGR_PLLSRC_MSK (0x3UL << STM32_RCC_PLLCFGR_PLLSRC_POS) +#define STM32_RCC_PLLCFGR_PLLSRC STM32_RCC_PLLCFGR_PLLSRC_MSK + +#define STM32_RCC_PLLCFGR_PLLSRC_MSI_POS 0U +#define STM32_RCC_PLLCFGR_PLLSRC_MSI_MSK \ + (0x1UL << STM32_RCC_PLLCFGR_PLLSRC_MSI_POS) +#define STM32_RCC_PLLCFGR_PLLSRC_MSI STM32_RCC_PLLCFGR_PLLSRC_MSI_MSK +#define STM32_RCC_PLLCFGR_PLLSRC_HSI_POS 1U +#define STM32_RCC_PLLCFGR_PLLSRC_HSI_MSK \ + (0x1UL << STM32_RCC_PLLCFGR_PLLSRC_HSI_POS) +#define STM32_RCC_PLLCFGR_PLLSRC_HSI STM32_RCC_PLLCFGR_PLLSRC_HSI_MSK +#define STM32_RCC_PLLCFGR_PLLSRC_HSE_POS 0U +#define STM32_RCC_PLLCFGR_PLLSRC_HSE_MSK \ + (0x3UL << STM32_RCC_PLLCFGR_PLLSRC_HSE_POS) +#define STM32_RCC_PLLCFGR_PLLSRC_HSE STM32_RCC_PLLCFGR_PLLSRC_HSE_MSK + +#define STM32_RCC_PLLCFGR_PLLM_POS 4U +#define STM32_RCC_PLLCFGR_PLLM_MSK (0x7UL << STM32_RCC_PLLCFGR_PLLM_POS) +#define STM32_RCC_PLLCFGR_PLLM STM32_RCC_PLLCFGR_PLLM_MSK +#define STM32_RCC_PLLCFGR_PLLM_0 (0x1UL << STM32_RCC_PLLCFGR_PLLM_POS) +#define STM32_RCC_PLLCFGR_PLLM_1 (0x2UL << STM32_RCC_PLLCFGR_PLLM_POS) +#define STM32_RCC_PLLCFGR_PLLM_2 (0x4UL << STM32_RCC_PLLCFGR_PLLM_POS) + +#define STM32_RCC_PLLCFGR_PLLN_POS 8U +#define STM32_RCC_PLLCFGR_PLLN_MSK (0x7FUL << STM32_RCC_PLLCFGR_PLLN_POS) +#define STM32_RCC_PLLCFGR_PLLN STM32_RCC_PLLCFGR_PLLN_MSK +#define STM32_RCC_PLLCFGR_PLLN_0 (0x01UL << STM32_RCC_PLLCFGR_PLLN_POS) +#define STM32_RCC_PLLCFGR_PLLN_1 (0x02UL << STM32_RCC_PLLCFGR_PLLN_POS) +#define STM32_RCC_PLLCFGR_PLLN_2 (0x04UL << STM32_RCC_PLLCFGR_PLLN_POS) +#define STM32_RCC_PLLCFGR_PLLN_3 (0x08UL << STM32_RCC_PLLCFGR_PLLN_POS) +#define STM32_RCC_PLLCFGR_PLLN_4 (0x10UL << STM32_RCC_PLLCFGR_PLLN_POS) +#define STM32_RCC_PLLCFGR_PLLN_5 (0x20UL << STM32_RCC_PLLCFGR_PLLN_POS) +#define STM32_RCC_PLLCFGR_PLLN_6 (0x40UL << STM32_RCC_PLLCFGR_PLLN_POS) + +#define STM32_RCC_PLLCFGR_PLLPEN_POS 16U +#define STM32_RCC_PLLCFGR_PLLPEN_MSK (0x1UL << STM32_RCC_PLLCFGR_PLLPEN_POS) +#define STM32_RCC_PLLCFGR_PLLPEN STM32_RCC_PLLCFGR_PLLPEN_MSK +#define STM32_RCC_PLLCFGR_PLLP_POS 17U +#define STM32_RCC_PLLCFGR_PLLP_MSK (0x1UL << STM32_RCC_PLLCFGR_PLLP_POS) +#define STM32_RCC_PLLCFGR_PLLP STM32_RCC_PLLCFGR_PLLP_MSK +#define STM32_RCC_PLLCFGR_PLLQEN_POS 20U +#define STM32_RCC_PLLCFGR_PLLQEN_MSK (0x1UL << STM32_RCC_PLLCFGR_PLLQEN_POS) +#define STM32_RCC_PLLCFGR_PLLQEN STM32_RCC_PLLCFGR_PLLQEN_MSK + +#define STM32_RCC_PLLCFGR_PLLQ_POS 21U +#define STM32_RCC_PLLCFGR_PLLQ_MSK (0x3UL << STM32_RCC_PLLCFGR_PLLQ_POS) +#define STM32_RCC_PLLCFGR_PLLQ STM32_RCC_PLLCFGR_PLLQ_MSK +#define STM32_RCC_PLLCFGR_PLLQ_0 (0x1UL << STM32_RCC_PLLCFGR_PLLQ_POS) +#define STM32_RCC_PLLCFGR_PLLQ_1 (0x2UL << STM32_RCC_PLLCFGR_PLLQ_POS) + +#define STM32_RCC_PLLCFGR_PLLREN_POS 24U +#define STM32_RCC_PLLCFGR_PLLREN_MSK (0x1UL << STM32_RCC_PLLCFGR_PLLREN_POS) +#define STM32_RCC_PLLCFGR_PLLREN STM32_RCC_PLLCFGR_PLLREN_MSK +#define STM32_RCC_PLLCFGR_PLLR_POS 25U +#define STM32_RCC_PLLCFGR_PLLR_MSK (0x3UL << STM32_RCC_PLLCFGR_PLLR_POS) +#define STM32_RCC_PLLCFGR_PLLR STM32_RCC_PLLCFGR_PLLR_MSK +#define STM32_RCC_PLLCFGR_PLLR_0 (0x1UL << STM32_RCC_PLLCFGR_PLLR_POS) +#define STM32_RCC_PLLCFGR_PLLR_1 (0x2UL << STM32_RCC_PLLCFGR_PLLR_POS) + +#define STM32_RCC_PLLCFGR_PLLPDIV_POS 27U +#define STM32_RCC_PLLCFGR_PLLPDIV_MSK (0x1FUL << STM32_RCC_PLLCFGR_PLLPDIV_POS) +#define STM32_RCC_PLLCFGR_PLLPDIV STM32_RCC_PLLCFGR_PLLPDIV_MSK +#define STM32_RCC_PLLCFGR_PLLPDIV_0 (0x01UL << STM32_RCC_PLLCFGR_PLLPDIV_POS) +#define STM32_RCC_PLLCFGR_PLLPDIV_1 (0x02UL << STM32_RCC_PLLCFGR_PLLPDIV_POS) +#define STM32_RCC_PLLCFGR_PLLPDIV_2 (0x04UL << STM32_RCC_PLLCFGR_PLLPDIV_POS) +#define STM32_RCC_PLLCFGR_PLLPDIV_3 (0x08UL << STM32_RCC_PLLCFGR_PLLPDIV_POS) +#define STM32_RCC_PLLCFGR_PLLPDIV_4 (0x10UL << STM32_RCC_PLLCFGR_PLLPDIV_POS) + +/**************** BIT DEFINITION FOR STM32_RCC_PLLSAI1CFGR REGISTER ********/ +#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS 8U +#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_MSK \ + (0x7FUL << STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS) +#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N STM32_RCC_PLLSAI1CFGR_PLLSAI1N_MSK +#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_0 \ + (0x01UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS) +#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_1 \ + (0x02UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS) +#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_2 \ + (0x04UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS) +#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_3 \ + (0x08UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS) +#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_4 \ + (0x10UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS) +#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_5 \ + (0x20UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS) +#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_6 \ + (0x40UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS) + +#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PEN_POS 16U +#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PEN_MSK \ + (0x1UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1PEN_POS) +#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PEN STM32_RCC_PLLSAI1CFGR_PLLSAI1PEN_MSK +#define STM32_RCC_PLLSAI1CFGR_PLLSAI1P_POS 17U +#define STM32_RCC_PLLSAI1CFGR_PLLSAI1P_MSK \ + (0x1UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1P_POS) +#define STM32_RCC_PLLSAI1CFGR_PLLSAI1P STM32_RCC_PLLSAI1CFGR_PLLSAI1P_MSK + +#define STM32_RCC_PLLSAI1CFGR_PLLSAI1QEN_POS 20U +#define STM32_RCC_PLLSAI1CFGR_PLLSAI1QEN_MSK \ + (0x1UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1QEN_POS) +#define STM32_RCC_PLLSAI1CFGR_PLLSAI1QEN STM32_RCC_PLLSAI1CFGR_PLLSAI1QEN_MSK +#define STM32_RCC_PLLSAI1CFGR_PLLSAI1Q_POS 21U +#define STM32_RCC_PLLSAI1CFGR_PLLSAI1Q_MSK \ + (0x3UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1Q_POS) +#define STM32_RCC_PLLSAI1CFGR_PLLSAI1Q STM32_RCC_PLLSAI1CFGR_PLLSAI1Q_MSK +#define STM32_RCC_PLLSAI1CFGR_PLLSAI1Q_0 \ + (0x1UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1Q_POS) +#define STM32_RCC_PLLSAI1CFGR_PLLSAI1Q_1 \ + (0x2UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1Q_POS) + +#define STM32_RCC_PLLSAI1CFGR_PLLSAI1REN_POS 24U +#define STM32_RCC_PLLSAI1CFGR_PLLSAI1REN_MSK \ + (0x1UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1REN_POS) +#define STM32_RCC_PLLSAI1CFGR_PLLSAI1REN STM32_RCC_PLLSAI1CFGR_PLLSAI1REN_MSK +#define STM32_RCC_PLLSAI1CFGR_PLLSAI1R_POS 25U +#define STM32_RCC_PLLSAI1CFGR_PLLSAI1R_MSK \ + (0x3UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1R_POS) +#define STM32_RCC_PLLSAI1CFGR_PLLSAI1R STM32_RCC_PLLSAI1CFGR_PLLSAI1R_MSK +#define STM32_RCC_PLLSAI1CFGR_PLLSAI1R_0 \ + (0x1UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1R_POS) +#define STM32_RCC_PLLSAI1CFGR_PLLSAI1R_1 \ + (0x2UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1R_POS) + +#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_POS 27U +#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_MSK \ + (0x1FUL << STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_POS) +#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_MSK +#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_0 \ + (0x01UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_POS) +#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_1 \ + (0x02UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_POS) +#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_2 \ + (0x04UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_POS) +#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_3 \ + (0x08UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_POS) +#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_4 \ + (0x10UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_POS) + +/************** BIT DEFINITION FOR STM32_RCC_CIER REGISTER ******************/ +#define STM32_RCC_CIER_LSIRDYIE_POS 0U +#define STM32_RCC_CIER_LSIRDYIE_MSK (0x1UL << STM32_RCC_CIER_LSIRDYIE_POS) +#define STM32_RCC_CIER_LSIRDYIE STM32_RCC_CIER_LSIRDYIE_MSK +#define STM32_RCC_CIER_LSERDYIE_POS 1U +#define STM32_RCC_CIER_LSERDYIE_MSK (0x1UL << STM32_RCC_CIER_LSERDYIE_POS) +#define STM32_RCC_CIER_LSERDYIE STM32_RCC_CIER_LSERDYIE_MSK +#define STM32_RCC_CIER_MSIRDYIE_POS 2U +#define STM32_RCC_CIER_MSIRDYIE_MSK (0x1UL << STM32_RCC_CIER_MSIRDYIE_POS) +#define STM32_RCC_CIER_MSIRDYIE STM32_RCC_CIER_MSIRDYIE_MSK +#define STM32_RCC_CIER_HSIRDYIE_POS 3U +#define STM32_RCC_CIER_HSIRDYIE_MSK (0x1UL << STM32_RCC_CIER_HSIRDYIE_POS) +#define STM32_RCC_CIER_HSIRDYIE STM32_RCC_CIER_HSIRDYIE_MSK +#define STM32_RCC_CIER_HSERDYIE_POS 4U +#define STM32_RCC_CIER_HSERDYIE_MSK (0x1UL << STM32_RCC_CIER_HSERDYIE_POS) +#define STM32_RCC_CIER_HSERDYIE STM32_RCC_CIER_HSERDYIE_MSK +#define STM32_RCC_CIER_PLLRDYIE_POS 5U +#define STM32_RCC_CIER_PLLRDYIE_MSK (0x1UL << STM32_RCC_CIER_PLLRDYIE_POS) +#define STM32_RCC_CIER_PLLRDYIE STM32_RCC_CIER_PLLRDYIE_MSK +#define STM32_RCC_CIER_PLLSAI1RDYIE_POS 6U +#define STM32_RCC_CIER_PLLSAI1RDYIE_MSK \ + (0x1UL << STM32_RCC_CIER_PLLSAI1RDYIE_POS) +#define STM32_RCC_CIER_PLLSAI1RDYIE STM32_RCC_CIER_PLLSAI1RDYIE_MSK +#define STM32_RCC_CIER_LSECSSIE_POS 9U +#define STM32_RCC_CIER_LSECSSIE_MSK (0x1UL << STM32_RCC_CIER_LSECSSIE_POS) +#define STM32_RCC_CIER_LSECSSIE STM32_RCC_CIER_LSECSSIE_MSK +#define STM32_RCC_CIER_HSI48RDYIE_POS 10U +#define STM32_RCC_CIER_HSI48RDYIE_MSK (0x1UL << STM32_RCC_CIER_HSI48RDYIE_POS) +#define STM32_RCC_CIER_HSI48RDYIE STM32_RCC_CIER_HSI48RDYIE_MSK + +/************** BIT DEFINITION FOR STM32_RCC_CIFR REGISTER ******************/ +#define STM32_RCC_CIFR_LSIRDYF_POS 0U +#define STM32_RCC_CIFR_LSIRDYF_MSK (0x1UL << STM32_RCC_CIFR_LSIRDYF_POS) +#define STM32_RCC_CIFR_LSIRDYF STM32_RCC_CIFR_LSIRDYF_MSK +#define STM32_RCC_CIFR_LSERDYF_POS 1U +#define STM32_RCC_CIFR_LSERDYF_MSK (0x1UL << STM32_RCC_CIFR_LSERDYF_POS) +#define STM32_RCC_CIFR_LSERDYF STM32_RCC_CIFR_LSERDYF_MSK +#define STM32_RCC_CIFR_MSIRDYF_POS 2U +#define STM32_RCC_CIFR_MSIRDYF_MSK (0x1UL << STM32_RCC_CIFR_MSIRDYF_POS) +#define STM32_RCC_CIFR_MSIRDYF STM32_RCC_CIFR_MSIRDYF_MSK +#define STM32_RCC_CIFR_HSIRDYF_POS 3U +#define STM32_RCC_CIFR_HSIRDYF_MSK (0x1UL << STM32_RCC_CIFR_HSIRDYF_POS) +#define STM32_RCC_CIFR_HSIRDYF STM32_RCC_CIFR_HSIRDYF_MSK +#define STM32_RCC_CIFR_HSERDYF_POS 4U +#define STM32_RCC_CIFR_HSERDYF_MSK (0x1UL << STM32_RCC_CIFR_HSERDYF_POS) +#define STM32_RCC_CIFR_HSERDYF STM32_RCC_CIFR_HSERDYF_MSK +#define STM32_RCC_CIFR_PLLRDYF_POS 5U +#define STM32_RCC_CIFR_PLLRDYF_MSK (0x1UL << STM32_RCC_CIFR_PLLRDYF_POS) +#define STM32_RCC_CIFR_PLLRDYF STM32_RCC_CIFR_PLLRDYF_MSK +#define STM32_RCC_CIFR_PLLSAI1RDYF_POS 6U +#define STM32_RCC_CIFR_PLLSAI1RDYF_MSK (0x1UL << STM32_RCC_CIFR_PLLSAI1RDYF_POS) +#define STM32_RCC_CIFR_PLLSAI1RDYF STM32_RCC_CIFR_PLLSAI1RDYF_MSK +#define STM32_RCC_CIFR_CSSF_POS 8U +#define STM32_RCC_CIFR_CSSF_MSK (0x1UL << STM32_RCC_CIFR_CSSF_POS) +#define STM32_RCC_CIFR_CSSF STM32_RCC_CIFR_CSSF_MSK +#define STM32_RCC_CIFR_LSECSSF_POS 9U +#define STM32_RCC_CIFR_LSECSSF_MSK (0x1UL << STM32_RCC_CIFR_LSECSSF_POS) +#define STM32_RCC_CIFR_LSECSSF STM32_RCC_CIFR_LSECSSF_MSK +#define STM32_RCC_CIFR_HSI48RDYF_POS 10U +#define STM32_RCC_CIFR_HSI48RDYF_MSK (0x1UL << STM32_RCC_CIFR_HSI48RDYF_POS) +#define STM32_RCC_CIFR_HSI48RDYF STM32_RCC_CIFR_HSI48RDYF_MSK + +/************** BIT DEFINITION FOR STM32_RCC_CICR REGISTER ******************/ +#define STM32_RCC_CICR_LSIRDYC_POS 0U +#define STM32_RCC_CICR_LSIRDYC_MSK (0x1UL << STM32_RCC_CICR_LSIRDYC_POS) +#define STM32_RCC_CICR_LSIRDYC STM32_RCC_CICR_LSIRDYC_MSK +#define STM32_RCC_CICR_LSERDYC_POS 1U +#define STM32_RCC_CICR_LSERDYC_MSK (0x1UL << STM32_RCC_CICR_LSERDYC_POS) +#define STM32_RCC_CICR_LSERDYC STM32_RCC_CICR_LSERDYC_MSK +#define STM32_RCC_CICR_MSIRDYC_POS 2U +#define STM32_RCC_CICR_MSIRDYC_MSK (0x1UL << STM32_RCC_CICR_MSIRDYC_POS) +#define STM32_RCC_CICR_MSIRDYC STM32_RCC_CICR_MSIRDYC_MSK +#define STM32_RCC_CICR_HSIRDYC_POS 3U +#define STM32_RCC_CICR_HSIRDYC_MSK (0x1UL << STM32_RCC_CICR_HSIRDYC_POS) +#define STM32_RCC_CICR_HSIRDYC STM32_RCC_CICR_HSIRDYC_MSK +#define STM32_RCC_CICR_HSERDYC_POS 4U +#define STM32_RCC_CICR_HSERDYC_MSK (0x1UL << STM32_RCC_CICR_HSERDYC_POS) +#define STM32_RCC_CICR_HSERDYC STM32_RCC_CICR_HSERDYC_MSK +#define STM32_RCC_CICR_PLLRDYC_POS 5U +#define STM32_RCC_CICR_PLLRDYC_MSK (0x1UL << STM32_RCC_CICR_PLLRDYC_POS) +#define STM32_RCC_CICR_PLLRDYC STM32_RCC_CICR_PLLRDYC_MSK +#define STM32_RCC_CICR_PLLSAI1RDYC_POS 6U +#define STM32_RCC_CICR_PLLSAI1RDYC_MSK (0x1UL << STM32_RCC_CICR_PLLSAI1RDYC_POS) +#define STM32_RCC_CICR_PLLSAI1RDYC STM32_RCC_CICR_PLLSAI1RDYC_MSK +#define STM32_RCC_CICR_CSSC_POS 8U +#define STM32_RCC_CICR_CSSC_MSK (0x1UL << STM32_RCC_CICR_CSSC_POS) +#define STM32_RCC_CICR_CSSC STM32_RCC_CICR_CSSC_MSK +#define STM32_RCC_CICR_LSECSSC_POS 9U +#define STM32_RCC_CICR_LSECSSC_MSK (0x1UL << STM32_RCC_CICR_LSECSSC_POS) +#define STM32_RCC_CICR_LSECSSC STM32_RCC_CICR_LSECSSC_MSK +#define STM32_RCC_CICR_HSI48RDYC_POS 10U +#define STM32_RCC_CICR_HSI48RDYC_MSK (0x1UL << STM32_RCC_CICR_HSI48RDYC_POS) +#define STM32_RCC_CICR_HSI48RDYC STM32_RCC_CICR_HSI48RDYC_MSK + +/************** BIT DEFINITION FOR STM32_RCC_AHB1RSTR REGISTER **************/ +#define STM32_RCC_AHB1RSTR_DMA1RST_POS 0U +#define STM32_RCC_AHB1RSTR_DMA1RST_MSK (0x1UL << STM32_RCC_AHB1RSTR_DMA1RST_POS) +#define STM32_RCC_AHB1RSTR_DMA1RST STM32_RCC_AHB1RSTR_DMA1RST_MSK +#define STM32_RCC_AHB1RSTR_DMA2RST_POS 1U +#define STM32_RCC_AHB1RSTR_DMA2RST_MSK (0x1UL << STM32_RCC_AHB1RSTR_DMA2RST_POS) +#define STM32_RCC_AHB1RSTR_DMA2RST STM32_RCC_AHB1RSTR_DMA2RST_MSK +#define STM32_RCC_AHB1RSTR_FLASHRST_POS 8U +#define STM32_RCC_AHB1RSTR_FLASHRST_MSK \ + (0x1UL << STM32_RCC_AHB1RSTR_FLASHRST_POS) +#define STM32_RCC_AHB1RSTR_FLASHRST STM32_RCC_AHB1RSTR_FLASHRST_MSK +#define STM32_RCC_AHB1RSTR_CRCRST_POS 12U +#define STM32_RCC_AHB1RSTR_CRCRST_MSK (0x1UL << STM32_RCC_AHB1RSTR_CRCRST_POS) +#define STM32_RCC_AHB1RSTR_CRCRST STM32_RCC_AHB1RSTR_CRCRST_MSK +#define STM32_RCC_AHB1RSTR_TSCRST_POS 16U +#define STM32_RCC_AHB1RSTR_TSCRST_MSK (0x1UL << STM32_RCC_AHB1RSTR_TSCRST_POS) +#define STM32_RCC_AHB1RSTR_TSCRST STM32_RCC_AHB1RSTR_TSCRST_MSK + +/************** BIT DEFINITION FOR STM32_RCC_AHB2RSTR REGISTER **************/ +#define STM32_RCC_AHB2RSTR_GPIOARST_POS 0U +#define STM32_RCC_AHB2RSTR_GPIOARST_MSK \ + (0x1UL << STM32_RCC_AHB2RSTR_GPIOARST_POS) +#define STM32_RCC_AHB2RSTR_GPIOARST STM32_RCC_AHB2RSTR_GPIOARST_MSK +#define STM32_RCC_AHB2RSTR_GPIOBRST_POS 1U +#define STM32_RCC_AHB2RSTR_GPIOBRST_MSK \ + (0x1UL << STM32_RCC_AHB2RSTR_GPIOBRST_POS) +#define STM32_RCC_AHB2RSTR_GPIOBRST STM32_RCC_AHB2RSTR_GPIOBRST_MSK +#define STM32_RCC_AHB2RSTR_GPIOCRST_POS 2U +#define STM32_RCC_AHB2RSTR_GPIOCRST_MSK \ + (0x1UL << STM32_RCC_AHB2RSTR_GPIOCRST_POS) +#define STM32_RCC_AHB2RSTR_GPIOCRST STM32_RCC_AHB2RSTR_GPIOCRST_MSK +#define STM32_RCC_AHB2RSTR_GPIODRST_POS 3U +#define STM32_RCC_AHB2RSTR_GPIODRST_MSK \ + (0x1UL << STM32_RCC_AHB2RSTR_GPIODRST_POS) +#define STM32_RCC_AHB2RSTR_GPIODRST STM32_RCC_AHB2RSTR_GPIODRST_MSK +#define STM32_RCC_AHB2RSTR_GPIOERST_POS 4U +#define STM32_RCC_AHB2RSTR_GPIOERST_MSK \ + (0x1UL << STM32_RCC_AHB2RSTR_GPIOERST_POS) +#define STM32_RCC_AHB2RSTR_GPIOERST STM32_RCC_AHB2RSTR_GPIOERST_MSK +#define STM32_RCC_AHB2RSTR_GPIOHRST_POS 7U +#define STM32_RCC_AHB2RSTR_GPIOHRST_MSK \ + (0x1UL << STM32_RCC_AHB2RSTR_GPIOHRST_POS) +#define STM32_RCC_AHB2RSTR_GPIOHRST STM32_RCC_AHB2RSTR_GPIOHRST_MSK +#define STM32_RCC_AHB2RSTR_ADCRST_POS 13U +#define STM32_RCC_AHB2RSTR_ADCRST_MSK (0x1UL << STM32_RCC_AHB2RSTR_ADCRST_POS) +#define STM32_RCC_AHB2RSTR_ADCRST STM32_RCC_AHB2RSTR_ADCRST_MSK +#define STM32_RCC_AHB2RSTR_AESRST_POS 16U +#define STM32_RCC_AHB2RSTR_AESRST_MSK (0x1UL << STM32_RCC_AHB2RSTR_AESRST_POS) +#define STM32_RCC_AHB2RSTR_AESRST STM32_RCC_AHB2RSTR_AESRST_MSK +#define STM32_RCC_AHB2RSTR_RNGRST_POS 18U +#define STM32_RCC_AHB2RSTR_RNGRST_MSK (0x1UL << STM32_RCC_AHB2RSTR_RNGRST_POS) +#define STM32_RCC_AHB2RSTR_RNGRST STM32_RCC_AHB2RSTR_RNGRST_MSK + +/************* BIT DEFINITION FOR STM32_RCC_AHB3RSTR REGISTER **************/ +#define STM32_RCC_AHB3RSTR_QSPIRST_POS 8U +#define STM32_RCC_AHB3RSTR_QSPIRST_MSK (0x1UL << STM32_RCC_AHB3RSTR_QSPIRST_POS) +#define STM32_RCC_AHB3RSTR_QSPIRST STM32_RCC_AHB3RSTR_QSPIRST_MSK + +/************* BIT DEFINITION FOR STM32_RCC_APB1RSTR1 REGISTER **************/ +#define STM32_RCC_APB1RSTR1_TIM2RST_POS 0U +#define STM32_RCC_APB1RSTR1_TIM2RST_MSK \ + (0x1UL << STM32_RCC_APB1RSTR1_TIM2RST_POS) +#define STM32_RCC_APB1RSTR1_TIM2RST STM32_RCC_APB1RSTR1_TIM2RST_MSK +#define STM32_RCC_APB1RSTR1_TIM6RST_POS 4U +#define STM32_RCC_APB1RSTR1_TIM6RST_MSK \ + (0x1UL << STM32_RCC_APB1RSTR1_TIM6RST_POS) +#define STM32_RCC_APB1RSTR1_TIM6RST STM32_RCC_APB1RSTR1_TIM6RST_MSK +#define STM32_RCC_APB1RSTR1_TIM7RST_POS 5U +#define STM32_RCC_APB1RSTR1_TIM7RST_MSK \ + (0x1UL << STM32_RCC_APB1RSTR1_TIM7RST_POS) +#define STM32_RCC_APB1RSTR1_TIM7RST STM32_RCC_APB1RSTR1_TIM7RST_MSK +#define STM32_RCC_APB1RSTR1_LCDRST_POS 9U +#define STM32_RCC_APB1RSTR1_LCDRST_MSK (0x1UL << STM32_RCC_APB1RSTR1_LCDRST_POS) +#define STM32_RCC_APB1RSTR1_LCDRST STM32_RCC_APB1RSTR1_LCDRST_MSK +#define STM32_RCC_APB1RSTR1_SPI2RST_POS 14U +#define STM32_RCC_APB1RSTR1_SPI2RST_MSK \ + (0x1UL << STM32_RCC_APB1RSTR1_SPI2RST_POS) +#define STM32_RCC_APB1RSTR1_SPI2RST STM32_RCC_APB1RSTR1_SPI2RST_MSK +#define STM32_RCC_APB1RSTR1_SPI3RST_POS 15U +#define STM32_RCC_APB1RSTR1_SPI3RST_MSK \ + (0x1UL << STM32_RCC_APB1RSTR1_SPI3RST_POS) +#define STM32_RCC_APB1RSTR1_SPI3RST STM32_RCC_APB1RSTR1_SPI3RST_MSK +#define STM32_RCC_APB1RSTR1_USART2RST_POS 17U +#define STM32_RCC_APB1RSTR1_USART2RST_MSK \ + (0x1UL << STM32_RCC_APB1RSTR1_USART2RST_POS) +#define STM32_RCC_APB1RSTR1_USART2RST STM32_RCC_APB1RSTR1_USART2RST_MSK +#define STM32_RCC_APB1RSTR1_USART3RST_POS 18U +#define STM32_RCC_APB1RSTR1_USART3RST_MSK \ + (0x1UL << STM32_RCC_APB1RSTR1_USART3RST_POS) +#define STM32_RCC_APB1RSTR1_USART3RST STM32_RCC_APB1RSTR1_USART3RST_MSK +#define STM32_RCC_APB1RSTR1_I2C1RST_POS 21U +#define STM32_RCC_APB1RSTR1_I2C1RST_MSK \ + (0x1UL << STM32_RCC_APB1RSTR1_I2C1RST_POS) +#define STM32_RCC_APB1RSTR1_I2C1RST STM32_RCC_APB1RSTR1_I2C1RST_MSK +#define STM32_RCC_APB1RSTR1_I2C2RST_POS 22U +#define STM32_RCC_APB1RSTR1_I2C2RST_MSK \ + (0x1UL << STM32_RCC_APB1RSTR1_I2C2RST_POS) +#define STM32_RCC_APB1RSTR1_I2C2RST STM32_RCC_APB1RSTR1_I2C2RST_MSK +#define STM32_RCC_APB1RSTR1_I2C3RST_POS 23U +#define STM32_RCC_APB1RSTR1_I2C3RST_MSK \ + (0x1UL << STM32_RCC_APB1RSTR1_I2C3RST_POS) +#define STM32_RCC_APB1RSTR1_I2C3RST STM32_RCC_APB1RSTR1_I2C3RST_MSK +#define STM32_RCC_APB1RSTR1_CRSRST_POS 24U +#define STM32_RCC_APB1RSTR1_CRSRST_MSK (0x1UL << STM32_RCC_APB1RSTR1_CRSRST_POS) +#define STM32_RCC_APB1RSTR1_CRSRST STM32_RCC_APB1RSTR1_CRSRST_MSK +#define STM32_RCC_APB1RSTR1_CAN1RST_POS 25U +#define STM32_RCC_APB1RSTR1_CAN1RST_MSK \ + (0x1UL << STM32_RCC_APB1RSTR1_CAN1RST_POS) +#define STM32_RCC_APB1RSTR1_CAN1RST STM32_RCC_APB1RSTR1_CAN1RST_MSK +#define STM32_RCC_APB1RSTR1_USBFSRST_POS 26U +#define STM32_RCC_APB1RSTR1_USBFSRST_MSK \ + (0x1UL << STM32_RCC_APB1RSTR1_USBFSRST_POS) +#define STM32_RCC_APB1RSTR1_USBFSRST STM32_RCC_APB1RSTR1_USBFSRST_MSK +#define STM32_RCC_APB1RSTR1_PWRRST_POS 28U +#define STM32_RCC_APB1RSTR1_PWRRST_MSK (0x1UL << STM32_RCC_APB1RSTR1_PWRRST_POS) +#define STM32_RCC_APB1RSTR1_PWRRST STM32_RCC_APB1RSTR1_PWRRST_MSK +#define STM32_RCC_APB1RSTR1_DAC1RST_POS 29U +#define STM32_RCC_APB1RSTR1_DAC1RST_MSK \ + (0x1UL << STM32_RCC_APB1RSTR1_DAC1RST_POS) +#define STM32_RCC_APB1RSTR1_DAC1RST STM32_RCC_APB1RSTR1_DAC1RST_MSK +#define STM32_RCC_APB1RSTR1_OPAMPRST_POS 30U +#define STM32_RCC_APB1RSTR1_OPAMPRST_MSK \ + (0x1UL << STM32_RCC_APB1RSTR1_OPAMPRST_POS) +#define STM32_RCC_APB1RSTR1_OPAMPRST STM32_RCC_APB1RSTR1_OPAMPRST_MSK +#define STM32_RCC_APB1RSTR1_LPTIM1RST_POS 31U +#define STM32_RCC_APB1RSTR1_LPTIM1RST_MSK \ + (0x1UL << STM32_RCC_APB1RSTR1_LPTIM1RST_POS) +#define STM32_RCC_APB1RSTR1_LPTIM1RST STM32_RCC_APB1RSTR1_LPTIM1RST_MSK + +/************* BIT DEFINITION FOR STM32_RCC_APB1RSTR2 REGISTER **************/ +#define STM32_RCC_APB1RSTR2_LPUART1RST_POS 0U +#define STM32_RCC_APB1RSTR2_LPUART1RST_MSK \ + (0x1UL << STM32_RCC_APB1RSTR2_LPUART1RST_POS) +#define STM32_RCC_APB1RSTR2_LPUART1RST STM32_RCC_APB1RSTR2_LPUART1RST_MSK +#define STM32_RCC_APB1RSTR2_SWPMI1RST_POS 2U +#define STM32_RCC_APB1RSTR2_SWPMI1RST_MSK \ + (0x1UL << STM32_RCC_APB1RSTR2_SWPMI1RST_POS) +#define STM32_RCC_APB1RSTR2_SWPMI1RST STM32_RCC_APB1RSTR2_SWPMI1RST_MSK +#define STM32_RCC_APB1RSTR2_LPTIM2RST_POS 5U +#define STM32_RCC_APB1RSTR2_LPTIM2RST_MSK \ + (0x1UL << STM32_RCC_APB1RSTR2_LPTIM2RST_POS) +#define STM32_RCC_APB1RSTR2_LPTIM2RST STM32_RCC_APB1RSTR2_LPTIM2RST_MSK + +/************** BIT DEFINITION FOR STM32_RCC_APB2RSTR REGISTER **************/ +#define STM32_RCC_APB2RSTR_SYSCFGRST_POS 0U +#define STM32_RCC_APB2RSTR_SYSCFGRST_MSK \ + (0x1UL << STM32_RCC_APB2RSTR_SYSCFGRST_POS) +#define STM32_RCC_APB2RSTR_SYSCFGRST STM32_RCC_APB2RSTR_SYSCFGRST_MSK +#define STM32_RCC_APB2RSTR_SDMMC1RST_POS 10U +#define STM32_RCC_APB2RSTR_SDMMC1RST_MSK \ + (0x1UL << STM32_RCC_APB2RSTR_SDMMC1RST_POS) +#define STM32_RCC_APB2RSTR_SDMMC1RST STM32_RCC_APB2RSTR_SDMMC1RST_MSK +#define STM32_RCC_APB2RSTR_TIM1RST_POS 11U +#define STM32_RCC_APB2RSTR_TIM1RST_MSK (0x1UL << STM32_RCC_APB2RSTR_TIM1RST_POS) +#define STM32_RCC_APB2RSTR_TIM1RST STM32_RCC_APB2RSTR_TIM1RST_MSK +#define STM32_RCC_APB2RSTR_SPI1RST_POS 12U +#define STM32_RCC_APB2RSTR_SPI1RST_MSK (0x1UL << STM32_RCC_APB2RSTR_SPI1RST_POS) +#define STM32_RCC_APB2RSTR_SPI1RST STM32_RCC_APB2RSTR_SPI1RST_MSK +#define STM32_RCC_APB2RSTR_USART1RST_POS 14U +#define STM32_RCC_APB2RSTR_USART1RST_MSK \ + (0x1UL << STM32_RCC_APB2RSTR_USART1RST_POS) +#define STM32_RCC_APB2RSTR_USART1RST STM32_RCC_APB2RSTR_USART1RST_MSK +#define STM32_RCC_APB2RSTR_TIM15RST_POS 16U +#define STM32_RCC_APB2RSTR_TIM15RST_MSK \ + (0x1UL << STM32_RCC_APB2RSTR_TIM15RST_POS) +#define STM32_RCC_APB2RSTR_TIM15RST STM32_RCC_APB2RSTR_TIM15RST_MSK +#define STM32_RCC_APB2RSTR_TIM16RST_POS 17U +#define STM32_RCC_APB2RSTR_TIM16RST_MSK \ + (0x1UL << STM32_RCC_APB2RSTR_TIM16RST_POS) +#define STM32_RCC_APB2RSTR_TIM16RST STM32_RCC_APB2RSTR_TIM16RST_MSK +#define STM32_RCC_APB2RSTR_SAI1RST_POS 21U +#define STM32_RCC_APB2RSTR_SAI1RST_MSK (0x1UL << STM32_RCC_APB2RSTR_SAI1RST_POS) +#define STM32_RCC_APB2RSTR_SAI1RST STM32_RCC_APB2RSTR_SAI1RST_MSK + +/************** BIT DEFINITION FOR STM32_RCC_AHB1ENR REGISTER ***************/ +#define STM32_RCC_AHB1ENR_DMA1EN_POS 0U +#define STM32_RCC_AHB1ENR_DMA1EN_MSK (0x1UL << STM32_RCC_AHB1ENR_DMA1EN_POS) +#define STM32_RCC_AHB1ENR_DMA1EN STM32_RCC_AHB1ENR_DMA1EN_MSK +#define STM32_RCC_AHB1ENR_DMA2EN_POS 1U +#define STM32_RCC_AHB1ENR_DMA2EN_MSK (0x1UL << STM32_RCC_AHB1ENR_DMA2EN_POS) +#define STM32_RCC_AHB1ENR_DMA2EN STM32_RCC_AHB1ENR_DMA2EN_MSK +#define STM32_RCC_AHB1ENR_FLASHEN_POS 8U +#define STM32_RCC_AHB1ENR_FLASHEN_MSK (0x1UL << STM32_RCC_AHB1ENR_FLASHEN_POS) +#define STM32_RCC_AHB1ENR_FLASHEN STM32_RCC_AHB1ENR_FLASHEN_MSK +#define STM32_RCC_AHB1ENR_CRCEN_POS 12U +#define STM32_RCC_AHB1ENR_CRCEN_MSK (0x1UL << STM32_RCC_AHB1ENR_CRCEN_POS) +#define STM32_RCC_AHB1ENR_CRCEN STM32_RCC_AHB1ENR_CRCEN_MSK +#define STM32_RCC_AHB1ENR_TSCEN_POS 16U +#define STM32_RCC_AHB1ENR_TSCEN_MSK (0x1UL << STM32_RCC_AHB1ENR_TSCEN_POS) +#define STM32_RCC_AHB1ENR_TSCEN STM32_RCC_AHB1ENR_TSCEN_MSK + +/*************** BIT DEFINITION FOR STM32_RCC_AHB2ENR REGISTER *********/ +#define STM32_RCC_AHB2ENR_GPIOAEN_POS 0U +#define STM32_RCC_AHB2ENR_GPIOAEN_MSK (0x1UL << STM32_RCC_AHB2ENR_GPIOAEN_POS) +#define STM32_RCC_AHB2ENR_GPIOAEN STM32_RCC_AHB2ENR_GPIOAEN_MSK +#define STM32_RCC_AHB2ENR_GPIOBEN_POS 1U +#define STM32_RCC_AHB2ENR_GPIOBEN_MSK (0x1UL << STM32_RCC_AHB2ENR_GPIOBEN_POS) +#define STM32_RCC_AHB2ENR_GPIOBEN STM32_RCC_AHB2ENR_GPIOBEN_MSK +#define STM32_RCC_AHB2ENR_GPIOCEN_POS 2U +#define STM32_RCC_AHB2ENR_GPIOCEN_MSK (0x1UL << STM32_RCC_AHB2ENR_GPIOCEN_POS) +#define STM32_RCC_AHB2ENR_GPIOCEN STM32_RCC_AHB2ENR_GPIOCEN_MSK +#define STM32_RCC_AHB2ENR_GPIODEN_POS 3U +#define STM32_RCC_AHB2ENR_GPIODEN_MSK (0x1UL << STM32_RCC_AHB2ENR_GPIODEN_POS) +#define STM32_RCC_AHB2ENR_GPIODEN STM32_RCC_AHB2ENR_GPIODEN_MSK +#define STM32_RCC_AHB2ENR_GPIOEEN_POS 4U +#define STM32_RCC_AHB2ENR_GPIOEEN_MSK (0x1UL << STM32_RCC_AHB2ENR_GPIOEEN_POS) +#define STM32_RCC_AHB2ENR_GPIOEEN STM32_RCC_AHB2ENR_GPIOEEN_MSK +#define STM32_RCC_AHB2ENR_GPIOHEN_POS 7U +#define STM32_RCC_AHB2ENR_GPIOHEN_MSK (0x1UL << STM32_RCC_AHB2ENR_GPIOHEN_POS) +#define STM32_RCC_AHB2ENR_GPIOHEN STM32_RCC_AHB2ENR_GPIOHEN_MSK +#define STM32_RCC_AHB2ENR_ADCEN_POS 13U +#define STM32_RCC_AHB2ENR_ADCEN_MSK (0x1UL << STM32_RCC_AHB2ENR_ADCEN_POS) +#define STM32_RCC_AHB2ENR_ADCEN STM32_RCC_AHB2ENR_ADCEN_MSK +#define STM32_RCC_AHB2ENR_AESEN_POS 16U +#define STM32_RCC_AHB2ENR_AESEN_MSK (0x1UL << STM32_RCC_AHB2ENR_AESEN_POS) +#define STM32_RCC_AHB2ENR_AESEN STM32_RCC_AHB2ENR_AESEN_MSK +#define STM32_RCC_AHB2ENR_RNGEN_POS 18U +#define STM32_RCC_AHB2ENR_RNGEN_MSK (0x1UL << STM32_RCC_AHB2ENR_RNGEN_POS) +#define STM32_RCC_AHB2ENR_RNGEN STM32_RCC_AHB2ENR_RNGEN_MSK + +/************** BIT DEFINITION FOR STM32_RCC_AHB3ENR REGISTER ***************/ +#define STM32_RCC_AHB3ENR_QSPIEN_POS 8U +#define STM32_RCC_AHB3ENR_QSPIEN_MSK (0x1UL << STM32_RCC_AHB3ENR_QSPIEN_POS) +#define STM32_RCC_AHB3ENR_QSPIEN STM32_RCC_AHB3ENR_QSPIEN_MSK + +/************** BIT DEFINITION FOR STM32_RCC_APB1ENR1 REGISTER **************/ +#define STM32_RCC_APB1ENR1_TIM2EN_POS 0U +#define STM32_RCC_APB1ENR1_TIM2EN_MSK (0x1UL << STM32_RCC_APB1ENR1_TIM2EN_POS) +#define STM32_RCC_APB1ENR1_TIM2EN STM32_RCC_APB1ENR1_TIM2EN_MSK +#define STM32_RCC_APB1ENR1_TIM6EN_POS 4U +#define STM32_RCC_APB1ENR1_TIM6EN_MSK (0x1UL << STM32_RCC_APB1ENR1_TIM6EN_POS) +#define STM32_RCC_APB1ENR1_TIM6EN STM32_RCC_APB1ENR1_TIM6EN_MSK +#define STM32_RCC_APB1ENR1_TIM7EN_POS 5U +#define STM32_RCC_APB1ENR1_TIM7EN_MSK (0x1UL << STM32_RCC_APB1ENR1_TIM7EN_POS) +#define STM32_RCC_APB1ENR1_TIM7EN STM32_RCC_APB1ENR1_TIM7EN_MSK +#define STM32_RCC_APB1ENR1_LCDEN_POS 9U +#define STM32_RCC_APB1ENR1_LCDEN_MSK (0x1UL << STM32_RCC_APB1ENR1_LCDEN_POS) +#define STM32_RCC_APB1ENR1_LCDEN STM32_RCC_APB1ENR1_LCDEN_MSK +#define STM32_RCC_APB1ENR1_RTCAPBEN_POS 10U +#define STM32_RCC_APB1ENR1_RTCAPBEN_MSK \ + (0x1UL << STM32_RCC_APB1ENR1_RTCAPBEN_POS) +#define STM32_RCC_APB1ENR1_RTCAPBEN STM32_RCC_APB1ENR1_RTCAPBEN_MSK +#define STM32_RCC_APB1ENR1_WWDGEN_POS 11U +#define STM32_RCC_APB1ENR1_WWDGEN_MSK (0x1UL << STM32_RCC_APB1ENR1_WWDGEN_POS) +#define STM32_RCC_APB1ENR1_WWDGEN STM32_RCC_APB1ENR1_WWDGEN_MSK +#define STM32_RCC_APB1ENR1_SPI2EN_POS 14U +#define STM32_RCC_APB1ENR1_SPI2EN_MSK (0x1UL << STM32_RCC_APB1ENR1_SPI2EN_POS) +#define STM32_RCC_APB1ENR1_SPI2EN STM32_RCC_APB1ENR1_SPI2EN_MSK +#define STM32_RCC_APB1ENR1_SPI3EN_POS 15U +#define STM32_RCC_APB1ENR1_SPI3EN_MSK (0x1UL << STM32_RCC_APB1ENR1_SPI3EN_POS) +#define STM32_RCC_APB1ENR1_SPI3EN STM32_RCC_APB1ENR1_SPI3EN_MSK +#define STM32_RCC_APB1ENR1_USART2EN_POS 17U +#define STM32_RCC_APB1ENR1_USART2EN_MSK \ + (0x1UL << STM32_RCC_APB1ENR1_USART2EN_POS) +#define STM32_RCC_APB1ENR1_USART2EN STM32_RCC_APB1ENR1_USART2EN_MSK +#define STM32_RCC_APB1ENR1_USART3EN_POS 18U +#define STM32_RCC_APB1ENR1_USART3EN_MSK \ + (0x1UL << STM32_RCC_APB1ENR1_USART3EN_POS) +#define STM32_RCC_APB1ENR1_USART3EN STM32_RCC_APB1ENR1_USART3EN_MSK +#define STM32_RCC_APB1ENR1_I2C1EN_POS 21U +#define STM32_RCC_APB1ENR1_I2C1EN_MSK (0x1UL << STM32_RCC_APB1ENR1_I2C1EN_POS) +#define STM32_RCC_APB1ENR1_I2C1EN STM32_RCC_APB1ENR1_I2C1EN_MSK +#define STM32_RCC_APB1ENR1_I2C2EN_POS 22U +#define STM32_RCC_APB1ENR1_I2C2EN_MSK (0x1UL << STM32_RCC_APB1ENR1_I2C2EN_POS) +#define STM32_RCC_APB1ENR1_I2C2EN STM32_RCC_APB1ENR1_I2C2EN_MSK +#define STM32_RCC_APB1ENR1_I2C3EN_POS 23U +#define STM32_RCC_APB1ENR1_I2C3EN_MSK (0x1UL << STM32_RCC_APB1ENR1_I2C3EN_POS) +#define STM32_RCC_APB1ENR1_I2C3EN STM32_RCC_APB1ENR1_I2C3EN_MSK +#define STM32_RCC_APB1ENR1_CRSEN_POS 24U +#define STM32_RCC_APB1ENR1_CRSEN_MSK (0x1UL << STM32_RCC_APB1ENR1_CRSEN_POS) +#define STM32_RCC_APB1ENR1_CRSEN STM32_RCC_APB1ENR1_CRSEN_MSK +#define STM32_RCC_APB1ENR1_CAN1EN_POS 25U +#define STM32_RCC_APB1ENR1_CAN1EN_MSK (0x1UL << STM32_RCC_APB1ENR1_CAN1EN_POS) +#define STM32_RCC_APB1ENR1_CAN1EN STM32_RCC_APB1ENR1_CAN1EN_MSK +#define STM32_RCC_APB1ENR1_USBFSEN_POS 26U +#define STM32_RCC_APB1ENR1_USBFSEN_MSK (0x1UL << STM32_RCC_APB1ENR1_USBFSEN_POS) +#define STM32_RCC_APB1ENR1_USBFSEN STM32_RCC_APB1ENR1_USBFSEN_MSK +#define STM32_RCC_APB1ENR1_PWREN_POS 28U +#define STM32_RCC_APB1ENR1_PWREN_MSK (0x1UL << STM32_RCC_APB1ENR1_PWREN_POS) +#define STM32_RCC_APB1ENR1_PWREN STM32_RCC_APB1ENR1_PWREN_MSK +#define STM32_RCC_APB1ENR1_DAC1EN_POS 29U +#define STM32_RCC_APB1ENR1_DAC1EN_MSK (0x1UL << STM32_RCC_APB1ENR1_DAC1EN_POS) +#define STM32_RCC_APB1ENR1_DAC1EN STM32_RCC_APB1ENR1_DAC1EN_MSK +#define STM32_RCC_APB1ENR1_OPAMPEN_POS 30U +#define STM32_RCC_APB1ENR1_OPAMPEN_MSK (0x1UL << STM32_RCC_APB1ENR1_OPAMPEN_POS) +#define STM32_RCC_APB1ENR1_OPAMPEN STM32_RCC_APB1ENR1_OPAMPEN_MSK +#define STM32_RCC_APB1ENR1_LPTIM1EN_POS 31U +#define STM32_RCC_APB1ENR1_LPTIM1EN_MSK \ + (0x1UL << STM32_RCC_APB1ENR1_LPTIM1EN_POS) +#define STM32_RCC_APB1ENR1_LPTIM1EN STM32_RCC_APB1ENR1_LPTIM1EN_MSK + +/************ BIT DEFINITION FOR STM32_RCC_APB1RSTR2 REGISTER **************/ +#define STM32_RCC_APB1ENR2_LPUART1EN_POS 0U +#define STM32_RCC_APB1ENR2_LPUART1EN_MSK \ + (0x1UL << STM32_RCC_APB1ENR2_LPUART1EN_POS) +#define STM32_RCC_APB1ENR2_LPUART1EN STM32_RCC_APB1ENR2_LPUART1EN_MSK +#define STM32_RCC_APB1ENR2_SWPMI1EN_POS 2U +#define STM32_RCC_APB1ENR2_SWPMI1EN_MSK \ + (0x1UL << STM32_RCC_APB1ENR2_SWPMI1EN_POS) +#define STM32_RCC_APB1ENR2_SWPMI1EN STM32_RCC_APB1ENR2_SWPMI1EN_MSK +#define STM32_RCC_APB1ENR2_LPTIM2EN_POS 5U +#define STM32_RCC_APB1ENR2_LPTIM2EN_MSK \ + (0x1UL << STM32_RCC_APB1ENR2_LPTIM2EN_POS) +#define STM32_RCC_APB1ENR2_LPTIM2EN STM32_RCC_APB1ENR2_LPTIM2EN_MSK + +/************** BIT DEFINITION FOR STM32_RCC_APB2ENR REGISTER ***************/ +#define STM32_RCC_APB2ENR_SYSCFGEN_POS 0U +#define STM32_RCC_APB2ENR_SYSCFGEN_MSK (0x1UL << STM32_RCC_APB2ENR_SYSCFGEN_POS) +#define STM32_RCC_APB2ENR_SYSCFGEN STM32_RCC_APB2ENR_SYSCFGEN_MSK +#define STM32_RCC_APB2ENR_FWEN_POS 7U +#define STM32_RCC_APB2ENR_FWEN_MSK (0x1UL << STM32_RCC_APB2ENR_FWEN_POS) +#define STM32_RCC_APB2ENR_FWEN STM32_RCC_APB2ENR_FWEN_MSK +#define STM32_RCC_APB2ENR_SDMMC1EN_POS 10U +#define STM32_RCC_APB2ENR_SDMMC1EN_MSK (0x1UL << STM32_RCC_APB2ENR_SDMMC1EN_POS) +#define STM32_RCC_APB2ENR_SDMMC1EN STM32_RCC_APB2ENR_SDMMC1EN_MSK +#define STM32_RCC_APB2ENR_TIM1EN_POS 11U +#define STM32_RCC_APB2ENR_TIM1EN_MSK (0x1UL << STM32_RCC_APB2ENR_TIM1EN_POS) +#define STM32_RCC_APB2ENR_TIM1EN STM32_RCC_APB2ENR_TIM1EN_MSK +#define STM32_RCC_APB2ENR_SPI1EN_POS 12U +#define STM32_RCC_APB2ENR_SPI1EN_MSK (0x1UL << STM32_RCC_APB2ENR_SPI1EN_POS) +#define STM32_RCC_APB2ENR_SPI1EN STM32_RCC_APB2ENR_SPI1EN_MSK +#define STM32_RCC_APB2ENR_USART1EN_POS 14U +#define STM32_RCC_APB2ENR_USART1EN_MSK (0x1UL << STM32_RCC_APB2ENR_USART1EN_POS) +#define STM32_RCC_APB2ENR_USART1EN STM32_RCC_APB2ENR_USART1EN_MSK +#define STM32_RCC_APB2ENR_TIM15EN_POS 16U +#define STM32_RCC_APB2ENR_TIM15EN_MSK (0x1UL << STM32_RCC_APB2ENR_TIM15EN_POS) +#define STM32_RCC_APB2ENR_TIM15EN STM32_RCC_APB2ENR_TIM15EN_MSK +#define STM32_RCC_APB2ENR_TIM16EN_POS 17U +#define STM32_RCC_APB2ENR_TIM16EN_MSK (0x1UL << STM32_RCC_APB2ENR_TIM16EN_POS) +#define STM32_RCC_APB2ENR_TIM16EN STM32_RCC_APB2ENR_TIM16EN_MSK +#define STM32_RCC_APB2ENR_SAI1EN_POS 21U +#define STM32_RCC_APB2ENR_SAI1EN_MSK (0x1UL << STM32_RCC_APB2ENR_SAI1EN_POS) +#define STM32_RCC_APB2ENR_SAI1EN STM32_RCC_APB2ENR_SAI1EN_MSK + +/************ BIT DEFINITION FOR STM32_RCC_AHB1SMENR REGISTER ***************/ +#define STM32_RCC_AHB1SMENR_DMA1SMEN_POS 0U +#define STM32_RCC_AHB1SMENR_DMA1SMEN_MSK \ + (0x1UL << STM32_RCC_AHB1SMENR_DMA1SMEN_POS) +#define STM32_RCC_AHB1SMENR_DMA1SMEN STM32_RCC_AHB1SMENR_DMA1SMEN_MSK +#define STM32_RCC_AHB1SMENR_DMA2SMEN_POS 1U +#define STM32_RCC_AHB1SMENR_DMA2SMEN_MSK \ + (0x1UL << STM32_RCC_AHB1SMENR_DMA2SMEN_POS) +#define STM32_RCC_AHB1SMENR_DMA2SMEN STM32_RCC_AHB1SMENR_DMA2SMEN_MSK +#define STM32_RCC_AHB1SMENR_FLASHSMEN_POS 8U +#define STM32_RCC_AHB1SMENR_FLASHSMEN_MSK \ + (0x1UL << STM32_RCC_AHB1SMENR_FLASHSMEN_POS) +#define STM32_RCC_AHB1SMENR_FLASHSMEN STM32_RCC_AHB1SMENR_FLASHSMEN_MSK +#define STM32_RCC_AHB1SMENR_SRAM1SMEN_POS 9U +#define STM32_RCC_AHB1SMENR_SRAM1SMEN_MSK \ + (0x1UL << STM32_RCC_AHB1SMENR_SRAM1SMEN_POS) +#define STM32_RCC_AHB1SMENR_SRAM1SMEN STM32_RCC_AHB1SMENR_SRAM1SMEN_MSK +#define STM32_RCC_AHB1SMENR_CRCSMEN_POS 12U +#define STM32_RCC_AHB1SMENR_CRCSMEN_MSK \ + (0x1UL << STM32_RCC_AHB1SMENR_CRCSMEN_POS) +#define STM32_RCC_AHB1SMENR_CRCSMEN STM32_RCC_AHB1SMENR_CRCSMEN_MSK +#define STM32_RCC_AHB1SMENR_TSCSMEN_POS 16U +#define STM32_RCC_AHB1SMENR_TSCSMEN_MSK \ + (0x1UL << STM32_RCC_AHB1SMENR_TSCSMEN_POS) +#define STM32_RCC_AHB1SMENR_TSCSMEN STM32_RCC_AHB1SMENR_TSCSMEN_MSK + +/************** BIT DEFINITION FOR STM32_RCC_AHB2SMENR REGISTER *************/ +#define STM32_RCC_AHB2SMENR_GPIOASMEN_POS 0U +#define STM32_RCC_AHB2SMENR_GPIOASMEN_MSK \ + (0x1UL << STM32_RCC_AHB2SMENR_GPIOASMEN_POS) +#define STM32_RCC_AHB2SMENR_GPIOASMEN STM32_RCC_AHB2SMENR_GPIOASMEN_MSK +#define STM32_RCC_AHB2SMENR_GPIOBSMEN_POS 1U +#define STM32_RCC_AHB2SMENR_GPIOBSMEN_MSK \ + (0x1UL << STM32_RCC_AHB2SMENR_GPIOBSMEN_POS) +#define STM32_RCC_AHB2SMENR_GPIOBSMEN STM32_RCC_AHB2SMENR_GPIOBSMEN_MSK +#define STM32_RCC_AHB2SMENR_GPIOCSMEN_POS 2U +#define STM32_RCC_AHB2SMENR_GPIOCSMEN_MSK \ + (0x1UL << STM32_RCC_AHB2SMENR_GPIOCSMEN_POS) +#define STM32_RCC_AHB2SMENR_GPIOCSMEN STM32_RCC_AHB2SMENR_GPIOCSMEN_MSK +#define STM32_RCC_AHB2SMENR_GPIODSMEN_POS 3U +#define STM32_RCC_AHB2SMENR_GPIODSMEN_MSK \ + (0x1UL << STM32_RCC_AHB2SMENR_GPIODSMEN_POS) +#define STM32_RCC_AHB2SMENR_GPIODSMEN STM32_RCC_AHB2SMENR_GPIODSMEN_MSK +#define STM32_RCC_AHB2SMENR_GPIOESMEN_POS 4U +#define STM32_RCC_AHB2SMENR_GPIOESMEN_MSK \ + (0x1UL << STM32_RCC_AHB2SMENR_GPIOESMEN_POS) +#define STM32_RCC_AHB2SMENR_GPIOESMEN STM32_RCC_AHB2SMENR_GPIOESMEN_MSK +#define STM32_RCC_AHB2SMENR_GPIOHSMEN_POS 7U +#define STM32_RCC_AHB2SMENR_GPIOHSMEN_MSK \ + (0x1UL << STM32_RCC_AHB2SMENR_GPIOHSMEN_POS) +#define STM32_RCC_AHB2SMENR_GPIOHSMEN STM32_RCC_AHB2SMENR_GPIOHSMEN_MSK +#define STM32_RCC_AHB2SMENR_SRAM2SMEN_POS 9U +#define STM32_RCC_AHB2SMENR_SRAM2SMEN_MSK \ + (0x1UL << STM32_RCC_AHB2SMENR_SRAM2SMEN_POS) +#define STM32_RCC_AHB2SMENR_SRAM2SMEN STM32_RCC_AHB2SMENR_SRAM2SMEN_MSK +#define STM32_RCC_AHB2SMENR_ADCSMEN_POS 13U +#define STM32_RCC_AHB2SMENR_ADCSMEN_MSK \ + (0x1UL << STM32_RCC_AHB2SMENR_ADCSMEN_POS) +#define STM32_RCC_AHB2SMENR_ADCSMEN STM32_RCC_AHB2SMENR_ADCSMEN_MSK +#define STM32_RCC_AHB2SMENR_AESSMEN_POS 16U +#define STM32_RCC_AHB2SMENR_AESSMEN_MSK \ + (0x1UL << STM32_RCC_AHB2SMENR_AESSMEN_POS) +#define STM32_RCC_AHB2SMENR_AESSMEN STM32_RCC_AHB2SMENR_AESSMEN_MSK +#define STM32_RCC_AHB2SMENR_RNGSMEN_POS 18U +#define STM32_RCC_AHB2SMENR_RNGSMEN_MSK \ + (0x1UL << STM32_RCC_AHB2SMENR_RNGSMEN_POS) +#define STM32_RCC_AHB2SMENR_RNGSMEN STM32_RCC_AHB2SMENR_RNGSMEN_MSK + +/************** BIT DEFINITION FOR STM32_RCC_AHB3SMENR REGISTER *************/ +#define STM32_RCC_AHB3SMENR_QSPISMEN_POS 8U +#define STM32_RCC_AHB3SMENR_QSPISMEN_MSK \ + (0x1UL << STM32_RCC_AHB3SMENR_QSPISMEN_POS) +#define STM32_RCC_AHB3SMENR_QSPISMEN STM32_RCC_AHB3SMENR_QSPISMEN_MSK + +/************* BIT DEFINITION FOR STM32_RCC_APB1SMENR1 REGISTER *************/ +#define STM32_RCC_APB1SMENR1_TIM2SMEN_POS 0U +#define STM32_RCC_APB1SMENR1_TIM2SMEN_MSK \ + (0x1UL << STM32_RCC_APB1SMENR1_TIM2SMEN_POS) +#define STM32_RCC_APB1SMENR1_TIM2SMEN STM32_RCC_APB1SMENR1_TIM2SMEN_MSK +#define STM32_RCC_APB1SMENR1_TIM6SMEN_POS 4U +#define STM32_RCC_APB1SMENR1_TIM6SMEN_MSK \ + (0x1UL << STM32_RCC_APB1SMENR1_TIM6SMEN_POS) +#define STM32_RCC_APB1SMENR1_TIM6SMEN STM32_RCC_APB1SMENR1_TIM6SMEN_MSK +#define STM32_RCC_APB1SMENR1_TIM7SMEN_POS 5U +#define STM32_RCC_APB1SMENR1_TIM7SMEN_MSK \ + (0x1UL << STM32_RCC_APB1SMENR1_TIM7SMEN_POS) +#define STM32_RCC_APB1SMENR1_TIM7SMEN STM32_RCC_APB1SMENR1_TIM7SMEN_MSK +#define STM32_RCC_APB1SMENR1_LCDSMEN_POS 9U +#define STM32_RCC_APB1SMENR1_LCDSMEN_MSK \ + (0x1UL << STM32_RCC_APB1SMENR1_LCDSMEN_POS) +#define STM32_RCC_APB1SMENR1_LCDSMEN STM32_RCC_APB1SMENR1_LCDSMEN_MSK +#define STM32_RCC_APB1SMENR1_RTCAPBSMEN_POS 10U +#define STM32_RCC_APB1SMENR1_RTCAPBSMEN_MSK \ + (0x1UL << STM32_RCC_APB1SMENR1_RTCAPBSMEN_POS) +#define STM32_RCC_APB1SMENR1_RTCAPBSMEN STM32_RCC_APB1SMENR1_RTCAPBSMEN_MSK +#define STM32_RCC_APB1SMENR1_WWDGSMEN_POS 11U +#define STM32_RCC_APB1SMENR1_WWDGSMEN_MSK \ + (0x1UL << STM32_RCC_APB1SMENR1_WWDGSMEN_POS) +#define STM32_RCC_APB1SMENR1_WWDGSMEN STM32_RCC_APB1SMENR1_WWDGSMEN_MSK +#define STM32_RCC_APB1SMENR1_SPI2SMEN_POS 14U +#define STM32_RCC_APB1SMENR1_SPI2SMEN_MSK \ + (0x1UL << STM32_RCC_APB1SMENR1_SPI2SMEN_POS) +#define STM32_RCC_APB1SMENR1_SPI2SMEN STM32_RCC_APB1SMENR1_SPI2SMEN_MSK +#define STM32_RCC_APB1SMENR1_SPI3SMEN_POS 15U +#define STM32_RCC_APB1SMENR1_SPI3SMEN_MSK \ + (0x1UL << STM32_RCC_APB1SMENR1_SPI3SMEN_POS) +#define STM32_RCC_APB1SMENR1_SPI3SMEN STM32_RCC_APB1SMENR1_SPI3SMEN_MSK +#define STM32_RCC_APB1SMENR1_USART2SMEN_POS 17U +#define STM32_RCC_APB1SMENR1_USART2SMEN_MSK \ + (0x1UL << STM32_RCC_APB1SMENR1_USART2SMEN_POS) +#define STM32_RCC_APB1SMENR1_USART2SMEN STM32_RCC_APB1SMENR1_USART2SMEN_MSK +#define STM32_RCC_APB1SMENR1_USART3SMEN_POS 18U +#define STM32_RCC_APB1SMENR1_USART3SMEN_MSK \ + (0x1UL << STM32_RCC_APB1SMENR1_USART3SMEN_POS) +#define STM32_RCC_APB1SMENR1_USART3SMEN STM32_RCC_APB1SMENR1_USART3SMEN_MSK +#define STM32_RCC_APB1SMENR1_I2C1SMEN_POS 21U +#define STM32_RCC_APB1SMENR1_I2C1SMEN_MSK \ + (0x1UL << STM32_RCC_APB1SMENR1_I2C1SMEN_POS) +#define STM32_RCC_APB1SMENR1_I2C1SMEN STM32_RCC_APB1SMENR1_I2C1SMEN_MSK +#define STM32_RCC_APB1SMENR1_I2C2SMEN_POS 22U +#define STM32_RCC_APB1SMENR1_I2C2SMEN_MSK \ + (0x1UL << STM32_RCC_APB1SMENR1_I2C2SMEN_POS) +#define STM32_RCC_APB1SMENR1_I2C2SMEN STM32_RCC_APB1SMENR1_I2C2SMEN_MSK +#define STM32_RCC_APB1SMENR1_I2C3SMEN_POS 23U +#define STM32_RCC_APB1SMENR1_I2C3SMEN_MSK \ + (0x1UL << STM32_RCC_APB1SMENR1_I2C3SMEN_POS) +#define STM32_RCC_APB1SMENR1_I2C3SMEN STM32_RCC_APB1SMENR1_I2C3SMEN_MSK +#define STM32_RCC_APB1SMENR1_CRSSMEN_POS 24U +#define STM32_RCC_APB1SMENR1_CRSSMEN_MSK \ + (0x1UL << STM32_RCC_APB1SMENR1_CRSSMEN_POS) +#define STM32_RCC_APB1SMENR1_CRSSMEN STM32_RCC_APB1SMENR1_CRSSMEN_MSK +#define STM32_RCC_APB1SMENR1_CAN1SMEN_POS 25U +#define STM32_RCC_APB1SMENR1_CAN1SMEN_MSK \ + (0x1UL << STM32_RCC_APB1SMENR1_CAN1SMEN_POS) +#define STM32_RCC_APB1SMENR1_CAN1SMEN STM32_RCC_APB1SMENR1_CAN1SMEN_MSK +#define STM32_RCC_APB1SMENR1_USBFSSMEN_POS 26U +#define STM32_RCC_APB1SMENR1_USBFSSMEN_MSK \ + (0x1UL << STM32_RCC_APB1SMENR1_USBFSSMEN_POS) +#define STM32_RCC_APB1SMENR1_USBFSSMEN STM32_RCC_APB1SMENR1_USBFSSMEN_MSK +#define STM32_RCC_APB1SMENR1_PWRSMEN_POS 28U +#define STM32_RCC_APB1SMENR1_PWRSMEN_MSK \ + (0x1UL << STM32_RCC_APB1SMENR1_PWRSMEN_POS) +#define STM32_RCC_APB1SMENR1_PWRSMEN STM32_RCC_APB1SMENR1_PWRSMEN_MSK +#define STM32_RCC_APB1SMENR1_DAC1SMEN_POS 29U +#define STM32_RCC_APB1SMENR1_DAC1SMEN_MSK \ + (0x1UL << STM32_RCC_APB1SMENR1_DAC1SMEN_POS) +#define STM32_RCC_APB1SMENR1_DAC1SMEN STM32_RCC_APB1SMENR1_DAC1SMEN_MSK +#define STM32_RCC_APB1SMENR1_OPAMPSMEN_POS 30U +#define STM32_RCC_APB1SMENR1_OPAMPSMEN_MSK \ + (0x1UL << STM32_RCC_APB1SMENR1_OPAMPSMEN_POS) +#define STM32_RCC_APB1SMENR1_OPAMPSMEN STM32_RCC_APB1SMENR1_OPAMPSMEN_MSK +#define STM32_RCC_APB1SMENR1_LPTIM1SMEN_POS 31U +#define STM32_RCC_APB1SMENR1_LPTIM1SMEN_MSK \ + (0x1UL << STM32_RCC_APB1SMENR1_LPTIM1SMEN_POS) +#define STM32_RCC_APB1SMENR1_LPTIM1SMEN STM32_RCC_APB1SMENR1_LPTIM1SMEN_MSK + +/************* BIT DEFINITION FOR STM32_RCC_APB1SMENR2 REGISTER *************/ +#define STM32_RCC_APB1SMENR2_LPUART1SMEN_POS 0U +#define STM32_RCC_APB1SMENR2_LPUART1SMEN_MSK \ + (0x1UL << STM32_RCC_APB1SMENR2_LPUART1SMEN_POS) +#define STM32_RCC_APB1SMENR2_LPUART1SMEN STM32_RCC_APB1SMENR2_LPUART1SMEN_MSK +#define STM32_RCC_APB1SMENR2_SWPMI1SMEN_POS 2U +#define STM32_RCC_APB1SMENR2_SWPMI1SMEN_MSK \ + (0x1UL << STM32_RCC_APB1SMENR2_SWPMI1SMEN_POS) +#define STM32_RCC_APB1SMENR2_SWPMI1SMEN STM32_RCC_APB1SMENR2_SWPMI1SMEN_MSK +#define STM32_RCC_APB1SMENR2_LPTIM2SMEN_POS 5U +#define STM32_RCC_APB1SMENR2_LPTIM2SMEN_MSK \ + (0x1UL << STM32_RCC_APB1SMENR2_LPTIM2SMEN_POS) +#define STM32_RCC_APB1SMENR2_LPTIM2SMEN STM32_RCC_APB1SMENR2_LPTIM2SMEN_MSK + +/************ BIT DEFINITION FOR STM32_RCC_APB2SMENR REGISTER *************/ +#define STM32_RCC_APB2SMENR_SYSCFGSMEN_POS 0U +#define STM32_RCC_APB2SMENR_SYSCFGSMEN_MSK \ + (0x1UL << STM32_RCC_APB2SMENR_SYSCFGSMEN_POS) +#define STM32_RCC_APB2SMENR_SYSCFGSMEN STM32_RCC_APB2SMENR_SYSCFGSMEN_MSK +#define STM32_RCC_APB2SMENR_SDMMC1SMEN_POS 10U +#define STM32_RCC_APB2SMENR_SDMMC1SMEN_MSK \ + (0x1UL << STM32_RCC_APB2SMENR_SDMMC1SMEN_POS) +#define STM32_RCC_APB2SMENR_SDMMC1SMEN STM32_RCC_APB2SMENR_SDMMC1SMEN_MSK +#define STM32_RCC_APB2SMENR_TIM1SMEN_POS 11U +#define STM32_RCC_APB2SMENR_TIM1SMEN_MSK \ + (0x1UL << STM32_RCC_APB2SMENR_TIM1SMEN_POS) +#define STM32_RCC_APB2SMENR_TIM1SMEN STM32_RCC_APB2SMENR_TIM1SMEN_MSK +#define STM32_RCC_APB2SMENR_SPI1SMEN_POS 12U +#define STM32_RCC_APB2SMENR_SPI1SMEN_MSK \ + (0x1UL << STM32_RCC_APB2SMENR_SPI1SMEN_POS) +#define STM32_RCC_APB2SMENR_SPI1SMEN STM32_RCC_APB2SMENR_SPI1SMEN_MSK +#define STM32_RCC_APB2SMENR_USART1SMEN_POS 14U +#define STM32_RCC_APB2SMENR_USART1SMEN_MSK \ + (0x1UL << STM32_RCC_APB2SMENR_USART1SMEN_POS) +#define STM32_RCC_APB2SMENR_USART1SMEN STM32_RCC_APB2SMENR_USART1SMEN_MSK +#define STM32_RCC_APB2SMENR_TIM15SMEN_POS 16U +#define STM32_RCC_APB2SMENR_TIM15SMEN_MSK \ + (0x1UL << STM32_RCC_APB2SMENR_TIM15SMEN_POS) +#define STM32_RCC_APB2SMENR_TIM15SMEN STM32_RCC_APB2SMENR_TIM15SMEN_MSK +#define STM32_RCC_APB2SMENR_TIM16SMEN_POS 17U +#define STM32_RCC_APB2SMENR_TIM16SMEN_MSK \ + (0x1UL << STM32_RCC_APB2SMENR_TIM16SMEN_POS) +#define STM32_RCC_APB2SMENR_TIM16SMEN STM32_RCC_APB2SMENR_TIM16SMEN_MSK +#define STM32_RCC_APB2SMENR_SAI1SMEN_POS 21U +#define STM32_RCC_APB2SMENR_SAI1SMEN_MSK \ + (0x1UL << STM32_RCC_APB2SMENR_SAI1SMEN_POS) +#define STM32_RCC_APB2SMENR_SAI1SMEN STM32_RCC_APB2SMENR_SAI1SMEN_MSK + +/************* BIT DEFINITION FOR STM32_RCC_CCIPR REGISTER ******************/ +#define STM32_RCC_CCIPR_USART1SEL_POS 0U +#define STM32_RCC_CCIPR_USART1SEL_MSK (0x3UL << STM32_RCC_CCIPR_USART1SEL_POS) +#define STM32_RCC_CCIPR_USART1SEL STM32_RCC_CCIPR_USART1SEL_MSK +#define STM32_RCC_CCIPR_USART1SEL_0 (0x1UL << STM32_RCC_CCIPR_USART1SEL_POS) +#define STM32_RCC_CCIPR_USART1SEL_1 (0x2UL << STM32_RCC_CCIPR_USART1SEL_POS) + +#define STM32_RCC_CCIPR_USART2SEL_POS 2U +#define STM32_RCC_CCIPR_USART2SEL_MSK (0x3UL << STM32_RCC_CCIPR_USART2SEL_POS) +#define STM32_RCC_CCIPR_USART2SEL STM32_RCC_CCIPR_USART2SEL_MSK +#define STM32_RCC_CCIPR_USART2SEL_0 (0x1UL << STM32_RCC_CCIPR_USART2SEL_POS) +#define STM32_RCC_CCIPR_USART2SEL_1 (0x2UL << STM32_RCC_CCIPR_USART2SEL_POS) + +#define STM32_RCC_CCIPR_USART3SEL_POS 4U +#define STM32_RCC_CCIPR_USART3SEL_MSK (0x3UL << STM32_RCC_CCIPR_USART3SEL_POS) +#define STM32_RCC_CCIPR_USART3SEL STM32_RCC_CCIPR_USART3SEL_MSK +#define STM32_RCC_CCIPR_USART3SEL_0 (0x1UL << STM32_RCC_CCIPR_USART3SEL_POS) +#define STM32_RCC_CCIPR_USART3SEL_1 (0x2UL << STM32_RCC_CCIPR_USART3SEL_POS) + +#define STM32_RCC_CCIPR_LPUART1SEL_POS 10U +#define STM32_RCC_CCIPR_LPUART1SEL_MSK (0x3UL << STM32_RCC_CCIPR_LPUART1SEL_POS) +#define STM32_RCC_CCIPR_LPUART1SEL STM32_RCC_CCIPR_LPUART1SEL_MSK +#define STM32_RCC_CCIPR_LPUART1SEL_0 (0x1UL << STM32_RCC_CCIPR_LPUART1SEL_POS) +#define STM32_RCC_CCIPR_LPUART1SEL_1 (0x2UL << STM32_RCC_CCIPR_LPUART1SEL_POS) + +#define STM32_RCC_CCIPR_I2C1SEL_POS 12U +#define STM32_RCC_CCIPR_I2C1SEL_MSK (0x3UL << STM32_RCC_CCIPR_I2C1SEL_POS) +#define STM32_RCC_CCIPR_I2C1SEL STM32_RCC_CCIPR_I2C1SEL_MSK +#define STM32_RCC_CCIPR_I2C1SEL_0 (0x1UL << STM32_RCC_CCIPR_I2C1SEL_POS) +#define STM32_RCC_CCIPR_I2C1SEL_1 (0x2UL << STM32_RCC_CCIPR_I2C1SEL_POS) + +#define STM32_RCC_CCIPR_I2C2SEL_POS 14U +#define STM32_RCC_CCIPR_I2C2SEL_MSK (0x3UL << STM32_RCC_CCIPR_I2C2SEL_POS) +#define STM32_RCC_CCIPR_I2C2SEL STM32_RCC_CCIPR_I2C2SEL_MSK +#define STM32_RCC_CCIPR_I2C2SEL_0 (0x1UL << STM32_RCC_CCIPR_I2C2SEL_POS) +#define STM32_RCC_CCIPR_I2C2SEL_1 (0x2UL << STM32_RCC_CCIPR_I2C2SEL_POS) + +#define STM32_RCC_CCIPR_I2C3SEL_POS 16U +#define STM32_RCC_CCIPR_I2C3SEL_MSK (0x3UL << STM32_RCC_CCIPR_I2C3SEL_POS) +#define STM32_RCC_CCIPR_I2C3SEL STM32_RCC_CCIPR_I2C3SEL_MSK +#define STM32_RCC_CCIPR_I2C3SEL_0 (0x1UL << STM32_RCC_CCIPR_I2C3SEL_POS) +#define STM32_RCC_CCIPR_I2C3SEL_1 (0x2UL << STM32_RCC_CCIPR_I2C3SEL_POS) + +#define STM32_RCC_CCIPR_LPTIM1SEL_POS 18U +#define STM32_RCC_CCIPR_LPTIM1SEL_MSK (0x3UL << STM32_RCC_CCIPR_LPTIM1SEL_POS) +#define STM32_RCC_CCIPR_LPTIM1SEL STM32_RCC_CCIPR_LPTIM1SEL_MSK +#define STM32_RCC_CCIPR_LPTIM1SEL_0 (0x1UL << STM32_RCC_CCIPR_LPTIM1SEL_POS) +#define STM32_RCC_CCIPR_LPTIM1SEL_1 (0x2UL << STM32_RCC_CCIPR_LPTIM1SEL_POS) + +#define STM32_RCC_CCIPR_LPTIM2SEL_POS 20U +#define STM32_RCC_CCIPR_LPTIM2SEL_MSK (0x3UL << STM32_RCC_CCIPR_LPTIM2SEL_POS) +#define STM32_RCC_CCIPR_LPTIM2SEL STM32_RCC_CCIPR_LPTIM2SEL_MSK +#define STM32_RCC_CCIPR_LPTIM2SEL_0 (0x1UL << STM32_RCC_CCIPR_LPTIM2SEL_POS) +#define STM32_RCC_CCIPR_LPTIM2SEL_1 (0x2UL << STM32_RCC_CCIPR_LPTIM2SEL_POS) + +#define STM32_RCC_CCIPR_SAI1SEL_POS 22U +#define STM32_RCC_CCIPR_SAI1SEL_MSK (0x3UL << STM32_RCC_CCIPR_SAI1SEL_POS) +#define STM32_RCC_CCIPR_SAI1SEL STM32_RCC_CCIPR_SAI1SEL_MSK +#define STM32_RCC_CCIPR_SAI1SEL_0 (0x1UL << STM32_RCC_CCIPR_SAI1SEL_POS) +#define STM32_RCC_CCIPR_SAI1SEL_1 (0x2UL << STM32_RCC_CCIPR_SAI1SEL_POS) + +#define STM32_RCC_CCIPR_CLK48SEL_POS 26U +#define STM32_RCC_CCIPR_CLK48SEL_MSK (0x3UL << STM32_RCC_CCIPR_CLK48SEL_POS) +#define STM32_RCC_CCIPR_CLK48SEL STM32_RCC_CCIPR_CLK48SEL_MSK +#define STM32_RCC_CCIPR_CLK48SEL_0 (0x1UL << STM32_RCC_CCIPR_CLK48SEL_POS) +#define STM32_RCC_CCIPR_CLK48SEL_1 (0x2UL << STM32_RCC_CCIPR_CLK48SEL_POS) + +#define STM32_RCC_CCIPR_ADCSEL_POS 28U +#define STM32_RCC_CCIPR_ADCSEL_MSK (0x3UL << STM32_RCC_CCIPR_ADCSEL_POS) +#define STM32_RCC_CCIPR_ADCSEL STM32_RCC_CCIPR_ADCSEL_MSK +#define STM32_RCC_CCIPR_ADCSEL_0 (0x1UL << STM32_RCC_CCIPR_ADCSEL_POS) +#define STM32_RCC_CCIPR_ADCSEL_1 (0x2UL << STM32_RCC_CCIPR_ADCSEL_POS) + +#define STM32_RCC_CCIPR_SWPMI1SEL_POS 30U +#define STM32_RCC_CCIPR_SWPMI1SEL_MSK (0x1UL << STM32_RCC_CCIPR_SWPMI1SEL_POS) +#define STM32_RCC_CCIPR_SWPMI1SEL STM32_RCC_CCIPR_SWPMI1SEL_MSK + +/************** BIT DEFINITION FOR STM32_RCC_BDCR REGISTER ******************/ +#define STM32_RCC_BDCR_LSEBYP_POS 2U +#define STM32_RCC_BDCR_LSEBYP_MSK (0x1UL << STM32_RCC_BDCR_LSEBYP_POS) +#define STM32_RCC_BDCR_LSEBYP STM32_RCC_BDCR_LSEBYP_MSK + +#define STM32_RCC_BDCR_LSEDRV_POS 3U +#define STM32_RCC_BDCR_LSEDRV_MSK (0x3UL << STM32_RCC_BDCR_LSEDRV_POS) +#define STM32_RCC_BDCR_LSEDRV STM32_RCC_BDCR_LSEDRV_MSK +#define STM32_RCC_BDCR_LSEDRV_0 (0x1UL << STM32_RCC_BDCR_LSEDRV_POS) +#define STM32_RCC_BDCR_LSEDRV_1 (0x2UL << STM32_RCC_BDCR_LSEDRV_POS) + +#define STM32_RCC_BDCR_LSECSSON_POS 5U +#define STM32_RCC_BDCR_LSECSSON_MSK (0x1UL << STM32_RCC_BDCR_LSECSSON_POS) +#define STM32_RCC_BDCR_LSECSSON STM32_RCC_BDCR_LSECSSON_MSK +#define STM32_RCC_BDCR_LSECSSD_POS 6U +#define STM32_RCC_BDCR_LSECSSD_MSK (0x1UL << STM32_RCC_BDCR_LSECSSD_POS) +#define STM32_RCC_BDCR_LSECSSD STM32_RCC_BDCR_LSECSSD_MSK + +#define STM32_RCC_BDCR_RTCSEL_POS 8U +#define STM32_RCC_BDCR_RTCSEL_MSK (0x3UL << STM32_RCC_BDCR_RTCSEL_POS) +#define STM32_RCC_BDCR_RTCSEL STM32_RCC_BDCR_RTCSEL_MSK +#define STM32_RCC_BDCR_RTCSEL_0 (0x1UL << STM32_RCC_BDCR_RTCSEL_POS) +#define STM32_RCC_BDCR_RTCSEL_1 (0x2UL << STM32_RCC_BDCR_RTCSEL_POS) + +#define STM32_RCC_BDCR_LSCOEN_POS 24U +#define STM32_RCC_BDCR_LSCOEN_MSK (0x1UL << STM32_RCC_BDCR_LSCOEN_POS) +#define STM32_RCC_BDCR_LSCOEN STM32_RCC_BDCR_LSCOEN_MSK +#define STM32_RCC_BDCR_LSCOSEL_POS 25U +#define STM32_RCC_BDCR_LSCOSEL_MSK (0x1UL << STM32_RCC_BDCR_LSCOSEL_POS) +#define STM32_RCC_BDCR_LSCOSEL STM32_RCC_BDCR_LSCOSEL_MSK + +/************** BIT DEFINITION FOR STM32_RCC_CSR REGISTER *******************/ +#define STM32_RCC_CSR_LSION_POS 0U +#define STM32_RCC_CSR_LSION_MSK (0x1UL << STM32_RCC_CSR_LSION_POS) +#define STM32_RCC_CSR_LSION STM32_RCC_CSR_LSION_MSK +#define STM32_RCC_CSR_LSIRDY_POS 1U +#define STM32_RCC_CSR_LSIRDY_MSK (0x1UL << STM32_RCC_CSR_LSIRDY_POS) +#define STM32_RCC_CSR_LSIRDY STM32_RCC_CSR_LSIRDY_MSK + +#define STM32_RCC_CSR_MSISRANGE_POS 8U +#define STM32_RCC_CSR_MSISRANGE_MSK (0xFUL << STM32_RCC_CSR_MSISRANGE_POS) +#define STM32_RCC_CSR_MSISRANGE STM32_RCC_CSR_MSISRANGE_MSK +#define STM32_RCC_CSR_MSISRANGE_1 (0x4UL << STM32_RCC_CSR_MSISRANGE_POS) +#define STM32_RCC_CSR_MSISRANGE_2 (0x5UL << STM32_RCC_CSR_MSISRANGE_POS) +#define STM32_RCC_CSR_MSISRANGE_4 (0x6UL << STM32_RCC_CSR_MSISRANGE_POS) +#define STM32_RCC_CSR_MSISRANGE_8 (0x7UL << STM32_RCC_CSR_MSISRANGE_POS) + +#define STM32_RCC_CSR_RMVF_POS 23U +#define STM32_RCC_CSR_RMVF_MSK (0x1UL << STM32_RCC_CSR_RMVF_POS) +#define STM32_RCC_CSR_RMVF STM32_RCC_CSR_RMVF_MSK +#define STM32_RCC_CSR_FWRSTF_POS 24U +#define STM32_RCC_CSR_FWRSTF_MSK (0x1UL << STM32_RCC_CSR_FWRSTF_POS) +#define STM32_RCC_CSR_FWRSTF STM32_RCC_CSR_FWRSTF_MSK +#define STM32_RCC_CSR_OBLRSTF_POS 25U +#define STM32_RCC_CSR_OBLRSTF_MSK (0x1UL << STM32_RCC_CSR_OBLRSTF_POS) +#define STM32_RCC_CSR_OBLRSTF STM32_RCC_CSR_OBLRSTF_MSK +#define STM32_RCC_CSR_PINRSTF_POS 26U +#define STM32_RCC_CSR_PINRSTF_MSK (0x1UL << STM32_RCC_CSR_PINRSTF_POS) +#define STM32_RCC_CSR_PINRSTF STM32_RCC_CSR_PINRSTF_MSK +#define STM32_RCC_CSR_BORRSTF_POS 27U +#define STM32_RCC_CSR_BORRSTF_MSK (0x1UL << STM32_RCC_CSR_BORRSTF_POS) +#define STM32_RCC_CSR_BORRSTF STM32_RCC_CSR_BORRSTF_MSK +#define STM32_RCC_CSR_SFTRSTF_POS 28U +#define STM32_RCC_CSR_SFTRSTF_MSK (0x1UL << STM32_RCC_CSR_SFTRSTF_POS) +#define STM32_RCC_CSR_SFTRSTF STM32_RCC_CSR_SFTRSTF_MSK +#define STM32_RCC_CSR_IWDGRSTF_POS 29U +#define STM32_RCC_CSR_IWDGRSTF_MSK (0x1UL << STM32_RCC_CSR_IWDGRSTF_POS) +#define STM32_RCC_CSR_IWDGRSTF STM32_RCC_CSR_IWDGRSTF_MSK +#define STM32_RCC_CSR_WWDGRSTF_POS 30U +#define STM32_RCC_CSR_WWDGRSTF_MSK (0x1UL << STM32_RCC_CSR_WWDGRSTF_POS) +#define STM32_RCC_CSR_WWDGRSTF STM32_RCC_CSR_WWDGRSTF_MSK +#define STM32_RCC_CSR_LPWRRSTF_POS 31U +#define STM32_RCC_CSR_LPWRRSTF_MSK (0x1UL << STM32_RCC_CSR_LPWRRSTF_POS) +#define STM32_RCC_CSR_LPWRRSTF STM32_RCC_CSR_LPWRRSTF_MSK + +/************** Bit definition for STM32_RCC_CRRCR register *****************/ +#define STM32_RCC_CRRCR_HSI48ON_POS 0U +#define STM32_RCC_CRRCR_HSI48ON_MSK (0x1UL << STM32_RCC_CRRCR_HSI48ON_POS) +#define STM32_RCC_CRRCR_HSI48ON STM32_RCC_CRRCR_HSI48ON_MSK +#define STM32_RCC_CRRCR_HSI48RDY_POS 1U +#define STM32_RCC_CRRCR_HSI48RDY_MSK (0x1UL << STM32_RCC_CRRCR_HSI48RDY_POS) +#define STM32_RCC_CRRCR_HSI48RDY STM32_RCC_CRRCR_HSI48RDY_MSK + +/*!< HSI48CAL configuration */ +#define STM32_RCC_CRRCR_HSI48CAL_POS 7U +#define STM32_RCC_CRRCR_HSI48CAL_MSK (0x1FFUL << STM32_RCC_CRRCR_HSI48CAL_POS) +#define STM32_RCC_CRRCR_HSI48CAL STM32_RCC_CRRCR_HSI48CAL_MSK +#define STM32_RCC_CRRCR_HSI48CAL_0 (0x001UL << STM32_RCC_CRRCR_HSI48CAL_POS) +#define STM32_RCC_CRRCR_HSI48CAL_1 (0x002UL << STM32_RCC_CRRCR_HSI48CAL_POS) +#define STM32_RCC_CRRCR_HSI48CAL_2 (0x004UL << STM32_RCC_CRRCR_HSI48CAL_POS) +#define STM32_RCC_CRRCR_HSI48CAL_3 (0x008UL << STM32_RCC_CRRCR_HSI48CAL_POS) +#define STM32_RCC_CRRCR_HSI48CAL_4 (0x010UL << STM32_RCC_CRRCR_HSI48CAL_POS) +#define STM32_RCC_CRRCR_HSI48CAL_5 (0x020UL << STM32_RCC_CRRCR_HSI48CAL_POS) +#define STM32_RCC_CRRCR_HSI48CAL_6 (0x040UL << STM32_RCC_CRRCR_HSI48CAL_POS) +#define STM32_RCC_CRRCR_HSI48CAL_7 (0x080UL << STM32_RCC_CRRCR_HSI48CAL_POS) +#define STM32_RCC_CRRCR_HSI48CAL_8 (0x100UL << STM32_RCC_CRRCR_HSI48CAL_POS) + +#define STM32_SYSCFG_CFGR1 REG32(STM32_SYSCFG_BASE + 0x04) +#define STM32_SYSCFG_EXTICR(n) REG32(STM32_SYSCFG_BASE + 8 + 4 * (n)) +#define STM32_SYSCFG_I2CFMP(n) BIT(n + 21) + +/* Peripheral bits for STM32_RCC_APB/AHB and DBGMCU regs */ +#define STM32_RCC_PB1_PWREN BIT(28) + +#define STM32_RCC_PB2_SYSCFGEN BIT(0) +#define STM32_RCC_PB2_USART1 BIT(14) +#define STM32_RCC_HB1_DMA1 BIT(0) +#define STM32_RCC_HB1_DMA2 BIT(1) -/* Peripheral bits for RCC_APB/AHB and DBGMCU regs */ -#define STM32_RCC_PB2_USART1 BIT(14) +#define STM32_RCC_HB2_GPIOA BIT(0) +#define STM32_RCC_HB2_GPIOB BIT(1) +#define STM32_RCC_HB2_GPIOC BIT(2) +#define STM32_RCC_HB2_GPIOD BIT(3) +#define STM32_RCC_HB2_GPIOE BIT(4) +#define STM32_RCC_HB2_GPIOH BIT(7) +#define STM32_RCC_HB2_ADC1 BIT(13) /* Reset causes definitions */ /* Reset causes in RCC CSR register */ -#define STM32_RCC_RESET_CAUSE STM32_RCC_CSR +#define STM32_RCC_RESET_CAUSE STM32_RCC_CSR #define RESET_CAUSE_WDG 0x60000000 #define RESET_CAUSE_SFT 0x10000000 #define RESET_CAUSE_POR 0x08000000 #define RESET_CAUSE_PIN 0x04000000 -#define RESET_CAUSE_OTHER 0xfe000000 -#define RESET_CAUSE_RMVF 0x01000000 +#define RESET_CAUSE_OTHER 0xff000000 +#define RESET_CAUSE_RMVF BIT(23) /* Power cause in PWR CSR register */ -#define STM32_PWR_RESET_CAUSE STM32_PWR_CSR -#define STM32_PWR_RESET_CAUSE_CLR STM32_PWR_CR -#define RESET_CAUSE_SBF 0x00000002 -#define RESET_CAUSE_SBF_CLR 0x00000004 +#define STM32_PWR_RESET_CAUSE STM32_PWR_CSR +#define STM32_PWR_RESET_CAUSE_CLR STM32_PWR_SCR +#define RESET_CAUSE_SBF BIT(8) +#define RESET_CAUSE_SBF_CLR BIT(8) /* --- Watchdogs --- */ @@ -522,13 +1740,18 @@ #define STM32_RTC_CR REG32(STM32_RTC_BASE + 0x08) #define STM32_RTC_CR_BYPSHAD BIT(5) #define STM32_RTC_CR_ALRAE BIT(8) +#define STM32_RTC_CR_WUTE BIT(10) #define STM32_RTC_CR_ALRAIE BIT(12) +#define STM32_RTC_CR_WUTIE BIT(14) #define STM32_RTC_ISR REG32(STM32_RTC_BASE + 0x0C) #define STM32_RTC_ISR_ALRAWF BIT(0) +#define STM32_RTC_ISR_WUTWF BIT(2) +#define STM32_RTC_ISR_INITS BIT(4) #define STM32_RTC_ISR_RSF BIT(5) #define STM32_RTC_ISR_INITF BIT(6) #define STM32_RTC_ISR_INIT BIT(7) #define STM32_RTC_ISR_ALRAF BIT(8) +#define STM32_RTC_ISR_WUTF BIT(9) #define STM32_RTC_PRER REG32(STM32_RTC_BASE + 0x10) #define STM32_RTC_PRER_A_MASK (0x7f << 16) #define STM32_RTC_PRER_S_MASK (0x7fff << 0) @@ -544,9 +1767,37 @@ #define STM32_RTC_ALRMASSR REG32(STM32_RTC_BASE + 0x44) #define STM32_RTC_BACKUP(n) REG32(STM32_RTC_BASE + 0x50 + 4 * (n)) +#define STM32_RTC_CLEAR_FLAG(x) \ + (STM32_RTC_ISR = (~((x) | STM32_RTC_ISR_INIT) | \ + (STM32_RTC_ISR & STM32_RTC_ISR_INIT))) + #define STM32_BKP_DATA(n) STM32_RTC_BACKUP(n) #define STM32_BKP_BYTES 128 +#define RTC_TR_PM_POS 22U +#define RTC_TR_PM_MSK (0x1UL << RTC_TR_PM_POS) +#define RTC_TR_PM RTC_TR_PM_MSK +#define RTC_TR_HT_POS 20U +#define RTC_TR_HT_MSK (0x3UL << RTC_TR_HT_POS) +#define RTC_TR_HT RTC_TR_HT_MSK +#define RTC_TR_HU_POS 16U +#define RTC_TR_HU_MSK (0xFUL << RTC_TR_HU_POS) +#define RTC_TR_HU RTC_TR_HU_MSK +#define RTC_TR_MNT_POS 12U +#define RTC_TR_MNT_MSK (0x7UL << RTC_TR_MNT_POS) +#define RTC_TR_MNT RTC_TR_MNT_MSK +#define RTC_TR_MNU_POS 8U +#define RTC_TR_MNU_MSK (0xFUL << RTC_TR_MNU_POS) +#define RTC_TR_MNU RTC_TR_MNU_MSK +#define RTC_TR_ST_POS 4U +#define RTC_TR_ST_MSK (0x7UL << RTC_TR_ST_POS) +#define RTC_TR_ST RTC_TR_ST_MSK +#define RTC_TR_SU_POS 0U +#define RTC_TR_SU_MSK (0xFUL << RTC_TR_SU_POS) +#define RTC_TR_SU RTC_TR_SU_MSK + + + /* --- SPI --- */ /* The SPI controller registers */ @@ -555,15 +1806,15 @@ struct stm32_spi_regs { uint16_t _pad0; uint16_t cr2; uint16_t _pad1; - unsigned sr; + unsigned int sr; uint8_t dr; uint8_t _pad2; uint16_t _pad3; - unsigned crcpr; - unsigned rxcrcr; - unsigned txcrcr; - unsigned i2scfgr; /* STM32L only */ - unsigned i2spr; /* STM32L only */ + unsigned int crcpr; + unsigned int rxcrcr; + unsigned int txcrcr; + unsigned int i2scfgr; /* STM32L only */ + unsigned int i2spr; /* STM32L only */ }; /* Must be volatile, or compiler optimizes out repeated accesses */ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; @@ -654,11 +1905,71 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; #define STM32_EXTI_SWIER REG32(STM32_EXTI_BASE + 0x10) #define STM32_EXTI_PR REG32(STM32_EXTI_BASE + 0x14) +#define EXTI_RTC_ALR_EVENT BIT(18) /* --- ADC --- */ - -/* --- Comparators --- */ - +#define STM32_ADC1_ISR REG32(STM32_ADC1_BASE + 0x00) +#define STM32_ADC1_ISR_ADRDY BIT(0) +#define STM32_ADC1_IER REG32(STM32_ADC1_BASE + 0x04) +#define STM32_ADC1_IER_AWDIE BIT(7) +#define STM32_ADC1_IER_OVRIE BIT(4) +#define STM32_ADC1_IER_EOSEQIE BIT(3) +#define STM32_ADC1_IER_EOCIE BIT(2) +#define STM32_ADC1_IER_EOSMPIE BIT(1) +#define STM32_ADC1_IER_ADRDYIE BIT(0) + +#define STM32_ADC1_CR REG32(STM32_ADC1_BASE + 0x08) +#define STM32_ADC1_CR_ADEN BIT(0) +#define STM32_ADC1_CR_ADDIS BIT(1) +#define STM32_ADC1_CR_ADSTP BIT(4) +#define STM32_ADC1_CR_ADVREGEN BIT(28) +#define STM32_ADC1_CR_DEEPPWD BIT(29) +#define STM32_ADC1_CR_ADCAL BIT(31) +#define STM32_ADC1_CFGR REG32(STM32_ADC1_BASE + 0x0C) +/* Analog watchdog channel selection */ +#define STM32_ADC1_CFGR_AWDCH_MASK (0x1f << 26) +#define STM32_ADC1_CFGR_AWDEN BIT(23) +#define STM32_ADC1_CFGR_AWDSGL BIT(22) +#define STM32_ADC1_CFGR_AUTDLY BIT(14) +/* Selects single vs continuous */ +#define STM32_ADC1_CFGR_CONT BIT(13) +/* Selects ADC_DR overwrite vs preserve */ +#define STM32_ADC1_CFGR_OVRMOD BIT(12) +/* External trigger polarity selection */ +#define STM32_ADC1_CFGR_EXTEN_DIS (0 << 10) +#define STM32_ADC1_CFGR_EXTEN_RISE (1 << 10) +#define STM32_ADC1_CFGR_EXTEN_FALL (2 << 10) +#define STM32_ADC1_CFGR_EXTEN_BOTH (3 << 10) +#define STM32_ADC1_CFGR_EXTEN_MASK (3 << 10) +#define STM32_ADC1_CFGR_ALIGN BIT(5) +/* External trigger selection */ +#define STM32_ADC1_CFGR_TRG0 (0 << 6) +#define STM32_ADC1_CFGR_TRG1 (1 << 6) +#define STM32_ADC1_CFGR_TRG2 (2 << 6) +#define STM32_ADC1_CFGR_TRG3 (3 << 6) +#define STM32_ADC1_CFGR_TRG4 (4 << 6) +#define STM32_ADC1_CFGR_TRG5 (5 << 6) +#define STM32_ADC1_CFGR_TRG6 (6 << 6) +#define STM32_ADC1_CFGR_TRG7 (7 << 6) +#define STM32_ADC1_CFGR_TRG_MASK (7 << 6) +/* Selects circular vs one-shot */ +#define STM32_ADC1_CFGR_DMACFG BIT(1) +#define STM32_ADC1_CFGR_DMAEN BIT(0) +#define STM32_ADC1_CFGR2 REG32(STM32_ADC1_BASE + 0x10) +/* Sampling time selection - 1.5 ADC cycles min, 239.5 cycles max */ +#define STM32_ADC1_SMPR1 REG32(STM32_ADC1_BASE + 0x14) +#define STM32_ADC1_SMPR2 REG32(STM32_ADC1_BASE + 0x18) +/* Macro to convert enum stm32_adc_smpr to SMP bits of the ADC_SMPR register */ +#define STM32_ADC1_SMPR_SMP(s) ((s) - 1) +#define STM32_ADC1_TR REG32(STM32_ADC1_BASE + 0x20) +#define STM32_ADC1_CHSELR REG32(STM32_ADC1_BASE + 0x28) +#define STM32_ADC1_DR REG32(STM32_ADC1_BASE + 0x40) +#define STM32_ADC1_JSQR REG32(STM32_ADC1_BASE + 0x4C) +#define STM32_ADC1_JDR1 REG32(STM32_ADC1_BASE + 0x80) +#define STM32_ADC1_JDR2 REG32(STM32_ADC1_BASE + 0x84) +#define STM32_ADC1_JDR3 REG32(STM32_ADC1_BASE + 0x88) +#define STM32_ADC1_JDR4 REG32(STM32_ADC1_BASE + 0x8C) +#define STM32_ADC1_CCR REG32(STM32_ADC1_BASE + 0x308) /* --- DMA --- */ @@ -692,28 +2003,18 @@ enum dma_channel { STM32_DMAC_CH12 = 11, STM32_DMAC_CH13 = 12, STM32_DMAC_CH14 = 13, + STM32_DMAC_CH15 = 14, /* Channel functions */ - STM32_DMAC_ADC = STM32_DMAC_CH1, STM32_DMAC_SPI1_RX = STM32_DMAC_CH2, STM32_DMAC_SPI1_TX = STM32_DMAC_CH3, - STM32_DMAC_DAC_CH1 = STM32_DMAC_CH2, - STM32_DMAC_DAC_CH2 = STM32_DMAC_CH3, - STM32_DMAC_I2C2_TX = STM32_DMAC_CH4, - STM32_DMAC_I2C2_RX = STM32_DMAC_CH5, - STM32_DMAC_USART1_TX = STM32_DMAC_CH4, - STM32_DMAC_USART1_RX = STM32_DMAC_CH5, - STM32_DMAC_USART2_RX = STM32_DMAC_CH6, - STM32_DMAC_USART2_TX = STM32_DMAC_CH7, - STM32_DMAC_I2C1_TX = STM32_DMAC_CH6, - STM32_DMAC_I2C1_RX = STM32_DMAC_CH7, - STM32_DMAC_PMSE_ROW = STM32_DMAC_CH6, - STM32_DMAC_PMSE_COL = STM32_DMAC_CH7, + STM32_DMAC_USART1_TX = STM32_DMAC_CH14, + STM32_DMAC_USART1_RX = STM32_DMAC_CH15, STM32_DMAC_SPI2_RX = STM32_DMAC_CH4, STM32_DMAC_SPI2_TX = STM32_DMAC_CH5, STM32_DMAC_SPI3_RX = STM32_DMAC_CH9, STM32_DMAC_SPI3_TX = STM32_DMAC_CH10, - STM32_DMAC_COUNT = 14, + STM32_DMAC_COUNT = 15, }; #define STM32_DMAC_PER_CTLR 8 @@ -809,124 +2110,5 @@ typedef volatile struct stm32_dma_regs stm32_dma_regs_t; #define STM32_DMA_CCR_PL_VERY_HIGH (3 << 12) #define STM32_DMA_CCR_MEM2MEM BIT(14) - -/* --- CRC --- */ -#define STM32_CRC_DR REG32(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR32 REG32(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR16 REG16(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR8 REG8(STM32_CRC_BASE + 0x0) - -#define STM32_CRC_IDR REG32(STM32_CRC_BASE + 0x4) -#define STM32_CRC_CR REG32(STM32_CRC_BASE + 0x8) -#define STM32_CRC_INIT REG32(STM32_CRC_BASE + 0x10) -#define STM32_CRC_POL REG32(STM32_CRC_BASE + 0x14) - -#define STM32_CRC_CR_RESET BIT(0) -#define STM32_CRC_CR_POLYSIZE_32 (0 << 3) -#define STM32_CRC_CR_POLYSIZE_16 (1 << 3) -#define STM32_CRC_CR_POLYSIZE_8 (2 << 3) -#define STM32_CRC_CR_POLYSIZE_7 (3 << 3) -#define STM32_CRC_CR_REV_IN_BYTE (1 << 5) -#define STM32_CRC_CR_REV_IN_HWORD (2 << 5) -#define STM32_CRC_CR_REV_IN_WORD (3 << 5) -#define STM32_CRC_CR_REV_OUT BIT(7) - -/* --- USB --- */ -#define STM32_USB_EP(n) REG16(STM32_USB_FS_BASE + (n) * 4) - -#define STM32_USB_CNTR REG16(STM32_USB_FS_BASE + 0x40) - -#define STM32_USB_CNTR_FRES BIT(0) -#define STM32_USB_CNTR_PDWN BIT(1) -#define STM32_USB_CNTR_LP_MODE BIT(2) -#define STM32_USB_CNTR_FSUSP BIT(3) -#define STM32_USB_CNTR_RESUME BIT(4) -#define STM32_USB_CNTR_L1RESUME BIT(5) -#define STM32_USB_CNTR_L1REQM BIT(7) -#define STM32_USB_CNTR_ESOFM BIT(8) -#define STM32_USB_CNTR_SOFM BIT(9) -#define STM32_USB_CNTR_RESETM BIT(10) -#define STM32_USB_CNTR_SUSPM BIT(11) -#define STM32_USB_CNTR_WKUPM BIT(12) -#define STM32_USB_CNTR_ERRM BIT(13) -#define STM32_USB_CNTR_PMAOVRM BIT(14) -#define STM32_USB_CNTR_CTRM BIT(15) - -#define STM32_USB_ISTR REG16(STM32_USB_FS_BASE + 0x44) - -#define STM32_USB_ISTR_EP_ID_MASK (0x000f) -#define STM32_USB_ISTR_DIR BIT(4) -#define STM32_USB_ISTR_L1REQ BIT(7) -#define STM32_USB_ISTR_ESOF BIT(8) -#define STM32_USB_ISTR_SOF BIT(9) -#define STM32_USB_ISTR_RESET BIT(10) -#define STM32_USB_ISTR_SUSP BIT(11) -#define STM32_USB_ISTR_WKUP BIT(12) -#define STM32_USB_ISTR_ERR BIT(13) -#define STM32_USB_ISTR_PMAOVR BIT(14) -#define STM32_USB_ISTR_CTR BIT(15) - -#define STM32_USB_FNR REG16(STM32_USB_FS_BASE + 0x48) - -#define STM32_USB_FNR_RXDP_RXDM_SHIFT (14) -#define STM32_USB_FNR_RXDP_RXDM_MASK (3 << STM32_USB_FNR_RXDP_RXDM_SHIFT) - -#define STM32_USB_DADDR REG16(STM32_USB_FS_BASE + 0x4C) -#define STM32_USB_BTABLE REG16(STM32_USB_FS_BASE + 0x50) -#define STM32_USB_LPMCSR REG16(STM32_USB_FS_BASE + 0x54) -#define STM32_USB_BCDR REG16(STM32_USB_FS_BASE + 0x58) - -#define STM32_USB_BCDR_BCDEN BIT(0) -#define STM32_USB_BCDR_DCDEN BIT(1) -#define STM32_USB_BCDR_PDEN BIT(2) -#define STM32_USB_BCDR_SDEN BIT(3) -#define STM32_USB_BCDR_DCDET BIT(4) -#define STM32_USB_BCDR_PDET BIT(5) -#define STM32_USB_BCDR_SDET BIT(6) -#define STM32_USB_BCDR_PS2DET BIT(7) - -#define EP_MASK 0x0F0F -#define EP_TX_DTOG 0x0040 -#define EP_TX_MASK 0x0030 -#define EP_TX_VALID 0x0030 -#define EP_TX_NAK 0x0020 -#define EP_TX_STALL 0x0010 -#define EP_TX_DISAB 0x0000 -#define EP_RX_DTOG 0x4000 -#define EP_RX_MASK 0x3000 -#define EP_RX_VALID 0x3000 -#define EP_RX_NAK 0x2000 -#define EP_RX_STALL 0x1000 -#define EP_RX_DISAB 0x0000 - -#define EP_STATUS_OUT 0x0100 - -#define EP_TX_RX_MASK (EP_TX_MASK | EP_RX_MASK) -#define EP_TX_RX_VALID (EP_TX_VALID | EP_RX_VALID) - -#define STM32_TOGGLE_EP(n, mask, val, flags) \ - STM32_USB_EP(n) = (((STM32_USB_EP(n) & (EP_MASK | (mask))) \ - ^ (val)) | (flags)) - -/* --- TRNG --- */ -#define STM32_RNG_CR REG32(STM32_RNG_BASE + 0x0) -#define STM32_RNG_CR_RNGEN BIT(2) -#define STM32_RNG_CR_IE BIT(3) -#define STM32_RNG_CR_CED BIT(5) -#define STM32_RNG_SR REG32(STM32_RNG_BASE + 0x4) -#define STM32_RNG_SR_DRDY BIT(0) -#define STM32_RNG_DR REG32(STM32_RNG_BASE + 0x8) - -/* --- AXI interconnect --- */ - -/* STM32H7: AXI_TARGx_FN_MOD exists for masters x = 1, 2 and 7 */ -#define STM32_AXI_TARG_FN_MOD(x) REG32(STM32_GPV_BASE + 0x1108 + \ - 0x1000 * (x)) -#define WRITE_ISS_OVERRIDE BIT(1) -#define READ_ISS_OVERRIDE BIT(0) - -/* --- MISC --- */ -#define STM32_UNIQUE_ID_ADDRESS REG32_ADDR(STM32_UNIQUE_ID_BASE) -#define STM32_UNIQUE_ID_LENGTH (3 * 4) - #endif /* !__ASSEMBLER__ */ + diff --git a/chip/stm32/system.c b/chip/stm32/system.c index 1f5f9c9108..8d63ba8567 100644 --- a/chip/stm32/system.c +++ b/chip/stm32/system.c @@ -168,11 +168,20 @@ void chip_pre_init(void) STM32_RCC_PB2_TIM1 | STM32_RCC_PB2_TIM8 | STM32_RCC_PB2_TIM9 | STM32_RCC_PB2_TIM10 | STM32_RCC_PB2_TIM11; #elif defined(CHIP_FAMILY_STM32L4) + +#ifdef CHIP_VARIANT_STM32L431X + apb1fz_reg = + STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM7 | STM32_RCC_PB1_TIM6 | + STM32_RCC_PB1_WWDG | STM32_RCC_PB1_IWDG; + apb2fz_reg = + STM32_RCC_PB2_TIM1 | STM32_RCC_PB2_TIM15 | STM32_RCC_PB2_TIM16; +#else apb1fz_reg = STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM3 | STM32_RCC_PB1_TIM4 | STM32_RCC_PB1_TIM5 | STM32_RCC_PB1_TIM6 | STM32_RCC_PB1_TIM7 | STM32_RCC_PB1_WWDG | STM32_RCC_PB1_IWDG; apb2fz_reg = STM32_RCC_PB2_TIM1 | STM32_RCC_PB2_TIM8; +#endif #elif defined(CHIP_FAMILY_STM32L) apb1fz_reg = STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM3 | STM32_RCC_PB1_TIM4 | @@ -254,14 +263,21 @@ void system_pre_init(void) /* enable clock on Power module */ #ifndef CHIP_FAMILY_STM32H7 +#ifdef CHIP_FAMILY_STM32L4 + STM32_RCC_APB1ENR1 |= STM32_RCC_PWREN; +#else STM32_RCC_APB1ENR |= STM32_RCC_PWREN; #endif +#endif #if defined(CHIP_FAMILY_STM32F4) /* enable backup registers */ STM32_RCC_AHB1ENR |= STM32_RCC_AHB1ENR_BKPSRAMEN; #elif defined(CHIP_FAMILY_STM32H7) /* enable backup registers */ STM32_RCC_AHB4ENR |= BIT(28); +#elif defined(CHIP_FAMILY_STM32L4) + /* enable RTC APB clock */ + STM32_RCC_APB1ENR1 |= STM32_RCC_APB1ENR1_RTCAPBEN; #else /* enable backup registers */ STM32_RCC_APB1ENR |= BIT(27); |