Cr50: I2CS TPM: Ensure HW read fifo is empty for register reads

This change is a safegaurd to ensure that TPM register data is always
placed in the correct location in the HW read I2CS fifo. It is only
checked for 1 or 4 byte regsiter reads. Because of the way in which a
TPM command is sent and the response is read, there are multiple reads
of the STS register prior to reading the TPM fifo register. Therefore
ensuring the fifo has zero depth when 1 or 4 byte regsiter reads,
improves the robustness of the design.

Added a counter to track the number of times the fifo is adjusted and
a new console command 'i2cs disp|rst' to display the count and reset
it to 0 if desired.

Removed section in code for TPM fifo register reads intended to handle
the case where there was a mismatch between how many bytes were copied
into the fifo and the number read by the host. Since the burstcount
field in the status register always contains a valid amount of data
that can be read by the host, there should not be cases where the
host reads less data than was copied from the TPM fifo register. In
the unexpected cases where the host may not drain all of the I2CS read
fifo data during a TPM register read, the I2CS fifo depth will be
corrected the next time that it reads either the access or STS
register which happens prior to the start of any TPM transaction.

BRANCH=none
BUG=chrome-os-partner:57338,chrome-os-partner:59191
TEST=manual
Booted Reef and verfied that TPM functionality is working.

Change-Id: I065a55e64bbcc0cb3357a2bd83447a05400b8899
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/382689
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>

2 files changed, 17 insertions, 5 deletions

diff --git a/chip/g/i2cs.c b/chip/g/i2cs.c
index 5c54af9d9d..38668ac932 100644
--- a/chip/g/i2cs.c
+++ b/chip/g/i2cs.c
@@ -290,7 +290,7 @@ int i2cs_register_write_complete_handler(wr_complete_handler_f wc_handler)
 	return 0;
 }
 
-size_t i2cs_get_read_fifo_buffer_depth(void)
+size_t i2cs_zero_read_fifo_buffer_depth(void)
 {
 	uint32_t hw_read_pointer;
 	size_t depth;
@@ -303,6 +303,15 @@ size_t i2cs_get_read_fifo_buffer_depth(void)
 	hw_read_pointer = GREAD(I2CS, READ_PTR) >> 3;
 	/* Determine the number of bytes buffered in the HW fifo */
 	depth = (last_read_pointer - hw_read_pointer) & REGISTER_FILE_MASK;
-
+	/*
+	 * If queue depth is not zero, force it to 0 by adjusting
+	 * last_read_pointer to where the hw read pointer is.
+	 */
+	if (depth)
+		last_read_pointer = (uint16_t)hw_read_pointer;
+	/*
+	 * Return number of bytes queued when this funciton is called so it can
+	 * be tracked or logged by caller if desired.
+	 */
 	return depth;
 }
diff --git a/chip/g/i2cs.h b/chip/g/i2cs.h
index 76e8117be0..809e4127a0 100644
--- a/chip/g/i2cs.h
+++ b/chip/g/i2cs.h
@@ -31,11 +31,14 @@ void i2cs_post_read_data(uint8_t byte_to_read);
 void i2cs_set_pinmux(void);
 
 /*
- * Determine the number of bytes currently buffered in the I2CS READ fifo. This
+ * Ensure no bytes are currently buffered in the I2CS READ fifo. This
  * value is calculated by finding the difference between read pointer that's
- * used by FW to add bytes to the HW fifo and the HW's read pointer.
+ * used by FW to add bytes to the HW fifo and the current value of the
+ * I2CS_READ_PTR register.
+ *
+ * @returns: the number of bytes buffered when the function is called
  */
-size_t i2cs_get_read_fifo_buffer_depth(void);
+size_t i2cs_zero_read_fifo_buffer_depth(void);
 
 /*
  * Write buffer of data into the I2CS HW read fifo. The function will operate a