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| author | Jack Rosenthal <jrosenth@chromium.org> | 2022-07-06 11:43:43 -0600 |
|---|---|---|
| committer | Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> | 2022-07-07 04:55:41 +0000 |
| commit | 6f02a2dcc9b8443b4a48022e605f191939d3e25d (patch) | |
| tree | f522b8d40f5ebbb6f3a116b1bdcb2e0a34c008d9 /chip | |
| parent | 1d52e542f10884962f238080eaf227c6e7278078 (diff) | |
| download | chrome-ec-6f02a2dcc9b8443b4a48022e605f191939d3e25d.tar.gz | |
chip/stm32/usart-stm32l5.c: Format with clang-format
BUG=b:236386294
BRANCH=none
TEST=none
Tricium: disable
Change-Id: I5d2cc33dd442535ebf84e316993c4bd6b67950ed
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749464
Reviewed-by: Jeremy Bettis <jbettis@chromium.org>
Diffstat (limited to 'chip')
| -rw-r--r-- | chip/stm32/usart-stm32l5.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/chip/stm32/usart-stm32l5.c b/chip/stm32/usart-stm32l5.c index 3a8db09202..73f0c3c3cb 100644 --- a/chip/stm32/usart-stm32l5.c +++ b/chip/stm32/usart-stm32l5.c @@ -169,12 +169,12 @@ DECLARE_IRQ(STM32_IRQ_USART5, usart5_interrupt, 2); #if defined(CONFIG_STREAM_USART9) struct usart_hw_config const usart9_hw = { - .index = 5, - .base = STM32_USART9_BASE, - .irq = STM32_IRQ_USART9, + .index = 5, + .base = STM32_USART9_BASE, + .irq = STM32_IRQ_USART9, .clock_register = &STM32_RCC_APB1ENR2, - .clock_enable = STM32_RCC_APB1ENR2_LPUART1EN, - .ops = &usart_variant_hw_ops, + .clock_enable = STM32_RCC_APB1ENR2_LPUART1EN, + .ops = &usart_variant_hw_ops, }; static void usart9_interrupt(void) |