npcx7: Set the erase size to 64 KiB

The NPCX flash layout was setting the erase size based on RO image size
to ensure the host can erase the entire image using.

When 1/2 flash is smaller than code RAM, the NPCX reserves one 4 KiB
flash block for the NPCX header. This has the side effect of reducing
the erase block size from 64 KiB to 4 KiB, and introduces a boot time
regression when processing flash blocks.

CL:2325764 modified the common flash support to allow the host to
program up to CONFIG_WP_STORAGE_SIZE bytes for the RO image and
CONFIG_EC_WRITABLE_STORAGE_SIZE bytes for the RW image.

Set the erase size to a fixed value of 64 KiB, with build checks
to verify the total flash size is a multiple of 64 KiB.

Both the RO and RW image starting addresses are already aligned to at
least a 64 KiB boundary, so there is no impact when the RW firmware
is upgraded.

BUG=b:175115527
BRANCH=volteer
TEST=make buildall
TEST=Boot EC on Delbin with NPCX797FC
TEST=Increase the RW image size to 0x3ed1c (maximum is 0x3F000) and
verify EC software sync is successful at updating the image.

Signed-off-by: Keith Short <keithshort@chromium.org>
Change-Id: I8823da2b909dfa36646b411a146001c618ce0e8c
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2643579
Reviewed-by: caveh jalali <caveh@chromium.org>
Commit-Queue: caveh jalali <caveh@chromium.org>

1 files changed, 24 insertions, 15 deletions

diff --git a/chip/npcx/config_flash_layout.h b/chip/npcx/config_flash_layout.h
index c45f4c53fd..79961548c9 100644
--- a/chip/npcx/config_flash_layout.h
+++ b/chip/npcx/config_flash_layout.h
@@ -91,24 +91,33 @@
 #endif
 
 /*
- * CONFIG_FLASH_ERASE_SIZE is set to maximum possible out of 64k, 32k and 4k
- * depending upon alignment of CONFIG_RO_SIZE. There are two assumptions here:
- * 1. CONFIG_RO_MEM_OFF is always 0 i.e. RO starts at 0.
- * 2. CONFIG_RO_SIZE and CONFIG_RW_SIZE are the same.
+ * The common flash support requires that the CONFIG_WP_STORAGE_SIZE and
+ * CONFIG_EC_WRITABLE_STORAGE_SIZE are both a multiple of
+ * CONFIG_FLASH_ERASE_SIZE.
  *
- * If above assumptions are not true, then additional checks would be required
- * to ensure that erase block size is selected based on the alignment of both
- * CONFIG_RO_SIZE and CONFIG_RW_SIZE and the offset of RO.
+ * THE NPCX supports erase sizes of 64 KiB, 32 KiB, and 4 KiB. The NPCX flash
+ * driver does not currently support CONFIG_FLASH_MULTIPLE_REGION, so set
+ * the erase size to the maximum (64 KiB) for the best performance.
+ * Using smaller erase sizes increases boot time. If write protected and
+ * writable flash regions are not a multiple of 64 KiB, then support
+ * for CONFIG_FLASH_MULTIPLE_REGION must be added.
  */
-#if ((CONFIG_RO_SIZE & (0x10000 - 1)) == 0)
-#define CONFIG_FLASH_ERASE_SIZE	0x10000
+#define CONFIG_FLASH_ERASE_SIZE		0x10000
 #define NPCX_ERASE_COMMAND		CMD_BLOCK_64K_ERASE
-#elif ((CONFIG_RO_SIZE & (0x8000 - 1)) == 0)
-#define CONFIG_FLASH_ERASE_SIZE	0x8000
-#define NPCX_ERASE_COMMAND		CMD_BLOCK_32K_ERASE
-#else
-#define CONFIG_FLASH_ERASE_SIZE	0x1000
-#define NPCX_ERASE_COMMAND		CMD_SECTOR_ERASE
+
+#if (CONFIG_WP_STORAGE_SIZE != CONFIG_EC_WRITABLE_STORAGE_SIZE)
+#error "NPCX flash support assumes CONFIG_WP_STORAGE_SIZE and " \
+	"CONFIG_EC_WRITABLE_STORAGE_SIZE are the same."
+#endif
+
+/*
+ * If the total flash size is not a multiple of 64k, this slows the boot
+ * time. CONFIG_FLASH_MULTIPLE_REGION should be enabled in this case to
+ * optimize the erase block handling.
+ */
+#if ((CONFIG_WP_STORAGE_SIZE % CONFIG_FLASH_ERASE_SIZE) != 0)
+#error "CONFIG_WP_STORAGE_SIZE is not a multiple of 64K. Correct the flash " \
+	"size or add support for CONFIG_FLASH_MULTIPLE_REGION."
 #endif
 
 #define CONFIG_FLASH_BANK_SIZE		CONFIG_FLASH_ERASE_SIZE