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| author | Tzung-Bi Shih <tzungbi@chromium.org> | 2020-08-26 11:15:39 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-09-03 03:18:05 +0000 |
| commit | 8db1cf02395cb38b44fea2ffb9c3660624e227a8 (patch) | |
| tree | 2c8aca4237031bdb550c5a6983fc09a32bb230c0 /chip/mt8192_scp | |
| parent | 217dd1c56883dcf64db887886c885d130d875370 (diff) | |
| download | chrome-ec-8db1cf02395cb38b44fea2ffb9c3660624e227a8.tar.gz | |
chip/mt8192_scp: remove chip_disable_irq
Disabling INTC IRQ in runtime is unstable in MT8192 SCP.
BRANCH=none
BUG=b:163682416
TEST=make BOARD=asurada_scp
Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org>
Change-Id: I2817cd14be2f7d9188c188405b79acb2a2d5504d
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2377046
Reviewed-by: Jett Rink <jettrink@chromium.org>
Diffstat (limited to 'chip/mt8192_scp')
| -rw-r--r-- | chip/mt8192_scp/intc.c | 20 |
1 files changed, 8 insertions, 12 deletions
diff --git a/chip/mt8192_scp/intc.c b/chip/mt8192_scp/intc.c index a5aa1bccd5..bd7416c31e 100644 --- a/chip/mt8192_scp/intc.c +++ b/chip/mt8192_scp/intc.c @@ -5,6 +5,7 @@ /* INTC control module */ +#include "console.h" #include "csr.h" #include "registers.h" @@ -202,18 +203,13 @@ void chip_enable_irq(int irq) void chip_disable_irq(int irq) { - unsigned int word, group, mask; - - word = SCP_INTC_WORD(irq); - group = irqs[irq].group; - mask = BIT(SCP_INTC_BIT(irq)); - - /* disable interrupt */ - SCP_CORE0_INTC_IRQ_EN(word) &= ~mask; - /* clear group setting */ - SCP_CORE0_INTC_IRQ_GRP(group, word) &= ~mask; - /* clear wakeup source setting */ - SCP_CORE0_INTC_SLP_WAKE_EN(word) &= ~mask; + /* + * Disabling INTC IRQ in runtime is unstable in MT8192 SCP. + * See b/163682416#comment17. + * + * Ideally, this function will be removed by LTO. + */ + ccprints("WARNING: %s is unsupported", __func__); } void chip_clear_pending_irq(int irq) |