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| author | Tzung-Bi Shih <tzungbi@chromium.org> | 2020-12-15 14:34:11 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-12-16 06:36:03 +0000 |
| commit | 59797476b4ad70cfe4209e6f9fdd3b78e49c12ed (patch) | |
| tree | 72a3465191211fc00b1da617d565b67b16fb8bdd /chip/mt8192_scp | |
| parent | f7df2b59796fb9239ea390c1f027f47c25d604c9 (diff) | |
| download | chrome-ec-59797476b4ad70cfe4209e6f9fdd3b78e49c12ed.tar.gz | |
chip/mt8192_scp: add memory barrier after writing to cache
Writing to AXI is asynchronous. Adds memory barrier to writeback and
flush cache operations to make sure the writing is done.
BRANCH=none
BUG=b:175512991
TEST=make BOARD=asurada_scp
Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org>
Change-Id: I6d04a2604f4eddae54aee4ba3ee4600e909e2784
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2592299
Reviewed-by: Ting Shen <phoenixshen@chromium.org>
Diffstat (limited to 'chip/mt8192_scp')
| -rw-r--r-- | chip/mt8192_scp/cache.h | 14 |
1 files changed, 12 insertions, 2 deletions
diff --git a/chip/mt8192_scp/cache.h b/chip/mt8192_scp/cache.h index f5a9d55489..13e5ad1a42 100644 --- a/chip/mt8192_scp/cache.h +++ b/chip/mt8192_scp/cache.h @@ -78,12 +78,17 @@ static inline void cache_barrier_dcache(void) static inline void cache_writeback_dcache(void) { cache_op_all(COP_OP_WRITEBACK_DCACHE); + cache_barrier_icache(); + cache_barrier_dcache(); } /* writeback a range of D$ */ static inline int cache_writeback_dcache_range(uintptr_t addr, uint32_t length) { - return cache_op_addr(addr, length, COP_OP_WRITEBACK_DCACHE_ADDR); + int ret = cache_op_addr(addr, length, COP_OP_WRITEBACK_DCACHE_ADDR); + cache_barrier_icache(); + cache_barrier_dcache(); + return ret; } /* invalidate all D$ */ @@ -102,12 +107,17 @@ static inline int cache_invalidate_dcache_range(uintptr_t addr, uint32_t length) static inline void cache_flush_dcache(void) { cache_op_all(COP_OP_FLUSH_DCACHE); + cache_barrier_icache(); + cache_barrier_dcache(); } /* writeback and invalidate a range of D$ */ static inline int cache_flush_dcache_range(uintptr_t addr, uint32_t length) { - return cache_op_addr(addr, length, COP_OP_FLUSH_DCACHE_ADDR); + int ret = cache_op_addr(addr, length, COP_OP_FLUSH_DCACHE_ADDR); + cache_barrier_icache(); + cache_barrier_dcache(); + return ret; } struct mpu_entry { |