diff options
author | Daisuke Nojiri <dnojiri@chromium.org> | 2016-10-18 09:27:34 -0700 |
---|---|---|
committer | chrome-bot <chrome-bot@chromium.org> | 2016-11-09 23:26:30 -0800 |
commit | b2f14a26b9e5b72486e9a7ad0e232fed269704c2 (patch) | |
tree | 0bad437caabacc37e80b4756c11c105da9992ebc /board | |
parent | d57ca415774be9bf136d9350b9ca52bb29c0ebfb (diff) | |
download | chrome-ec-b2f14a26b9e5b72486e9a7ad0e232fed269704c2.tar.gz |
eCTS: Add nested interrupt test (Low->High)
Add a nested interrupt test to eCTS. Lower priority IRQ is fired,
followed by higher priority IRQ. Handler executions should be nested.
P1 *-----*
/ \
P2 *----* *----*
/ \
task_cts ----* *----
A B C D
BUG=chromium:653195
BRANCH=none
TEST=cts.py -m gpio, interrupt, timer; make buildall
Change-Id: I34dc7b4e819051b9070a11e69d13d6be704f2e5f
Reviewed-on: https://chromium-review.googlesource.com/408797
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Diffstat (limited to 'board')
-rw-r--r-- | board/nucleo-f072rb/board.c | 5 | ||||
-rw-r--r-- | board/nucleo-f072rb/board.h | 4 | ||||
-rw-r--r-- | board/nucleo-f072rb/gpio.inc | 3 | ||||
-rw-r--r-- | board/stm32l476g-eval/gpio.inc | 5 |
4 files changed, 11 insertions, 6 deletions
diff --git a/board/nucleo-f072rb/board.c b/board/nucleo-f072rb/board.c index 1d60231ebe..48a51c7b02 100644 --- a/board/nucleo-f072rb/board.c +++ b/board/nucleo-f072rb/board.c @@ -21,9 +21,8 @@ void button_event(enum gpio_signal signal) * Dummy interrupt handler. It's supposed to be overwritten by each suite * if needed. */ -__attribute__((weak)) void cts_irq(enum gpio_signal signal) -{ -} +__attribute__((weak)) void cts_irq1(enum gpio_signal signal) {} +__attribute__((weak)) void cts_irq2(enum gpio_signal signal) {} #endif #include "gpio_list.h" diff --git a/board/nucleo-f072rb/board.h b/board/nucleo-f072rb/board.h index c008deb395..9cc2fc2d0b 100644 --- a/board/nucleo-f072rb/board.h +++ b/board/nucleo-f072rb/board.h @@ -18,10 +18,14 @@ /* Optional features */ #define CONFIG_STM_HWTIMER32 +#ifdef CTS_MODULE +#undef STM32_IRQ_EXT2_3_PRIORITY +#define STM32_IRQ_EXT2_3_PRIORITY 2 #ifdef CTS_MODULE_I2C #define CONFIG_I2C #define CONFIG_I2C_MASTER #endif +#endif #undef CONFIG_WATCHDOG_HELP #undef CONFIG_LID_SWITCH diff --git a/board/nucleo-f072rb/gpio.inc b/board/nucleo-f072rb/gpio.inc index 31149bf633..6f3b592845 100644 --- a/board/nucleo-f072rb/gpio.inc +++ b/board/nucleo-f072rb/gpio.inc @@ -13,11 +13,12 @@ GPIO_INT(USER_BUTTON, PIN(C, 13), GPIO_INT_FALLING, button_event) #ifndef CTS_MODULE_GPIO /* Overload C1 for interrupt. Enabled only for non-GPIO suites as * GPIO tests don't require a separate notification line. */ -GPIO_INT(CTS_IRQ, PIN(C, 1), GPIO_INT_FALLING | GPIO_PULL_UP , cts_irq) +GPIO_INT(CTS_IRQ1, PIN(C, 1), GPIO_INT_FALLING | GPIO_PULL_UP , cts_irq1) /* Used to disable interrupt. This IRQ# has to match the number used for the * pin set above */ #define CTS_IRQ_NUMBER STM32_IRQ_EXTI0_1 #endif +GPIO_INT(CTS_IRQ2, PIN(C, 2), GPIO_INT_FALLING | GPIO_PULL_UP , cts_irq2) #endif /* Outputs */ diff --git a/board/stm32l476g-eval/gpio.inc b/board/stm32l476g-eval/gpio.inc index ff896d8da5..9cf5bc0aa4 100644 --- a/board/stm32l476g-eval/gpio.inc +++ b/board/stm32l476g-eval/gpio.inc @@ -28,9 +28,10 @@ ALTERNATE(PIN_MASK(G, 0x0180), GPIO_ALT_F8, MODULE_UART, 0) /* LPUART: PG7/8 */ #ifdef CTS_MODULE /* CTS Signals */ -GPIO(HANDSHAKE_OUTPUT, PIN(D, 2), GPIO_ODR_LOW) -GPIO(HANDSHAKE_INPUT, PIN(C, 12), GPIO_INPUT | GPIO_PULL_UP) +GPIO(HANDSHAKE_OUTPUT, PIN(A, 9), GPIO_ODR_LOW) +GPIO(HANDSHAKE_INPUT, PIN(A, 8), GPIO_INPUT | GPIO_PULL_UP) GPIO(OUTPUT_TEST, PIN(C, 11), GPIO_ODR_LOW) +GPIO(CTS_IRQ2, PIN(C, 12), GPIO_ODR_LOW) #ifdef CTS_MODULE_GPIO GPIO(INPUT_TEST, PIN(C, 10), GPIO_INPUT | GPIO_PULL_UP) #endif |