diff options
| author | Keith Short <keithshort@chromium.org> | 2019-09-19 15:26:16 -0600 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2019-09-29 17:06:12 +0000 |
| commit | c967310d1ec9fdda6b36bd7dfcfa735286fec3c5 (patch) | |
| tree | e982ae70e4b577fd74ea5ebfff7a59118e33184e /board/nocturne | |
| parent | 946331e651bf333b209c2f3124e3b35b33b11efe (diff) | |
| download | chrome-ec-c967310d1ec9fdda6b36bd7dfcfa735286fec3c5.tar.gz | |
volteer: Add RTC reset
Add support for the RTC reset on Volteer. This change also deduplicates
the board_rtc_reset() function which was identical on boards that
enabled CONFIG_BOARD_HAS_RTC_RESET.
BUG=b:141321096
BRANCH=none
TEST=make buildall
Change-Id: Ifc6959f8271400174fd4999a3c70800b03b9c2d0
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1816869
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Diffstat (limited to 'board/nocturne')
| -rw-r--r-- | board/nocturne/board.c | 8 | ||||
| -rw-r--r-- | board/nocturne/board.h | 1 |
2 files changed, 1 insertions, 8 deletions
diff --git a/board/nocturne/board.c b/board/nocturne/board.c index 16a30571d4..eac0b14b27 100644 --- a/board/nocturne/board.c +++ b/board/nocturne/board.c @@ -685,14 +685,6 @@ void board_set_tcpc_power_mode(int port, int mode) board_reset_pd_mcu(); } -void board_rtc_reset(void) -{ - cprints(CC_SYSTEM, "Asserting RTCRST# to PCH"); - gpio_set_level(GPIO_EC_PCH_RTCRST, 1); - udelay(100); - gpio_set_level(GPIO_EC_PCH_RTCRST, 0); -} - int board_set_active_charge_port(int port) { int is_real_port = (port >= 0 && diff --git a/board/nocturne/board.h b/board/nocturne/board.h index 24768bf7c4..b836fbdf99 100644 --- a/board/nocturne/board.h +++ b/board/nocturne/board.h @@ -190,6 +190,7 @@ #define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW #define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_L #define GPIO_PCH_RSMRST_L GPIO_RSMRST_L +#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST #define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L #define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L #define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L |