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authorAseda Aboagye <aaboagye@google.com>2018-06-07 18:07:45 -0700
committerchrome-bot <chrome-bot@chromium.org>2018-06-08 16:14:15 -0700
commit532e135d039c686dfbdf26e4dadbcd6e9b71d107 (patch)
tree75a27daa1d0d5cd20c080d52d9f5f9e688180033 /board/nocturne
parentf39c9fb0466ab5729aeba13ec4a52079d561f03b (diff)
downloadchrome-ec-532e135d039c686dfbdf26e4dadbcd6e9b71d107.tar.gz
nocturne: Fix CPU_PROCHOT polarity.
Nocturne's CPU_PROCHOT is active low. Additionally, it's a 1V signal, so enable 1.8V GPIO logic to give it a chance of reporting the right thing. BUG=b:109882953 BRANCH=poppy TEST=Flash nocturne; verify that PROCHOT isn't asserted by default. Change-Id: I90126b3e495fa6e83b03c893cc3090cad90e1d5a Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/1092151 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org>
Diffstat (limited to 'board/nocturne')
-rw-r--r--board/nocturne/board.h1
-rw-r--r--board/nocturne/gpio.inc2
2 files changed, 2 insertions, 1 deletions
diff --git a/board/nocturne/board.h b/board/nocturne/board.h
index 2b84d1f933..fa0febf7d4 100644
--- a/board/nocturne/board.h
+++ b/board/nocturne/board.h
@@ -96,6 +96,7 @@
#define CONFIG_CHIPSET_SKYLAKE
#define CONFIG_CHIPSET_HAS_PLATFORM_PMIC_RESET
#define CONFIG_CHIPSET_RESET_HOOK
+#define CONFIG_CPU_PROCHOT_ACTIVE_LOW
#define CONFIG_POWER_COMMON
#define CONFIG_POWER_BUTTON
#define CONFIG_POWER_BUTTON_X86
diff --git a/board/nocturne/gpio.inc b/board/nocturne/gpio.inc
index ef73e4fe1b..5dfb36ffd9 100644
--- a/board/nocturne/gpio.inc
+++ b/board/nocturne/gpio.inc
@@ -40,7 +40,7 @@ GPIO(EC_PCH_PWR_BTN_L, PIN(C, 1), GPIO_OUT_HIGH)
GPIO(EC_PCH_RTCRST, PIN(7, 6), GPIO_OUT_LOW)
GPIO(SLP_SUS_L_PMIC, PIN(D, 7), GPIO_OUT_LOW)
GPIO(EC_PCH_WAKE_L, PIN(7, 4), GPIO_ODR_HIGH | GPIO_PULL_UP)
-GPIO(EC_PROCHOT_ODL, PIN(3, 4), GPIO_ODR_HIGH)
+GPIO(EC_PROCHOT_ODL, PIN(3, 4), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
GPIO(SYS_RESET_L, PIN(0, 2), GPIO_ODR_HIGH)
GPIO(USB_C0_DP_HPD, PIN(C, 5), GPIO_OUT_LOW)
GPIO(USB_C1_DP_HPD, PIN(C, 6), GPIO_OUT_LOW)