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authorEric Yilun Lin <yllin@chromium.org>2021-08-17 14:38:36 +0800
committerCommit Bot <commit-bot@chromium.org>2021-11-17 09:16:27 +0000
commit2dec0f631c832c67f876764772492f6dc8b29dfa (patch)
tree92f165d7acd6f9f1597c6e32e720deef7cebcbba /baseboard/goroh
parentf5081fe6cb357f5903d50396421e5a0256c0584d (diff)
downloadchrome-ec-2dec0f631c832c67f876764772492f6dc8b29dfa.tar.gz
goroh: move USB-C code to baseboard/usbc_config
Move USB-C code to baseboard/usbc_config and correct the GPIO configuration. BUG=b:185846337 TEST=make BOARD=goroh BRANCH=none Change-Id: I3bff677b4b47b62d2fe638c50b370c3e51c5699c Signed-off-by: Eric Yilun Lin <yllin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3099387 Reviewed-by: Rong Chang <rongchang@chromium.org> Commit-Queue: Eric Yilun Lin <yllin@google.com> Tested-by: Eric Yilun Lin <yllin@google.com>
Diffstat (limited to 'baseboard/goroh')
-rw-r--r--baseboard/goroh/baseboard.c78
-rw-r--r--baseboard/goroh/baseboard.h6
-rw-r--r--baseboard/goroh/baseboard_usbc_config.h15
-rw-r--r--baseboard/goroh/build.mk4
-rw-r--r--baseboard/goroh/usbc_config.c131
5 files changed, 153 insertions, 81 deletions
diff --git a/baseboard/goroh/baseboard.c b/baseboard/goroh/baseboard.c
index ba4f452289..ee88d1e713 100644
--- a/baseboard/goroh/baseboard.c
+++ b/baseboard/goroh/baseboard.c
@@ -6,6 +6,8 @@
/* Goroh baseboard-specific configuration */
#include "adc.h"
+#include "adc_chip.h"
+#include "baseboard_usbc_config.h"
#include "button.h"
#include "charge_manager.h"
#include "charger.h"
@@ -44,8 +46,6 @@
#include "usb_pd.h"
#include "usb_pd_tcpm.h"
-static void ppc_interrupt(enum gpio_signal signal);
-
#include "gpio_list.h"
#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
@@ -74,40 +74,6 @@ struct bc12_config bc12_ports[CHARGE_PORT_COUNT] = {
const int usb_port_enable[USB_PORT_COUNT] = {
};
-/* Detect subboard */
-static void board_tcpc_init(void)
-{
- gpio_enable_interrupt(GPIO_USB_C0_FAULT_ODL);
- gpio_enable_interrupt(GPIO_USB_C1_FAULT_ODL);
-}
-/* Must be done after I2C and subboard */
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1);
-
-/* PPC */
-struct ppc_config_t ppc_chips[CONFIG_USB_PD_PORT_MAX_COUNT] = {
- {
- .i2c_port = I2C_PORT_PPC0,
- .i2c_addr_flags = SYV682X_ADDR0_FLAGS,
- .drv = &syv682x_drv,
- },
- {
- .i2c_port = I2C_PORT_PPC1,
- .i2c_addr_flags = SYV682X_ADDR0_FLAGS,
- .drv = &syv682x_drv,
- },
-};
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-static void ppc_interrupt(enum gpio_signal signal)
-{
- if (signal == GPIO_USB_C0_FAULT_ODL)
- /* C0: PPC interrupt */
- syv682x_interrupt(0);
- else
- /* C1: PPC interrupt */
- syv682x_interrupt(1);
-}
-
/* Called on AP S3 -> S0 transition */
static void board_chipset_resume(void)
{
@@ -124,11 +90,6 @@ DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
/* USB Mux */
-/* TODO(yllin): configure USB mux */
-
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-};
-
/*
* I2C channels (A, B, and C) are using the same timing registers (00h~07h)
* at default.
@@ -166,24 +127,6 @@ void board_overcurrent_event(int port, int is_overcurrented)
/* TODO: check correct operation for GOROH */
}
-/* TCPC */
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
- {
- .bus_type = EC_BUS_TYPE_EMBEDDED,
- /* TCPC is embedded within EC so no i2c config needed */
- .drv = &it8xxx2_tcpm_drv,
- /* Alert is active-low, push-pull */
- .flags = 0,
- },
- {
- .bus_type = EC_BUS_TYPE_EMBEDDED,
- /* TCPC is embedded within EC so no i2c config needed */
- .drv = &it8xxx2_tcpm_drv,
- /* Alert is active-low, push-pull */
- .flags = 0,
- },
-};
-
const struct cc_para_t *board_get_cc_tuning_parameter(enum usbpd_port port)
{
const static struct cc_para_t
@@ -201,23 +144,6 @@ const struct cc_para_t *board_get_cc_tuning_parameter(enum usbpd_port port)
return &cc_parameter[port];
}
-uint16_t tcpc_get_alert_status(void)
-{
- /*
- * C0 & C1: TCPC is embedded in the EC and processes interrupts in the
- * chip code (it83xx/intc.c)
- */
- return 0;
-}
-
-void board_reset_pd_mcu(void)
-{
- /*
- * C0 & C1: TCPC is embedded in the EC and processes interrupts in the
- * chip code (it83xx/intc.c)
- */
-}
-
void board_set_charge_limit(int port, int supplier, int charge_ma,
int max_ma, int charge_mv)
{
diff --git a/baseboard/goroh/baseboard.h b/baseboard/goroh/baseboard.h
index 18bb27c244..83f0f0ad64 100644
--- a/baseboard/goroh/baseboard.h
+++ b/baseboard/goroh/baseboard.h
@@ -79,10 +79,8 @@
#define I2C_PORT_CHARGER IT83XX_I2C_CH_A
#define I2C_PORT_BATTERY IT83XX_I2C_CH_A
#define I2C_PORT_ACCEL IT83XX_I2C_CH_B
-#define I2C_PORT_PPC0 IT83XX_I2C_CH_C
-#define I2C_PORT_PPC1 IT83XX_I2C_CH_E
-#define I2C_PORT_USB_MUX0 IT83XX_I2C_CH_C
-#define I2C_PORT_USB_MUX1 IT83XX_I2C_CH_E
+#define I2C_PORT_USB_C0 IT83XX_I2C_CH_C
+#define I2C_PORT_USB_C1 IT83XX_I2C_CH_E
#define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY
#define CONFIG_SMBUS_PEC
diff --git a/baseboard/goroh/baseboard_usbc_config.h b/baseboard/goroh/baseboard_usbc_config.h
new file mode 100644
index 0000000000..b5e76644ee
--- /dev/null
+++ b/baseboard/goroh/baseboard_usbc_config.h
@@ -0,0 +1,15 @@
+/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* goroh family-specific USB-C configuration */
+
+#ifndef __CROS_EC_BASEBOARD_USBC_CONFIG_H
+#define __CROS_EC_BASEBOARD_USBC_CONFIG_H
+
+#include "gpio_signal.h"
+
+/* Common definition for the USB PD interrupt handlers. */
+void ppc_interrupt(enum gpio_signal signal);
+#endif /* __CROS_EC_BASEBOARD_USBC_CONFIG_H */
diff --git a/baseboard/goroh/build.mk b/baseboard/goroh/build.mk
index 58e9934bc0..4488c4b395 100644
--- a/baseboard/goroh/build.mk
+++ b/baseboard/goroh/build.mk
@@ -6,5 +6,7 @@
# Baseboard specific files build
#
-baseboard-y=baseboard.o board_id.o
+baseboard-y+=baseboard.o
+baseboard-y+=board_id.o
+baseboard-y+=usbc_config.o
baseboard-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o
diff --git a/baseboard/goroh/usbc_config.c b/baseboard/goroh/usbc_config.c
new file mode 100644
index 0000000000..4c02528285
--- /dev/null
+++ b/baseboard/goroh/usbc_config.c
@@ -0,0 +1,131 @@
+/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Goroh family-specific USB-C configuration */
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "config.h"
+#include "console.h"
+#include "hooks.h"
+#include "driver/tcpm/it8xxx2_pd_public.h"
+#include "driver/ppc/syv682x_public.h"
+#include "driver/retimer/ps8818.h"
+#include "driver/tcpm/tcpci.h"
+#include "usb_pd.h"
+#include "usbc_ppc.h"
+#include "gpio.h"
+#include "gpio_signal.h"
+
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
+
+#ifdef CONFIG_BRINGUP
+#define GPIO_SET_LEVEL(pin, lvl) gpio_set_level_verbose(CC_USBPD, pin, lvl)
+#else
+#define GPIO_SET_LEVEL(pin, lvl) gpio_set_level(pin, lvl)
+#endif
+
+/* PPC */
+struct ppc_config_t ppc_chips[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+ {
+ .i2c_port = I2C_PORT_USB_C0,
+ .i2c_addr_flags = SYV682X_ADDR0_FLAGS,
+ .drv = &syv682x_drv,
+ },
+ {
+ .i2c_port = I2C_PORT_USB_C1,
+ .i2c_addr_flags = SYV682X_ADDR0_FLAGS,
+ .drv = &syv682x_drv,
+ },
+};
+unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
+
+/* USB Mux */
+
+__overridable int board_c1_ps8818_mux_init(const struct usb_mux *me)
+{
+ /* enable C1 mux power */
+ GPIO_SET_LEVEL(GPIO_EN_USB_C1_MUX_PWR, 1);
+ return 0;
+}
+
+__overridable int board_c1_ps8818_mux_set(const struct usb_mux *me,
+ mux_state_t mux_state)
+{
+ if (mux_state == USB_PD_MUX_NONE)
+ GPIO_SET_LEVEL(GPIO_EN_USB_C1_MUX_PWR, 0);
+
+ return 0;
+}
+
+const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+ {
+ /* C0 no mux */
+ },
+ {
+ .usb_port = USBC_PORT_C1,
+ .i2c_port = I2C_PORT_USB_C1,
+ .i2c_addr_flags = PS8818_I2C_ADDR_FLAGS,
+ .driver = &ps8818_usb_retimer_driver,
+ .board_init = &board_c1_ps8818_mux_init,
+ .board_set = &board_c1_ps8818_mux_set,
+ },
+};
+BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
+
+/* TCPC */
+const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+ {
+ .bus_type = EC_BUS_TYPE_EMBEDDED,
+ /* TCPC is embedded within EC so no i2c config needed */
+ .drv = &it8xxx2_tcpm_drv,
+ /* Alert is active-low, push-pull */
+ .flags = 0,
+ },
+ {
+ .bus_type = EC_BUS_TYPE_EMBEDDED,
+ /* TCPC is embedded within EC so no i2c config needed */
+ .drv = &it8xxx2_tcpm_drv,
+ /* Alert is active-low, push-pull */
+ .flags = 0,
+ },
+};
+
+void ppc_interrupt(enum gpio_signal signal)
+{
+ if (signal == GPIO_USB_C0_FAULT_ODL)
+ /* C0: PPC interrupt */
+ syv682x_interrupt(0);
+ else
+ /* C1: PPC interrupt */
+ syv682x_interrupt(1);
+}
+
+
+static void board_tcpc_init(void)
+{
+ gpio_enable_interrupt(GPIO_USB_C0_FAULT_ODL);
+ gpio_enable_interrupt(GPIO_USB_C1_FAULT_ODL);
+}
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1);
+
+void board_reset_pd_mcu(void)
+{
+ /*
+ * C0 & C1: TCPC is embedded in the EC and processes interrupts in the
+ * chip code (it83xx/intc.c)
+ */
+}
+
+uint16_t tcpc_get_alert_status(void)
+{
+ /*
+ * C0 & C1: TCPC is embedded in the EC and processes interrupts in the
+ * chip code (it83xx/intc.c)
+ */
+ return 0;
+}