diff options
| author | Jack Rosenthal <jrosenth@chromium.org> | 2022-06-27 14:54:27 -0600 |
|---|---|---|
| committer | Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> | 2022-07-01 18:25:37 +0000 |
| commit | e3df97358a251c8f4516b9a56ae33f31a2b0afc8 (patch) | |
| tree | 1e5c1c9766d83be4a917f0ea53d3ed14c1c0e755 | |
| parent | 05b310dda90e1870c18926b2fb7e75adf7193a47 (diff) | |
| download | chrome-ec-e3df97358a251c8f4516b9a56ae33f31a2b0afc8.tar.gz | |
driver/tcpm/anx7688.c: Format with clang-format
BUG=b:236386294
BRANCH=none
TEST=none
Change-Id: I280d845e33494866093c82cd4f8f5d9c95244ad4
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730075
Reviewed-by: Jeremy Bettis <jbettis@chromium.org>
| -rw-r--r-- | driver/tcpm/anx7688.c | 56 |
1 files changed, 28 insertions, 28 deletions
diff --git a/driver/tcpm/anx7688.c b/driver/tcpm/anx7688.c index 5e37352bc5..4ee87fdaa4 100644 --- a/driver/tcpm/anx7688.c +++ b/driver/tcpm/anx7688.c @@ -12,24 +12,24 @@ #include "usb_mux.h" #if defined(CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE) || \ - defined(CONFIG_USB_PD_TCPC_LOW_POWER) || \ + defined(CONFIG_USB_PD_TCPC_LOW_POWER) || \ defined(CONFIG_USB_PD_DISCHARGE_TCPC) #error "Unsupported config options of anx7688 PD driver" #endif -#define ANX7688_VENDOR_ALERT BIT(15) +#define ANX7688_VENDOR_ALERT BIT(15) -#define ANX7688_REG_STATUS 0x82 +#define ANX7688_REG_STATUS 0x82 #define ANX7688_REG_STATUS_LINK BIT(0) -#define ANX7688_REG_HPD 0x83 -#define ANX7688_REG_HPD_HIGH BIT(0) -#define ANX7688_REG_HPD_IRQ BIT(1) -#define ANX7688_REG_HPD_ENABLE BIT(2) +#define ANX7688_REG_HPD 0x83 +#define ANX7688_REG_HPD_HIGH BIT(0) +#define ANX7688_REG_HPD_IRQ BIT(1) +#define ANX7688_REG_HPD_ENABLE BIT(2) -#define ANX7688_USBC_ADDR_FLAGS 0x28 -#define ANX7688_REG_RAMCTRL 0xe7 -#define ANX7688_REG_RAMCTRL_BOOT_DONE BIT(6) +#define ANX7688_USBC_ADDR_FLAGS 0x28 +#define ANX7688_REG_RAMCTRL 0xe7 +#define ANX7688_REG_RAMCTRL_BOOT_DONE BIT(6) static int anx7688_init(int port) { @@ -85,9 +85,9 @@ static void anx7688_update_hpd_enable(int port) !(status & ANX7688_REG_STATUS_LINK)) { reg &= ~ANX7688_REG_HPD_IRQ; tcpc_write(port, ANX7688_REG_HPD, - (status & ANX7688_REG_STATUS_LINK) - ? reg | ANX7688_REG_HPD_ENABLE - : reg & ~ANX7688_REG_HPD_ENABLE); + (status & ANX7688_REG_STATUS_LINK) ? + reg | ANX7688_REG_HPD_ENABLE : + reg & ~ANX7688_REG_HPD_ENABLE); } } @@ -195,25 +195,25 @@ static bool anx7688_tcpm_check_vbus_level(int port, enum vbus_level level) /* ANX7688 is a TCPCI compatible port controller */ const struct tcpm_drv anx7688_tcpm_drv = { - .init = &anx7688_init, - .release = &anx7688_release, - .get_cc = &tcpci_tcpm_get_cc, + .init = &anx7688_init, + .release = &anx7688_release, + .get_cc = &tcpci_tcpm_get_cc, #ifdef CONFIG_USB_PD_VBUS_DETECT_TCPC - .check_vbus_level = &anx7688_tcpm_check_vbus_level, + .check_vbus_level = &anx7688_tcpm_check_vbus_level, #endif - .select_rp_value = &tcpci_tcpm_select_rp_value, - .set_cc = &tcpci_tcpm_set_cc, - .set_polarity = &tcpci_tcpm_set_polarity, + .select_rp_value = &tcpci_tcpm_select_rp_value, + .set_cc = &tcpci_tcpm_set_cc, + .set_polarity = &tcpci_tcpm_set_polarity, #ifdef CONFIG_USB_PD_DECODE_SOP - .sop_prime_enable = &tcpci_tcpm_sop_prime_enable, + .sop_prime_enable = &tcpci_tcpm_sop_prime_enable, #endif - .set_vconn = &tcpci_tcpm_set_vconn, - .set_msg_header = &tcpci_tcpm_set_msg_header, - .set_rx_enable = &tcpci_tcpm_set_rx_enable, - .get_message_raw = &tcpci_tcpm_get_message_raw, - .transmit = &tcpci_tcpm_transmit, - .tcpc_alert = &anx7688_tcpc_alert, - .set_bist_test_mode = &tcpci_set_bist_test_mode, + .set_vconn = &tcpci_tcpm_set_vconn, + .set_msg_header = &tcpci_tcpm_set_msg_header, + .set_rx_enable = &tcpci_tcpm_set_rx_enable, + .get_message_raw = &tcpci_tcpm_get_message_raw, + .transmit = &tcpci_tcpm_transmit, + .tcpc_alert = &anx7688_tcpc_alert, + .set_bist_test_mode = &tcpci_set_bist_test_mode, }; #ifdef CONFIG_USB_PD_TCPM_MUX |