it83xx: add config for reading observation register of external timer issue

In IT8320 BX version, there is a chance of failure in reading
external timer observation register. We are using the time delay
of CPU in order to read register twice that can avoid the bug of
reading time failure when CPU and EC are counting at the same time.
There will be once successful read. The bug has been fixed in
the later version of chip.

BUG=none
BRANCH=none
TEST=Ensure the observation register of external timer will
     be read successful in IT8320 DX chip.

Change-Id: I0ec2d0bb83afd1549118de9383dc16cf5adb6b5a
Signed-off-by: tim <tim2.lin@ite.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/1215523
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: Tim2 Lin <tim2.lin@ite.corp-partner.google.com>
Reviewed-by: Jett Rink <jettrink@chromium.org>

4 files changed, 20 insertions, 22 deletions

diff --git a/chip/it83xx/clock.c b/chip/it83xx/clock.c
index b10a31d19f..6ab644912f 100644
--- a/chip/it83xx/clock.c
+++ b/chip/it83xx/clock.c
@@ -339,11 +339,10 @@ static void clock_htimer_enable(void)
 	uint32_t c;
 
 	/* change event timer clock source to 32.768 KHz */
-#if 0
-	c = TIMER_CNT_8M_32P768K(IT83XX_ETWD_ETXCNTOR(EVENT_EXT_TIMER));
-#else
-	/* TODO(crosbug.com/p/55044) */
+#ifdef IT83XX_EXT_OBSERVATION_REG_READ_TWO_TIMES
 	c = TIMER_CNT_8M_32P768K(ext_observation_reg_read(EVENT_EXT_TIMER));
+#else
+	c = TIMER_CNT_8M_32P768K(IT83XX_ETWD_ETXCNTOR(EVENT_EXT_TIMER));
 #endif
 	clock_event_timer_clock_change(EXT_PSR_32P768K_HZ, c);
 }
@@ -357,11 +356,10 @@ static int clock_allow_low_power_idle(void)
 		et_ctrl_regs[EVENT_EXT_TIMER].mask)
 		return 0;
 
-#if 0
-	if (EVENT_TIMER_COUNT_TO_US(IT83XX_ETWD_ETXCNTOR(EVENT_EXT_TIMER)) <
-#else
-	/* TODO(crosbug.com/p/55044) */
+#ifdef IT83XX_EXT_OBSERVATION_REG_READ_TWO_TIMES
 	if (EVENT_TIMER_COUNT_TO_US(ext_observation_reg_read(EVENT_EXT_TIMER)) <
+#else
+	if (EVENT_TIMER_COUNT_TO_US(IT83XX_ETWD_ETXCNTOR(EVENT_EXT_TIMER)) <
 #endif
 		SLEEP_SET_HTIMER_DELAY_USEC)
 		return 0;
diff --git a/chip/it83xx/config_chip.h b/chip/it83xx/config_chip.h
index 1266353dcd..77afe9d9b2 100644
--- a/chip/it83xx/config_chip.h
+++ b/chip/it83xx/config_chip.h
@@ -77,6 +77,10 @@
 #define IT83XX_USBPD_CC_VOLTAGE_DETECTOR_INDEPENDENT
 /* For IT8320BX, we have to write 0xff to clear pending bit.*/
 #define IT83XX_ESPI_VWCTRL1_WRITE_FF_CLEAR
+/* For IT8320BX, we have to read observation register of external timer two
+ * times to get correct time.
+ */
+#define IT83XX_EXT_OBSERVATION_REG_READ_TWO_TIMES
 #elif defined(CHIP_VARIANT_IT8320DX)
 #define CONFIG_FLASH_SIZE  0x00080000
 /* The slave frequency is adjustable (bit[2-0] at register IT83XX_ESPI_GCAC1) */
diff --git a/chip/it83xx/hwtimer.c b/chip/it83xx/hwtimer.c
index 915fe3f6dd..e65fea38fa 100644
--- a/chip/it83xx/hwtimer.c
+++ b/chip/it83xx/hwtimer.c
@@ -98,15 +98,14 @@ static void event_timer_clear_pending_isr(void)
 
 uint32_t __ram_code __hw_clock_source_read(void)
 {
-#if 0
+#ifdef IT83XX_EXT_OBSERVATION_REG_READ_TWO_TIMES
 	/*
 	 * In combinational mode, the counter observation register of
 	 * timer 4(TIMER_H) will increment.
 	 */
-	return IT83XX_ETWD_ETXCNTOR(FREE_EXT_TIMER_H);
-#else
-	/* TODO(crosbug.com/p/55044) */
 	return ext_observation_reg_read(FREE_EXT_TIMER_H);
+#else
+	return IT83XX_ETWD_ETXCNTOR(FREE_EXT_TIMER_H);
 #endif
 }
 
@@ -143,11 +142,10 @@ uint32_t __hw_clock_event_get(void)
 	if (IT83XX_ETWD_ETXCTRL(EVENT_EXT_TIMER) & (1 << 0)) {
 		/* timer counter observation value to microseconds */
 		next_event_us += EVENT_TIMER_COUNT_TO_US(
-#if 0
-			IT83XX_ETWD_ETXCNTOR(EVENT_EXT_TIMER));
-#else
-			/* TODO(crosbug.com/p/55044) */
+#ifdef IT83XX_EXT_OBSERVATION_REG_READ_TWO_TIMES
 			ext_observation_reg_read(EVENT_EXT_TIMER));
+#else
+			IT83XX_ETWD_ETXCNTOR(EVENT_EXT_TIMER));
 #endif
 	}
 	return next_event_us;
@@ -225,11 +223,7 @@ static void __hw_clock_source_irq(void)
 }
 DECLARE_IRQ(CPU_INT_GROUP_3, __hw_clock_source_irq, 1);
 
-/*
- * TODO(crosbug.com/p/55044):
- * observation register of external timer latch issue.
- * we can remove this workaround after version change.
- */
+#ifdef IT83XX_EXT_OBSERVATION_REG_READ_TWO_TIMES
 /* Number of CPU cycles in 125 us */
 #define CYCLES_125NS (125*(PLL_CLOCK/SECOND) / 1000)
 uint32_t __ram_code ext_observation_reg_read(enum ext_timer_sel ext_timer)
@@ -259,6 +253,7 @@ uint32_t __ram_code ext_observation_reg_read(enum ext_timer_sel ext_timer)
 
 	return val;
 }
+#endif
 
 void ext_timer_start(enum ext_timer_sel ext_timer, int en_irq)
 {
diff --git a/chip/it83xx/hwtimer_chip.h b/chip/it83xx/hwtimer_chip.h
index 54b51d373a..ef53c4e871 100644
--- a/chip/it83xx/hwtimer_chip.h
+++ b/chip/it83xx/hwtimer_chip.h
@@ -57,8 +57,9 @@ struct ext_timer_ctrl_t {
 };
 
 extern const struct ext_timer_ctrl_t et_ctrl_regs[];
-/* TODO(crosbug.com/p/55044) */
+#ifdef IT83XX_EXT_OBSERVATION_REG_READ_TWO_TIMES
 uint32_t __ram_code ext_observation_reg_read(enum ext_timer_sel ext_timer);
+#endif
 void ext_timer_start(enum ext_timer_sel ext_timer, int en_irq);
 void ext_timer_stop(enum ext_timer_sel ext_timer, int dis_irq);
 void fan_ext_timer_interrupt(void);