diff options
| author | Nicolas Boichat <drinkcat@chromium.org> | 2020-12-29 17:32:15 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-12-30 04:31:42 +0000 |
| commit | b3584dd1ea0b11c269424ab7693cb9609b15e568 (patch) | |
| tree | 4a8c2b89bd8f81727389729e18da43d8d1436b61 | |
| parent | 10738dbd195361177eb079143e256278b6b4c558 (diff) | |
| download | chrome-ec-b3584dd1ea0b11c269424ab7693cb9609b15e568.tar.gz | |
core/riscv-rv32i: Add exception_panic
software_panic is meant for exceptions that are usually
software-driven (stack overflow, etc.).
Create a new exception_panic function that can be used for the
corner cases where we want to replicate exception behaviour of
other cores (e.g. integer division by zero), that we do not
want to be disabled by CONFIG_SOFTWARE_PANIC.
BRANCH=none
BUG=b:173969773
TEST=buildall
Change-Id: I2253383e356637a62a401f0e695388e514de330f
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2606167
Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
| -rw-r--r-- | core/riscv-rv32i/cpu.h | 4 | ||||
| -rw-r--r-- | core/riscv-rv32i/panic.c | 19 |
2 files changed, 16 insertions, 7 deletions
diff --git a/core/riscv-rv32i/cpu.h b/core/riscv-rv32i/cpu.h index e46b893ad6..94d6db4e81 100644 --- a/core/riscv-rv32i/cpu.h +++ b/core/riscv-rv32i/cpu.h @@ -21,6 +21,7 @@ #ifndef __ASSEMBLER__ #include <stdint.h> +#include <stdnoreturn.h> /* write Exception Program Counter register */ static inline void set_mepc(uint32_t val) @@ -46,6 +47,9 @@ static inline uint32_t get_mcause(void) return ret; } +/* Trigger a panic. */ +noreturn void exception_panic(uint32_t reason, uint32_t info); + /* Generic CPU core initialization */ void cpu_init(void); extern uint32_t ec_reset_lp; diff --git a/core/riscv-rv32i/panic.c b/core/riscv-rv32i/panic.c index 3d8cec1b06..cc95eb19a4 100644 --- a/core/riscv-rv32i/panic.c +++ b/core/riscv-rv32i/panic.c @@ -33,13 +33,7 @@ static const char * const exc_type[16] = { }; #endif /* CONFIG_DEBUG_EXCEPTIONS */ -#ifdef CONFIG_SOFTWARE_PANIC -/* General purpose register (s0) for saving software panic reason */ -#define SOFT_PANIC_GPR_REASON 11 -/* General purpose register (s1) for saving software panic information */ -#define SOFT_PANIC_GPR_INFO 10 - -void software_panic(uint32_t reason, uint32_t info) +void exception_panic(uint32_t reason, uint32_t info) { asm volatile ("mv s0, %0" : : "r"(reason)); asm volatile ("mv s1, %0" : : "r"(info)); @@ -50,6 +44,17 @@ void software_panic(uint32_t reason, uint32_t info) __builtin_unreachable(); } +#ifdef CONFIG_SOFTWARE_PANIC +/* General purpose register (s0) for saving software panic reason */ +#define SOFT_PANIC_GPR_REASON 11 +/* General purpose register (s1) for saving software panic information */ +#define SOFT_PANIC_GPR_INFO 10 + +void software_panic(uint32_t reason, uint32_t info) +{ + exception_panic(reason, info); +} + void panic_set_reason(uint32_t reason, uint32_t info, uint8_t exception) { /* |