diff options
| author | Jun Lin <CHLin56@nuvoton.com> | 2021-06-29 10:29:31 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-06-29 17:02:51 +0000 |
| commit | af430856c637235d9f705a51e7a69da0867d8f3a (patch) | |
| tree | 5a413bc76115ee95384c63125687aba456cd2de8 | |
| parent | de4118192e3fb8d1bb7065d054fd297d748675b9 (diff) | |
| download | chrome-ec-af430856c637235d9f705a51e7a69da0867d8f3a.tar.gz | |
zephyr: dts: npcx: move SHI node to npcx.dtsi
SHI is supported in all npcx family chips. Its dts node should be
declared in the common location (i.e. npcx.dtsi.)
BRANCH=none
BUG=b:192295048
TEST=build lazor
TEST=with CL:2993220, build herobrine_npcx7 and herobrine_npcx9 with
CONFIG_CROS_SHI_NPCX enabled
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Change-Id: I6b6d9ba9a666d86a0993fa59c3cb7ff8249b7595
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2993926
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Wai-Hong Tam <waihong@google.com>
Commit-Queue: Wai-Hong Tam <waihong@google.com>
| -rw-r--r-- | zephyr/include/cros/nuvoton/npcx.dtsi | 10 | ||||
| -rw-r--r-- | zephyr/include/cros/nuvoton/npcx7.dtsi | 10 |
2 files changed, 10 insertions, 10 deletions
diff --git a/zephyr/include/cros/nuvoton/npcx.dtsi b/zephyr/include/cros/nuvoton/npcx.dtsi index 743cbf76fc..7b189bf0f0 100644 --- a/zephyr/include/cros/nuvoton/npcx.dtsi +++ b/zephyr/include/cros/nuvoton/npcx.dtsi @@ -128,5 +128,15 @@ label = "FLASH_INTERFACE_UNIT0"; pinctrl-0 = <>; }; + + shi: shi@4000f000 { + compatible = "nuvoton,npcx-cros-shi"; + reg = <0x4000f000 0x120>; + interrupts = <18 1>; + clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL5 1>; + pinctrl-0 = <&altc_shi_sl>; + shi-cs-wui =<&wui_io53>; + label = "SHI"; + }; }; }; diff --git a/zephyr/include/cros/nuvoton/npcx7.dtsi b/zephyr/include/cros/nuvoton/npcx7.dtsi index 5d1b9f4acf..1f757d48ad 100644 --- a/zephyr/include/cros/nuvoton/npcx7.dtsi +++ b/zephyr/include/cros/nuvoton/npcx7.dtsi @@ -19,16 +19,6 @@ label = "DBG"; status = "disabled"; }; - - shi: shi@4000f000 { - compatible = "nuvoton,npcx-cros-shi"; - reg = <0x4000f000 0x120>; - interrupts = <18 1>; - clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL5 1>; - pinctrl-0 = <&altc_shi_sl>; - shi-cs-wui =<&wui_io53>; - label = "SHI"; - }; }; power-states { |