diff options
| author | Bossen WU <bossen.wu@stmicro.corp-partner.google.com> | 2021-07-19 13:57:42 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-07-20 02:31:22 +0000 |
| commit | 43d48363f12aed7635cc079bb7038985c6156a5a (patch) | |
| tree | 3c50b2ef30dc050645bbe807d1adb9903b19e406 | |
| parent | 0f91a4ed8c55e338f287f4d0baec2253c6111b6e (diff) | |
| download | chrome-ec-43d48363f12aed7635cc079bb7038985c6156a5a.tar.gz | |
stm32: change stm32l431 flash layout
Due to increase of RW size, stm32l431 flash layout were change to RO:
124KB, PSTATE: 2KB, RW:130KB
BRANCH=kukui
BUG=b:188117811
TEST=make BOARD=munna; make buidall
Signed-off-by: Bossen WU <bossen.wu@stmicro.corp-partner.google.com>
Change-Id: I8cf2d2dbdc8a2ae5e95d1d54c6672796eb02fc02
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3037292
Reviewed-by: Chen-Tsung Hsieh <chentsung@chromium.org>
Reviewed-by: Ting Shen <phoenixshen@chromium.org>
| -rw-r--r-- | chip/stm32/config-stm32l431.h | 52 | ||||
| -rw-r--r-- | chip/stm32/config_chip.h | 3 |
2 files changed, 54 insertions, 1 deletions
diff --git a/chip/stm32/config-stm32l431.h b/chip/stm32/config-stm32l431.h index fb2eff77ba..7021bc2ce8 100644 --- a/chip/stm32/config-stm32l431.h +++ b/chip/stm32/config-stm32l431.h @@ -23,3 +23,55 @@ /* Number of IRQ vectors on the NVIC */ #define CONFIG_IRQ_COUNT 82 + +/* + * STM32L431 flash layout: + * - RO image starts at the beginning of flash: sector 0 ~ 61 + * - PSTATE immediately follows the RO image: sector 62 + * - RW image starts at 0x1f800: sector 63 + * - Protected region consists of the RO image + PSTATE: sector 0 ~ 62 + * - Unprotected region consists of second half of RW image + * + * PSTATE(2KB) + * | + * (126KB) v (130KB) + * |<-----Protected Region------>|<------Unprotected Region----->| + * |<--------RO image--------->| |<----------RW image----------->| + * 0 (124KB) ^ ^ + * | | + * | 63(2KB sector) + * | + * 62 + * + */ + + + +/* The EC uses one sector to emulate persistent state */ +#define CONFIG_FLASH_PSTATE +#define CONFIG_FW_PSTATE_SIZE CONFIG_FLASH_BANK_SIZE +#define CONFIG_FW_PSTATE_OFF (62 * CONFIG_FLASH_BANK_SIZE) + +#define CONFIG_RO_MEM_OFF 0 +#define CONFIG_RO_STORAGE_OFF 0 +#define CONFIG_RO_SIZE (62 * CONFIG_FLASH_BANK_SIZE) +#define CONFIG_RW_MEM_OFF (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE + \ + CONFIG_FW_PSTATE_SIZE) +#define CONFIG_RW_STORAGE_OFF 0 +#define CONFIG_RW_SIZE (CONFIG_FLASH_SIZE_BYTES - CONFIG_RW_MEM_OFF - \ + CONFIG_RW_STORAGE_OFF) + +#define CONFIG_EC_PROTECTED_STORAGE_OFF 0 +#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RW_MEM_OFF +#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF +#define CONFIG_EC_WRITABLE_STORAGE_SIZE (CONFIG_FLASH_SIZE_BYTES - \ + CONFIG_EC_WRITABLE_STORAGE_OFF) + +#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF +#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE + +/* We map each write protect sector to a bank */ +#define PHYSICAL_BANKS 128 +#define WP_BANK_COUNT 63 +#define PSTATE_BANK 62 +#define PSTATE_BANK_COUNT 1 diff --git a/chip/stm32/config_chip.h b/chip/stm32/config_chip.h index 53f31215ea..b17989a379 100644 --- a/chip/stm32/config_chip.h +++ b/chip/stm32/config_chip.h @@ -88,7 +88,8 @@ #if !defined(CHIP_FAMILY_STM32F4) && \ !defined(CHIP_FAMILY_STM32F7) && \ !defined(CHIP_FAMILY_STM32H7) && \ - !defined(CHIP_VARIANT_STM32F09X) + !defined(CHIP_VARIANT_STM32F09X) && \ + !defined(CHIP_VARIANT_STM32L431X) /* Compute the rest of the flash params from these */ #include "config_std_internal_flash.h" #endif |