diff options
| author | Craig Hesling <hesling@chromium.org> | 2019-12-09 11:46:31 -0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2019-12-16 18:09:07 +0000 |
| commit | d29c928cda0bf730e6d0a5762205b330dea09639 (patch) | |
| tree | 4cffeb1cf5f5250b132f113d1f754c996565033c | |
| parent | c13071f4e5625ac1aee104a7127d712add0c7808 (diff) | |
| download | chrome-ec-d29c928cda0bf730e6d0a5762205b330dea09639.tar.gz | |
stm32f4: Cleanup reset reg constants
This brings no function change.
BRANCH=hatch
BUG=none
TEST=make buildall -j
Change-Id: I9a9363d4771039244ed79408674a598f768075e9
Signed-off-by: Craig Hesling <hesling@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1958846
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
| -rw-r--r-- | chip/stm32/registers-stm32f4.h | 17 |
1 files changed, 9 insertions, 8 deletions
diff --git a/chip/stm32/registers-stm32f4.h b/chip/stm32/registers-stm32f4.h index 452737254a..84fcf1dff1 100644 --- a/chip/stm32/registers-stm32f4.h +++ b/chip/stm32/registers-stm32f4.h @@ -591,17 +591,18 @@ /* Reset causes definitions */ /* Reset causes in RCC CSR register */ #define STM32_RCC_RESET_CAUSE STM32_RCC_CSR -#define RESET_CAUSE_WDG 0x60000000 -#define RESET_CAUSE_SFT 0x10000000 -#define RESET_CAUSE_POR 0x08000000 -#define RESET_CAUSE_PIN 0x04000000 -#define RESET_CAUSE_OTHER 0xfe000000 -#define RESET_CAUSE_RMVF 0x01000000 +#define RESET_CAUSE_WDG (BIT(30)|BIT(29)) +#define RESET_CAUSE_SFT BIT(28) +#define RESET_CAUSE_POR BIT(27) +#define RESET_CAUSE_PIN BIT(26) +#define RESET_CAUSE_OTHER (BIT(31)|BIT(30)|BIT(29)|BIT(28)| \ + BIT(27)|BIT(26)|BIT(25)) +#define RESET_CAUSE_RMVF BIT(24) /* Power cause in PWR CSR register */ #define STM32_PWR_RESET_CAUSE STM32_PWR_CSR +#define RESET_CAUSE_SBF BIT(1) #define STM32_PWR_RESET_CAUSE_CLR STM32_PWR_CR -#define RESET_CAUSE_SBF 0x00000002 -#define RESET_CAUSE_SBF_CLR 0x00000004 +#define RESET_CAUSE_SBF_CLR BIT(2) /* --- Watchdogs --- */ |