diff options
| author | Bill Richardson <wfrichar@chromium.org> | 2016-02-26 17:28:46 -0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2016-02-27 03:25:53 -0800 |
| commit | ee86be472d74c3245c0443171b3552fcbdde8929 (patch) | |
| tree | ef4e423bfe7f379ff9ec1d0c56ef639b28929355 | |
| parent | b6f3e288c175fa6720cb9d67c0935acad3c577bf (diff) | |
| download | chrome-ec-stabilize-7978.B.tar.gz | |
Cr50: SAFE MODE: all GPIOs are inputs for Kevin0stabilize-7978.Bstabilize-7978.18.B
Except for the console UART TX and the SPI slave MISO, this CL
configures all the formerly output GPIOs as inputs. The Cr50
firmware at this point doesn't actually DO anything useful with
the GPIOs that would normally be outputs on the Kevin board (we
don't assert SYS_RESET, or EC_FLASH_SELECT, for example), and the
board *should* be designed so that no important signals like
those just float.
By using this configuration, we're trying to limit the potential
harm done by unexpected schematic changes. Once the system boots,
we should be able to use the SPI bus to update Cr50 to add more
features, such as testing Cr50 GPIOs individually.
BUG=chrome-os-partner:49952
BRANCH=none
TEST=make buildall, run on Cr50 board
Change-Id: I1f0a164e2cd3e4f632b862e33dba69f0dc944322
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/329557
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
| -rw-r--r-- | board/cr50/gpio.inc | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/board/cr50/gpio.inc b/board/cr50/gpio.inc index ab50cc6f6e..451e3075ff 100644 --- a/board/cr50/gpio.inc +++ b/board/cr50/gpio.inc @@ -8,24 +8,24 @@ * Note: Those with interrupt handlers must be declared first. */ /* Pull this low to interrupt the AP */ -GPIO(INT_AP_L, PIN(0, 0), GPIO_ODR_HIGH) +GPIO(INT_AP_L, PIN(0, 0), GPIO_INPUT) /* Use these to take over the AP & EC flash (only when AP & EC are off!) */ -GPIO(EC_FLASH_SELECT, PIN(0, 1), GPIO_OUT_LOW) -GPIO(AP_FLASH_SELECT, PIN(0, 2), GPIO_OUT_LOW) +GPIO(EC_FLASH_SELECT, PIN(0, 1), GPIO_INPUT) +GPIO(AP_FLASH_SELECT, PIN(0, 2), GPIO_INPUT) /* As an input this mirrors EC_WP_L (which is controlled by RBOX, not a GPIO). * As an output it can override EC_WP_L, although why would we? */ GPIO(AP_WP_L, PIN(0, 3), GPIO_INPUT) /* Drive high to reset the EC & AP */ -GPIO(SYS_RST, PIN(0, 4), GPIO_OUT_LOW) +GPIO(SYS_RST, PIN(0, 4), GPIO_INPUT) /* Indicate to EC when CCD is enabled */ -GPIO(CCD_MODE, PIN(0, 5), GPIO_OUT_LOW) +GPIO(CCD_MODE, PIN(0, 5), GPIO_INPUT) /* Battery has a 10K pulldown on its side. We provide the pullup. */ -GPIO(BATT_PRES, PIN(0, 6), GPIO_INPUT | GPIO_PULL_UP) +GPIO(BATT_PRES, PIN(0, 6), GPIO_INPUT) /* Unimplemented signals which we need to emulate for now */ /* TODO(wfrichar): Half the boards don't use this signal. Take it out. */ @@ -53,14 +53,14 @@ PINMUX(GPIO(BATT_PRES), M2, 0) /* UARTs */ PINMUX(FUNC(UART0_TX), A0, DIO_OUTPUT) /* Cr50 console */ PINMUX(FUNC(UART0_RX), A1, DIO_INPUT) -PINMUX(FUNC(UART1_TX), B3, DIO_OUTPUT) /* AP console */ +PINMUX(FUNC(UART1_TX), B3, DIO_INPUT) /* AP console */ PINMUX(FUNC(UART1_RX), B2, DIO_INPUT) -PINMUX(FUNC(UART2_TX), B5, DIO_OUTPUT) /* EC console */ +PINMUX(FUNC(UART2_TX), B5, DIO_INPUT) /* EC console */ PINMUX(FUNC(UART2_RX), B6, DIO_INPUT) /* I2C pins are bi-directional */ -PINMUX(FUNC(I2C0_SCL), B0, DIO_OUTPUT|DIO_INPUT) -PINMUX(FUNC(I2C0_SDA), B1, DIO_OUTPUT|DIO_INPUT) +PINMUX(FUNC(I2C0_SCL), B0, DIO_INPUT) +PINMUX(FUNC(I2C0_SDA), B1, DIO_INPUT) /* Both SPI master and slave buses are wired directly to specific pads * |