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| author | Duncan Laurie <dlaurie@chromium.org> | 2015-08-13 18:49:35 -0700 |
|---|---|---|
| committer | ChromeOS Commit Bot <chromeos-commit-bot@chromium.org> | 2015-08-17 20:15:42 +0000 |
| commit | aa14b36f1890e373424463afc584659b2834dce6 (patch) | |
| tree | cba698773bbc8d79ebf1f3e7555ddbdbea3d47d9 | |
| parent | 5a4ae0c3cd8d88767fce95c21c28b0ba97817b83 (diff) | |
| download | chrome-ec-stabilize-7374.B.tar.gz | |
skylake: Wake from Deep S5 after battery low is deassertedstabilize-7374.B
The system will not wake from Deep S5 if BATLOW# is asserted,
so wait for that to deassert, then pulse the wake pin and wait
for SLP_SUS_L to deassert.
BUG=chrome-os-partner:43545,chrome-os-partner:44079
BRANCH=none
TEST=verified on P2 board
Change-Id: I3b36159b574d418c9b79c478d0a41f753474fa6a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/293595
Reviewed-by: Shawn N <shawnn@chromium.org>
| -rw-r--r-- | power/skylake.c | 23 |
1 files changed, 16 insertions, 7 deletions
diff --git a/power/skylake.c b/power/skylake.c index d0fafb0bc2..54866cb72e 100644 --- a/power/skylake.c +++ b/power/skylake.c @@ -100,7 +100,7 @@ void chipset_reset(int cold_reset) } } -void chipset_thottle_cpu(int throttle) +void chipset_throttle_cpu(int throttle) { if (chipset_in_state(CHIPSET_STATE_ON)) gpio_set_level(GPIO_CPU_PROCHOT, throttle); @@ -192,11 +192,6 @@ enum power_state power_handle_state(enum power_state state) /* Call hooks to initialize PMIC */ hook_notify(HOOK_CHIPSET_PRE_INIT); - if (power_wait_signals(IN_PCH_SLP_SUS_DEASSERTED)) { - chipset_force_shutdown(); - return POWER_G3; - } - #ifndef BOARD_KUNIMITSU /* * Allow up to 1s for charger to be initialized, in case @@ -216,10 +211,24 @@ enum power_state power_handle_state(enum power_state state) } /* Allow AP to power on */ - gpio_set_level(GPIO_PMIC_SLP_SUS_L, 1); gpio_set_level(GPIO_PCH_BATLOW_L, 1); + + /* Assert wake pin to PCH to wake from Deep S5 */ + if (gpio_get_level(GPIO_PCH_WAKE_L) == 1) { + gpio_set_level(GPIO_PCH_WAKE_L, 0); + udelay(65); + gpio_set_level(GPIO_PCH_WAKE_L, 1); + } #endif + if (power_wait_signals(IN_PCH_SLP_SUS_DEASSERTED)) { + chipset_force_shutdown(); + return POWER_G3; + } + +#ifndef BOARD_KUNIMITSU + gpio_set_level(GPIO_PMIC_SLP_SUS_L, 1); +#endif return POWER_S5; case POWER_S5S3: |