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authorShawn Nematbakhsh <shawnn@chromium.org>2015-06-18 15:31:21 -0700
committerChromeOS Commit Bot <chromeos-commit-bot@chromium.org>2015-06-20 06:07:51 +0000
commitd5c318329abbec47e30fdade870db421c021b826 (patch)
tree073d0447e972be50c60876917b61953fed1548ad
parent104f811e6730e129a98fac6fc3941bbe0d0e857f (diff)
downloadchrome-ec-stabilize-7199.B.tar.gz
power: skylake: Delay 10ms before deasserting PCH_RSMRST_Lstabilize-7199.B
According to spec, RSMRST shouldn't be deasserted until 10ms after power signals become active. BUG=chrome-os-partner:41556 TEST=Manual on Glados. Verify that AP boots to S0 on power-on, goes to G3 on apshutdown, and back to S0 on powerbtn. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I0acc897fff7c18ad83fc87734569ec7639ae5cf4 Reviewed-on: https://chromium-review.googlesource.com/280571 Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
-rw-r--r--power/skylake.c18
1 files changed, 17 insertions, 1 deletions
diff --git a/power/skylake.c b/power/skylake.c
index 515c77697e..7ae1a3cc43 100644
--- a/power/skylake.c
+++ b/power/skylake.c
@@ -118,7 +118,23 @@ enum power_state power_chipset_init(void)
enum power_state power_handle_state(enum power_state state)
{
- gpio_set_level(GPIO_PCH_RSMRST_L, gpio_get_level(GPIO_RSMRST_L_PGOOD));
+ /*
+ * Pass through RSMRST asynchronously, as PCH may not react
+ * immediately to power changes.
+ */
+ int rsmrst_in = gpio_get_level(GPIO_RSMRST_L_PGOOD);
+ int rsmrst_out = gpio_get_level(GPIO_PCH_RSMRST_L);
+
+ if (rsmrst_in != rsmrst_out) {
+ /*
+ * Wait at least 10ms between power signals going high
+ * and deasserting RSMRST to PCH.
+ */
+ if (rsmrst_in)
+ msleep(10);
+ gpio_set_level(GPIO_PCH_RSMRST_L, rsmrst_in);
+ CPRINTS("RSMRST: %d", rsmrst_in);
+ }
switch (state) {
case POWER_G3: