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| author | Alexandru M Stan <amstan@chromium.org> | 2014-12-16 15:23:57 -0800 |
|---|---|---|
| committer | chrome-internal-fetch <chrome-internal-fetch@google.com> | 2014-12-18 00:46:33 +0000 |
| commit | 2d25b40b758445fa29fa003534817acc1244e132 (patch) | |
| tree | 788956abe539421d04855b10e14a5a0ad69a3d49 | |
| parent | a0395b1ea9941db5febc7fe6602b0c108644901a (diff) | |
| download | chrome-ec-stabilize-6592.B.tar.gz | |
cortex-m0: NVIC: Fix macro for the priority registersstabilize-6592.B
We actually need to care about x, the PRI register is actually a list of
registers (and we have code that uses some of the later ones).
BUG=None, discovered while chrome-os-partner:33451
TEST=Change priorities of irqs(like UART over GPIO(spi_event)), note how they
actually work and override each other as told
BRANCH=None
Change-Id: I9f5bf7ba9d4211f782ff260fbce17deb7c53a31f
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/236087
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
| -rw-r--r-- | core/cortex-m0/cpu.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/core/cortex-m0/cpu.h b/core/cortex-m0/cpu.h index 8b874d9688..52e46551b0 100644 --- a/core/cortex-m0/cpu.h +++ b/core/cortex-m0/cpu.h @@ -18,7 +18,7 @@ #define CPU_NVIC_DIS(x) CPUREG(0xe000e180) #define CPU_NVIC_UNPEND(x) CPUREG(0xe000e280) #define CPU_NVIC_ISPR(x) CPUREG(0xe000e200) -#define CPU_NVIC_PRI(x) CPUREG(0xe000e400) +#define CPU_NVIC_PRI(x) CPUREG(0xe000e400 + 4 * (x)) /* System Control Block */ |