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authorKyle Lin <kylelinck@google.com>2022-07-07 11:20:50 +0000
committerChromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com>2022-07-08 04:45:29 +0000
commit97e7110972c274e1b8fbe804030f31422755e4fc (patch)
tree04263ecd0f9b5d90a013b88866080a8c03cc721d
parent63f8aface4fc2a59a3125e4ffd0ad459b326576b (diff)
downloadchrome-ec-stabilize-14964.B-main.tar.gz
pdeval-stm32f072: Update for inclusive terminologystabilize-14964.B-main
Replace 'slave' with 'target' for more inclusive terminology. BUG=none BRANCH=none TEST=none Change-Id: I290a3616ddfdcd9993acfd1fbb2eb585d07c1f54 Signed-off-by: Kyle Lin <kylelinck@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3750968 Reviewed-by: Marco Chen <marcochen@chromium.org>
-rw-r--r--board/pdeval-stm32f072/PD_evaluation.md4
1 files changed, 2 insertions, 2 deletions
diff --git a/board/pdeval-stm32f072/PD_evaluation.md b/board/pdeval-stm32f072/PD_evaluation.md
index 4f1c8636c6..fd4763a849 100644
--- a/board/pdeval-stm32f072/PD_evaluation.md
+++ b/board/pdeval-stm32f072/PD_evaluation.md
@@ -43,12 +43,12 @@ also need to create/delete the corresponding `PD_Cx` tasks in
[board/pdeval-stm32f072/ec.tasklist](ec.tasklist).
By default, the firmware is using I2C1 with SCL/SDA on pins PB6 and PB7, running
-with a 100kHz clock, and tries to talk to TCPCs at i2c slave addresses 0x9c and
+with a 100kHz clock, and tries to talk to TCPCs at i2c target addresses 0x9c and
0x9e. To change the pins or speed, you need to edit `i2c_ports` in
[board/pdeval-stm32f072/board.c](board.c), update `I2C_PORT_TCPC` in
[board/pdeval-stm32f072/board.h](board.h) with the right controller number, and
change the pin mux in [board/pdeval-stm32f072/gpio.inc](gpio.inc). To change
-TCPC i2c slave addresses, update `TCPC1_I2C_ADDR` and `TCPC2_I2C_ADDR` in
+TCPC i2c target addresses, update `TCPC1_I2C_ADDR` and `TCPC2_I2C_ADDR` in
[board/pdeval-stm32f072/board.h](board.h).
The I2C bus needs pull-up resistors on SCL/SDA. If your setup doesn't have