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| author | Bhanu Prakash Maiya <bhanumaiya@chromium.org> | 2021-03-01 11:53:35 -0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-03-03 23:23:39 +0000 |
| commit | bcb0249efd09fa9fc844f047e87adad99d139149 (patch) | |
| tree | 60a1350ecb958bf013b8e2551650081da64ce077 | |
| parent | 6b59de88156fc1ff447b29a80d25feb0441bfc48 (diff) | |
| download | chrome-ec-stabilize-13729.57.B-main.tar.gz | |
flash_fp_mcu: Fix Zork's gpiochip base from 320 -> 256stabilize-13729.57.B-mainstabilize-13729.56.B-mainstabilize-13729.49.B-mainstabilize-13729.45.B-main
On Zork's SoC change was caused by changing the amount of reserved
space for GPIO banks from 0x300 to 0x400. This resulted in base change.
Previous: 512 - 192 = 320
Current: 512 - 256 = 256
BRANCH=none
BUG=b:181349369
TEST=1. Run flash_fp_mcu on Zork device with FW 13434.212
Signed-off-by: Bhanu Prakash Maiya <bhanumaiya@google.com>
Change-Id: Ied4a5fd9281d59f1bfa30a4ee9677f9a0a11387e
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2727865
Commit-Queue: Tom Hughes <tomhughes@chromium.org>
Reviewed-by: Tom Hughes <tomhughes@chromium.org>
| -rw-r--r-- | util/flash_fp_mcu | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/util/flash_fp_mcu b/util/flash_fp_mcu index cb65b20544..1d7f51da91 100644 --- a/util/flash_fp_mcu +++ b/util/flash_fp_mcu @@ -369,17 +369,17 @@ config_volteer() { } config_zork() { - check_gpio_chip_exists "gpiochip320" + check_gpio_chip_exists "gpiochip256" readonly TRANSPORT="UART" readonly DEVICE="/dev/ttyS1" - # FPMCU RST_ODL is on AGPIO 11 = 320 + 11 = 331 - readonly GPIO_NRST=331 - # FPMCU BOOT0 is on AGPIO 69 = 320 + 69 = 389 - readonly GPIO_BOOT0=389 - # FPMCU PWR_EN is on AGPIO 32 = 320 + 32 = 352, but should not be + # FPMCU RST_ODL is on AGPIO 11 = 256 + 11 = 267 + readonly GPIO_NRST=267 + # FPMCU BOOT0 is on AGPIO 69 = 256 + 69 = 325 + readonly GPIO_BOOT0=325 + # FPMCU PWR_EN is on AGPIO 32 = 256 + 32 = 288, but should not be # necessary for flashing. Set invalid value. readonly GPIO_PWREN=-1 } |