diff options
| author | Dino Li <Dino.Li@ite.com.tw> | 2020-04-07 15:51:36 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-04-28 06:17:28 +0000 |
| commit | 6430b8b4536758473cfe4c71ef6afaeaeecc9c63 (patch) | |
| tree | 02c4331bd387d5e7c972bba378d3e4535f3bda83 | |
| parent | 156d34f4a27750a512f78894068cdd82a950192b (diff) | |
| download | chrome-ec-6430b8b4536758473cfe4c71ef6afaeaeecc9c63.tar.gz | |
it8xxx2: lpc/espi: mapping host I/O cycle to h2ram section
On it8xxx2 series, host I/O cycles are mapped to the first block
(0x80080000~0x80080fff) at default, and it is adjustable.
We should set the correct offset depends on the base address of
H2RAM section, so EC will be able to receive/handle commands from
host.
BUG=b:133460224
BRANCH=none
TEST=not yet. just check the register setting is correct (I/O cycles
are mapped to 0x80081000~0x80081fff) after EC initialization.
Change-Id: Ib9085181917712bf735b83487720f12c8cd7ca31
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2038223
Reviewed-by: Jett Rink <jettrink@chromium.org>
| -rw-r--r-- | chip/it83xx/config_chip_it8xxx2.h | 4 | ||||
| -rw-r--r-- | chip/it83xx/lpc.c | 11 | ||||
| -rw-r--r-- | chip/it83xx/registers.h | 1 |
3 files changed, 16 insertions, 0 deletions
diff --git a/chip/it83xx/config_chip_it8xxx2.h b/chip/it83xx/config_chip_it8xxx2.h index d2a54eac47..a14a87ae03 100644 --- a/chip/it83xx/config_chip_it8xxx2.h +++ b/chip/it83xx/config_chip_it8xxx2.h @@ -68,6 +68,8 @@ #define IT83XX_GPIO_1P8V_PIN_EXTENDED /* All GPIOs support interrupt on rising, falling, and either edge. */ #define IT83XX_GPIO_INT_FLEXIBLE +/* Remap host I/O cycles to base address of H2RAM section. */ +#define IT83XX_H2RAM_REMAPPING /* Enable detect type-c plug in interrupt. */ #define IT83XX_INTC_PLUG_IN_SUPPORT /* Chip IT83202BX actually has TCPC physical port count. */ @@ -111,6 +113,8 @@ #define IT83XX_GPIO_H7_DEFAULT_OUTPUT_LOW /* All GPIOs support interrupt on rising, falling, and either edge. */ #define IT83XX_GPIO_INT_FLEXIBLE +/* Remap host I/O cycles to base address of H2RAM section. */ +#define IT83XX_H2RAM_REMAPPING /* Enable detect type-c plug in interrupt. */ #define IT83XX_INTC_PLUG_IN_SUPPORT /* Wake up CPU from low power mode even if interrupts are disabled */ diff --git a/chip/it83xx/lpc.c b/chip/it83xx/lpc.c index cd4f9ad608..0431019101 100644 --- a/chip/it83xx/lpc.c +++ b/chip/it83xx/lpc.c @@ -602,6 +602,17 @@ static void lpc_init(void) memset(lpc_host_args, 0, sizeof(*lpc_host_args)); /* Host LPC I/O cycle mapping to RAM */ +#ifdef IT83XX_H2RAM_REMAPPING + /* + * On it8xxx2 series, host I/O cycles are mapped to the first block + * (0x80080000~0x80080fff) at default, and it is adjustable. + * We should set the correct offset depends on the base address of + * H2RAM section, so EC will be able to receive/handle commands from + * host. + */ + IT83XX_GCTRL_H2ROFSR = + (CONFIG_H2RAM_BASE - CONFIG_RAM_BASE) / CONFIG_H2RAM_SIZE; +#endif /* * bit[4], H2RAM through LPC IO cycle. * bit[1], H2RAM window 1 enabled. diff --git a/chip/it83xx/registers.h b/chip/it83xx/registers.h index b5bcd59ca0..d30d8c754e 100644 --- a/chip/it83xx/registers.h +++ b/chip/it83xx/registers.h @@ -974,6 +974,7 @@ enum clock_gate_offsets { #define IT83XX_GCTRL_SSCR REG8(IT83XX_GCTRL_BASE+0x4A) #define IT83XX_GCTRL_ETWDUARTCR REG8(IT83XX_GCTRL_BASE+0x4B) #define IT83XX_GCTRL_WMCR REG8(IT83XX_GCTRL_BASE+0x4C) +#define IT83XX_GCTRL_H2ROFSR REG8(IT83XX_GCTRL_BASE+0x53) /* bit[0] = 0 or 1 : disable or enable ETWD hardware reset */ #define ETWD_HW_RST_EN BIT(0) #define IT83XX_GCTRL_RVILMCR0 REG8(IT83XX_GCTRL_BASE+0x5D) |