From 835f951f295e34d3579f1f9f2e1f11f0c3b085cd Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Sat, 3 Sep 2022 17:55:08 -0600 Subject: mb/google/skyrim: Add initial APCB release for skyrim board This is a data file that gives configuration data to AMD's ABL, the PSP AGESA Bootloader. As there is no code, there is no ABI, license, or version number. Specified contents describing memory initialization: Memory is 2 channel, LPDDR5/LPDDR5x The GPIOs to use for the SPD identifiers: Bit 0: GPIO 144 Bit 1: GPIO 85 Bit 2: GPIO 79 Bit 3: GPIO 91 Contains 16 slots for possible SPD entries. UMA size is set to 64MB. eSPI I/O range address and size configuration. MEMRESTORECTL is enabled to leverage MRC Cache. Signed-off-by: Martin Roth Change-Id: Ia72eb4bd3ea74d813cad34e06fb0452814460144 --- mainboard/google/skyrim/APCB_MDN_D5.bin | Bin 0 -> 39204 bytes mainboard/google/skyrim/Release.txt | 25 +++++++++++++++++++++++++ 2 files changed, 25 insertions(+) create mode 100644 mainboard/google/skyrim/APCB_MDN_D5.bin create mode 100644 mainboard/google/skyrim/Release.txt diff --git a/mainboard/google/skyrim/APCB_MDN_D5.bin b/mainboard/google/skyrim/APCB_MDN_D5.bin new file mode 100644 index 0000000..2e58266 Binary files /dev/null and b/mainboard/google/skyrim/APCB_MDN_D5.bin differ diff --git a/mainboard/google/skyrim/Release.txt b/mainboard/google/skyrim/Release.txt new file mode 100644 index 0000000..fb5149d --- /dev/null +++ b/mainboard/google/skyrim/Release.txt @@ -0,0 +1,25 @@ +Files: + APCB_MDN_D5.bin - Data only - No license, ABI or Version # + +2022-09-02: Initial public release: +- Add APCB_MDN_D5.bin + This is a data file that gives configuration data to AMD's ABL, + the PSP AGESA Bootloader. As there is no code, there is no ABI, + license, or version number. + + Specified contents describing memory initialization: + Memory is 2 channel, LPDDR5/LPDDR5x + + The GPIOs to use for the SPD identifiers: + Bit 0: GPIO 144 + Bit 1: GPIO 85 + Bit 2: GPIO 79 + Bit 3: GPIO 91 + + Contains 16 slots for possible SPD entries. + UMA size is set to 64MB. + eSPI I/O range address and size configuration. + MEMRESTORECTL is enabled to leverage MRC Cache. + +sha1sum: +a91237472d662b8035450e19f118adaece4748f4 APCB_MDN_D5.bin -- cgit v1.2.1