blob: 34c281dc8197fe941c7ceb5205576304b3a9c10c (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
|
/*
* Copyright (c) 2021, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <mmio.h>
#include <mt_cpu_pm.h>
#include <mt_cpu_pm_mbox.h>
#include <platform_def.h>
#include <sspm_reg.h>
#ifdef MCDI_TINYSYS_MBOX_SHARE_SRAM
struct cpu_pm_mbox {
unsigned int ap_ready;
unsigned int reserved1;
unsigned int reserved2;
unsigned int reserved3;
unsigned int pwr_ctrl_en;
unsigned int l3_cache_mode;
unsigned int buck_mode;
unsigned int armpll_mode;
unsigned int task_sta;
unsigned int reserved9;
unsigned int reserved10;
unsigned int reserved11;
unsigned int wakeup_cpu;
};
struct cpu_pm_mbox *_cpu_pm_box = (struct cpu_pm_mbox *)SSPM_MBOX_3_BASE;
#endif
void mtk_set_cpu_pm_pll_mode(unsigned int mode)
{
#ifdef MCDI_TINYSYS_MBOX_SHARE_SRAM
if (_cpu_pm_box) {
_cpu_pm_box->armpll_mode = mode;
}
#endif
}
int mtk_get_cpu_pm_pll_mode(void)
{
#ifdef MCDI_TINYSYS_MBOX_SHARE_SRAM
if (!_cpu_pm_box) {
return 0;
}
return _cpu_pm_box->armpll_mode;
#endif
}
void mtk_set_cpu_pm_buck_mode(unsigned int mode)
{
#ifdef MCDI_TINYSYS_MBOX_SHARE_SRAM
if (_cpu_pm_box) {
_cpu_pm_box->buck_mode = mode;
}
#endif
}
int mtk_get_cpu_pm_buck_mode(void)
{
#ifdef MCDI_TINYSYS_MBOX_SHARE_SRAM
if (!_cpu_pm_box) {
return 0;
}
return _cpu_pm_box->buck_mode;
#endif
}
void mtk_set_cpu_pm_preffered_cpu(unsigned int cpuid)
{
#ifdef MCDI_TINYSYS_MBOX_SHARE_SRAM
if (_cpu_pm_box) {
_cpu_pm_box->wakeup_cpu = cpuid;
}
#endif
}
int mtk_set_cpu_pm_mbox_addr(uint64_t phy_addr)
{
#ifdef MCDI_TINYSYS_MBOX_SHARE_SRAM
if (_cpu_pm_box || (phy_addr == 0)) {
return -1;
}
_cpu_pm_box = (struct cpu_pm_mbox *)(MTK_SSPM_BASE + phy_addr);
#endif
return 0;
}
|
