diff options
| author | Garmin.Chang <Garmin.Chang@mediatek.com> | 2021-11-14 10:14:45 +0800 |
|---|---|---|
| committer | Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> | 2021-12-22 18:06:53 +0800 |
| commit | 06cb65ef079941d0525dca75dd0e110e9330906d (patch) | |
| tree | 86432fe86a364114f5815beb941d93fa97caf833 /plat/mediatek/mt8186/drivers/mcdi/mt_cpu_pm_mbox_sspm.c | |
| parent | 1da57e54b2270b3b49710afa6fd947b01d61b261 (diff) | |
| download | arm-trusted-firmware-06cb65ef079941d0525dca75dd0e110e9330906d.tar.gz | |
feat(plat/mediatek/mt8186): add MCDI drivers
Add MCDI related drivers to handle CPU powered on/off in CPU suspend.
TEST=build pass
BUG=b:202871018
Change-Id: I85aaaf3a0e992a39d17c58f3d9d5ff1b5770f748
Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
Diffstat (limited to 'plat/mediatek/mt8186/drivers/mcdi/mt_cpu_pm_mbox_sspm.c')
| -rw-r--r-- | plat/mediatek/mt8186/drivers/mcdi/mt_cpu_pm_mbox_sspm.c | 90 |
1 files changed, 90 insertions, 0 deletions
diff --git a/plat/mediatek/mt8186/drivers/mcdi/mt_cpu_pm_mbox_sspm.c b/plat/mediatek/mt8186/drivers/mcdi/mt_cpu_pm_mbox_sspm.c new file mode 100644 index 000000000..34c281dc8 --- /dev/null +++ b/plat/mediatek/mt8186/drivers/mcdi/mt_cpu_pm_mbox_sspm.c @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2021, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <mmio.h> +#include <mt_cpu_pm.h> +#include <mt_cpu_pm_mbox.h> +#include <platform_def.h> +#include <sspm_reg.h> + +#ifdef MCDI_TINYSYS_MBOX_SHARE_SRAM +struct cpu_pm_mbox { + unsigned int ap_ready; + unsigned int reserved1; + unsigned int reserved2; + unsigned int reserved3; + unsigned int pwr_ctrl_en; + unsigned int l3_cache_mode; + unsigned int buck_mode; + unsigned int armpll_mode; + unsigned int task_sta; + unsigned int reserved9; + unsigned int reserved10; + unsigned int reserved11; + unsigned int wakeup_cpu; +}; + +struct cpu_pm_mbox *_cpu_pm_box = (struct cpu_pm_mbox *)SSPM_MBOX_3_BASE; +#endif + +void mtk_set_cpu_pm_pll_mode(unsigned int mode) +{ +#ifdef MCDI_TINYSYS_MBOX_SHARE_SRAM + if (_cpu_pm_box) { + _cpu_pm_box->armpll_mode = mode; + } +#endif +} + +int mtk_get_cpu_pm_pll_mode(void) +{ +#ifdef MCDI_TINYSYS_MBOX_SHARE_SRAM + if (!_cpu_pm_box) { + return 0; + } + return _cpu_pm_box->armpll_mode; +#endif +} + +void mtk_set_cpu_pm_buck_mode(unsigned int mode) +{ +#ifdef MCDI_TINYSYS_MBOX_SHARE_SRAM + if (_cpu_pm_box) { + _cpu_pm_box->buck_mode = mode; + } +#endif +} + +int mtk_get_cpu_pm_buck_mode(void) +{ +#ifdef MCDI_TINYSYS_MBOX_SHARE_SRAM + if (!_cpu_pm_box) { + return 0; + } + return _cpu_pm_box->buck_mode; +#endif +} + +void mtk_set_cpu_pm_preffered_cpu(unsigned int cpuid) +{ +#ifdef MCDI_TINYSYS_MBOX_SHARE_SRAM + if (_cpu_pm_box) { + _cpu_pm_box->wakeup_cpu = cpuid; + } +#endif +} + +int mtk_set_cpu_pm_mbox_addr(uint64_t phy_addr) +{ +#ifdef MCDI_TINYSYS_MBOX_SHARE_SRAM + if (_cpu_pm_box || (phy_addr == 0)) { + return -1; + } + + _cpu_pm_box = (struct cpu_pm_mbox *)(MTK_SSPM_BASE + phy_addr); +#endif + return 0; +} |