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path: root/plat/intel/soc/agilex
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* intel: mailbox: Ensure time out duration is predictiveChee Hong Ang2020-10-272-2/+4
* intel: clear 'PLAT_SEC_ENTRY' in early platform setupChee Hong Ang2020-10-241-2/+4
* intel: platform: Include GICv2 makefileAbdul Halim, Muhammad Hadi Asyrafi2020-08-191-4/+8
* plat: intel: Add FPGAINTF configuration to when configuring pinmuxTien Hock Loh2020-06-081-0/+8
* plat: intel: set DRVSEL and SMPLSEL for DWMMCTien Hock Loh2020-06-085-0/+30
* plat: intel: Fix clock configuration bugsTien Hock Loh2020-06-081-34/+42
* Merge "intel: Enable EMAC PHY in Intel FPGA platform" into integrationSandrine Bailleux2020-02-282-4/+7
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| * intel: Enable EMAC PHY in Intel FPGA platformTien Hock, Loh2020-02-252-4/+7
* | 16550: Use generic console_t data structureAndre Przywara2020-02-252-2/+2
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* Merge "intel: Change boot source selection" into integrationSandrine Bailleux2020-02-122-2/+2
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| * intel: Change boot source selectionHadi Asyrafi2020-02-032-2/+2
* | intel: Extend SiP service to support mailbox's RSUHadi Asyrafi2020-02-051-0/+3
* | intel: agilex: Enable uboot BL31 loadingHadi Asyrafi2020-01-291-8/+24
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* intel: Add function to check fpga readinessHadi Asyrafi2020-01-161-1/+3
* intel: Add bridge control for FPGA reconfigHadi Asyrafi2020-01-161-0/+1
* intel: System Manager refactoringHadi Asyrafi2020-01-166-198/+14
* intel: Refactor reset manager driverHadi Asyrafi2020-01-165-234/+3
* intel: Enable bridge access in Intel platformHadi Asyrafi2020-01-165-5/+81
* intel: Modify non secure access functionHadi Asyrafi2020-01-163-1/+9
* Merge "intel: Fix memory calibration" into integrationManish Pandey2020-01-141-4/+3
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| * intel: Fix memory calibrationHadi Asyrafi2019-12-301-4/+3
* | Remove redundant declarations.Madhukar Pappireddy2020-01-081-1/+0
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* intel: Refactor common platform code [5/5]Hadi Asyrafi2019-11-283-25/+16
* intel: Refactor common platform code [4/5]Hadi Asyrafi2019-11-283-578/+2
* intel: Refactor common platform code [3/5]Hadi Asyrafi2019-11-286-412/+5
* intel: Refactor common platform code [2/5]Hadi Asyrafi2019-11-284-230/+2
* intel: Refactor common platform code [1/5]Hadi Asyrafi2019-11-2810-343/+33
* Invalidate dcache build option for bl2 entry at EL3Hadi Asyrafi2019-09-121-0/+1
* intel: agilex: Fix psci power domain offHadi Asyrafi2019-09-121-8/+2
* Merge "intel: agilex: Clear PLL lostlock bypass mode" into integrationPaul Beesley2019-08-282-0/+13
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| * intel: agilex: Clear PLL lostlock bypass modeHadi Asyrafi2019-08-192-0/+13
* | intel: agilex: HMC driver calculate DDR sizeHadi Asyrafi2019-08-191-10/+8
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* Merge "intel: agilex: Fix memory controller driver" into integrationPaul Beesley2019-08-152-11/+22
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| * intel: agilex: Fix memory controller driverHadi Asyrafi2019-08-152-11/+22
* | intel: agilex: Fix reliance on hard coded clock informationHadi Asyrafi2019-08-145-78/+159
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* Merge changes from topic "intel-plat-refactor" into integrationSandrine Bailleux2019-08-0711-464/+11
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| * intel: Platform common code refactorHadi Asyrafi2019-08-077-241/+6
| * intel: Platform common code refactorHadi Asyrafi2019-08-015-223/+5
* | intel: agilex: Fix BL31 memory mappingHadi Asyrafi2019-07-301-1/+1
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* intel: agilex: Fix build errorAmbroise Vincent2019-07-241-1/+3
* intel: Adds support for Agilex platformHadi Asyrafi2019-07-1731-0/+4002
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