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* feat(libc): add %c to printf/snprintfMaksims Svecovs2023-05-112-2/+11
| | | | | | | | Adds %c support for printf and snprintf to print one character. Required by most recent MbedTLS 3.4.0. Change-Id: I4d9b2725127a929d58946353324f99ff22b3b28b Signed-off-by: Maksims Svecovs <maksims.svecovs@arm.com>
* feat(compiler-rt): update source filesMaksims Svecovs2023-05-112-2/+2
| | | | | | | | Update the compiler-rt source files to the tip of the llvm-project [1] [1]: https://github.com/llvm/llvm-project/commit/d9683a7 Change-Id: Icec9ec73094a2b39b0240fc8253c36e7485d3a98 Signed-off-by: Maksims Svecovs <maksims.svecovs@arm.com>
* chore(libfdt): update to v1.7.0 source filesMaksims Svecovs2023-05-111-8/+12
| | | | | | | | | Update libfdt to source files from v1.7.0 release. Upstream commit: https://github.com/dgibson/dtc/commit/039a99414e778332d8f9c04cbd3072e1dcc62798 Change-Id: I7e0475d2ddb819691f476e1753d1c899f8d7c278 Signed-off-by: Maksims Svecovs <maksims.svecovs@arm.com>
* feat(optee): add device tree for coreboot tableJeffrey Kardatzke2023-05-111-0/+10
| | | | | | | | | | | This adds creation of a device tree that will be passed to OP-TEE. Currently that device tree only contains the coreboot table per the Linux coreboot device tree specification. This device tree is then passed to OP-TEE so it can extract the CBMEM console information from the coreboot table for logging purposes. Signed-off-by: Jeffrey Kardatzke <jkardatzke@google.com> Change-Id: I6a26d335e16f7226018c56ad571cca77b81b0f6a
* Merge "fix(psci): do not panic on illegal MPIDR" into integrationManish Pandey2023-05-102-6/+6
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| * fix(psci): do not panic on illegal MPIDRAndre Przywara2023-05-032-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 66327414fb1e ("fix(psci): potential array overflow with cpu on") changed an assert in the PSCI library's psci_cpu_on_start() function to a runtime error message, followed by a panic. This does not seem right for two reasons: - We must not panic() triggered by conditions influenced by lower EL callers. If non-secure world provides illegal arguments to a PSCI call, we can easily detect this and return -PSCI_E_INVALID_PARAMS, as the PSCI spec demands. In fact this is done already, which brings us to the next reason: - psci_cpu_on_start() is effectively a function private to the PSCI library: its prototype is in psci_private.h. It's just not static because it lives in a different code file from the main PSCI code. We check for illegal MPID values already in psci_cpu_on(), and return an error value to the caller, as we should. This function is the ONLY caller of psci_cpu_on_start(), so there is no way we get an illegal target_cpu argument into this function. An assert() is thus the proper way to check for this. Mostly revert the patch mentioned above, just extending the assert so that it does also check for not exceeding the array boundaries. To harden the code, add a check against PLATFORM_MAX_CORE_COUNT in psci_validate_mpidr(), and return with the proper PSCI error code if this number is exceeded. This also fixes the sun50i_a64 build with DEBUG=1, which exceeded an SRAM limit due to the error message. Change-Id: I48fc58d96b0173da5b934750f4cadf7884ef5e42 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* | Merge "fix(pmu): unconditionally save PMCR_EL0" into integrationManish Pandey2023-05-101-60/+1
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| * | fix(pmu): unconditionally save PMCR_EL0Boyan Karatotev2023-05-051-60/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reading back a RES0 bit does not necessarily mean it will be read as 0. The Arm ARM explicitly warns against doing this. The PMU initialisation code tries to set such bits to 1 (in MDCR_EL3) regardless of whether they are in use or are RES0, checking their value could be wrong and PMCR_EL0 might not end up being saved. Save PMCR_EL0 unconditionally to prevent this. Remove the security state change as the outgoing state is not relevant to what the root world context should look like. Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com> Change-Id: Id43667d37b0e2da3ded0beaf23fa0d4f9013f470
* | | Merge changes I1bfa797e,I0ec7a70e into integrationManish Pandey2023-05-097-7/+7
|\ \ \ | | | | | | | | | | | | | | | | | | | | * changes: fix(tree): correct some typos fix(rockchip): use semicolon instead of comma
| * | | fix(tree): correct some typosElyes Haouas2023-05-097-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | found using codespell (https://github.com/codespell-project/codespell). Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I1bfa797e3460adddeefa916bb68e22beddaf6373
* | | | Merge changes from topic "mp/feat_ras" into integrationManish Pandey2023-05-092-36/+19
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | * changes: refactor(cpufeat): enable FEAT_RAS for FEAT_STATE_CHECKED refactor(ras): replace RAS_EXTENSION with FEAT_RAS
| * | | | refactor(cpufeat): enable FEAT_RAS for FEAT_STATE_CHECKEDAndre Przywara2023-05-092-35/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At the moment we only support FEAT_RAS to be either unconditionally compiled in, or to be not supported at all. Add support for runtime detection (FEAT_RAS=2), by splitting is_armv8_2_feat_ras_present() into an ID register reading function and a second function to report the support status. That function considers both build time settings and runtime information (if needed), and is used before we access RAS related registers. Also move the context saving code from assembly to C, and use the new is_feat_ras_supported() function to guard its execution. Change the FVP platform default to the now supported dynamic option (=2), so the right decision can be made by the code at runtime. Change-Id: I30498f72fd80b136850856244687400456a03d0e Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
| * | | | refactor(ras): replace RAS_EXTENSION with FEAT_RASManish Pandey2023-05-092-8/+8
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current usage of RAS_EXTENSION in TF-A codebase is to cater for two things in TF-A : 1. Pull in necessary framework and platform hooks for Firmware first handling(FFH) of RAS errors. 2. Manage the FEAT_RAS extension when switching the worlds. FFH means that all the EAs from NS are trapped in EL3 first and signaled to NS world later after the first handling is done in firmware. There is an alternate way of handling RAS errors viz Kernel First handling(KFH). Tying FEAT_RAS to RAS_EXTENSION build flag was not correct as the feature is needed for proper handling KFH in as well. This patch breaks down the RAS_EXTENSION flag into a flag to denote the CPU architecture `ENABLE_FEAT_RAS` which is used in context management during world switch and another flag `RAS_FFH_SUPPORT` to pull in required framework and platform hooks for FFH. Proper support for KFH will be added in future patches. BREAKING CHANGE: The previous RAS_EXTENSION is now deprecated. The equivalent functionality can be achieved by the following 2 options: - ENABLE_FEAT_RAS - RAS_FFH_SUPPORT Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: I1abb9ab6622b8f1b15712b12f17612804d48a6ec
* | | | Merge changes from topic "srm/Errata_ABI_El3" into integrationMadhukar Pappireddy2023-05-091-0/+43
|\ \ \ \ | |_|/ / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | * changes: docs(errata_abi): document the errata abi changes feat(fvp): enable errata management interface fix(cpus): workaround platforms non-arm interconnect refactor(errata_abi): factor in non-arm interconnect feat(errata_abi): errata management firmware interface
| * | | fix(cpus): workaround platforms non-arm interconnectSona Mathew2023-05-051-0/+43
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The workarounds for these below mentioned errata are not implemented in EL3, but the flags can be enabled/disabled at a platform level based on arm/non-arm interconnect IP. The ABI helps assist the Kernel in the process of mitigation for the following errata: Cortex-A715: erratum 2701951 Neoverse V2: erratum 2719103 Cortex-A710: erratum 2701952 Cortex-X2: erratum 2701952 Neoverse N2: erratum 2728475 Neoverse V1: erratum 2701953 Cortex-A78: erratum 2712571 Cortex-A78AE: erratum 2712574 Cortex-A78C: erratum 2712575 EL3 provides an appropriate return value via errata ABI when the kernel makes an SMC call using the EM_CPU_ERRATUM_FEATURES FID with the appropriate erratum ID. Change-Id: I35bd69d812dba37410dd8bc2bbde20d4955b0850 Signed-off-by: Sona Mathew <SonaRebecca.Mathew@arm.com>
* | | refactor(cm): make SVE and SME build dependencies logicalBoyan Karatotev2023-05-052-23/+21
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, enabling SME forces SVE off. However, the SME enablement requires SVE to be enabled, which is reflected in code. This is the opposite of what the build flags require. Further, the few platforms that enable SME also explicitly enable SVE. Their platform.mk runs after the defaults.mk file so this override never materializes. As a result, the override is only present on the commandline. Change it to something sensible where if SME is on then code can rely on SVE being on too. Do this with a check in the Makefile as it is the more widely used pattern. This maintains all valid use cases but subtly changes corner cases no one uses at the moment to require a slightly different combination of flags. Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com> Change-Id: If7ca3972ebc3c321e554533d7bc81af49c2472be
* | build(psci): move `runtime_errata.S` to PSCIChris Kay2023-05-032-1/+1
| | | | | | | | | | | | | | | | | | Move the runtime errata source file into the PSCI library, as PSCI is the only component directly dependent on it, and it doesn't require internal access to the CPUs library. Change-Id: I92826714d49b1b0131f62c158543b4c167ab9aa8 Signed-off-by: Chris Kay <chris.kay@arm.com>
* | Merge changes I9d06e0ee,I6980e84f into integrationManish Pandey2023-05-031-0/+14
|\ \ | | | | | | | | | | | | | | | * changes: feat(tegra): implement 'pwr_domain_off_early' handler feat(psci): introduce 'pwr_domain_off_early' hook
| * | feat(psci): introduce 'pwr_domain_off_early' hookVarun Wadekar2023-04-261-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces the 'pwr_domain_off_early' hook for platforms wanting to perform housekeeping steps before the PSCI framework starts the CPU power off sequence. Platforms might also want to use ths opportunity to ensure that the CPU off sequence can proceed. The PSCI framework expects a return code of PSCI_E_DENIED, if the platform wants to halt the CPU off sequence. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: I6980e84fc4d6cb80537a178d0d3d26fb28a13853
* | | refactor(cpus): use BIT macro in a consistent mannerOkash Khawaja2023-04-281-3/+3
| |/ |/| | | | | | | | | | | | | | | In assembly code, BIT macro is used with a preceding hash #. Let's update Cortex X1 code to follow the same convention. Excluding hash doesn't cause compilation to fail or emit incorrect code. Signed-off-by: Okash Khawaja <okash@google.com> Change-Id: If304cdf90542d2edcab3e2d66cd7e905ff7fd047
* | feat(sme): enable SME2 functionality for NS worldJayanth Dodderi Chidanand2023-04-271-1/+13
|/ | | | | | | | | | | | | | | | | | | FEAT_SME2 is an extension of FEAT_SME and an optional feature from v9.2. Its an extension of SME, wherein it not only processes matrix operations efficiently, but also provides outer-product instructions to accelerate matrix operations. It affords instructions for multi-vector operations. Further, it adds an 512 bit architectural register ZT0. This patch implements all the changes introduced with FEAT_SME2 to ensure that the instructions are allowed to access ZT0 register from Non-secure lower exception levels. Additionally, it adds support to ensure FEAT_SME2 is aligned with the existing FEATURE DETECTION mechanism, and documented. Change-Id: Iee0f61943304a9cfc3db8f986047b1321d0a6463 Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
* Merge "refactor(cpufeat): enable FEAT_DIT for FEAT_STATE_CHECKED" into ↵Manish Pandey2023-04-251-0/+6
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| * refactor(cpufeat): enable FEAT_DIT for FEAT_STATE_CHECKEDAndre Przywara2023-04-251-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At the moment we only support FEAT_DIT to be either unconditionally compiled in, or to be not supported at all. Add support for runtime detection (ENABLE_DIT=2), by splitting is_armv8_4_dit_present() into an ID register reading function and a second function to report the support status. That function considers both build time settings and runtime information (if needed). We use ENABLE_DIT in two occassions in assembly code, where we just set the DIT bit in the DIT system register. Protect those two cases by reading the CPU ID register when ENABLE_DIT is set to 2. Change the FVP platform default to the now supported dynamic option (=2), so the right decision can be made by the code at runtime. Change-Id: I506d352f18e23c60db8cdf08edb449f60adbe098 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* | Merge "fix(cpus): do not put RAS check before using esb" into integrationManish Pandey2023-04-251-2/+0
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| * fix(cpus): do not put RAS check before using esbManish Pandey2023-04-241-2/+0
| | | | | | | | | | | | | | | | | | | | If RAS Extension is not implemented esb instruction executes as a NOP. No need to have a check for RAS presence in the code. Also, The handler is related to a synchronous exceptions which implicitly is part of BL31 image only, so remove that check too. Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: If4264504cba9f0642b7b9c581ae66cd4deace32b
* | feat(gcs): support guarded control stackMark Brown2023-04-181-0/+15
|/ | | | | | | | | | | | | | Arm v9.4 introduces support for Guarded Control Stack, providing mitigations against some forms of RPO attacks and an efficient mechanism for obtaining the current call stack without requiring a full stack unwind. Enable access to this feature for EL2 and below, context switching the newly added EL2 registers as appropriate. Change the FVP platform to default to handling this as a dynamic option so the right decision can be made by the code at runtime. Signed-off-by: Mark Brown <broonie@kernel.org> Change-Id: I691aa7c22e3547bb3abe98d96993baf18c5f0e7b
* Merge "fix(cpus): use hint instruction for "tsb csync"" into integrationBipin Ravi2023-04-141-1/+5
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| * fix(cpus): use hint instruction for "tsb csync"Andre Przywara2023-03-231-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The "tsb csync" instruction is part of the Armv8.4 architecture extension, and is not supported by many older assemblers. We already cater for this in lib/extensions/trbe/trbe.c, where we use the equivalent "hint #18" encoding for this, but use the new mnemonic in the Cortex-A510 CPU support code. Replace "tsb csync" with the hint encoding there as well, to support building with older binutils versions. Change-Id: Idf39f5c6c4dbf72802c3c120047b8bc499145e3b Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* | Merge "feat(hcx): initialize HCRX_EL2 to its default value" into integrationManish Pandey2023-04-131-1/+28
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| * | feat(hcx): initialize HCRX_EL2 to its default valueJuan Pablo Conde2023-04-121-1/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The value of register HCRX_EL2 is UNKNOWN out of reset. This can affect the behavior in lower exception levels, such as traps to EL2 due to a wrong configuration of the register upon reset. This patch initializes the register at EL3 and disables all traps related to it. On the other hand, new fields have been introduced for HCRX_EL2, which are now defined in this patch, so they can be used in further development. Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com> Change-Id: I0bf1e949aa0d3be9f227358ad088a1ecb96ce222
* | | Merge "feat(pie/por): support permission indirection and overlay" into ↵André Przywara2023-04-121-0/+28
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| * | | feat(pie/por): support permission indirection and overlayMark Brown2023-04-121-0/+28
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Arm v8.9 introduces a series of features providing a new way to set memory permissions. Instead of directly encoding the permissions in the page tables the PTEs contain indexes into an array of permissions stored in system registers, allowing greater flexibility and density of encoding. Enable access to these features for EL2 and below, context switching the newly added EL2 registers as appropriate. Since all of FEAT_S[12]P[IO]E are separately discoverable we have separate build time options for enabling them, but note that there is overlap in the registers that they implement and the enable bit required for lower EL access. Change the FVP platform to default to handling them as dynamic options so the right decision can be made by the code at runtime. Signed-off-by: Mark Brown <broonie@kernel.org> Change-Id: Icf89e444e39e1af768739668b505661df18fb234
* | | fix(psci): potential array overflow with cpu onOlivier Deprez2023-04-111-2/+7
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix coverity finding in psci_cpu_on, in which target_idx is directly assigned the return value from plat_core_pos_by_mpidr. If the latter returns a negative or large positive value, it can trigger an out of bounds overflow for the psci_cpu_pd_nodes array. >>>> CID 382009: (OVERRUN) >>>> Overrunning callee's array of size 8 by passing argument "target_idx" (which evaluates to 4294967295) in call to "psci_spin_lock_cpu". > 80 psci_spin_lock_cpu(target_idx); >>>> CID 382009: (OVERRUN) >>>> Overrunning callee's array of size 8 by passing argument "target_idx" (which evaluates to 4294967295) in call to "psci_spin_unlock_cpu". > 160 psci_spin_unlock_cpu(target_idx); Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Change-Id: Ibc46934e9ca7fdcaeebd010e5c6954dcf2dcf8c7
* | feat(cpus): add support for blackhawk cpuGovindraj Raja2023-04-041-0/+77
| | | | | | | | | | | | | | | | | | Add basic CPU library code to support the Blackhawk CPU, BlackHawk core is based out of Hunter ELP core, so overall library code was adapted based on that. Change-Id: I4750e774732218ee669dceb734cd107f46b78492 Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
* | feat(cpus): add support for chaberton cpuGovindraj Raja2023-04-041-0/+77
| | | | | | | | | | | | | | | | | | Add basic CPU library code to support the Chaberton CPU, Chaberton cores are based out of Hunter core, so overall library code was adapted based on that. Change-Id: I58321c77f2c364225a764da6fa65656d1bec33f1 Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
* | fix(psci): remove unreachable switch/case blocksAndre Przywara2023-04-041-10/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PSCI function dispatcher switch/case is split up between 32-bit and 64-bit function IDs, based on bit 30 of the encoding. This bit just encodes the maximum size of the arguments, not necessarily whether they are used from AArch64 or AArch32. So while some functions exist in both worlds (CPU_ON, for instance), some functions take no or only 32-bit arguments (CPU_OFF, PSCI_FEATURES), so they only exist as a 32-bit function call. Commit b88a4416b5e5 ("feat(psci): add support for PSCI_SET_SUSPEND_MODE" , gerrit ID Iebf65f5f7846aef6b8643ad6082db99b4dcc4bef) and commit 9a70e69e0598 ("feat(psci): update PSCI_FEATURES", gerrit ID I5da8a989b53419ad2ab55b73ddeee6e882c25554) introduced two "case" sections for 32-bit function IDs in the 64-bit branch, which will never trigger. The one small extra case caused the sun50i_a64 DEBUG build to go beyond its RAM limit. Removed the redundant switch/case blocks, to make sun50i_a64 build again. Change-Id: Ic65b7403d128837296a0c3af42c6f23f9f57778e Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* | feat(cpufeat): enable FEAT_SVE for FEAT_STATE_CHECKEDJayanth Dodderi Chidanand2023-03-283-65/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for runtime detection (ENABLE_SVE_FOR_NS=2), by splitting sve_supported() into an ID register reading function and a second function to report the support status. That function considers both build time settings and runtime information (if needed), and is used before we do SVE specific setup. Change the FVP platform default to the now supported dynamic option (=2), so the right decision can be made by the code at runtime. Change-Id: I1caaba2216e8e2a651452254944a003607503216 Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
* | feat(cpufeat): enable FEAT_SME for FEAT_STATE_CHECKEDJayanth Dodderi Chidanand2023-03-282-23/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for runtime detection (ENABLE_SME_FOR_NS=2), by splitting feat_sme_supported() into an ID register reading function and a second function to report the support status. That function considers both build time settings and runtime information (if needed), and is used before we do SME specific setup. Change the FVP platform default to the now supported dynamic option (=2),so the right decision can be made by the code at runtime. Change-Id: Ida9ccf737db5be20865b84f42b1f9587be0626ab Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
* | Merge changes from topic "psci-osi" into integrationManish Pandey2023-03-285-35/+412
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * changes: feat(sc7280): add support for PSCI_OS_INIT_MODE feat(fvp): enable support for PSCI OS-initiated mode feat(psci): update PSCI_FEATURES feat(psci): add support for OS-initiated mode feat(psci): add support for PSCI_SET_SUSPEND_MODE build(psci): add build option for OS-initiated mode docs(psci): add design proposal for OS-initiated mode
| * | feat(psci): update PSCI_FEATURESWing Li2023-03-201-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch updates the PSCI_FEATURES handler to indicate support for OS-initiated mode per section 5.15.2 of the PSCI spec (DEN0022D.b) based on the value of `FF_SUPPORTS_OS_INIT_MODE`, which is conditionally enabled by the `PSCI_OS_INIT_MODE` build option. Change-Id: I5da8a989b53419ad2ab55b73ddeee6e882c25554 Signed-off-by: Wing Li <wingers@google.com>
| * | feat(psci): add support for OS-initiated modeWing Li2023-03-204-28/+293
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a `psci_validate_state_coordination` function that is called by `psci_cpu_suspend_start` in OS-initiated mode. This function validates the request per sections 4.2.3.2, 5.4.5, and 6.3 of the PSCI spec (DEN0022D.b): - The requested power states are consistent with the system's state - The calling core is the last running core at the requested power level This function differs from `psci_do_state_coordination` in that: - The `psci_req_local_pwr_states` map is not modified if the request were to be denied - The `state_info` argument is never modified since it contains the power states requested by the calling OS This is conditionally compiled into the build depending on the value of the `PSCI_OS_INIT_MODE` build option. Change-Id: I667041c842d2856e9d128c98db4d5ae4e4552df3 Signed-off-by: Wing Li <wingers@google.com>
| * | feat(psci): add support for PSCI_SET_SUSPEND_MODEWing Li2023-03-204-1/+113
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a PSCI_SET_SUSPEND_MODE handler that validates the request per section 5.20.2 of the PSCI spec (DEN0022D.b), and updates the suspend mode to the requested mode. This is conditionally compiled into the build depending on the value of the `PSCI_OS_INIT_MODE` build option. Change-Id: Iebf65f5f7846aef6b8643ad6082db99b4dcc4bef Signed-off-by: Wing Li <wingers@google.com>
* | | refactor(amu): use new AMU feature check routinesAndre Przywara2023-03-274-90/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | The AMU extension code was using its own feature detection routines. Replace them with the generic CPU feature handlers (defined in arch_features.h), which get updated to cover the v1p1 variant as well. Change-Id: I8540f1e745d7b02a25a6c6cdf2a39d6f5e21f2aa Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* | | refactor(amu): unify ENABLE_AMU and ENABLE_FEAT_AMUv1Andre Przywara2023-03-279-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | So far we have the ENABLE_AMU build option to include AMU register handling code for enabling and context switch. There is also an ENABLE_FEAT_AMUv1 option, solely to protect the HAFGRTR_EL2 system register handling. The latter needs some alignment with the new feature scheme, but it conceptually overlaps with the ENABLE_AMU option. Since there is no real need for two separate options, unify both into a new ENABLE_FEAT_AMU name in a first step. This is mostly just renaming at this point, a subsequent patch will make use of the new feature handling scheme. Change-Id: I97d8a55bdee2ed1e1509fa9f2b09fd0bdd82736e Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* | | Merge changes from topic "feat_state_part4" into integrationManish Pandey2023-03-275-149/+74
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * changes: refactor(cpufeat): enable FEAT_RNG for FEAT_STATE_CHECKED refactor(cpufeat): align FEAT_SEL2 to new feature handling refactor(cpufeat): enable FEAT_NV2 for FEAT_STATE_CHECKED refactor(cpufeat): enable FEAT_TWED for FEAT_STATE_CHECKED refactor(cpufeat): enable FEAT_CSV2_2 for FEAT_STATE_CHECKED refactor(cpufeat): enable FEAT_ECV for FEAT_STATE_CHECKED refactor(cpufeat): enable FEAT_PAN for FEAT_STATE_CHECKED refactor(cpufeat): align FEAT_SB to new feature handling refactor(cpufeat): use alternative encoding for "SB" barrier refactor(cpufeat): enable SYS_REG_TRACE for FEAT_STATE_CHECKED fix(cpufeat): make stub enable functions "static inline" fix(mpam): feat_detect: support major/minor
| * | | refactor(cpufeat): align FEAT_SEL2 to new feature handlingAndre Przywara2023-03-221-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In ARMv8.4, the EL2 exception level got added to the secure world. Adapt and rename the existing is_armv8_4_sel2_present() function, to align its handling with the other CPU features. Change-Id: If11e1942fdeb63c63f36ab9e89be810347d1a952 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * | | refactor(cpufeat): enable FEAT_NV2 for FEAT_STATE_CHECKEDAndre Przywara2023-03-222-30/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At the moment we only support for FEAT_NV2 to be either unconditionally compiled in, or to be not supported at all. Add support for runtime detection (CTX_INCLUDE_NEVE_REGS=2), by splitting get_armv8_4_feat_nv_support() into an ID register reading function and a second function to report the support status. That function considers both build time settings and runtime information (if needed), and is used before we access the VNCR_EL2 system register. Also move the context saving code from assembly to C, and use the new is_feat_nv2_supported() function to guard its execution. Change the FVP platform default to the now supported dynamic option (=2), so the right decision can be made by the code at runtime. Change-Id: I85b080641995fb72cfd4ac933f7a3f75770c2cb9 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * | | refactor(cpufeat): enable FEAT_TWED for FEAT_STATE_CHECKEDAndre Przywara2023-03-221-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At the moment we only support FEAT_TWED to be either unconditionally compiled in, or to be not supported at all. Add support for runtime detection (ENABLE_FEAT_TWED=2), by splitting is_armv8_6_twed_present() into an ID register reading function and a second function to report the support status. That function considers both build time settings and runtime information (if needed), and is used before we set the trap delay time. Change the FVP platform default to the now supported dynamic option (=2), so the right decision can be made by the code at runtime. Change-Id: I58626230ef0af49886c0a197abace01e81f661d2 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * | | refactor(cpufeat): enable FEAT_CSV2_2 for FEAT_STATE_CHECKEDAndre Przywara2023-03-222-38/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At the moment we only support FEAT_CSV2_2 to be either unconditionally compiled in, or to be not supported at all. Add support for runtime detection (ENABLE_FEAT_CSV2_2=2), by splitting is_armv8_0_feat_csv2_2_present() into an ID register reading function and a second function to report the support status. That function considers both build time settings and runtime information (if needed), and is used before we access the SCXTNUM_EL2 system register. Also move the context saving code from assembly to C, and use the new is_feat_csv2_2_supported() function to guard its execution. Change the FVP platform default to the now supported dynamic option (=2), so the right decision can be made by the code at runtime. Change-Id: I89c7bc883e6a65727fdbdd36eb3bfbffb2196da7 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * | | refactor(cpufeat): enable FEAT_ECV for FEAT_STATE_CHECKEDAndre Przywara2023-03-222-26/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At the moment we only support FEAT_ECV to be either unconditionally compiled in, or to be not supported at all. Add support for runtime detection (ENABLE_FEAT_ECV=2), by splitting is_feat_ecv_present() into an ID register reading function and a second function to report the support status. That function considers both build time settings and runtime information (if needed), and is used before we access the CNTPOFF_EL2 system register. Also move the context saving code from assembly to C, and use the new is_feat_ecv_supported() function to guard its execution. Change the FVP platform default to the now supported dynamic option (=2), so the right decision can be made by the code at runtime. Change-Id: I4acd5384929f1902b62a87ae073aafa1472cd66b Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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