diff options
| author | Bipin Ravi <bipin.ravi@arm.com> | 2023-04-14 23:01:32 +0200 |
|---|---|---|
| committer | TrustedFirmware Code Review <review@review.trustedfirmware.org> | 2023-04-14 23:01:32 +0200 |
| commit | b516a6f46c73a527a0e4c4d2f5f31bdab161812a (patch) | |
| tree | 4f9e9bb6febca19e95b55f4b9b03caca5520a15a /lib | |
| parent | 4a24538ae9cfa523d59f63ecd40438b42661f249 (diff) | |
| parent | 7a181b7d046a710db5238fb37047816636d2bb8a (diff) | |
| download | arm-trusted-firmware-b516a6f46c73a527a0e4c4d2f5f31bdab161812a.tar.gz | |
Merge "fix(cpus): use hint instruction for "tsb csync"" into integration
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/cpus/aarch64/cortex_a510.S | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/lib/cpus/aarch64/cortex_a510.S b/lib/cpus/aarch64/cortex_a510.S index 886e1f3c8..e10ebb0b8 100644 --- a/lib/cpus/aarch64/cortex_a510.S +++ b/lib/cpus/aarch64/cortex_a510.S @@ -382,7 +382,11 @@ func errata_cortex_a510_2684597_wa bl check_errata_2684597 cbz x0, 2f - tsb csync + /* + * Many assemblers do not yet understand the "tsb csync" mnemonic, + * so use the equivalent hint instruction. + */ + hint #18 /* tsb csync */ 2: ret x17 endfunc errata_cortex_a510_2684597_wa |