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| author | Andre Przywara <andre.przywara@arm.com> | 2022-11-17 16:42:09 +0000 |
|---|---|---|
| committer | Andre Przywara <andre.przywara@arm.com> | 2023-03-20 13:37:37 +0000 |
| commit | ea735bf556f8768fd4c82a7b3c224b529aee057a (patch) | |
| tree | c1d33d0cd74ed595f2e9fd8b4d96752c088ce6f3 /include/arch/aarch64/arch.h | |
| parent | 9448f2b88e4afcea5ef671211882f09e7f64f9df (diff) | |
| download | arm-trusted-firmware-ea735bf556f8768fd4c82a7b3c224b529aee057a.tar.gz | |
refactor(cpufeat): enable FEAT_VHE for FEAT_STATE_CHECKED
At the moment we only support FEAT_VHE to be either unconditionally
compiled in, or to be not supported at all.
Add support for runtime detection (ENABLE_FEAT_VHE=2), by splitting
is_armv8_1_vhe_present() into an ID register reading function and a
second function to report the support status. That function considers
both build time settings and runtime information (if needed), and is
used before we access VHE related registers.
Also move the context saving code from assembly to C, and use the new
is_feat_vhe_supported() function to guard its execution.
Enable VHE in its runtime detection version for all FVP builds.
Change-Id: Ib397cd0c83e8c709bd6fed603560e39901fa672b
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Diffstat (limited to 'include/arch/aarch64/arch.h')
| -rw-r--r-- | include/arch/aarch64/arch.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h index cafc1e8bc..85546ec47 100644 --- a/include/arch/aarch64/arch.h +++ b/include/arch/aarch64/arch.h @@ -121,6 +121,8 @@ #define TRFCR_EL2 S3_4_C1_C2_1 #define PMSCR_EL2 S3_4_C9_C9_0 #define TFSR_EL2 S3_4_C5_C6_0 +#define CONTEXTIDR_EL2 S3_4_C13_C0_1 +#define TTBR1_EL2 S3_4_C2_C0_1 /******************************************************************************* * Generic timer memory mapped registers & offsets |