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| author | johpow01 <john.powell@arm.com> | 2022-03-09 16:23:04 -0600 |
|---|---|---|
| committer | John Powell <john.powell@arm.com> | 2022-05-09 20:02:10 +0200 |
| commit | af220ebbe467aa580e6b9ba554676f78ffec930f (patch) | |
| tree | 882e7385a1c98ec9ea8b032695a76553cfa8fa9e /include/arch/aarch64/arch.h | |
| parent | c3bdd3d3cf0f9cdf3be117e39386492e645a1bb5 (diff) | |
| download | arm-trusted-firmware-af220ebbe467aa580e6b9ba554676f78ffec930f.tar.gz | |
fix(errata): workaround for Cortex-A710 erratum 2008768
Cortex-A710 erratum 2008768 is a Cat B erratum that applies to revisions
r0p0, r1p0, and r2p0, and is fixed in r2p1. The workaround is to clear
the ED bit in each ERXCTLR_EL1 register before setting the PWRDN bit in
CPUPWRCTLR_EL1.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775101
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ib2171c06da762dd4155b02c03d86766f1616381d
Diffstat (limited to 'include/arch/aarch64/arch.h')
| -rw-r--r-- | include/arch/aarch64/arch.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h index bbbc77adb..cdd852dcf 100644 --- a/include/arch/aarch64/arch.h +++ b/include/arch/aarch64/arch.h @@ -1222,7 +1222,8 @@ #define ERXMISC0_EL1 S3_0_C5_C5_0 #define ERXMISC1_EL1 S3_0_C5_C5_1 -#define ERXCTLR_ED_BIT (U(1) << 0) +#define ERXCTLR_ED_SHIFT U(0) +#define ERXCTLR_ED_BIT (U(1) << ERXCTLR_ED_SHIFT) #define ERXCTLR_UE_BIT (U(1) << 4) #define ERXPFGCTL_UC_BIT (U(1) << 1) |