diff options
| -rw-r--r-- | docs/design/cpu-specific-build-macros.rst | 4 | ||||
| -rw-r--r-- | include/arch/aarch64/arch.h | 3 | ||||
| -rw-r--r-- | lib/cpus/aarch64/cortex_a710.S | 52 | ||||
| -rw-r--r-- | lib/cpus/cpu-ops.mk | 8 |
4 files changed, 66 insertions, 1 deletions
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index 3029458ef..fd2f97c89 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -433,6 +433,10 @@ For Cortex-A710, the following errata build flags are defined : Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 of the CPU and is fixed in r2p1. +- ``ERRATA_A710_2008768``: This applies errata 2008768 workaround to + Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 + of the CPU and is fixed in r2p1. + For Neoverse N2, the following errata build flags are defined : - ``ERRATA_N2_2002655``: This applies errata 2002655 workaround to Neoverse-N2 diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h index bbbc77adb..cdd852dcf 100644 --- a/include/arch/aarch64/arch.h +++ b/include/arch/aarch64/arch.h @@ -1222,7 +1222,8 @@ #define ERXMISC0_EL1 S3_0_C5_C5_0 #define ERXMISC1_EL1 S3_0_C5_C5_1 -#define ERXCTLR_ED_BIT (U(1) << 0) +#define ERXCTLR_ED_SHIFT U(0) +#define ERXCTLR_ED_BIT (U(1) << ERXCTLR_ED_SHIFT) #define ERXCTLR_UE_BIT (U(1) << 4) #define ERXPFGCTL_UC_BIT (U(1) << 1) diff --git a/lib/cpus/aarch64/cortex_a710.S b/lib/cpus/aarch64/cortex_a710.S index aea62aea6..63d55bbc0 100644 --- a/lib/cpus/aarch64/cortex_a710.S +++ b/lib/cpus/aarch64/cortex_a710.S @@ -310,6 +310,49 @@ func check_errata_2282622 b cpu_rev_var_ls endfunc check_errata_2282622 +/* --------------------------------------------------------------- + * Errata Workaround for Cortex-A710 Erratum 2008768. + * This applies to revision r0p0, r1p0 and r2p0. + * It is fixed in r2p1. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0, x1, x2, x17 + * --------------------------------------------------------------- + */ +func errata_a710_2008768_wa + mov x17, x30 + bl check_errata_2008768 + cbz x0, 1f + + /* Stash ERRSELR_EL1 in x2 */ + mrs x2, ERRSELR_EL1 + + /* Select error record 0 and clear ED bit */ + msr ERRSELR_EL1, xzr + mrs x1, ERXCTLR_EL1 + bfi x1, xzr, #ERXCTLR_ED_SHIFT, #1 + msr ERXCTLR_EL1, x1 + + /* Select error record 1 and clear ED bit */ + mov x0, #1 + msr ERRSELR_EL1, x0 + mrs x1, ERXCTLR_EL1 + bfi x1, xzr, #ERXCTLR_ED_SHIFT, #1 + msr ERXCTLR_EL1, x1 + + /* Restore ERRSELR_EL1 from x2 */ + msr ERRSELR_EL1, x2 + +1: + ret x17 +endfunc errata_a710_2008768_wa + +func check_errata_2008768 + /* Applies to r0p0, r1p0 and r2p0 */ + mov x1, #0x20 + b cpu_rev_var_ls +endfunc check_errata_2008768 + func check_errata_cve_2022_23960 #if WORKAROUND_CVE_2022_23960 mov x0, #ERRATA_APPLIES @@ -324,6 +367,14 @@ endfunc check_errata_cve_2022_23960 * ---------------------------------------------------- */ func cortex_a710_core_pwr_dwn + +#if ERRATA_A710_2008768 + mov x4, x30 + bl cpu_get_rev_var + bl errata_a710_2008768_wa + mov x30, x4 +#endif + /* --------------------------------------------------- * Enable CPU power down bit in power control register * --------------------------------------------------- @@ -358,6 +409,7 @@ func cortex_a710_errata_report report_errata ERRATA_A710_2267065, cortex_a710, 2267065 report_errata ERRATA_A710_2136059, cortex_a710, 2136059 report_errata ERRATA_A710_2282622, cortex_a710, 2282622 + report_errata ERRATA_A710_2008768, cortex_a710, 2008768 report_errata WORKAROUND_CVE_2022_23960, cortex_a710, cve_2022_23960 ldp x8, x30, [sp], #16 diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index 462ca9dff..fe98a30af 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -484,6 +484,10 @@ ERRATA_A710_2136059 ?=0 # to revision r0p0, r1p0 and r2p0 of the Cortex-A710 cpu and is fixed in r2p1. ERRATA_A710_2282622 ?=0 +# Flag to apply erratum 2008768 workaround during reset. This erratum applies +# to revision r0p0, r1p0 and r2p0 of the Cortex-A710 cpu and is fixed in r2p1. +ERRATA_A710_2008768 ?=0 + # Flag to apply erratum 2067956 workaround during reset. This erratum applies # to revision r0p0 of the Neoverse N2 cpu and is still open. ERRATA_N2_2067956 ?=0 @@ -990,6 +994,10 @@ $(eval $(call add_define,ERRATA_A710_2136059)) $(eval $(call assert_boolean,ERRATA_A710_2282622)) $(eval $(call add_define,ERRATA_A710_2282622)) +# Process ERRATA_A710_2008768 flag +$(eval $(call assert_boolean,ERRATA_A710_2008768)) +$(eval $(call add_define,ERRATA_A710_2008768)) + # Process ERRATA_N2_2067956 flag $(eval $(call assert_boolean,ERRATA_N2_2067956)) $(eval $(call add_define,ERRATA_N2_2067956)) |