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* opcodes/mips: use .word/.short for undefined instructionsAndrew Burgess2022-12-051-3/+6
| | | | | | | | | | | | | While working on disassembler styling for MIPS, I noticed that undefined instructions are printed by the disassembler as raw number with no assembler directive prefix (e.g. without .word or .short). I think adding something like .word, or .short, helps to make it clearer the size of the value that is being displayed, and is inline with what many of the other libopcode disassemblers do. In this commit I've added the .word and .short directives, and updated all the tests that I spotted that failed as a result.
* x86: Allow 16-bit register source for LAR and LSLH.J. Lu2022-12-033-18/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since LAR and LSL only access 16 bits of the source operand, regardless of operand size, allow 16-bit register source for LAR and LSL, and always disassemble LAR and LSL with 16-bit source operand. gas/ PR gas/29844 * testsuite/gas/i386/i386.s: Add tests for LAR and LSL. * testsuite/gas/i386/x86_64.s: Likewise. * testsuite/gas/i386/intelbad.s: Remove "lar/lsl eax, ax". * testsuite/gas/i386/i386-intel.d: Updated. * testsuite/gas/i386/i386.d: Likewise. * testsuite/gas/i386/intel-intel.d: Likewise. * testsuite/gas/i386/intel.d: Likewise. * testsuite/gas/i386/intelbad.l: Likewise. * testsuite/gas/i386/x86_64-intel.d: Likewise. * testsuite/gas/i386/x86_64.d: Likewise. opcodes/ PR gas/29844 * i386-dis.c (MOD_0F02): Removed. (MOD_0F03): Likewise. (dis386_twobyte): Restore larS and lslS. (mod_table): Remove MOD_0F02 and MOD_0F03. * i386-opc.tbl: Allow 16-bit register source for LAR and LSL. * i386-tbl.h: Regenerated.
* x86: drop most OPERAND_TYPE_* (and rework the rest)Jan Beulich2022-12-022-287/+0
| | | | | | | | | With the general use of C99 there's no need anymore to have i386-gen produce these. For more frequently used ones introduce local #define-s, while others are simply spelled out directly. While doing this move some static constants into more narrow scopes. Note that as a "side effect" this corrects type_names[]'es imm8s entry.
* x86: also use D for XCHG and TESTJan Beulich2022-12-022-57/+9
| | | | | | Leverage the C (commutative) attribute to also reduce the number of XCHG and TEST templates we have. This way the reg <-> r/m (and reg <-> reg for XCHG) forms can also be folded into a single template each, utilizing D.
* opcodes: Remove i386-init.h and i386-tbl.h from HFILESH.J. Lu2022-12-013-6/+0
| | | | | | | | | i386-init.h and i386-tbl.h are generated files. There is nothing to translate. Remove them from HFILES (POTFILES). * Makefile.am (HFILES): Remove i386-init.h and i386-tbl.h. * Makefile.in: Regenerated. * po/POTFILES.in: Likewise.
* x86: drop No_ldSufJan Beulich2022-12-014-11598/+11594
| | | | | With LONG_DOUBLE_MNEM_SUFFIX gone there'salso no use for No_ldSuf anymore.
* x86/Intel: drop LONG_DOUBLE_MNEM_SUFFIXJan Beulich2022-12-012-4/+4
| | | | | | With the removal of its use for FPU insns the suffix is now finally properly misnamed. Drop its use altogether, replacing it by a separate boolean instead.
* x86/Intel: restrict use of LONG_DOUBLE_MNEM_SUFFIXJan Beulich2022-12-012-8/+8
| | | | | | | | As a comment near the top of match_template() already says: We really only need this pseudo-suffix for far branch handling. Stop "deriving" it for floating point insns. (Don't bother renaming the now properly misnamed LONG_DOUBLE_MNEM_SUFFIX, to e.g. FAR_BRANCH_SUFFIX - it's going to disappear anyway.)
* x86: clean up after removal of support for gcc <= 2.8.1Jan Beulich2022-11-302-36/+5
| | | | | | | | | | | | | | | | | At the very least a comment in process_operands() is stale. Beyond that there are effectively two options: 1) It is possible that FADDP and FMULP were mistakenly not marked as being in need of dealing with the compiler anomaly, and hence the respective templates weren't removed at the time when they should have been. 2) It is also possible that there are indeed uses known beyond compiler generated output for these two commutative opcodes, and hence the templates need to stay. To be on the safe side assume 2: Update the comment and fold the templates into their "normal" ones (utilizing D), adjusting consuming code accordingly. For FMULP also add a comment paralleling a similar one FADDP has.
* x86: drop FloatRJan Beulich2022-11-304-11255/+11187
| | | | | | | | | | | | | | There are just 4 templates using it, which can be easily identified by other means, as D is set only on a very limited number of FPU templates. Also move the respective conditional out of the code path taken by all "reverse match" insns (it probably should have been this way already before, to avoid the one conditional in the common case). With this the templates which had FloatR dropped no longer differ from their AT&T syntax + mnemonic counterparts - the only difference is now which of the two would be recognized. For this, however, we don't need two templates - we can simply arrange the condition for setting Opcode_FloatR accordingly.
* RISC-V: Better support for long instructions (disassembler)Tsukasa OI2022-11-281-5/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit bb996692bd96 ("RISC-V/gas: allow generating up to 176-bit instructions with .insn") tried to start supporting long instructions but it was insufficient. On the disassembler, correct ".byte" output was limited to the first 64-bits of an instruction. After that, zeroes are incorrectly printed. Note that, it only happens on ".byte" output (instruction part) and not on hexdump (data) part. For example, before this commit, hexdump and ".byte" produces different values: Assembly: .insn 22, 0xfedcba98765432100123456789abcdef55aa33cc607f objdump output example (before the fix): 10: 607f 33cc 55aa cdef .byte 0x7f, 0x60, 0xcc, 0x33, 0xaa, 0x55, 0xef, 0xcd, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 18: 89ab 4567 0123 3210 20: 7654 ba98 fedc Note that, after 0xcd (after first 64-bits of the target instruction), all ".byte" values are incorrectly printed as zero while hexdump prints correct instruction bits. To resolve this, this commit adds "packet" argument to support dumping instructions longer than 64-bits (to print correct instruction bits on ".byte"). This commit will be tested on the separate commit. Assembly: .insn 22, 0xfedcba98765432100123456789abcdef55aa33cc607f objdump output example (after the fix): 10: 607f 33cc 55aa cdef .byte 0x7f, 0x60, 0xcc, 0x33, 0xaa, 0x55, 0xef, 0xcd, 0xab, 0x89, 0x67, 0x45, 0x23, 0x01, 0x10, 0x32, 0x54, 0x76, 0x98, 0xba, 0xdc, 0xfe 18: 89ab 4567 0123 3210 20: 7654 ba98 fedc opcodes/ChangeLog: * riscv-dis.c (riscv_disassemble_insn): Print unknown instruction using the new argument packet. (riscv_disassemble_data): Add unused argument packet. (print_insn_riscv): Pass packet to the disassemble function.
* x86: widen applicability and use of CheckRegSizeJan Beulich2022-11-242-14/+14
| | | | | | | | | | | | | | | | | | | | | | | First of all make operand_type_register_match() apply to all sized operands, i.e. in Intel Syntax also to respective memory ones. This addresses gas wrongly accepting certain SIMD insns where register and memory operand sizes should match but don't. This apparently has affected all templates with one memory-only operand and one or more register ones, both permitting at least two sizes, due to CheckRegSize not taking effect. Then also add CheckRegSize to a couple of non-SIMD templates matching that same pattern of memory-only vs register operands. This replaces bogus (for Intel Syntax) diagnostics referring to a wrong suffix (when none was used at all) by "type mismatch" ones, just like already emitted for insns where the template allows a register operand alongside a memory one at any particular position. This also is a prereq to limiting (ideally eliminating in the long run) suffix "derivation" in Intel Syntax mode. While making the code adjustment also flip order of checks to do the cheaper one first in both cases.
* x86: add missing CheckRegSizeJan Beulich2022-11-242-6/+6
| | | | | | To properly and predictably determine operand size encoding (operand size or REX.W prefixes), consistent operand sizes need to be specified. Add CheckRegSize where this was previously missing.
* x86: correct handling of LAR and LSLJan Beulich2022-11-243-6/+50
| | | | | | | | Both uniformly only ever take 16-bit memory operands while at the same time requiring matching (in size) register operands, which then also should disassemble that way. This in particular requires splitting each of the templates for the assembler and separating decode of the register and memory forms in the disassembler.
* PR16995, m68k coldfire emac immediate to macsr incorrect disassemblyAlan Modra2022-11-241-2/+2
| | | | | | | | Mode/reg bits for these insns are 000 Dy, 001 Ay, and 111 100 for the move immediate. * m68k-opc.c (m68k_opcodes): Only accept 000 and 001 as mode for move reg to macsr/mask insns.
* opcodes: Correct address for ARC's "isa_config" aux regShahab Vahedi2022-11-222-1/+7
| | | | | | | | | | | This patch changes the address for "isa_config" auxiliary register from 0xC2 to the correct value 0xC1. Moreover, it only exists in arc700+ and not all ARCs. opcodes/ChangeLog: * arc-regs.h: Change isa_config address to 0xc1. isa_config exists for ARC700 and ARCV2 and not ARCALL.
* opcodes: Define NoSuf in i386-opc.tblH.J. Lu2022-11-171-1847/+1848
| | | | | | | | | | | Use NoSuf to replace No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf and add the explicit NoSuf to AddrPrefixOpReg in templates. * i386-opc.tbl (NoSuf): New macro. (AddrPrefixOpReg): Remove No_?Suf. Replace No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf with NoSuf in templates. Add NoSuf to AddrPrefixOpReg in templates.
* i386: Move i386_seg_prefixes to gasH.J. Lu2022-11-172-11/+0
| | | | | | | | | | | gas/ * config/tc-i386.c (i386_seg_prefixes): New. Moved from opcodes. opcodes/ * i386-opc.c (i386_seg_prefixes): Removed. * i386-opc.h (i386_seg_prefixes): Likewise.
* RISC-V: Add T-Head Int vendor extensionChristoph Müllner2022-11-171-0/+4
| | | | | | | | | | | | This patch adds the XTheadInt extension, which provides interrupt stack management instructions. The XTheadFmv extension is documented in the RISC-V toolchain contentions: https://github.com/riscv-non-isa/riscv-toolchain-conventions Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
* RISC-V: Add T-Head Fmv vendor extensionChristoph Müllner2022-11-171-0/+4
| | | | | | | | | | | | This patch adds the XTheadFmv extension, which allows to access the upper 32 bits of a double-precision floating-point register in RV32. The XTheadFmv extension is documented in the RISC-V toolchain contentions: https://github.com/riscv-non-isa/riscv-toolchain-conventions Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
* Add AMD znver4 processor supportTejas Joshi2022-11-156-4052/+4129
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 2022-09-28 Tejas Joshi <TejasSanjay.Joshi@amd.com> gas/ * config/tc-i386.c (cpu_arch): Add znver4 ARCH and rmpquery SUBARCH. (md_assemble): Expand comment before swap_operands() with rmpquery. * doc/c-i386.texi: Add znver4. * testsuite/gas/i386/arch-14-1.d: New. * testsuite/gas/i386/arch-14-1.s: New. * testsuite/gas/i386/arch-14-znver4.d: New. * testsuite/gas/i386/i386.exp: Add new znver4 test cases. * testsuite/gas/i386/rmpquery.d: New. * testsuite/gas/i386/rmpquery.s: New. * testsuite/gas/i386/x86-64-arch-4-1.d: New. * testsuite/gas/i386/x86-64-arch-4-1.s: New. * testsuite/gas/i386/x86-64-arch-4-znver4.d: New. opcodes/ * i386-dis.c (x86_64_table): Add rmpquery. * i386-gen.c (cpu_flag_init): Add CPU_ZNVER4_FLAGS and CPU_RMPQUERY_FLAGS. (cpu_flags): Add CpuRMPQUERY. * i386-opc.h (enum): Add CpuRMPQUERY. (i386_cpu_flags): Add cpurmpquery. * i386-opc.tbl: Add rmpquery insn. * i386-init.h: Re-generated. * i386-tbl.h: Re-generated.
* aarch64: Add support for Common Short Sequence Compression extensionAndre Vieira2022-11-146-49/+166
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the CSSC extension and its corresponding instructions: ABS, CNT, CTZ, SMAX, UMAX, SMIN, UMIN. gas/ChangeLog: * config/tc-aarch64.c (parse_operands): Handle new operand types. * doc/c-aarch64.texi: Document new extension. * testsuite/gas/aarch64/cssc.d: New test. * testsuite/gas/aarch64/cssc.s: New test. include/ChangeLog: * opcode/aarch64.h (AARCH64_FEATURE_CSSC): New feature Macro. (enum aarch64_opnd): New operand types. (enum aarch64_insn_class): New instruction class. opcodes/ChangeLog: * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. * aarch64-opc.c (operand_general_constraint_met_p): Update for new operand types. (aarch64_print_operand): Likewise. * aarch64-opc.h (enum aarch64_field_kind): Declare FLD_CSSC_imm8 field. * aarch64-tbl.h (aarch64_feature_cssc): Define new feature set. (CSSC): Define new feature set Macro. (CSSC_INSN): Define new instruction type. (aarch64_opcode_table): Add new instructions.
* x86: fold special-operand insn attributes into a single enumJan Beulich2022-11-144-11219/+11210
| | | | | | | | Attributes which aren't used together in any single insn template can be converted from individual booleans to a single enum, as was done for a few other attributes before. This is more space efficient. Collect together all attributes which express special operand constraints (and which fit the criteria for folding).
* PowerPC64 paddi -MrawAlan Modra2022-11-121-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On a testcase like pla 8,foo@pcrel disassembled with -Mpower10 results in 0: 00 00 10 06 pla r8,0 # 0 4: 00 00 00 39 0: R_PPC64_PCREL34 foo but with -Mpower10 -Mraw 0: 00 00 10 06 .long 0x6100000 0: R_PPC64_PCREL34 foo 4: 00 00 00 39 addi r8,0,0 The instruction is unrecognised due to the hack we have in extract_pcrel0 in order to disassemble paddi with RA0=0 and R=1 as pla. I could have just added "&& !(dialect & PPC_OPCODE_RAW)" to the condition in extract_pcrel0 under which *invalid is set, but went for this larger patch that reorders the extended insn pla to the more usual place before its underlying machine insn. (la is after addi because we never disassemble to la.) gas/ * testsuite/gas/ppc/raw.d, * testsuite/gas/ppc/raw.s: Add pla. opcodes/ * ppc-opc.c (extract_pcrel1): Rename from extract_pcrel0 and invert *invalid logic. (PCREL1): Rename from PCREL0. (prefix_opcodes): Sort pla before paddi, adjusting R operand for pla, paddi and psubi.
* x86: drop stray IsString from PadLock insnsJan Beulich2022-11-112-32/+32
| | | | | The need for IsString on the PadLock insns went away with the introduction of RepPrefixOk. Drop these leftovers.
* [opcodes/arm] Fix potential null pointer dereferencesLuis Machado2022-11-101-1/+5
| | | | | | | | | PR tdep/29598 As pointed out in the bug ticket, we have a couple potential null pointer dereferencing situations. Harden those. Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=29598
* RISC-V: xtheadfmemidx: Use fp register in mnemonicsChristoph Müllner2022-11-091-8/+8
| | | | | | | | | | | | | | | | | | | | | | Although the encoding for scalar and fp registers is identical, we should follow common pratice and use fp register names when referencing fp registers. The xtheadmemidx extension consists of indirect load/store instructions which all load to or store from fp registers. Let's use fp register names in this case and adjust the test cases accordingly. gas/ * testsuite/gas/riscv/x-thead-fmemidx-fail.l: Updated since rd need to be float register. * testsuite/gas/riscv/x-thead-fmemidx-fail.s: Likewise. * testsuite/gas/riscv/x-thead-fmemidx.d: Likewise. * testsuite/gas/riscv/x-thead-fmemidx.s: Likewise. opcodes/ * riscv-opc.c (riscv_opcodes): Updated since rd need to be float register. Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
* PowerPC: Add XSP operand definePeter Bergner2022-11-081-5/+6
| | | | | | opcodes/ * ppc-opc.c (XSP): New define. (powerpc_opcodes) <stxvp, stxvpx, pstxvp>: Use it.
* x86: Correct wrong comments in vex_w_tableHaochen Jiang2022-11-081-1/+1
| | | | | | | | | | | | | | | | Hi all, This wrong comment was introduced by previous AVX-VNNI-INT8 commit. Committed as obvious fix. BRs, Haochen opcodes/ChangeLog: * i386-dis.c (VEX_W_0F3851): Corrected from VEX_W_0F3851_P_0.
* Support Intel RAO-INTKong Lingling2022-11-086-4174/+4278
| | | | | | | | | | | | | | | | | | | | | | | | | | | gas/ChangeLog: * NEWS: Support Intel RAO-INT. * config/tc-i386.c: Add raoint. * doc/c-i386.texi: Document .raoint. * testsuite/gas/i386/i386.exp: Run RAO_INT tests. * testsuite/gas/i386/raoint-intel.d: New test. * testsuite/gas/i386/raoint.d: Ditto. * testsuite/gas/i386/raoint.s: Ditto. * testsuite/gas/i386/x86-64-raoint-intel.d: Ditto. * testsuite/gas/i386/x86-64-raoint.d: Ditto. * testsuite/gas/i386/x86-64-raoint.s: Ditto. opcodes/ChangeLog: * i386-dis.c (PREFIX_0F38FC): New. (prefix_table): Add PREFIX_0F38FC. * i386-gen.c: (cpu_flag_init): Add CPU_RAO_INT_FLAGS and CPU_ANY_RAO_INT_FLAGS. * i386-init.h: Regenerated. * i386-opc.h: (CpuRAO_INT): New. (i386_cpu_flags): Add cpuraoint. * i386-opc.tbl: Add RAO_INT instructions. * i386-tbl.h: Regenerated.
* opcodes/arm: silence compiler warning about uninitialized variable useAndrew Burgess2022-11-041-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After this commit: commit 6576bffe6cbbb53c5756b2fccd2593ba69b74cdf Date: Thu Jul 7 13:43:45 2022 +0100 opcodes/arm: add disassembler styling for arm Some people were seeing their builds failing with complaints about a possible uninitialized variable usage. I previously fixed an instance of this issue in this commit: commit 2df82cd4b459fbc32120e0ad1ce19e26349506fe Date: Tue Nov 1 10:36:59 2022 +0000 opcodes/arm: silence compiler warning about uninitialized variable use which did fix the build problems that the sourceware buildbot was hitting, however, an additional instance of the same problem was brought to my attention, and that is fixed in this commit. Where commit 2df82cd4b4 fixed the uninitialized variable problem in print_mve_unpredictable, this commit fixes the same problem in print_mve_undefined. As with the previous commit, I don't believe we could really ever get an uninitialized variable usage, based on the current usage of the function, so I have just initialized the reason variable to "??".
* Support Intel AVX-NE-CONVERTkonglin12022-11-046-4169/+4397
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gas/ChangeLog: * NEWS: Support Intel AVX-NE-CONVERT. * config/tc-i386.c: Add avx_ne_convert. * doc/c-i386.texi: Document .avx_ne_convert. * testsuite/gas/i386/i386.exp: Run AVX NE CONVERT tests. * testsuite/gas/i386/avx-ne-convert-intel.d: New test. * testsuite/gas/i386/avx-ne-convert.d: Ditto. * testsuite/gas/i386/avx-ne-convert.s: Ditto. * testsuite/gas/i386/x86-64-avx-ne-convert-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx-ne-convert.d: Ditto. * testsuite/gas/i386/x86-64-avx-ne-convert.s: Ditto. opcodes/ChangeLog: * i386-dis.c (Mw): New. (PREFIX_VEX_0F3872): Ditto. (PREFIX_VEX_0F38B0_W_0): Ditto. (PREFIX_VEX_0F38B1_W_0): Ditto. (VEX_W_0F3872_P_1): Ditto. (VEX_W_0F38B0): Ditto. (VEX_W_0F38B1): Ditto. (prefix_table): Add PREFIX_VEX_0F3872, PREFIX_VEX_0F38B0_W_0, PREFIX_VEX_0F38B1_W_0. (vex_w_table): Add VEX_W_0F3872_P_1, VEX_W_0F38B0, VEX_W_0F38B1. * i386-gen.c (cpu_flag_init): Add CPU_AVX_NE_CONVERT_FLGAS and CPU_ANY_AVX_NE_CONVERT_FLAGS. (cpu_flags): Add CpuAVX_NE_CONVERT. * i386-init.h: Regenerated. * i386-opc.h (CpuAVX_NE CONVERT): New. (i386_cpu_flags): Add cpuavx_ne_convert. * i386-opc.tbl: Add Intel AVX-NE-CONVERT instructions. * i386-tbl.h: Regenerated.
* i386: Rename <xy> template.konglin12022-11-041-17/+18
| | | | | | opcodes/ * i386-opc.tbl: Rename <xy> template for VEX insn with x/y suffix to <Vxy>. Rename <xy> for EVEX insn with x/y suffix to <Exy>.
* x86: drop bogus TbyteJan Beulich2022-11-022-4/+4
| | | | | | | | | | | Prior to commit 1cb0ab18ad24 ("x86/Intel: restrict suffix derivation") the Tbyte modifier on the FLDT and FSTPT templates was pointless, as No_ldSuf would have prevented it being accepted. Due to the special nature of LONG_DOUBLE_MNEM_SUFFIX said commit, however, has led to these insns being accepted in Intel syntax mode even when "tbyte ptr" was present. Restore original behavior by dropping Tbyte there. (Note that these insns in principle should by marked AT&T syntax only, but since they haven't been so far we probably shouldn't change that.)
* Support Intel MSRLISTHu, Lin12022-11-026-4161/+4237
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | gas/ChangeLog: * NEWS: Support Intel MSRLIST. * config/tc-i386.c: Add msrlist. * doc/c-i386.texi: Document .msrlist. * testsuite/gas/i386/i386.exp: Add MSRLIST tests. * testsuite/gas/i386/msrlist-inval.l: New test. * testsuite/gas/i386/msrlist-inval.s: Ditto. * testsuite/gas/i386/x86-64-msrlist-intel.d: Ditto. * testsuite/gas/i386/x86-64-msrlist.d: Ditto. * testsuite/gas/i386/x86-64-msrlist.s: Ditto. opcodes/ChangeLog: * i386-dis.c (X86_64_0F01_REG_0_MOD_3_RM_6_P_1): New. (X86_64_0F01_REG_0_MOD_3_RM_6_P_3): Ditto. (prefix_table): New entry for msrlist. (x86_64_table): Add X86_64_0F01_REG_0_MOD_3_RM_6_P_1 and X86_64_0F01_REG_0_MOD_3_RM_6_P_3. * i386-gen.c (cpu_flag_init): Add CPU_MSRLIST_FLAGS and CPU_ANY_MSRLIST_FLAGS. * i386-init.h: Regenerated. * i386-opc.h (CpuMSRLIST): New. (i386_cpu_flags): Add cpumsrlist. * i386-opc.tbl: Add MSRLIST instructions. * i386-tbl.h: Regenerated.
* Support Intel WRMSRNSHu, Lin12022-11-026-4160/+4212
| | | | | | | | | | | | | | | | | | | | | | | | | | | | gas/ChangeLog: * NEWS: Support Intel WRMSRNS. * config/tc-i386.c: Add wrmsrns. * doc/c-i386.texi: Document .wrmsrns. * testsuite/gas/i386/i386.exp: Add WRMSRNS tests. * testsuite/gas/i386/wrmsrns-intel.d: New test. * testsuite/gas/i386/wrmsrns.d: Ditto. * testsuite/gas/i386/wrmsrns.s: Ditto. * testsuite/gas/i386/x86-64-wrmsrns-intel.d: Ditto. * testsuite/gas/i386/x86-64-wrmsrns.d: Ditto. opcodes/ChangeLog: * i386-dis.c (PREFIX_0F01_REG_0_MOD_3_RM_6): New. (prefix_table): Add PREFIX_0F01_REG_0_MOD_3_RM_6. (rm_table): New entry for wrmsrns. * i386-gen.c (cpu_flag_init): Add CPU_WRMSRNS_FLAGS and CPU_ANY_WRMSRNS_FLAGS. (cpu_flags): Add CpuWRMSRNS. * i386-init.h: Regenerated. * i386-opc.h (CpuWRMSRNS): New. (i386_cpu_flags): Add cpuwrmsrns. * i386-opc.tbl: Add WRMSRNS instructions. * i386-tbl.h: Regenerated.
* Support Intel CMPccXADDHaochen Jiang2022-11-026-4150/+4805
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gas/ChangeLog: * NEWS: Support Intel CMPccXADD. * config/tc-i386.c: Add cmpccxadd. (build_modrm_byte): Add operations for Vex.VVVV reg on operand 0 while have memory operand. * doc/c-i386.texi: Document .cmpccxadd. * testsuite/gas/i386/i386.exp: Run CMPccXADD tests. * testsuite/gas/i386/cmpccxadd-inval.s: New test. * testsuite/gas/i386/cmpccxadd-inval.l: Ditto. * testsuite/gas/i386/x86-64-cmpccxadd-intel.d: Ditto. * testsuite/gas/i386/x86-64-cmpccxadd.s: Ditto. * testsuite/gas/i386/x86-64-cmpccxadd.d: Ditto. opcodes/ChangeLog: * i386-dis.c (Mdq): New. (X86_64_VEX_0F38E0): Ditto. (X86_64_VEX_0F38E1): Ditto. (X86_64_VEX_0F38E2): Ditto. (X86_64_VEX_0F38E3): Ditto. (X86_64_VEX_0F38E4): Ditto. (X86_64_VEX_0F38E5): Ditto. (X86_64_VEX_0F38E6): Ditto. (X86_64_VEX_0F38E7): Ditto. (X86_64_VEX_0F38E8): Ditto. (X86_64_VEX_0F38E9): Ditto. (X86_64_VEX_0F38EA): Ditto. (X86_64_VEX_0F38EB): Ditto. (X86_64_VEX_0F38EC): Ditto. (X86_64_VEX_0F38ED): Ditto. (X86_64_VEX_0F38EE): Ditto. (X86_64_VEX_0F38EF): Ditto. (x86_64_table): Add X86_64_VEX_0F38E0, X86_64_VEX_0F38E1, X86_64_VEX_0F38E2, X86_64_VEX_0F38E3, X86_64_VEX_0F38E4, X86_64_VEX_0F38E5, X86_64_VEX_0F38E6, X86_64_VEX_0F38E7, X86_64_VEX_0F38E8, X86_64_VEX_0F38E9, X86_64_VEX_0F38EA, X86_64_VEX_0F38EB, X86_64_VEX_0F38EC, X86_64_VEX_0F38ED, X86_64_VEX_0F38EE, X86_64_VEX_0F38EF. * i386-gen.c (cpu_flag_init): Add CPU_CMPCCXADD_FLAGS and CPU_ANY_CMPCCXADD_FLAGS. (cpu_flags): Add CpuCMPCCXADD. * i386-init.h: Regenerated. * i386-opc.h (CpuCMPCCXADD): New. (i386_cpu_flags): Add cpucmpccxadd. Comment unused for it is actually 0. * i386-opc.tbl: Add Intel CMPccXADD instructions. * i386-tbl.h: Regenerated.
* Support Intel AVX-VNNI-INT8Cui,Lili2022-11-026-456/+612
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gas/ * NEWS: Support Intel AVX-VNNI-INT8. * config/tc-i386.c: Add avx_vnni_int8. * doc/c-i386.texi: Document avx_vnni_int8. * testsuite/gas/i386/avx-vnni-int8-intel.d: New file. * testsuite/gas/i386/avx-vnni-int8.d: Likewise. * testsuite/gas/i386/avx-vnni-int8.s: Likewise. * testsuite/gas/i386/x86-64-avx-vnni-int8-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx-vnni-int8.d: Likewise. * testsuite/gas/i386/x86-64-avx-vnni-int8.s: Likewise. * testsuite/gas/i386/i386.exp: Run AVX VNNI INT8 tests. opcodes/ * i386-dis.c: (PREFIX_VEX_0F3850) New. (PREFIX_VEX_0F3851): Likewise. (VEX_W_0F3850_P_0): Likewise. (VEX_W_0F3850_P_1): Likewise. (VEX_W_0F3850_P_2): Likewise. (VEX_W_0F3850_P_3): Likewise. (VEX_W_0F3851_P_0): Likewise. (VEX_W_0F3851_P_1): Likewise. (VEX_W_0F3851_P_2): Likewise. (VEX_W_0F3851_P_3): Likewise. (VEX_W_0F3850): Delete. (VEX_W_0F3851): Likewise. (prefix_table): Add PREFIX_VEX_0F3850 and PREFIX_VEX_0F3851. (vex_table): Add PREFIX_VEX_0F3850 and PREFIX_VEX_0F3851, delete VEX_W_0F3850 and VEX_W_0F3851. (vex_w_table): Add VEX_W_0F3850_P_0, VEX_W_0F3850_P_1, VEX_W_0F3850_P_2 VEX_W_0F3850_P_3, VEX_W_0F3851_P_0, VEX_W_0F3851_P_1, VEX_W_0F3851_P_2 and VEX_W_0F3851_P_3, delete VEX_W_0F3850 and VEX_W_0F3851. * i386-gen.c: (cpu_flag_init): Add CPU_AVX_VNNI_INT8_FLAGS and CPU_ANY_AVX_VNNI_INT8_FLAGS. (cpu_flags): Add CpuAVX_VNNI_INT8. * i386-opc.h (CpuAVX_VNNI_INT8): New. * i386-opc.tbl: Add Intel AVX_VNNI_INT8 instructions. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
* Support Intel AVX-IFMAHongyu Wang2022-11-027-4145/+4224
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | x86: Support Intel AVX-IFMA Intel AVX IFMA instructions are marked with CpuVEX_PREFIX, which is cleared by default. Without {vex} pseudo prefix, Intel IFMA instructions are encoded with EVEX prefix. {vex} pseudo prefix will turn on VEX encoding for Intel IFMA instructions. gas/ * NEWS: Support Intel AVX-IFMA. * config/tc-i386.c (cpu_arch): Add avx_ifma. * doc/c-i386.texi: Document .avx_ifma. * testsuite/gas/i386/avx-ifma.d: New file. * testsuite/gas/i386/avx-ifma-intel.d: Likewise. * testsuite/gas/i386/avx-ifma.s: Likewise. * testsuite/gas/i386/x86-64-avx-ifma.d: Likewise. * testsuite/gas/i386/x86-64-avx-ifma-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx-ifma.s: Likewise. * testsuite/gas/i386/i386.exp: Run AVX IFMA tests. opcodes/ * i386-dis.c (PREFIX_VEX_0F38B4): New. (PREFIX_VEX_0F38B5): Likewise. (VEX_W_0F38B4_P_2): Likewise. (VEX_W_0F38B5_P_2): Likewise. (prefix_table): Add PREFIX_VEX_0F38B4 and PREFIX_VEX_0F38B5. (vex_table): Add VEX_W_0F38B4_P_2 and VEX_W_0F38B5_P_2. * i386-dis-evex.h: Fold AVX512IFMA entries to AVX-IFMA. * i386-gen.c (cpu_flag_init): Clear the CpuAVX_IFMA bit in CPU_UNKNOWN_FLAGS. Add CPU_AVX_IFMA_FLGAS and CPU_ANY_AVX_IFMA_FLAGS. Add CpuAVX_IFMA to CPU_AVX2_FLAGS. (cpu_flags): Add CpuAVX_IFMA. * i386-opc.h (CpuAVX_IFMA): New. (i386_cpu_flags): Add cpuavx_ifma. * i386-opc.tbl: Add Intel AVX IFMA instructions. * i386-init.h: Regenerated. * i386-tbl.h: Likewise. Co-authored-by: Haochen Jiang <haochen.jiang@intel.com>
* opcodes/arm: don't pass non-string literal to printf like functionAndrew Burgess2022-11-011-2/+3
| | | | | | | | | | | | | | | | | | | | The earlier commit: commit 6576bffe6cbbb53c5756b2fccd2593ba69b74cdf Date: Thu Jul 7 13:43:45 2022 +0100 opcodes/arm: add disassembler styling for arm introduced two places where a register name was passed as the format string to the disassembler's fprintf_styled_func callback. This will cause a warning from some compilers, like this: ../../binutils-gdb/opcodes/arm-dis.c: In function ‘print_mve_vld_str_addr’: ../../binutils-gdb/opcodes/arm-dis.c:6005:3: error: format not a string literal and no format arguments [-Werror=format-security] 6005 | func (stream, dis_style_register, arm_regnames[gpr]); | ^~~~ This commit fixes these by using "%s" as the format string.
* opcodes/arm: silence compiler warning about uninitialized variable useAndrew Burgess2022-11-011-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The earlier commit: commit 6576bffe6cbbb53c5756b2fccd2593ba69b74cdf Date: Thu Jul 7 13:43:45 2022 +0100 opcodes/arm: add disassembler styling for arm was causing a compiler warning about a possible uninitialized variable usage within opcodes/arm-dis.c. The problem is in print_mve_unpredictable, and relates to the reason variable, which is set by a switch table. Currently the switch table does cover every valid value, though there is no default case. The variable switched on is passed in as an argument to the print_mve_unpredictable function. Looking at how print_mve_unpredictable is used, there is only one use, the second argument is the one that is used for the switch table, looking at how this argument is set, I don't believe it is possible for this argument to take an invalid value. So, I think the compiler warning is a false positive. As such, my proposed solution is to initialize the reason variable to the string "??", this will silence the warning, and the "??" string should never end up being printed.
* opcodes/arm: add disassembler styling for armAndrew Burgess2022-11-012-1002/+1631
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds disassembler styling for the ARM architecture. The ARM disassembler is driven by several instruction tables, e.g. cde_opcodes, coprocessor_opcodes, neon_opcodes, etc The type for elements in each table can vary, but they all have one thing in common, a 'const char *assembler' field. This field contains a string that describes the assembler syntax of the instruction. Embedded within that assembler syntax are various escape characters, prefixed with a '%'. Here's an example of a very simple instruction from the arm_opcodes table: "pld\t%a" The '%a' indicates a particular type of operand, the function print_insn_arm processes the arm_opcodes table, and includes a switch statement that handles the '%a' operand, and takes care of printing the correct value for that instruction operand. It is worth noting that there are many print_* functions, each function handles a single *_opcodes table, and includes its own switch statement for operand handling. As a result, every *_opcodes table uses a different mapping for the operand escape sequences. This means that '%a' might print an address for one *_opcodes table, but in a different *_opcodes table '%a' might print a register operand. Notice as well that in our example above, the instruction mnemonic 'pld' is embedded within the assembler string. Some instructions also include comments within the assembler string, for example, also from the arm_opcodes table: "nop\t\t\t@ (mov r0, r0)" here, everything after the '@' is a comment that is displayed at the end of the instruction disassembly. The next complexity is that the meaning of some escape sequences is not necessarily fixed. Consider these two examples from arm_opcodes: "ldrex%c\tr%12-15d, [%16-19R]" "setpan\t#%9-9d" Here, the '%d' escape is used with a bitfield modifier, '%12-15d' in the first instruction, and '%9-9d' in the second instruction, but, both of these are the '%d' escape. However, in the first instruction, the '%d' is used to print a register number, notice the 'r' immediately before the '%d'. In the second instruction the '%d' is used to print an immediate, notice the '#' just before the '%d'. We have two problems here, first, the '%d' needs to know if it should use register style or immediate style, and secondly, the 'r' and '#' characters also need to be styled appropriately. The final thing we must consider is that some escape codes result in more than just a single operand being printed, for example, the '%q' operand as used in arm_opcodes ends up calling arm_decode_shift, which can print a register name, a shift type, and a shift amount, this could end up using register, sub-mnemonic, and immediate styles, as well as the text style for things like ',' between the different parts. I propose a three layer approach to adding styling: (1) Basic state machine: When we start printing an instruction we should maintain the idea of a 'base_style'. Every character from the assembler string will be printed using the base_style. The base_style will start as mnemonic, as each instruction starts with an instruction mnemonic. When we encounter the first '\t' character, the base_style will change to text. When we encounter the first '@' the base_style will change to comment_start. This simple state machine ensures that for simple instructions the basic parts, except for the operands themselves, will be printed in the correct style. (2) Simple operand styling: For operands that only have a single meaning, or which expand to multiple parts, all of which have a consistent meaning, then I will simply update the operand printing code to print the operand with the correct style. This will cover a large number of the operands, and is the most consistent with how styling has been added to previous architectures. (3) New styling syntax in assembler strings: For cases like the '%d' that I describe above, I propose adding a new extension to the assembler syntax. This extension will allow me to temporarily change the base_style. Operands like '%d', will then print using the base_style rather than using a fixed style. Here are the two examples from above that use '%d', updated with the new syntax extension: "ldrex%c\t%{R:r%12-15d%}, [%16-19R]" "setpan\t%{I:#%9-9d%}" The syntax has the general form '%{X:....%}' where the 'X' character changes to indicate a different style. In the first instruction I use '%{R:...%}' to change base_style to the register style, and in the second '%{I:...%}' changes base_style to immediate style. Notice that the 'r' and '#' characters are included within the new style group, this ensures that these characters are printed with the correct style rather than as text. The function decode_base_style maps from character to style. I've included a character for each style for completeness, though only a small number of styles are currently used. I have updated arm-dis.c to the above scheme, and checked all of the tests in gas/testsuite/gas/arm/, and the styling looks reasonable. There are no regressions on the ARM gas/binutils/ld tests that I can see, so I don't believe I've changed the output layout at all. There were two binutils tests for which I needed to force the disassembler styling off. I can't guarantee that I've not missed some untested corners of the disassembler, or that I might have just missed some incorrectly styled output when reviewing the test results, but I don't believe I've introduced any changes that could break the disassembler - the worst should be some aspect is not styled correctly.
* opcodes/arm: use '@' consistently for the comment characterAndrew Burgess2022-11-011-48/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Looking at the ARM disassembler output, every comment seems to start with a ';' character, so I assumed this was the correct character to start an assembler comment. I then spotted a couple of places where there was no ';', but instead, just a '@' character. I thought that this was a case of a missing ';', and proposed a patch to add the missing ';' characters. Turns out I was wrong, '@' is actually the ARM assembler comment character, while ';' is the statement separator. Thus this: nop ;@ comment is two statements, the first is the 'nop' instruction, while the second contains no instructions, just the '@ comment' comment text. This: nop @ comment is a single 'nop' instruction followed by a comment. And finally, this: nop ; comment is two statements, the first contains the 'nop' instruction, while the second contains the instruction 'comment', which obviously isn't actually an instruction at all. Why this matters is that, in the next commit, I would like to add libopcodes syntax styling support for ARM. The question then is how should the disassembler style the three cases above? As '@' is the actual comment start character then clearly the '@' and anything after it can be styled as a comment. But what about ';' in the second example? Style as text? Style as a comment? And the third example is even harder, what about the 'comment' text? Style as an instruction mnemonic? Style as text? Style as a comment? I think the only sensible answer is to move the disassembler to use '@' consistently as its comment character, and remove all the uses of ';'. Then, in the next commit, it's obvious what to do. There's obviously a *lot* of tests that get updated by this commit, the only actual code changes are in opcodes/arm-dis.c.
* x86: minor improvements to optimize_imm() (part III)Jan Beulich2022-10-312-6/+0
| | | | | | | | | Earlier tidying still missed an opportunity: There's no need for the "anyimm" static variable. Instead of using it in the loop to mask "allowed" (which is necessary to satisfy operand_type_or()'s assertions) simply use "mask", requiring it to be calculated first. That way the post-loop masking by "mask" ahead of the operand_type_all_zero() can be dropped.
* Updated Romainain translation for the binutils sub-directory and Swedish ↵Nick Clifton2022-10-311-399/+475
| | | | translations for the ld and opcodes sub-directories.
* Support Intel PREFETCHICui, Lili2022-10-316-4141/+4263
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gas/ChangeLog: * NEWS: Add support for Intel PREFETCHI instruction. * config/tc-i386.c (load_insn_p): Use prefetch* to fold all prefetches. (md_assemble): Add warning for illegal input of PREFETCHI. * doc/c-i386.texi: Document .prefetchi. * testsuite/gas/i386/i386.exp: Run PREFETCHI tests. * testsuite/gas/i386/x86-64-lfence-load.d: Add PREFETCHI. * testsuite/gas/i386/x86-64-lfence-load.s: Likewise. * testsuite/gas/i386/x86-64-prefetch.d: New test. * testsuite/gas/i386/x86-64-prefetchi-intel.d: Likewise. * testsuite/gas/i386/x86-64-prefetchi-inval-register.d: Likewise.. * testsuite/gas/i386/x86-64-prefetchi-inval-register.s: Likewise. * testsuite/gas/i386/x86-64-prefetchi-warn.l: Likewise. * testsuite/gas/i386/x86-64-prefetchi-warn.s: Likewise. * testsuite/gas/i386/x86-64-prefetchi.d: Likewise. * testsuite/gas/i386/x86-64-prefetchi.s: Likewise. opcodes/ChangeLog: * i386-dis.c (reg_table): Add MOD_0F18_REG_6 and MOD_0F18_REG_7 (x86_64_table): Add X86_64_0F18_REG_6_MOD_0 and X86_64_0F18_REG_7_MOD_0. (mod_table): Add MOD_0F18_REG_6 and MOD_0F18_REG_7. (prefix_table): Add PREFIX_0F18_REG_6_MOD_0_X86_64 and PREFIX_0F18_REG_7_MOD_0_X86_64. (PREFETCHI_Fixup): New. * i386-gen.c (cpu_flag_init): Add CPU_PREFETCHI_FLAGS. (cpu_flags): Add CpuPREFETCHI. * i386-opc.h (CpuPREFETCHI): New. (i386_cpu_flags): Add cpuprefetchi. * i386-opc.tbl: Add Intel PREFETCHI instructions. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
* RX assembler: switch arguments of thw MVTACGU insn.Yoshinori Sato2022-10-313-8/+13
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* RISC-V: Output mapping symbols with ISA string.Nelson Chu2022-10-281-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | RISC-V Psabi pr196, https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/196 bfd/ * elfxx-riscv.c (riscv_release_subset_list): Free arch_str if needed. (riscv_copy_subset_list): Copy arch_str as well. * elfxx-riscv.h (riscv_subset_list_t): Store arch_str for each subset list. gas/ * config/tc-riscv.c (riscv_reset_subsets_list_arch_str): Update the architecture string in the subset_list. (riscv_set_arch): Call riscv_reset_subsets_list_arch_str after parsing new architecture string. (s_riscv_option): Likewise. (need_arch_map_symbol): New boolean, used to indicate if .option directives do affect instructions. (make_mapping_symbol): New boolean parameter reset_seg_arch_str. Need to generate $x+arch for MAP_INSN, and then store it into tc_segment_info_data if reset_seg_arch_str is true. (riscv_mapping_state): Decide if we need to add $x+arch for MAP_INSN. For now, only add $x+arch if the architecture strings in subset list and segment are different. Besides, always add $x+arch at the start of section, and do not add $x+arch for code alignment, since rvc for alignment can be judged from addend of R_RISCV_ALIGN. (riscv_remove_mapping_symbol): If current and previous mapping symbol have same value, then remove the current $x only if the previous is $x+arch; Otherwise, always remove previous. (riscv_add_odd_padding_symbol): Updated. (riscv_check_mapping_symbols): Don't need to add any $x+arch if need_arch_map_symbol is false, so changed them to $x. (riscv_frag_align_code): Updated since riscv_mapping_state is changed. (riscv_init_frag): Likewise. (s_riscv_insn): Likewise. (riscv_elf_final_processing): Call riscv_release_subset_list to release subset_list of riscv_rps_as, rather than only release arch_str in the riscv_write_out_attrs. (riscv_write_out_attrs): No need to call riscv_arch_str, just get arch_str from subset_list of riscv_rps_as. * config/tc-riscv.h (riscv_segment_info_type): Record current $x+arch mapping symbol of each segment. * testsuite/gas/riscv/mapping-0*: Merged and replaced by mapping.s. * testsuite/gas/riscv/mapping.s: New testcase, to test most of the cases in one file. * testsuite/gas/riscv/mapping-symbols.d: Likewise. * testsuite/gas/riscv/mapping-dis.d: Likewise. * testsuite/gas/riscv/mapping-non-arch.s: New testcase for the case that does need any $x+arch. * testsuite/gas/riscv/mapping-non-arch.d: Likewise. * testsuite/gas/riscv/option-arch-01a.d: Updated. opcodes/ * riscv-dis.c (riscv_disassemble_insn): Set riscv_fpr_names back to riscv_fpr_names_abi or riscv_fpr_names_numeric when zfinx is disabled for some specfic code region. (riscv_get_map_state): Recognized mapping symbols $x+arch, and then reset the architecture string once the ISA is different.
* PowerPC: Add support for RFC02658 - MMA+ Outer-Product InstructionsPeter Bergner2022-10-271-1/+38
| | | | | | | | | | | | | | | | | | gas/ * config/tc-ppc.c (md_assemble): Only check for prefix opcodes. * testsuite/gas/ppc/rfc02658.s: New test. * testsuite/gas/ppc/rfc02658.d: Likewise. * testsuite/gas/ppc/ppc.exp: Run it. opcodes/ * ppc-opc.c (XMSK8, P_GERX4_MASK, P_GERX2_MASK, XX3GERX_MASK): New. (powerpc_opcodes): Add dmxvi8gerx4pp, dmxvi8gerx4, dmxvf16gerx2pp, dmxvf16gerx2, dmxvbf16gerx2pp, dmxvf16gerx2np, dmxvbf16gerx2, dmxvi8gerx4spp, dmxvbf16gerx2np, dmxvf16gerx2pn, dmxvbf16gerx2pn, dmxvf16gerx2nn, dmxvbf16gerx2nn, pmdmxvi8gerx4pp, pmdmxvi8gerx4, pmdmxvf16gerx2pp, pmdmxvf16gerx2, pmdmxvbf16gerx2pp, pmdmxvf16gerx2np, pmdmxvbf16gerx2, pmdmxvi8gerx4spp, pmdmxvbf16gerx2np, pmdmxvf16gerx2pn, pmdmxvbf16gerx2pn, pmdmxvf16gerx2nn, pmdmxvbf16gerx2nn.
* PowerPC: Add support for RFC02653 - Dense Math FacilityPeter Bergner2022-10-272-26/+191
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gas/ * config/tc-ppc.c (pre_defined_registers): Add dense math registers. (md_assemble): Check dmr specified in correct operand. * testsuite/gas/ppc/outerprod.s <dmsetaccz, dmxvbf16ger2, dmxvbf16ger2nn, dmxvbf16ger2np, dmxvbf16ger2pn, dmxvbf16ger2pp, dmxvf16ger2, dmxvf16ger2nn, dmxvf16ger2np, dmxvf16ger2pn, dmxvf16ger2pp, dmxvf32ger, dmxvf32gernn, dmxvf32gernp, dmxvf32gerpn, dmxvf32gerpp, dmxvf64ger, dmxvf64gernn, dmxvf64gernp, dmxvf64gerpn, dmxvf64gerpp, dmxvi16ger2, dmxvi16ger2pp, dmxvi16ger2s, dmxvi16ger2spp, dmxvi4ger8, dmxvi4ger8pp, dmxvi8ger4, dmxvi8ger4pp, dmxvi8ger4spp, dmxxmfacc, dmxxmtacc, pmdmxvbf16ger2, pmdmxvbf16ger2nn, pmdmxvbf16ger2np, pmdmxvbf16ger2pn, pmdmxvbf16ger2pp, pmdmxvf16ger2, pmdmxvf16ger2nn, pmdmxvf16ger2np, pmdmxvf16ger2pn, pmdmxvf16ger2pp, pmdmxvf32ger, pmdmxvf32gernn, pmdmxvf32gernp, pmdmxvf32gerpn, pmdmxvf32gerpp, pmdmxvf64ger, pmdmxvf64gernn, pmdmxvf64gernp, pmdmxvf64gerpn, pmdmxvf64gerpp, pmdmxvi16ger2, pmdmxvi16ger2pp, pmdmxvi16ger2s, pmdmxvi16ger2spp, pmdmxvi4ger8, pmdmxvi4ger8pp, pmdmxvi8ger4, pmdmxvi8ger4pp, pmdmxvi8ger4spp>: Add new tests. * testsuite/gas/ppc/outerprod.d: Likewise. * testsuite/gas/ppc/rfc02653.s: New test. * testsuite/gas/ppc/rfc02653.d: Likewise. * testsuite/gas/ppc/ppc.exp: Run it. include/ * opcode/ppc.h (PPC_OPERAND_DMR): Define. Renumber following PPC_OPERAND defines. opcodes/ * ppc-dis.c (print_insn_powerpc): Prepend 'dm' when printing DMR regs. * ppc-opc.c (insert_p2, (extract_p2, (insert_xa5, (extract_xa5, insert_xb5, (extract_xb5): New functions. (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a): Disallow operand overlap only on Power10. (DMR, DMRAB, P1, P2, XA5p, XB5p, XDMR_MASK, XDMRDMR_MASK, XX2ACC_MASK, XX2DMR_MASK, XX3DMR_MASK): New defines. (powerpc_opcodes): Add dmmr, dmsetaccz, dmsetdmrz, dmxor, dmxvbf16ger2, dmxvbf16ger2nn, dmxvbf16ger2np, dmxvbf16ger2pn, dmxvbf16ger2pp, dmxvf16ger2, dmxvf16ger2nn, dmxvf16ger2np, dmxvf16ger2pn, dmxvf16ger2pp, dmxvf32ger, dmxvf32gernn, dmxvf32gernp, dmxvf32gerpn, dmxvf32gerpp, dmxvf64ger, dmxvf64gernn, dmxvf64gernp, dmxvf64gerpn, dmxvf64gerpp, dmxvi16ger2, dmxvi16ger2pp, dmxvi16ger2s, dmxvi16ger2spp, dmxvi4ger8, dmxvi4ger8pp, dmxvi8ger4, dmxvi8ger4pp, dmxvi8ger4spp, dmxxextfdmr256, dmxxextfdmr512, dmxxinstdmr256, dmxxinstdmr512, dmxxmfacc, dmxxmtacc, pmdmxvbf16ger2, pmdmxvbf16ger2nn, pmdmxvbf16ger2np, pmdmxvbf16ger2pn, pmdmxvbf16ger2pp, pmdmxvf16ger2, pmdmxvf16ger2nn, pmdmxvf16ger2np, pmdmxvf16ger2pn, pmdmxvf16ger2pp, pmdmxvf32ger, pmdmxvf32gernn, pmdmxvf32gernp, pmdmxvf32gerpn, pmdmxvf32gerpp, pmdmxvf64ger, pmdmxvf64gernn, pmdmxvf64gernp, pmdmxvf64gerpn, pmdmxvf64gerpp, pmdmxvi16ger2, pmdmxvi16ger2pp, pmdmxvi16ger2s, pmdmxvi16ger2spp, pmdmxvi4ger8, pmdmxvi4ger8pp, pmdmxvi8ger4, pmdmxvi8ger4pp, pmdmxvi8ger4spp.
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