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* opcodes/mips: use .word/.short for undefined instructionsAndrew Burgess2022-12-051-3/+6
* x86: Allow 16-bit register source for LAR and LSLH.J. Lu2022-12-033-18/+6
* x86: drop most OPERAND_TYPE_* (and rework the rest)Jan Beulich2022-12-022-287/+0
* x86: also use D for XCHG and TESTJan Beulich2022-12-022-57/+9
* opcodes: Remove i386-init.h and i386-tbl.h from HFILESH.J. Lu2022-12-013-6/+0
* x86: drop No_ldSufJan Beulich2022-12-014-11598/+11594
* x86/Intel: drop LONG_DOUBLE_MNEM_SUFFIXJan Beulich2022-12-012-4/+4
* x86/Intel: restrict use of LONG_DOUBLE_MNEM_SUFFIXJan Beulich2022-12-012-8/+8
* x86: clean up after removal of support for gcc <= 2.8.1Jan Beulich2022-11-302-36/+5
* x86: drop FloatRJan Beulich2022-11-304-11255/+11187
* RISC-V: Better support for long instructions (disassembler)Tsukasa OI2022-11-281-5/+9
* x86: widen applicability and use of CheckRegSizeJan Beulich2022-11-242-14/+14
* x86: add missing CheckRegSizeJan Beulich2022-11-242-6/+6
* x86: correct handling of LAR and LSLJan Beulich2022-11-243-6/+50
* PR16995, m68k coldfire emac immediate to macsr incorrect disassemblyAlan Modra2022-11-241-2/+2
* opcodes: Correct address for ARC's "isa_config" aux regShahab Vahedi2022-11-222-1/+7
* opcodes: Define NoSuf in i386-opc.tblH.J. Lu2022-11-171-1847/+1848
* i386: Move i386_seg_prefixes to gasH.J. Lu2022-11-172-11/+0
* RISC-V: Add T-Head Int vendor extensionChristoph Müllner2022-11-171-0/+4
* RISC-V: Add T-Head Fmv vendor extensionChristoph Müllner2022-11-171-0/+4
* Add AMD znver4 processor supportTejas Joshi2022-11-156-4052/+4129
* aarch64: Add support for Common Short Sequence Compression extensionAndre Vieira2022-11-146-49/+166
* x86: fold special-operand insn attributes into a single enumJan Beulich2022-11-144-11219/+11210
* PowerPC64 paddi -MrawAlan Modra2022-11-121-10/+10
* x86: drop stray IsString from PadLock insnsJan Beulich2022-11-112-32/+32
* [opcodes/arm] Fix potential null pointer dereferencesLuis Machado2022-11-101-1/+5
* RISC-V: xtheadfmemidx: Use fp register in mnemonicsChristoph Müllner2022-11-091-8/+8
* PowerPC: Add XSP operand definePeter Bergner2022-11-081-5/+6
* x86: Correct wrong comments in vex_w_tableHaochen Jiang2022-11-081-1/+1
* Support Intel RAO-INTKong Lingling2022-11-086-4174/+4278
* opcodes/arm: silence compiler warning about uninitialized variable useAndrew Burgess2022-11-041-1/+3
* Support Intel AVX-NE-CONVERTkonglin12022-11-046-4169/+4397
* i386: Rename <xy> template.konglin12022-11-041-17/+18
* x86: drop bogus TbyteJan Beulich2022-11-022-4/+4
* Support Intel MSRLISTHu, Lin12022-11-026-4161/+4237
* Support Intel WRMSRNSHu, Lin12022-11-026-4160/+4212
* Support Intel CMPccXADDHaochen Jiang2022-11-026-4150/+4805
* Support Intel AVX-VNNI-INT8Cui,Lili2022-11-026-456/+612
* Support Intel AVX-IFMAHongyu Wang2022-11-027-4145/+4224
* opcodes/arm: don't pass non-string literal to printf like functionAndrew Burgess2022-11-011-2/+3
* opcodes/arm: silence compiler warning about uninitialized variable useAndrew Burgess2022-11-011-1/+3
* opcodes/arm: add disassembler styling for armAndrew Burgess2022-11-012-1002/+1631
* opcodes/arm: use '@' consistently for the comment characterAndrew Burgess2022-11-011-48/+48
* x86: minor improvements to optimize_imm() (part III)Jan Beulich2022-10-312-6/+0
* Updated Romainain translation for the binutils sub-directory and Swedish tran...Nick Clifton2022-10-311-399/+475
* Support Intel PREFETCHICui, Lili2022-10-316-4141/+4263
* RX assembler: switch arguments of thw MVTACGU insn.Yoshinori Sato2022-10-313-8/+13
* RISC-V: Output mapping symbols with ISA string.Nelson Chu2022-10-281-0/+9
* PowerPC: Add support for RFC02658 - MMA+ Outer-Product InstructionsPeter Bergner2022-10-271-1/+38
* PowerPC: Add support for RFC02653 - Dense Math FacilityPeter Bergner2022-10-272-26/+191
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