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authorAndre Vieira <andre.simoesdiasvieira@arm.com>2022-11-14 16:47:22 +0000
committerAndre Vieira <andre.simoesdiasvieira@arm.com>2022-11-14 16:47:22 +0000
commit1f7b42d52a8cb690c259eaa4975a608e82d7267a (patch)
tree8e0d1faeeb5f8cfb1cf2caf218936c625ac46e98 /opcodes
parent255571cdbf05213cc96feefb779c4158df453398 (diff)
downloadbinutils-gdb-1f7b42d52a8cb690c259eaa4975a608e82d7267a.tar.gz
aarch64: Add support for Common Short Sequence Compression extension
This patch adds support for the CSSC extension and its corresponding instructions: ABS, CNT, CTZ, SMAX, UMAX, SMIN, UMIN. gas/ChangeLog: * config/tc-aarch64.c (parse_operands): Handle new operand types. * doc/c-aarch64.texi: Document new extension. * testsuite/gas/aarch64/cssc.d: New test. * testsuite/gas/aarch64/cssc.s: New test. include/ChangeLog: * opcode/aarch64.h (AARCH64_FEATURE_CSSC): New feature Macro. (enum aarch64_opnd): New operand types. (enum aarch64_insn_class): New instruction class. opcodes/ChangeLog: * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. * aarch64-opc.c (operand_general_constraint_met_p): Update for new operand types. (aarch64_print_operand): Likewise. * aarch64-opc.h (enum aarch64_field_kind): Declare FLD_CSSC_imm8 field. * aarch64-tbl.h (aarch64_feature_cssc): Define new feature set. (CSSC): Define new feature set Macro. (CSSC_INSN): Define new instruction type. (aarch64_opcode_table): Add new instructions.
Diffstat (limited to 'opcodes')
-rw-r--r--opcodes/aarch64-asm-2.c2
-rw-r--r--opcodes/aarch64-dis-2.c177
-rw-r--r--opcodes/aarch64-opc-2.c2
-rw-r--r--opcodes/aarch64-opc.c5
-rw-r--r--opcodes/aarch64-opc.h3
-rw-r--r--opcodes/aarch64-tbl.h26
6 files changed, 166 insertions, 49 deletions
diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c
index 38bc5d7cfa6..23c4e817368 100644
--- a/opcodes/aarch64-asm-2.c
+++ b/opcodes/aarch64-asm-2.c
@@ -723,6 +723,8 @@ aarch64_insert_operand (const aarch64_operand *self,
case 190:
case 215:
case 221:
+ case 226:
+ case 227:
return aarch64_ins_imm (self, info, code, inst, errors);
case 44:
case 45:
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index 69a15789947..318b0717c39 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -4201,21 +4201,43 @@ aarch64_opcode_lookup_1 (uint32_t word)
}
else
{
- if (((word >> 30) & 0x1) == 0)
+ if (((word >> 14) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x0x11010110xxxxxxx1000xxxxxxxxxx
- lslv. */
- return 713;
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0x11010110xxxxxx01000xxxxxxxxxx
+ lslv. */
+ return 713;
+ }
+ else
+ {
+ if (((word >> 16) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1x11010110xxxx0x01000xxxxxxxxxx
+ abs. */
+ return 2640;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1x11010110xxxx1x01000xxxxxxxxxx
+ paciza. */
+ return 701;
+ }
+ }
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x1x11010110xxxxxxx1000xxxxxxxxxx
- paciza. */
- return 701;
+ xxx11010110xxxxxx11000xxxxxxxxxx
+ smax. */
+ return 2643;
}
}
}
@@ -4385,21 +4407,32 @@ aarch64_opcode_lookup_1 (uint32_t word)
}
else
{
- if (((word >> 30) & 0x1) == 0)
+ if (((word >> 14) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x0x11010110xxxxxxx1010xxxxxxxxxx
- asrv. */
- return 717;
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0x11010110xxxxxx01010xxxxxxxxxx
+ asrv. */
+ return 717;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1x11010110xxxxxx01010xxxxxxxxxx
+ pacdza. */
+ return 703;
+ }
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x1x11010110xxxxxxx1010xxxxxxxxxx
- pacdza. */
- return 703;
+ xxx11010110xxxxxx11010xxxxxxxxxx
+ smin. */
+ return 2645;
}
}
}
@@ -4409,11 +4442,22 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
if (((word >> 14) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxx11010110xxxxxx00110xxxxxxxxxx
- autda. */
- return 699;
+ if (((word >> 16) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxx11010110xxxx0x00110xxxxxxxxxx
+ ctz. */
+ return 2642;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxx11010110xxxx1x00110xxxxxxxxxx
+ autda. */
+ return 699;
+ }
}
else
{
@@ -4518,21 +4562,32 @@ aarch64_opcode_lookup_1 (uint32_t word)
}
else
{
- if (((word >> 30) & 0x1) == 0)
+ if (((word >> 14) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x0x11010x10xxxxxxx1001xxxxxxxxxx
- lsrv. */
- return 715;
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0x11010x10xxxxxx01001xxxxxxxxxx
+ lsrv. */
+ return 715;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1x11010x10xxxxxx01001xxxxxxxxxx
+ pacizb. */
+ return 702;
+ }
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x1x11010x10xxxxxxx1001xxxxxxxxxx
- pacizb. */
- return 702;
+ xxx11010x10xxxxxx11001xxxxxxxxxx
+ umax. */
+ return 2644;
}
}
}
@@ -4637,21 +4692,32 @@ aarch64_opcode_lookup_1 (uint32_t word)
}
else
{
- if (((word >> 30) & 0x1) == 0)
+ if (((word >> 14) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x0x11010xx0xxxxxxx1011xxxxxxxxxx
- rorv. */
- return 719;
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0x11010xx0xxxxxx01011xxxxxxxxxx
+ rorv. */
+ return 719;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1x11010xx0xxxxxx01011xxxxxxxxxx
+ pacdzb. */
+ return 704;
+ }
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x1x11010xx0xxxxxxx1011xxxxxxxxxx
- pacdzb. */
- return 704;
+ xxx11010xx0xxxxxx11011xxxxxxxxxx
+ umin. */
+ return 2646;
}
}
}
@@ -4661,11 +4727,22 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
if (((word >> 14) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxx11010xx0xxxxxx00111xxxxxxxxxx
- autdb. */
- return 700;
+ if (((word >> 16) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxx11010xx0xxxx0x00111xxxxxxxxxx
+ cnt. */
+ return 2641;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxx11010xx0xxxx1x00111xxxxxxxxxx
+ autdb. */
+ return 700;
+ }
}
else
{
@@ -25111,7 +25188,11 @@ aarch64_find_next_opcode (const aarch64_opcode *opcode)
case 2403: value = 2408; break; /* st1q --> st1q. */
case 2408: return NULL; /* st1q --> NULL. */
case 12: value = 19; break; /* add --> addg. */
- case 19: return NULL; /* addg --> NULL. */
+ case 19: value = 2636; break; /* addg --> smax. */
+ case 2636: value = 2637; break; /* smax --> umax. */
+ case 2637: value = 2638; break; /* umax --> smin. */
+ case 2638: value = 2639; break; /* smin --> umin. */
+ case 2639: return NULL; /* umin --> NULL. */
case 16: value = 20; break; /* sub --> subg. */
case 20: return NULL; /* subg --> NULL. */
case 971: value = 975; break; /* stnp --> stp. */
@@ -25830,6 +25911,8 @@ aarch64_extract_operand (const aarch64_operand *self,
case 190:
case 215:
case 221:
+ case 226:
+ case 227:
return aarch64_ext_imm (self, info, code, inst, errors);
case 44:
case 45:
diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c
index a6ef7097a67..b680225917e 100644
--- a/opcodes/aarch64-opc-2.c
+++ b/opcodes/aarch64-opc-2.c
@@ -250,6 +250,8 @@ const struct aarch64_operand aarch64_operands[] =
{AARCH64_OPND_CLASS_INT_REG, "MOPS_ADDR_Rd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "a register destination address with writeback"},
{AARCH64_OPND_CLASS_INT_REG, "MOPS_ADDR_Rs", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rs}, "a register source address with writeback"},
{AARCH64_OPND_CLASS_INT_REG, "MOPS_WB_Rd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an integer register with writeback"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "CSSC_SIMM8", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CSSC_imm8}, "an 8-bit signed immediate"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "CSSC_UIMM8", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CSSC_imm8}, "an 8-bit unsigned immediate"},
{AARCH64_OPND_CLASS_NIL, "", 0, {0}, "DUMMY"},
};
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index a2882bdfaba..dd888b332c9 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -342,6 +342,7 @@ const aarch64_field fields[] =
{ 12, 2 }, /* SM3: Indexed element SM3 2 bits index immediate. */
{ 22, 1 }, /* sz: 1-bit element size select. */
{ 10, 2 }, /* CRm_dsb_nxs: 2-bit imm. encoded in CRm<3:2>. */
+ { 10, 8 }, /* CSSC_imm8. */
};
enum aarch64_operand_class
@@ -2176,6 +2177,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
case AARCH64_OPND_SVE_UIMM7:
case AARCH64_OPND_SVE_UIMM8:
case AARCH64_OPND_SVE_UIMM8_53:
+ case AARCH64_OPND_CSSC_UIMM8:
size = get_operand_fields_width (get_operand_from_code (type));
assert (size < 32);
if (!value_fit_unsigned_field_p (opnd->imm.value, size))
@@ -2206,6 +2208,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
case AARCH64_OPND_SVE_SIMM5B:
case AARCH64_OPND_SVE_SIMM6:
case AARCH64_OPND_SVE_SIMM8:
+ case AARCH64_OPND_CSSC_SIMM8:
size = get_operand_fields_width (get_operand_from_code (type));
assert (size < 32);
if (!value_fit_signed_field_p (opnd->imm.value, size))
@@ -3620,6 +3623,8 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
case AARCH64_OPND_SVE_IMM_ROT1:
case AARCH64_OPND_SVE_IMM_ROT2:
case AARCH64_OPND_SVE_IMM_ROT3:
+ case AARCH64_OPND_CSSC_SIMM8:
+ case AARCH64_OPND_CSSC_UIMM8:
snprintf (buf, size, "%s",
style_imm (styler, "#%" PRIi64, opnd->imm.value));
break;
diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h
index 126565dca14..b61e8eb96a8 100644
--- a/opcodes/aarch64-opc.h
+++ b/opcodes/aarch64-opc.h
@@ -168,7 +168,8 @@ enum aarch64_field_kind
FLD_rotate3,
FLD_SM3_imm2,
FLD_sz,
- FLD_CRm_dsb_nxs
+ FLD_CRm_dsb_nxs,
+ FLD_CSSC_imm8
};
/* Field description. */
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index adcc2fe0091..541fdc2d41e 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -2508,6 +2508,8 @@ static const aarch64_feature_set aarch64_feature_mops_memtag =
AARCH64_FEATURE (AARCH64_FEATURE_MOPS | AARCH64_FEATURE_MEMTAG, 0);
static const aarch64_feature_set aarch64_feature_hbc =
AARCH64_FEATURE (AARCH64_FEATURE_HBC, 0);
+static const aarch64_feature_set aarch64_feature_cssc =
+ AARCH64_FEATURE (AARCH64_FEATURE_CSSC, 0);
#define CORE &aarch64_feature_v8
#define FP &aarch64_feature_fp
@@ -2562,6 +2564,7 @@ static const aarch64_feature_set aarch64_feature_hbc =
#define MOPS &aarch64_feature_mops
#define MOPS_MEMTAG &aarch64_feature_mops_memtag
#define HBC &aarch64_feature_hbc
+#define CSSC &aarch64_feature_cssc
#define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL }
@@ -2695,6 +2698,8 @@ static const aarch64_feature_set aarch64_feature_hbc =
CONSTRAINTS, 0, VERIFIER }
#define HBC_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, 0, HBC, OPS, QUALS, FLAGS, 0, 0, NULL }
+#define CSSC_INSN(NAME,OPCODE,MASK,OPS,QUALS,FLAGS) \
+ { NAME, OPCODE, MASK, cssc, 0, CSSC, OPS, QUALS, FLAGS, 0, 0, NULL }
#define MOPS_CPY_OP1_OP2_PME_INSN(NAME, OPCODE, MASK, FLAGS, CONSTRAINTS) \
MOPS_INSN (NAME, OPCODE, MASK, 0, \
@@ -5437,6 +5442,21 @@ const struct aarch64_opcode aarch64_opcode_table[] =
HBC_INSN ("bc.c", 0x54000010, 0xff000010, condbranch, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_COND),
+/* CSSC with immediates. */
+ CSSC_INSN ("smax", 0x11c00000, 0x7ffc0000, OP3 (Rd, Rn, CSSC_SIMM8), QL_R2NIL, F_SF),
+ CSSC_INSN ("umax", 0x11c40000, 0x7ffc0000, OP3 (Rd, Rn, CSSC_UIMM8), QL_R2NIL, F_SF),
+ CSSC_INSN ("smin", 0x11c80000, 0x7ffc0000, OP3 (Rd, Rn, CSSC_SIMM8), QL_R2NIL, F_SF),
+ CSSC_INSN ("umin", 0x11cc0000, 0x7ffc0000, OP3 (Rd, Rn, CSSC_UIMM8), QL_R2NIL, F_SF),
+
+/* CSSC with registers only. */
+ CSSC_INSN ("abs", 0x5ac02000, 0x7ffffc00, OP2 (Rd, Rn), QL_I2SAME, F_SF),
+ CSSC_INSN ("cnt", 0x5ac01c00, 0x7ffffc00, OP2 (Rd, Rn), QL_I2SAME, F_SF),
+ CSSC_INSN ("ctz", 0x5ac01800, 0x7ffffc00, OP2 (Rd, Rn), QL_I2SAME, F_SF),
+ CSSC_INSN ("smax", 0x1ac06000, 0x7fe0fc00, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF),
+ CSSC_INSN ("umax", 0x1ac06400, 0x7fe0fc00, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF),
+ CSSC_INSN ("smin", 0x1ac06800, 0x7fe0fc00, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF),
+ CSSC_INSN ("umin", 0x1ac06c00, 0x7fe0fc00, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF),
+
{0, 0, 0, 0, 0, 0, {}, {}, 0, 0, 0, NULL},
};
@@ -5928,4 +5948,8 @@ const struct aarch64_opcode aarch64_opcode_table[] =
Y(INT_REG, x0_to_x30, "MOPS_ADDR_Rs", 0, F(FLD_Rs), \
"a register source address with writeback") \
Y(INT_REG, x0_to_x30, "MOPS_WB_Rd", 0, F(FLD_Rn), \
- "an integer register with writeback")
+ "an integer register with writeback") \
+ Y(IMMEDIATE, imm, "CSSC_SIMM8", OPD_F_SEXT, F(FLD_CSSC_imm8), \
+ "an 8-bit signed immediate") \
+ Y(IMMEDIATE, imm, "CSSC_UIMM8", 0, F(FLD_CSSC_imm8), \
+ "an 8-bit unsigned immediate")
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