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* x86: change fetch error handling in ckprefix()Jan Beulich2023-04-211-12/+20
* x86: change fetch error handling in top-level functionJan Beulich2023-04-211-13/+59
* x86: move fetch error handling into a helper functionJan Beulich2023-04-211-28/+35
* RISC-V: Cache the latest mapping symbol and its boundary.Kito Cheng2023-04-181-0/+43
* arc: remove faulty instructionsClaudiu Zissulescu2023-04-122-720/+6
* Fix illegal memory access when disassembling corrupt NFP binaries.Nick Clifton2023-04-112-1/+9
* Support Intel AMX-COMPLEXHaochen Jiang2023-04-077-4711/+4808
* asan: csky floatformat_to_double uninitialised valueAlan Modra2023-04-031-10/+6
* opcodes/arm: adjust whitespace in cpsie instructionAndrew Burgess2023-04-031-2/+2
* RISC-V: Allocate "various" operand typeTsukasa OI2023-03-312-8/+24
* x86: parse VEX and alike specifiers for .insnJan Beulich2023-03-311-0/+2
* x86: introduce .insn directiveJan Beulich2023-03-313-0/+5
* aarch64: Add the RPRFM instructionRichard Sandiford2023-03-306-885/+925
* aarch64: Add the SVE FCLAMP instructionRichard Sandiford2023-03-302-759/+771
* aarch64: Add new SVE shift instructionsRichard Sandiford2023-03-302-873/+909
* aarch64: Add new SVE saturating conversion instructionsRichard Sandiford2023-03-302-752/+788
* aarch64: Add new SVE dot-product instructionsRichard Sandiford2023-03-306-841/+923
* aarch64: Add the SVE BFMLSL instructionsRichard Sandiford2023-03-302-742/+793
* aarch64: Add the SME2 UZP and ZIP instructionsRichard Sandiford2023-03-302-338/+438
* aarch64: Add the SME2 UNPK instructionsRichard Sandiford2023-03-302-709/+757
* aarch64: Add the SME2 shift instructionsRichard Sandiford2023-03-309-505/+679
* aarch64: Add the SME2 saturating conversion instructionsRichard Sandiford2023-03-306-468/+592
* aarch64: Add the SME2 FP<->FP conversion instructionsRichard Sandiford2023-03-302-948/+1000
* aarch64: Add the SME2 FP<->int conversion instructionsRichard Sandiford2023-03-302-749/+945
* aarch64: Add the SME2 CLAMP instructionsRichard Sandiford2023-03-302-820/+892
* aarch64: Add the SME2 MOPA and MOPS instructionsRichard Sandiford2023-03-302-717/+789
* aarch64: Add the SME2 vertical dot-product instructionsRichard Sandiford2023-03-302-669/+789
* aarch64: Add the SME2 dot-product instructionsRichard Sandiford2023-03-302-753/+1353
* aarch64: Add the SME2 MLALL and MLSLL instructionsRichard Sandiford2023-03-306-851/+1599
* aarch64: Add the SME2 MLAL and MLSL instructionsRichard Sandiford2023-03-308-665/+1485
* aarch64: Add the SME2 FMLA and FMLS instructionsRichard Sandiford2023-03-306-529/+753
* aarch64: Add the SME2 maximum/minimum instructionsRichard Sandiford2023-03-304-439/+979
* aarch64: Add the SME2 ADD and SUB instructionsRichard Sandiford2023-03-308-487/+750
* aarch64: Add the SME2 ZT0 instructionsRichard Sandiford2023-03-308-397/+686
* aarch64: Add the SME2 predicate-related instructionsRichard Sandiford2023-03-3010-821/+1270
* aarch64: Add the SME2 multivector LD1 and ST1 instructionsRichard Sandiford2023-03-3010-448/+2088
* aarch64: Add the SME2 MOVA instructionsRichard Sandiford2023-03-3010-312/+674
* aarch64: Add support for predicate-as-counter registersRichard Sandiford2023-03-306-1597/+1647
* aarch64; Add support for vector offset rangesRichard Sandiford2023-03-301-9/+48
* aarch64: Add support for vgx2 and vgx4Richard Sandiford2023-03-301-8/+41
* aarch64: Add _off4 suffix to AARCH64_OPND_SME_ZA_arrayRichard Sandiford2023-03-303-7/+7
* aarch64: Add a _10 suffix to FLD_imm3Richard Sandiford2023-03-306-8/+8
* aarch64: Prefer register ranges & support wrappingRichard Sandiford2023-03-301-1/+1
* aarch64: Add support for strided register listsRichard Sandiford2023-03-302-23/+56
* aarch64: Sort fields alphanumericallyRichard Sandiford2023-03-302-163/+164
* aarch64: Resync field namesRichard Sandiford2023-03-301-7/+7
* aarch64: Regularise FLD_* suffixesRichard Sandiford2023-03-306-55/+55
* aarch64: Add a aarch64_cpu_supports_inst_p helperRichard Sandiford2023-03-301-0/+13
* aarch64: Reorder some OP_SVE_* macrosRichard Sandiford2023-03-301-16/+16
* aarch64: Rename aarch64-tbl.h OP_SME_* macrosRichard Sandiford2023-03-301-81/+77
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